Semiconductor structure and mask layout
By introducing a protruding portion of the partition structure at the partition position of the source-drain interconnection line, the capacitance between the source-drain interconnection line and the gate structure is reduced, solving the problem of excessive capacitance of the semiconductor structure in high-frequency signal transmission and improving the operating frequency.
Patent Information
- Application Number
- CN202311022994.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-14
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2043-08-14
AI Technical Summary
When existing semiconductor structures transmit high-frequency signals, the Miller effect affects device performance and thus the operating frequency due to the large capacitance between the source-drain interconnect and the gate structure.
At the isolation position of the source-drain interconnection line, a protruding portion of the isolation structure is introduced to reduce the facing area between the source-drain interconnection line and the adjacent gate structure. The capacitance is reduced by designing the isolation structure.
The capacitance between the source-drain interconnection line and the adjacent gate structure is effectively reduced, the operating frequency of the semiconductor structure is improved, and the influence of the Miller effect is especially reduced.
Smart Images
Figure CN119517899B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a mask layout. Background Art
[0002] The layout structure of a standard cell determines the resistance and capacitance of a digital circuit, significantly impacting chip power and speed. Key MOS components and their corresponding resistor and capacitor networks are included in the layout design. However, when the cell is operational, the equivalent circuit can become even more complex. Therefore, each component of the layout structure must be considered and addressed individually.
[0003] Because there is a tiny capacitance between the input and output terminals of the transistor, when the input signal is shocked by the capacitance, it is fed back to the input terminal, affecting the performance of the device.
[0004] When using high-frequency signal transmission, the Miller effect may cause distortion of the output signal. In addition, the capacitance generated by isotropic components (such as diodes, transistors, etc.) inevitably introduces the Miller effect, thereby increasing errors and noise, and even causing system instability. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a mask layout to increase the operating frequency of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a base, including a substrate, and a plurality of channel structures protruding from the substrate, the channel structures extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; a gate structure, located on the substrate and spanning the plurality of channel structures, the gate structure extending along the second direction and arranged in parallel along the first direction; source-drain doped layers, located in the channel structures on both sides of the gate structure; source-drain interconnections, located between adjacent gate structures, the source-drain interconnections extending along the second direction across the plurality of source-drain doped layers and electrically connected thereto; a partition structure, extending along the first direction through one or more source-drain interconnections, and partitioning the source-drain interconnections on both sides thereof in the second direction, wherein at the position where the source-drain interconnections are partitioned, the partition structure has a protrusion extending along the second direction and penetrating the source-drain interconnections.
[0007] Optionally, the source-drain doped layer includes a source located on one side of the gate structure and a drain located on the other side of the gate structure; the isolation structure has a protrusion at a position where the source-drain interconnection line spanning multiple drains and electrically connected thereto is isolated.
[0008] Optionally, the semiconductor structure is an inverter, the gate structure is the input end of the inverter, and the drain is the output end of the inverter.
[0009] Optionally, the substrate includes a first region and a second region arranged adjacent to each other along a second direction, the first region and the second region both include a plurality of transistors arranged along the first direction, and the transistors in the first region and the transistors in the second region are of different types; the partition structure is at the junction of the first region and the second region, and extends along the first direction across the plurality of transistors.
[0010] Optionally, there is a gap between the protrusion of the partition structure and the channel structure located on one side of the protrusion of the partition structure and closest to the partition structure.
[0011] Optionally, the size of the interval is less than or equal to 30% of the total width of the partition structure having the protrusion along the second direction.
[0012] Optionally, at the position where the source-drain interconnection line is isolated, both sides of the isolation structure along the second direction have protrusions.
[0013] Correspondingly, an embodiment of the present invention further provides a mask pattern, comprising: a channel pattern layer, comprising a plurality of channel patterns, the channel patterns extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; a gate pattern layer, located above the channel pattern layer, the gate pattern layer comprising a plurality of gate patterns extending along the second direction and arranged in parallel along the first direction, the projection of the gate pattern in the channel pattern layer spanning the plurality of channel patterns; a source-drain pattern layer, located above the gate pattern layer, the source-drain pattern layer comprising source-drain patterns, the projection of the source-drain pattern in the channel pattern layer being located in the channel patterns on both sides of the gate pattern; an interconnection pattern layer, located above the source pattern layer; Above the stencil layer, the interconnection line layer includes a source-drain interconnection pattern, the projection of the source-drain interconnection pattern in the gate layer is located between adjacent gate patterns, and the projection of the source-drain interconnection pattern in the source-drain layer extends along the second direction across multiple source-drain patterns; the partition layer is located above the interconnection line layer, the partition layer includes a partition pattern, the projection of the partition pattern in the interconnection line layer extends along the first direction across one or more source-drain interconnection patterns, and isolates the source-drain interconnection patterns on both sides thereof in the second direction, and at the position where the source-drain interconnection pattern is isolated, the partition pattern has a protruding pattern extending along the second direction and covering part of the source-drain interconnection pattern.
[0014] Optionally, in the source-drain pattern layer, the source-drain pattern includes a source pattern located on one side of the gate pattern, and a drain pattern located on the other side of the gate pattern; in the interconnection line pattern layer, at the position where the source-drain interconnection pattern spanning multiple drain patterns is isolated, the isolation pattern has a protruding pattern.
[0015] Optionally, the mask pattern is used to form an inverter, the gate pattern is used to form an input end of the inverter, and the drain pattern is used to form an output end of the inverter.
[0016] Optionally, the mask pattern includes a first area and a second area arranged adjacent to each other along a second direction, the first area and the second area both include a plurality of transistors arranged along the first direction, and the transistors in the first area and the transistors in the second area are of different types; in the partition plate layer, the partition pattern is at the junction of the first area and the second area, and extends along the first direction across the plurality of transistors.
[0017] Optionally, in the partition plate layer, there is a gap between the protruding pattern of the partition pattern and the channel pattern located on one side of the protruding pattern of the partition pattern and closest to the partition pattern.
[0018] Optionally, the size of the interval is less than or equal to 30% of the total width of the partition pattern having the protruding pattern along the second direction.
[0019] Optionally, in the partition plate layer, at the position where the source-drain interconnection pattern is partitioned, both sides of the partition pattern along the second direction have protruding patterns.
[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0021] In the semiconductor structure provided by an embodiment of the present invention, a source-drain interconnection is located between adjacent gate structures, and the source-drain interconnection extends along a second direction across multiple source-drain doped layers and is electrically connected thereto. A partition structure extends along a first direction through one or more source-drain interconnections, and partitions the source-drain interconnections located on both sides thereof in a second direction. At the position where the source-drain interconnection is partitioned, the partition structure has a protrusion extending along the second direction and penetrating the source-drain interconnection. In the embodiment of the present invention, at the position where the source-drain interconnection is partitioned, the source-drain interconnection is additionally penetrated by the protrusion. That is, at the position where the source-drain interconnection is partitioned, while the partition structure partitions the source-drain interconnection, its protrusion additionally occupies a portion of the length of the source-drain interconnection along the second direction, correspondingly reducing the length of the source-drain interconnection in the second direction, thereby reducing the facing area between the source-drain interconnection and the adjacent gate structure, which is beneficial to reducing the capacitance between the source-drain interconnection and the adjacent gate structure, and further beneficial to improving the operating frequency of the semiconductor structure.
[0022] In the mask pattern provided by the embodiment of the present invention, the interconnection line pattern layer includes a source-drain interconnection pattern, the projection of the source-drain interconnection pattern in the gate pattern layer is located between adjacent gate patterns, and the projection of the source-drain interconnection pattern in the source-drain pattern layer extends along the second direction across multiple source-drain patterns, and the partition pattern layer includes a partition pattern, the projection of the partition pattern in the interconnection line pattern layer extends along the first direction across one or more source-drain interconnection patterns, and partitions the source-drain interconnection patterns on both sides thereof in the second direction, and at the position where the source-drain interconnection pattern is isolated, the partition pattern has a protruding pattern extending along the second direction and covering a portion of the source-drain interconnection pattern; in the embodiment of the present invention, the source-drain interconnection pattern is used to form a source-drain interconnection line, the partition pattern is used to form a partition structure, the protruding pattern is used to form a protruding portion, and the gate pattern is used to form a gate structure. At the position where the source-drain interconnection pattern is isolated, the source-drain interconnection pattern is additionally covered by the protruding pattern. That is to say, at the position where the source-drain interconnection line is isolated, while the partition structure isolates the source-drain interconnection line, its protruding portion also additionally occupies a portion of the length of the source-drain interconnection line along the second direction, correspondingly reducing the length of the source-drain interconnection line in the second direction, thereby reducing the facing area between the source-drain interconnection line and the adjacent gate structure, which is beneficial to reducing the capacitance between the source-drain interconnection line and the adjacent gate structure, and further beneficial to improving the operating frequency of the semiconductor structure formed by the mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is a corresponding structural schematic diagram of a semiconductor structure;
[0024] Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;
[0025] Figure 3 is a circuit diagram corresponding to an embodiment of a semiconductor structure of the present invention;
[0026] Figure 4 The mask of the present invention Figure 1 Schematic diagram corresponding to the embodiment;
[0027] Figure 5 The mask of the present invention Figure 1 Circuit diagram corresponding to the embodiment. DETAILED DESCRIPTION
[0028] The operating performance of current semiconductor structures needs to be improved. This article analyzes the reasons why the operating frequency of a semiconductor structure needs to be improved.
[0029] Figure 1 It is a structural schematic diagram corresponding to a semiconductor structure.
[0030] refer to Figure 1The semiconductor structure includes: a base, including a substrate (not shown), and a plurality of channel structures 10 protruding from the substrate, the channel structures 10 along a first direction (such as Figure 1 X direction) and extends along the second direction (as shown in FIG. Figure 1 The first direction is perpendicular to the second direction; the gate structure 20 is located on the substrate and spans multiple channel structures 10, and the gate structure 20 extends along the second direction and is arranged in parallel along the first direction; the source-drain doped layers (not marked) are located in the channel structures 10 on both sides of the gate structure 20; the source-drain interconnection line 30 is located between adjacent gate structures 20, and the source-drain interconnection line 30 extends along the second direction across multiple source-drain doped layers and is electrically connected thereto; the partition structure 40 extends along the first direction through one or more source-drain interconnections 30, and partitions the source-drain interconnections 30 on both sides thereof in the second direction.
[0031] The gate structure 20 and the source-drain interconnection line 30 extend along the second direction and are alternately arranged along the first direction. During the operation of the semiconductor, the gate structure 20 is electrically connected to the outside, and the source-drain interconnection line 30 is electrically connected to the outside. In the second direction, the relative length of the source-drain interconnection line 30 and the gate structure 20 is large. Correspondingly, the facing area between the source-drain interconnection line 30 and the adjacent gate structure 20 is large, which easily leads to a large capacitance generated between the source-drain interconnection line 30 and the adjacent gate structure 20, thereby affecting the operating frequency of the semiconductor structure.
[0032] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a base, including a substrate, and multiple channel structures protruding from the substrate, the channel structures extending along a first direction and arranged in parallel along a second direction, the first direction being perpendicular to the second direction; a gate structure, located on the substrate and spanning the multiple channel structures, the gate structure extending along the second direction and arranged in parallel along the first direction; source-drain doped layers, located in the channel structures on both sides of the gate structure; source-drain interconnections, located between adjacent gate structures, the source-drain interconnections extending along the second direction across the multiple source-drain doped layers and electrically connected thereto; a partition structure, extending along the first direction through one or more source-drain interconnections, and partitioning the source-drain interconnections on both sides thereof in the second direction, and at the position where the source-drain interconnections are partitioned, the partition structure has a protrusion extending along the second direction and penetrating the source-drain interconnections.
[0033] In an embodiment of the present invention, at the position where the source-drain interconnection line is isolated, the source-drain interconnection line is additionally penetrated by a protrusion. That is, at the position where the source-drain interconnection line is isolated, while the isolation structure isolates the source-drain interconnection line, its protrusion additionally occupies a portion of the length of the source-drain interconnection line along the second direction, which correspondingly reduces the length of the source-drain interconnection line in the second direction, thereby reducing the facing area between the source-drain interconnection line and the adjacent gate structure, which is beneficial to reducing the capacitance between the source-drain interconnection line and the adjacent gate structure, and further beneficial to improving the operating frequency of the semiconductor structure.
[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0035] Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention; Figure 3 FIG. 4 is a circuit diagram corresponding to an embodiment of a semiconductor structure of the present invention.
[0036] Combined with reference Figure 2 and Figure 3 , Figure 2 It is a structural diagram. Figure 3 The semiconductor structure includes: a base (not shown), a substrate (not shown), and a plurality of channel structures 100 protruding from the substrate, wherein the channel structures 100 are arranged along a first direction (such as Figure 2 X direction) and extends along the second direction (as shown in FIG. Figure 2 The first direction is perpendicular to the second direction; the gate structure 200 is located on the substrate and spans multiple channel structures 100, and the gate structure 200 extends along the second direction and is arranged in parallel along the first direction; the source-drain doped layer (not marked) is located in the channel structure 100 on both sides of the gate structure 200; the source-drain interconnection 300 is located between adjacent gate structures 200, and the source-drain interconnection 300 extends along the second direction to span multiple source-drain doped layers and is electrically connected thereto; the partition structure 400 extends along the first direction to penetrate one or more source-drain interconnections 300, and isolates the source-drain interconnections 300 on both sides thereof in the second direction. At the position where the source-drain interconnection 300 is isolated, the partition structure 400 has a protrusion 410 extending along the second direction and penetrating the source-drain interconnection 300.
[0037] The substrate provides the process operation basis for the formation process of semiconductor structure
[0038] Specifically, the substrate provides an operating platform for the formation process of the semiconductor structure.
[0039] In this embodiment, the substrate is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.
[0040] As an example, refer to Figure 3 In this embodiment, the semiconductor structure is an inverter, the gate structure 200 is the input end of the inverter, and the drain is the output end of the inverter.
[0041] Miller capacitance is the capacitance connected between the output and input of an inverter. The effect of Miller capacitance on the frequency characteristics of a device or circuit is known as the Miller effect. Specifically, due to the tiny capacitance between the input and output terminals, when the input signal is affected by this capacitance, the shock wave is fed back to the input terminal, affecting device performance.
[0042] Therefore, this embodiment is particularly suitable for inverters. Due to the Miller effect, reducing the capacitance between the input terminal (ie, the gate structure 200 ) and the output terminal (ie, the source-drain interconnection 300 ) in the inverter circuit has a greater benefit for the inverter.
[0043] Specifically, with reference to Figure 2 Semiconductor structures and Figure 3 Circuit diagram, in this embodiment, the semiconductor structure is an inverter, the substrate includes a first area 10a and a second area 10b arranged adjacent to each other along the second direction, the first area 10a and the second area 10b both include a plurality of transistors arranged along the first direction, and the transistors in the first area 10a and the transistors in the second area 10b are of different types.
[0044] The transistors in the first region 10 a and the transistors in the second region 10 b are of different types. One of the transistors in the first region 10 a and the transistors in the second region 10 b is a PMOS transistor, and the other is an NMOS transistor.
[0045] The channel structure 100 is used to provide a channel for a semiconductor structure.
[0046] In this embodiment, the channel structure 100 is a fin. In other embodiments, the channel structure may also be a channel stack.
[0047] In this embodiment, the material of the channel structure 100 includes silicon, germanium, silicon germanium, or a III-V semiconductor material. As an example, the material of the channel structure 100 is silicon. In other embodiments, the material of the channel structure is determined by the type and performance of the transistor.
[0048] It should be noted that, in this embodiment, the channel structure 100 and the substrate are made of the same material. In other embodiments, the channel structure and the substrate may be made of different materials.
[0049] The gate structure 200 is used to control the opening and closing of the channel of the transistor.
[0050] In this embodiment, the gate structure 200 includes a gate dielectric layer covering the channel structure 100 and a gate electrode layer located on the gate dielectric layer.
[0051] The gate dielectric layer is used to isolate the gate structure 200 from the channel structure 100 .
[0052] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.
[0053] It should be noted that the gate dielectric layer may further include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel structure 100. Specifically, the material of the gate oxide layer may be silicon oxide.
[0054] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0055] In this embodiment, the gate structure 200 is a metal gate structure.
[0056] Therefore, the gate electrode layer includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to electrically lead out the metal gate structure.
[0057] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.
[0058] In other embodiments, the gate structure may also be a dummy gate structure.
[0059] The source-drain doped layer is used as a source region or a drain region of the semiconductor structure. Specifically, the doping type of the source-drain doped layer is the same as the channel conductivity type of the corresponding transistor.
[0060] Specifically, when the substrate is used to form an NMOS transistor, the material of the source-drain doped layer is Si or SiC, and the source-drain doped layer provides tensile stress for the channel region of the NMOS transistor, thereby facilitating improvement of the carrier mobility of the NMOS transistor; when the substrate is used to form a PMOS transistor, the material of the source-drain doped layer is Si or SiGe, and the source-drain doped layer provides compressive stress for the channel region of the PMOS transistor, thereby facilitating improvement of the carrier mobility of the PMOS transistor.
[0061] In this embodiment, the source-drain doped layer includes a source (not labeled) located on one side of the gate structure 200 and a drain (not labeled) located on the other side of the gate structure 200 .
[0062] The source electrode is used as a source region of the semiconductor structure, and the drain electrode is used as a drain region of the semiconductor structure.
[0063] Specifically, in this embodiment, the semiconductor structure is an inverter, the gate structure 200 is the input end of the inverter, the drain is the output end of the inverter, and a Miller capacitor is provided between the input end and the output end.
[0064] The source-drain interconnection line 300 is used to electrically connect a plurality of source-drain doped layers, thereby loading electrical signals to the plurality of source-drain doped layers.
[0065] In this embodiment, the source-drain interconnection line 300 is made of a metal material, specifically tungsten. In other embodiments, the source-drain interconnection line 300 may be made of cobalt or ruthenium.
[0066] The isolation structure 400 is used to isolate the source-drain interconnection lines 300 on both sides thereof in the second direction.
[0067] In this embodiment, at the position where the source-drain interconnection line 300 is isolated, the source-drain interconnection line 300 is additionally penetrated by the protrusion 410. That is, at the position where the source-drain interconnection line 300 is isolated, while the isolation structure 400 isolates the source-drain interconnection line 300, its protrusion 410 also additionally occupies part of the length of the source-drain interconnection line 300 along the second direction, correspondingly reducing the length of the source-drain interconnection line 300 in the second direction, thereby reducing the facing area between the source-drain interconnection line 300 and the adjacent gate structure 200, which is beneficial to reducing the capacitance between the source-drain interconnection line 300 and the adjacent gate structure 200, and further beneficial to improving the operating frequency of the semiconductor structure.
[0068] In this embodiment, the partition structure 400 has a protruding portion 410 at a position where the source-drain interconnection line 300 that crosses over and is electrically connected to a plurality of drains is partitioned.
[0069] In this embodiment, the semiconductor structure is an inverter, the gate structure 200 is the input end of the inverter, the drain is the output end of the inverter, and there is a Miller capacitance between the input end and the output end. Therefore, by isolating the source-drain interconnection line 300 that spans multiple drains and is electrically connected to them at the position where it is isolated, the isolation structure 400 has a protrusion 410, which reduces the length of the source-drain interconnection line 300 corresponding to the drain in the second direction, thereby reducing the facing area between the source-drain interconnection line 300 corresponding to the drain and the adjacent gate structure 200, reducing the capacitance between the input end and the output end, and especially reducing the influence of the Miller effect on the semiconductor structure, thereby significantly improving the operating frequency of the semiconductor structure.
[0070] In other embodiments, the isolation structure may have a protrusion at a location where a source-drain interconnection line that spans across and is electrically connected to a plurality of sources is isolated.
[0071] In other embodiments, the partition structure may have protrusions at positions where source-drain interconnections spanning multiple sources and electrically connected thereto are isolated, and at positions where source-drain interconnections spanning multiple drains and electrically connected thereto are isolated.
[0072] In this embodiment, the partition structure 400 is located at the boundary between the first region 10 a and the second region 10 b and extends along the first direction across the plurality of transistors.
[0073] In this embodiment, the partition structure 400 at the junction of the first area 10a and the second area 10b extends across multiple transistors along the first direction. That is, the partition structure 400 at the junction of the first area 10a and the second area 10b is a structure that extends longer along the first direction. Then, a protrusion 410 is formed on the partition structure 400 at the junction of the first area 10a and the second area 10b, which can reduce the length of the multiple source-drain interconnections 300 in the second direction, thereby reducing the facing area between the multiple source-drain interconnections 300 and the adjacent gate structures 200. This is beneficial for reducing the capacitance between the multiple source-drain interconnections 300 and the adjacent gate structures 200 through one partition structure 400, thereby facilitating improving the operating frequency of the semiconductor structure, simplifying the process flow, and improving process efficiency.
[0074] In other embodiments, a partition structure with a protrusion may be formed at other locations.
[0075] In this embodiment, at the position where the source-drain interconnection line 300 is isolated, both sides of the isolation structure 400 along the second direction have protrusions 410 .
[0076] At the position where the source-drain interconnection line 300 is isolated, the partition structure 400 has protrusions 410 on both sides along the second direction, so that part of the length of the source-drain interconnection line 300 is additionally occupied on both sides of the partition structure 400, and the length of the source-drain interconnection line 300 on both sides is correspondingly reduced in the second direction, thereby reducing the facing area between the source-drain interconnection line 300 on both sides and the adjacent gate structure 200, which is beneficial to further reduce the capacitance between the source-drain interconnection line 300 and the adjacent gate structure 200, and further beneficial to further improve the operating frequency of the semiconductor structure.
[0077] In this embodiment, there is a gap between the protrusion 410 of the partition structure 400 and the channel structure 100 located on one side of the protrusion 410 of the partition structure 400 and closest to the partition structure 400 .
[0078] There is a gap between the protrusion 410 of the partition structure 400 and the channel structure 100 located on one side of the protrusion 410 of the partition structure 400 and closest to the partition structure 400, so that the formation of the protrusion 410 will not cause damage to the channel structure 100 as much as possible, thereby ensuring that the formation of the protrusion 410 will not affect the semiconductor structure.
[0079] It should be noted that in this embodiment, the size d of the gap should not be too large or too small. If the size d of the gap is too large, it is easy to cause the size of the protrusion 410 along the second direction to be too small, resulting in the length of the source-drain interconnect 300 additionally occupied by the protrusion 410 along the second direction being too small. Accordingly, the length of the source-drain interconnect 300 in the second direction does not change much, making it difficult to reduce the area directly facing the source-drain interconnect 300 and the adjacent gate structure 200, and further making it difficult to reduce the capacitance between the source-drain interconnect 300 and the adjacent gate structure 200, which is not effective in improving the operating frequency of the semiconductor structure. If the size d of the gap is too small, it is easy to cause the distance between the protrusion 410 and the channel structure 100 located on one side of the protrusion 410 of the partition structure 400 and closest to the partition structure 400 to be too close. In the step of forming the partition structure 400, the channel structure 100 closest to the partition structure 400 is easily damaged, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the size d of the interval is less than or equal to 30% of the total width of the partition structure 400 having the protrusion 410 along the second direction.
[0080] In this embodiment, the partition structure 400 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride.
[0081] This embodiment also provides a mask pattern.
[0082] Figure 4 The mask of the present invention Figure 1 Schematic diagram corresponding to the embodiment; Figure 5 The mask of the present invention Figure 1 Circuit diagram corresponding to the embodiment.
[0083] Combined with reference Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of the layout layer. Figure 5 The circuit diagram includes a mask pattern including a channel pattern layer including a plurality of channel patterns 101, the channel patterns 101 are arranged along a first direction (eg Figure 4 X direction) and extends along the second direction (as shown in FIG. Figure 4 The first direction is perpendicular to the second direction; the gate plate layer is located above the channel plate layer, the gate plate layer includes a plurality of gate patterns 201 extending along the second direction and arranged in parallel along the first direction, and the projection of the gate pattern 201 in the channel plate layer spans across the plurality of channel patterns 101; the source-drain plate layer is located above the gate plate layer, the source-drain plate layer includes source-drain patterns (not shown), and the projection of the source-drain patterns in the channel plate layer is located in the channel patterns 101 on both sides of the gate pattern 201; the interconnection line plate layer is located above the source-drain plate layer, the interconnection line plate layer includes a source-drain interconnection pattern 301, a source-drain interconnection pattern 301, and a source-drain interconnection pattern 301. The projection of the gate pattern 1 in the gate pattern layer is located between adjacent gate patterns 201, and the projection of the source-drain interconnection pattern 301 in the source-drain pattern layer extends along the second direction across multiple source-drain patterns; a partition pattern layer is located above the interconnection line pattern layer, and the partition pattern layer includes a partition pattern 401. The projection of the partition pattern 401 in the interconnection line pattern layer extends along the first direction across one or more source-drain interconnection patterns 301, and isolates the source-drain interconnection patterns 301 on both sides thereof in the second direction. At the location where the source-drain interconnection pattern 301 is isolated, the partition pattern 401 has a protruding pattern 411 extending along the second direction and covering a portion of the source-drain interconnection pattern 301.
[0084] Combined with reference Figure 5 In this embodiment, the mask pattern is used to form an inverter, the gate pattern 201 is used to form the input end of the inverter, and the drain pattern is used to form the output end of the inverter.
[0085] Miller capacitance is the capacitance connected between the output and input of an inverter. The effect of Miller capacitance on the frequency characteristics of a device or circuit is known as the Miller effect. Specifically, due to the tiny capacitance between the input and output terminals, when the input signal is affected by this capacitance, the shock wave is fed back to the input terminal, affecting device performance.
[0086] Therefore, this embodiment is particularly suitable for inverters. Due to the Miller effect, the reduction in capacitance between the input end (i.e., the gate structure corresponding to the gate pattern 201) and the output end (i.e., the source-drain interconnection line corresponding to the source-drain interconnection pattern 301) in the inverter circuit is of great benefit to the inverter.
[0087] Specifically, with reference to Figure 4 Semiconductor structures and Figure 5 Circuit diagram. In this embodiment, the semiconductor structure is an inverter. The mask pattern includes a first region 11a and a second region 11b adjacent to each other along a second direction. The first region 11a and the second region 11b both include a plurality of transistors arranged along the first direction. The transistors in the first region 11a and the transistors in the second region 11b are of different types.
[0088] The transistors in the first region 11 a and the transistors in the second region 11 b are of different types. One of the transistors in the first region 11 a and the transistors in the second region 11 b is a PMOS transistor, and the other is an NMOS transistor.
[0089] The channel pattern 101 in the channel plate layer is used to form a channel structure. Specifically, the channel structure is used to provide a channel for the semiconductor structure.
[0090] In this embodiment, the channel structure is a fin. In other embodiments, the channel structure may also be a channel stack.
[0091] The gate pattern 201 is used to form a gate structure. Specifically, the gate structure controls the opening and closing of the channel of the transistor.
[0092] The gate plate layer is located above the channel plate layer. In the semiconductor manufacturing process, the channel structure is formed first and then the gate structure is formed.
[0093] The source / drain patterns are used to form source / drain doped layers. Specifically, the source / drain doped layers are used as source regions or drain regions of a semiconductor structure.
[0094] The source and drain layer is located above the gate layer. In the semiconductor manufacturing process, a dummy gate structure is first formed to occupy the gate structure, and then the source and drain doping layers are formed.
[0095] Specifically, the doping type of the source and drain doping layers is the same as the channel conductivity type of the corresponding transistor.
[0096] In this embodiment, in the source / drain layer, the source / drain patterns include a source pattern (not labeled) located on one side of the gate pattern 201 and a drain pattern (not labeled) located on the other side of the gate pattern 201 .
[0097] The source pattern is used to form a source electrode, specifically, the source electrode is used to serve as a source region of the semiconductor structure. The drain pattern is used to form a drain electrode, specifically, the drain electrode is used to serve as a drain region of the semiconductor structure.
[0098] Specifically, in this embodiment, the semiconductor structure is an inverter, the gate structure is the input end of the inverter, the drain is the output end of the inverter, and a Miller capacitor is provided between the input end and the output end.
[0099] The source-drain interconnection pattern 301 is used to form a source-drain interconnection line. Specifically, the source-drain interconnection line electrically connects a plurality of source-drain doped layers, thereby loading electrical signals to the plurality of source-drain doped layers.
[0100] The interconnection line layer is located above the source and drain layer. In the semiconductor structure manufacturing process, the source and drain doping layers are formed first, and then the source and drain interconnection lines are formed.
[0101] The partition pattern 401 is used to form a partition structure, wherein the protruding pattern 411 is used to form a protruding portion of the partition structure. Specifically, the partition structure is used to isolate the source-drain interconnects located on both sides thereof in the second direction.
[0102] In this embodiment, at the position where the source-drain interconnection line is isolated, the source-drain interconnection line is additionally penetrated by the protrusion. That is to say, at the position where the source-drain interconnection line is isolated, while the isolation structure isolates the source-drain interconnection line, its protrusion also additionally occupies part of the length of the source-drain interconnection line along the second direction, and accordingly reduces the length of the source-drain interconnection line in the second direction, thereby reducing the facing area between the source-drain interconnection line and the adjacent gate structure, which is beneficial to reducing the capacitance between the source-drain interconnection line and the adjacent gate structure, and further beneficial to improving the operating frequency of the semiconductor structure formed by the mask pattern.
[0103] In this embodiment, in the interconnection line pattern layer, at a position where the source-drain interconnection pattern 301 that spans across a plurality of drain patterns is isolated, the isolation pattern 401 has a protruding pattern 411 .
[0104] That is, in this embodiment, the partition structure has a protruding portion at a position where the source-drain interconnection line that spans across the plurality of drains and is electrically connected thereto is partitioned.
[0105] In this embodiment, the semiconductor structure is an inverter, the gate structure is the input end of the inverter, the drain is the output end of the inverter, and there is a Miller capacitance between the input end and the output end. Therefore, by having a protrusion at the position where the source-drain interconnection line spanning multiple drains and electrically connected thereto is isolated, the isolation structure has a protrusion, which reduces the length of the source-drain interconnection line corresponding to the drain in the second direction, thereby reducing the facing area between the source-drain interconnection line corresponding to the drain and the adjacent gate structure, reducing the capacitance between the input end and the output end, and especially reducing the influence of the Miller effect on the semiconductor structure, thereby significantly improving the operating frequency of the semiconductor structure.
[0106] In other embodiments, in the interconnection line pattern layer, at a position where a source-drain interconnection pattern spanning a plurality of source patterns is isolated, the isolation pattern may have a protruding pattern.
[0107] In other embodiments, in the interconnection line pattern layer, at the position where the source-drain interconnection pattern spanning multiple source patterns is isolated, and at the position where the source-drain interconnection pattern spanning multiple drain patterns is isolated, the isolation pattern may have a protruding pattern.
[0108] In this embodiment, in the partition plate layer, the partition pattern 401 is located at the boundary between the first region 11 a and the second region 11 b and extends along the first direction across the plurality of transistors.
[0109] That is, in this embodiment, the isolation structure is located at the boundary between the first region and the second region, and extends along the first direction across the plurality of transistors.
[0110] In this embodiment, the partition structure at the junction of the first region and the second region extends across multiple transistors along the first direction. That is, the partition structure at the junction of the first region and the second region is a structure that extends longer along the first direction. A protrusion is formed on the partition structure at the junction of the first region and the second region, which can reduce the length of the multiple source-drain interconnections in the second direction, thereby reducing the facing area between the multiple source-drain interconnections and the adjacent gate structures. This is beneficial for reducing the capacitance between the multiple source-drain interconnections and the adjacent gate structures through a single partition structure, thereby facilitating an increase in the operating frequency of the semiconductor structure, and simplifying the process flow and improving process efficiency.
[0111] In other embodiments, partition patterns with protruding patterns may also be formed at other locations.
[0112] In this embodiment, in the partitioning layer, at the position where the source-drain interconnection pattern 301 is partitioned, both sides of the partitioning pattern 401 along the second direction have protruding patterns 411 .
[0113] That is to say, in this embodiment, at the position where the source-drain interconnection line is isolated, both sides of the isolation structure along the second direction have protrusions.
[0114] At the position where the source-drain interconnection line is isolated, the isolation structure has protrusions on both sides along the second direction, so that part of the length of the source-drain interconnection line is additionally occupied on both sides of the isolation structure, and the length of the source-drain interconnection line on both sides is correspondingly reduced in the second direction, thereby reducing the facing area between the source-drain interconnection line on both sides and the adjacent gate structure, which is beneficial to further reduce the capacitance between the source-drain interconnection line and the adjacent gate structure, and further beneficial to further improve the operating frequency of the semiconductor structure.
[0115] In this embodiment, in the partition plate layer, there is a gap between the protruding pattern 411 of the partition pattern 401 and the channel pattern 101 located on one side of the protruding pattern 411 of the partition pattern 401 and closest to the partition pattern 401 .
[0116] That is to say, in this embodiment, there is a gap between the protruding portion of the partition structure and the channel structure located on one side of the protruding portion of the partition structure and closest to the partition structure.
[0117] There is a gap between the protrusion of the partition structure and the channel structure located on one side of the protrusion of the partition structure and closest to the partition structure, so that the formation of the protrusion will not damage the channel structure as much as possible, thereby ensuring that the formation of the protrusion will not affect the semiconductor structure.
[0118] It should be noted that in this embodiment, the spacing dimension d should not be too large or too small. If the spacing dimension d is too large, the protrusion along the second direction may be too small, resulting in the protrusion occupying too little additional length of the source-drain interconnect along the second direction. Consequently, the length of the source-drain interconnect in the second direction does not change significantly, making it difficult to reduce the area of contact between the source-drain interconnect and the adjacent gate structure, and thus, the capacitance between the source-drain interconnect and the adjacent gate structure. This is not effective in increasing the operating frequency of the semiconductor structure. If the spacing dimension d is too small, the protrusion may be too close to the channel structure located on one side of the protrusion of the partition structure and closest to the partition structure. This may cause damage to the channel structure closest to the partition structure during the step of forming the partition structure, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the spacing dimension d is equal to or greater than 30% of the total width of the partition pattern 401 having the protrusion pattern 411 along the second direction.
[0119] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that include: A base, comprising a substrate and a plurality of channel structures protruding from the substrate, wherein the channel structures extend along a first direction and are arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction; a gate structure, located on the substrate and spanning the plurality of channel structures, the gate structure extending along the second direction and arranged in parallel along the first direction; source-drain doped layers, located in the channel structure on both sides of the gate structure; a source-drain interconnection line, located between adjacent gate structures, the source-drain interconnection line extending along the second direction across the plurality of source-drain doped layers and electrically connected thereto; A partition structure extends along the first direction through one or more of the source-drain interconnects and partitions the source-drain interconnects on both sides thereof in the second direction. At the position where the source-drain interconnects are partitioned, the partition structure has a protrusion extending along the second direction and penetrating the source-drain interconnects.
2. The semiconductor structure according to claim 1, wherein The source-drain doped layer includes a source electrode located on one side of the gate structure and a drain electrode located on the other side of the gate structure; The partition structure has the protrusion at a position where a source-drain interconnection line spanning over and electrically connected to the plurality of drain electrodes is partitioned.
3. The semiconductor structure according to claim 1 or 2, wherein: The semiconductor structure is an inverter, the gate structure is the input end of the inverter, and the drain is the output end of the inverter.
4. The semiconductor structure according to claim 3, wherein: The substrate includes a first region and a second region adjacently arranged along the second direction, the first region and the second region each including a plurality of transistors arranged along the first direction, and the transistors in the first region and the transistors in the second region are of different types; The isolation structure is located at a junction of the first region and the second region and extends along the first direction across the plurality of transistors.
5. The semiconductor structure according to claim 1, wherein There is a gap between the protruding portion of the partition structure and the channel structure located on one side of the protruding portion of the partition structure and closest to the partition structure.
6. The semiconductor structure according to claim 5, wherein: The size of the interval is less than or equal to 30% of the total width of the partition structure having the protrusion along the second direction.
7. The semiconductor structure according to claim 1, wherein: At the position where the source-drain interconnection line is isolated, both sides of the isolation structure along the second direction have the protruding portions.
8. A mask layout, characterized in that: include: a channel plate layer, comprising a plurality of channel patterns, wherein the channel patterns extend along a first direction and are arranged in parallel along a second direction, wherein the first direction is perpendicular to the second direction; a gate plate layer located above the channel plate layer, the gate plate layer comprising a plurality of gate patterns extending along the second direction and arranged in parallel along the first direction, wherein projections of the gate patterns in the channel plate layer span across the plurality of channel patterns; a source-drain plate layer, located above the gate plate layer, the source-drain plate layer including source-drain patterns, the projections of the source-drain patterns on the channel plate layer being located in the channel patterns on both sides of the gate pattern; an interconnection line layer located above the source-drain layer, the interconnection line layer including a source-drain interconnection pattern, the projection of the source-drain interconnection pattern in the gate layer being located between adjacent gate patterns, and the projection of the source-drain interconnection pattern in the source-drain layer extending along the second direction across a plurality of the source-drain patterns; A partition plate layer is located above the interconnection line plate layer, the partition plate layer includes a partition pattern, the projection of the partition pattern in the interconnection line plate layer extends along the first direction across one or more source-drain interconnection patterns, and isolates the source-drain interconnection patterns on both sides thereof in the second direction, and at the position where the source-drain interconnection pattern is isolated, the partition pattern has a protruding pattern extending along the second direction and covering a portion of the source-drain interconnection pattern.
9. The mask layout according to claim 8, wherein: In the source-drain layer, the source-drain pattern includes a source electrode pattern located on one side of the gate electrode pattern and a drain electrode pattern located on the other side of the gate electrode pattern; In the interconnection line pattern layer, at a position where a source-drain interconnection pattern spanning a plurality of drain patterns is isolated, the isolation pattern has the protruding pattern.
10. The mask layout according to claim 9, wherein: The mask pattern is used to form an inverter, the gate pattern is used to form an input end of the inverter, and the drain pattern is used to form an output end of the inverter.
11. The mask layout according to claim 10, wherein: The mask pattern includes a first region and a second region adjacently arranged along the second direction, the first region and the second region both including a plurality of transistors arranged along the first direction, and the transistors in the first region and the transistors in the second region are of different types; In the partition plate layer, the partition pattern is located at the junction of the first region and the second region, and extends along the first direction across the plurality of transistors.
12. The mask layout according to claim 8, wherein: In the partition plate layer, there is a gap between the protruding pattern of the partition pattern and the channel pattern located on one side of the protruding pattern of the partition pattern and closest to the partition pattern.
13. The mask layout according to claim 12, wherein: The size of the interval is less than or equal to 30% of the total width of the partition pattern having the protruding pattern along the second direction.
14. The mask layout according to claim 8, wherein: In the partitioning layer, at the position where the source-drain interconnection pattern is partitioned, both sides of the partitioning pattern along the second direction have the protruding patterns.