A rigid-flex hybrid three-dimensional wafer architecture millimeter wave chip-on-array

Abstract

The application discloses a rigid-flexible mixed three-dimensional wafer architecture millimeter wave on-chip array, which comprises a plurality of rigid silicon-based wafers, an intermediate layer flexible material wafer arranged between two adjacent rigid silicon-based wafers, a rigid glass-based wafer arranged on the upper end face of the uppermost layer of the rigid silicon-based wafers, an upper layer flexible material wafer arranged on the upper end face of the rigid glass-based wafer, and a lower layer flexible material wafer arranged on the lower end face of the lowermost layer of the rigid silicon-based wafers. The engineering technical route of the large-scale millimeter wave front-end array is evolved from the 'layer-by-layer stacking type' to the'splicing assembly type' of the heterogeneous material and the heterogeneous integration of various chips with different process technologies, the defects that the traditional rigid silicon-based wafer cannot realize the flexible conformal antenna are solved, the thermal mismatch pain points when the traditional silicon-based wafer and the PCB are directly interconnected are solved, and the pain points of the large transmission loss of the millimeter wave radio frequency signal of the traditional three-dimensional stacked silicon-based wafer are solved.

Description

Technical Field

[0001] This invention belongs to the field of on-chip systems technology, specifically relating to a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array. Background Technology

[0002] As integrated circuit lithography technology enters the 5 nm and below process nodes, transistor size miniaturization is gradually approaching physical limits, and Moore's Law seems to be nearing its end. The traditional approach of improving chip performance by increasing semiconductor process technology is becoming increasingly difficult, forcing the industry to explore new, more cost-effective technological routes to meet the growing demand for chip performance. These include various "Beyond Moore" technological routes.

[0003] System-on-a-Chip (SoC) technology is one of the most popular "more than Moore" technology routes in the industry. It integrates prefabricated components (unpackaged bare chips) for computing, sensing, storage, and communication functions onto the same silicon-based wafer according to application scenario requirements, forming one or more physical systems. Through system architecture innovation, ultra-high density interconnect integration, software-defined technologies, and other enabling technologies, it achieves an order-of-magnitude improvement in overall performance.

[0004] Millimeter-wave on-chip systems (MS / CS) primarily address the miniaturized, lightweight, and multifunctional application needs of integrated RF front-ends and active arrays in cutting-edge fields such as 5G communication and phased array radar. Based on microelectronics, optoelectronics, and MEMS electronic components, and employing microsystem heterogeneous integration technology, represented by micro-nano fabrication techniques, combined with architecture, software, and algorithms, MS / CS integrates RF, digital, optoelectronic, and energy subsystems at high density, achieving significant reductions in RF system size and power consumption, and substantial improvements in performance and reliability. MS / CS have wide applications in cutting-edge fields such as information technology, industrial control, and consumer electronics.

[0005] Traditional millimeter-wave front-end arrays employ a layer-by-layer engineering approach, stacking chips, modules, components, and arrays. This approach faces bottlenecks in performance, power consumption, latency, and reliability. While a chip can potentially achieve its full potential, by the time the system is built using this layered engineering method, only about 10% of that potential remains. To address the shortcomings of existing engineering approaches, this invention provides a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array. Summary of the Invention

[0006] Technical problems solved: To address the above-mentioned technical problems, this invention provides a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array, which evolves the engineering technology route of large-scale millimeter-wave front-end arrays from "layer-by-layer stacking" to "splicing and assembly" of various chips with heterogeneous materials and different process technologies. This solves the defect that traditional rigid silicon-based wafers cannot realize flexible conformal antennas, solves the thermal mismatch problem when traditional silicon-based wafers and PCBs are directly interconnected, and solves the problem of high transmission loss of millimeter-wave radio frequency signals in traditional three-dimensional stacked silicon-based wafers.

[0007] Technical solution: A rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array, comprising several rigid silicon-based wafers, an intermediate flexible material wafer between two adjacent rigid silicon-based wafers, a rigid glass-based wafer on the uppermost rigid silicon-based wafer, an upper flexible material wafer on the uppermost rigid glass-based wafer, and a lower flexible material wafer on the lowermost rigid silicon-based wafer;

[0008] The rigid silicon-based wafer, with one or more layers, contains bare chips, the positions of which are arranged according to the design requirements of the millimeter-wave on-chip array. The rigid silicon-based wafer also contains TSVs (Transient Video Vessels), the positions and numbers of which are designed according to the vertical transmission requirements of the millimeter-wave on-chip array. Both the upper and lower surfaces of the rigid silicon-based wafer contain RDLs (Representative Layers), the number and positions of which are designed according to the planar transmission requirements of the millimeter-wave on-chip array. The rigid silicon-based wafer also contains IPDs (Integrated Devices), the positions and numbers of which are arranged according to the circuit design of the millimeter-wave on-chip array. The upper flexible material wafer or the lower flexible material wafer... The upper and lower surfaces and interior of the material wafer are provided with metallized structures. The position and number of the metallized structures are arranged according to the circuit design of the upper or lower flexible material wafer. The lower surface of the lower flexible material wafer is provided with interconnect structures. The position and number of the interconnect structures are designed according to the interconnect transmission requirements of the lower flexible material wafer. The rigid silicon-based wafer in the middle layer is provided with a cantilever structure transmission line, which together with the upper and lower flexible material wafers forms a cantilever structure stripline. The position and size of the cantilever structure transmission line are designed according to the planar transmission requirements inside the rigid silicon-based wafer.

[0009] Preferably, the rigid silicon-based wafers are stacked in the Z direction through wafer-level bonding to achieve multilayer silicon-based wafer stacking.

[0010] Preferably, the rigid glass-based wafer is stacked on the upper surface of the top rigid silicon-based wafer by wafer-level bonding.

[0011] Preferably, the upper flexible material wafer and the lower flexible material wafer are stacked on the upper end face of the rigid glass-based wafer and the lower end face of the bottom rigid silicon-based wafer, respectively, through wafer-level bonding.

[0012] Preferably, the interconnect structure includes solder balls, solder pillars, or bumps.

[0013] Preferably, the rigid glass-based wafer has an air cavity structure, which, combined with the upper flexible material wafer, can realize an ultra-thin flexible conformal antenna with low dielectric constant and low loss.

[0014] Preferably, the coefficient of thermal expansion of the lower flexible material wafer is between that of silicon and PCB.

[0015] Beneficial effects: 1) The rigid-flexible hybrid three-dimensional wafer millimeter-wave on-chip array of the present invention has an upper flexible material wafer stacked on the upper surface of a rigid glass substrate wafer through wafer-level bonding. The rigid glass substrate wafer has a cavity structure, which, combined with the upper flexible material wafer, can realize an air cavity structure with low dielectric constant and low loss, ultra-thin flexible conformal antenna, solving the defect that traditional rigid silicon substrate wafers cannot realize flexible conformal antennas;

[0016] 2) The rigid-flexible hybrid three-dimensional wafer millimeter-wave crystal array of the present invention has a lower flexible material wafer stacked on the lower end face of a rigid silicon-based wafer through wafer-level bonding. The thermal expansion coefficient of the lower flexible material wafer is between that of silicon and PCB, which can effectively buffer the thermal stress between the rigid silicon-based wafer and PCB, and solve the problem of thermal mismatch when the traditional silicon-based wafer and PCB are directly interconnected.

[0017] 3) The rigid-flexible hybrid three-dimensional wafer millimeter-wave on-chip array of the present invention achieves ultra-low loss millimeter-wave radio frequency signal transmission through the cantilever structure stripline inside the rigid silicon-based wafer. A flexible material wafer is sandwiched between two adjacent rigid silicon-based wafers. The cantilever structure transmission line is set inside the rigid silicon-based wafer, and together with the adjacent upper and lower flexible material wafers, they form a cantilever structure stripline, thereby achieving ultra-low loss millimeter-wave radio frequency signal transmission and solving the pain point of high loss in traditional three-dimensional stacked silicon-based wafer millimeter-wave radio frequency signal transmission. Attached Figure Description

[0018] Figure 1 This is an overall three-dimensional view of a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array of the present invention;

[0019] Figure 2 This is an overall top view of a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array of the present invention;

[0020] Figure 3 This is an overall bottom view of a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array of the present invention;

[0021] Figure 4 This is an overall side view of a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to the present invention;

[0022] Figure 5 This is a schematic diagram of a rigid silicon-based wafer in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0023] Figure 6 This is a schematic diagram of a rigid glass-based wafer in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0024] Figure 7 This is a schematic diagram of the upper flexible material wafer in a millimeter-wave crystal array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0025] Figure 8 This is a schematic diagram of a flexible material wafer in the lower layer of a millimeter-wave crystal array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0026] Figure 9 This is a schematic diagram of a flexible material wafer in the middle layer of a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0027] Figure 10 This is a schematic diagram of a bare chip in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention;

[0028] Figure 11 This is a schematic diagram of a TSV in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention;

[0029] Figure 12 This is a schematic diagram of the RDL in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention;

[0030] Figure 13 This is a schematic diagram of IPD in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention;

[0031] Figure 14 This is a schematic diagram of the metallization structure in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention;

[0032] Figure 15 This is a schematic diagram of the interconnect structure in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention;

[0033] Figure 16 This is a schematic diagram of a cantilever structure stripline in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0034] Figure 17This is a schematic diagram of an air cavity structure in a millimeter-wave on-chip array of a rigid-flexible hybrid three-dimensional wafer architecture according to the present invention, wherein (a) is a top view and (b) is a side view;

[0035] The numbers in the diagram are: 1. Rigid silicon wafer, 2. Rigid glass wafer, 3. Upper flexible material wafer, 4. Lower flexible material wafer, 5. Middle flexible material wafer, 6. Bare chip, 7. TSV, 8. RDL, 9. IPD, 10. Metallized structure, 11. Interconnect structure, 12. Cantilever transmission line, 13. Air cavity structure. Detailed Implementation

[0036] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments: Example 1

[0037] like Figures 1-4 As shown, a rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array includes three layers of rigid silicon-based wafers 1, with an intermediate flexible material wafer 5 between adjacent rigid silicon-based wafers 1, a rigid glass-based wafer 2 on the uppermost rigid silicon-based wafer 1, an upper flexible material wafer 3 on the uppermost rigid glass-based wafer 2, and a lower flexible material wafer 4 on the lowermost rigid silicon-based wafer 1.

[0038] The rigid silicon wafer 1 in the middle layer contains bare chips 6, the positions of which are arranged according to the design requirements of the millimeter-wave on-chip array; the rigid silicon wafer 1 contains TSVs 7, the positions and numbers of which are designed according to the vertical transmission requirements of the millimeter-wave on-chip array; the upper and lower surfaces of the rigid silicon wafer 1 each contain RDLs 8, the number and positions of which are designed according to the planar transmission requirements of the millimeter-wave on-chip array; the rigid silicon wafer 1 contains IPDs 9, the IPDs... The position and number of 9 are arranged according to the circuit design of the millimeter-wave on-chip array; the upper end face, lower end face and interior of the upper flexible material wafer 3 or the lower flexible material wafer 4 are provided with metallization structure 10, and the position and number of the metallization structure 10 are arranged according to the circuit design of the upper flexible material wafer 3 or the lower flexible material wafer 4; the lower end face of the lower flexible material wafer 4 is provided with interconnection structure 11, and the position and number of the interconnection structure 11 are designed according to the interconnection transmission requirements of the lower flexible material wafer 4; the rigid silicon-based wafer 1 in the middle layer is provided with a cantilever structure transmission line 12, which together with the upper flexible material wafer 3 and the lower flexible material wafer 4 constitutes a cantilever structure stripline, and the position and size of the cantilever structure transmission line 12 are designed according to the planar transmission requirements inside the rigid silicon-based wafer 1.

[0039] like Figure 5As shown, the rigid silicon-based wafer 1 described above achieves the stacking of multiple silicon-based wafers in the Z direction through wafer-level bonding.

[0040] like Figure 6 As shown, the rigid glass-based wafer 2 is stacked on the upper surface of the top rigid silicon-based wafer 1 by wafer-level bonding.

[0041] like Figures 7-8 As shown, the upper flexible material wafer 3 and the lower flexible material wafer 4 are stacked on the upper surface of the rigid glass-based wafer 2 and the lower surface of the bottom rigid silicon-based wafer 1 respectively through wafer-level bonding.

[0042] like Figure 9 As shown, the aforementioned intermediate flexible material wafer 5 is sandwiched between two adjacent rigid silicon-based wafers 1.

[0043] like Figure 10 As shown, the bare chip 6 is disposed inside any one or more layers of rigid silicon-based wafer 1.

[0044] like Figure 11 As shown, the TSV7 is disposed inside each layer of rigid silicon-based wafer 1, serving as a vertical signal transmission medium in the Z direction.

[0045] like Figure 12 As shown, the aforementioned RDL 8 is disposed on the upper and lower surfaces of each layer of rigid silicon-based wafer 1, serving as the signal plane wiring medium in the X and Y directions.

[0046] like Figure 13 As shown, the aforementioned IPD 9 is disposed inside each layer of rigid silicon-based wafer 1 to form an integrated passive device.

[0047] like Figure 14 As shown, the aforementioned metallization structure 10 is disposed on the upper end face, lower end face, and interior of the upper flexible material wafer 3 or the lower flexible material wafer 4, serving as a signal transmission medium for the flexible material wafer.

[0048] like Figure 15 As shown, the above-mentioned interconnect structure 11 includes solder balls, solder pillars or bumps, serving as the interconnect medium between the underlying flexible material wafer 4 and the PCB.

[0049] like Figure 16 As shown, the suspended beam transmission line 12 disposed inside the rigid silicon-based wafer 1, together with the upper flexible material wafer 3 and the lower flexible material wafer 4, constitutes a suspended beam stripline, realizing ultra-low loss millimeter-wave radio frequency signal transmission.

[0050] like Figure 17As shown, the rigid glass-based wafer 2 is provided with an air cavity structure 13. Combined with the upper flexible material wafer 3, a low dielectric constant, low loss, ultra-thin flexible conformal antenna can be realized with the air cavity structure 13.

[0051] The thermal expansion coefficient of the aforementioned lower flexible material wafer 4 is between that of silicon and PCB, which can effectively buffer the thermal stress between the rigid silicon-based wafer and PCB.

[0052] This invention is applicable to on-chip arrays in the millimeter-wave band, and solves the pain points of traditional millimeter-wave front-end arrays in terms of performance, power consumption, and latency by using a layer-by-layer stacking engineering technology approach. It can realize radio frequency front-end arrays in the DC to 40GHz band.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array, characterized in that: It includes several layers of rigid silicon-based wafers (1), with an intermediate flexible material wafer (5) between two adjacent rigid silicon-based wafers (1), a rigid glass-based wafer (2) on the uppermost rigid silicon-based wafer (1), an upper flexible material wafer (3) on the uppermost rigid glass-based wafer (2), and a lower flexible material wafer (4) on the lowermost rigid silicon-based wafer (1). A bare chip (6) is provided inside any one or several layers of rigid silicon-based wafer (1), and the position of the bare chip (6) is arranged according to the design requirements of the millimeter-wave on-chip array; The rigid silicon-based wafer (1) has a TSV (7) inside, and the position and number of the TSV (7) are designed according to the vertical transmission requirements of the millimeter-wave on-chip array; The rigid silicon wafer (1) has RDL (8) on both its upper and lower surfaces. The number and position of the RDL (8) are designed according to the planar transmission requirements of the millimeter-wave on-chip array. The rigid silicon-based wafer (1) is provided with IPDs (9) inside, and the position and number of IPDs (9) are arranged according to the circuit design of the millimeter-wave on-chip array; The upper end face, lower end face and interior of the upper flexible material wafer (3) or the lower flexible material wafer (4) are provided with metallization structures (10), and the position and number of the metallization structures (10) are arranged according to the circuit design of the upper flexible material wafer (3) or the lower flexible material wafer (4). The lower end face of the lower flexible material wafer (4) is provided with an interconnect structure (11), and the position and number of the interconnect structure (11) are designed according to the interconnect transmission requirements of the lower flexible material wafer (4). The rigid silicon wafer (1) in the middle layer has a suspended beam structure transmission line (12) inside, which together with the upper flexible material wafer (3) and the lower flexible material wafer (4) forms a suspended beam structure strip line. The position and size of the suspended beam structure transmission line (12) are designed according to the planar transmission requirements inside the rigid silicon wafer (1).

2. The rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to claim 1, characterized in that: The rigid silicon-based wafer (1) achieves the stacking of multiple silicon-based wafers in the Z direction through wafer-level bonding.

3. The rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to claim 1, characterized in that: The rigid glass-based wafer (2) is stacked on the upper surface of the top rigid silicon-based wafer (1) by wafer-level bonding.

4. The rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to claim 1, characterized in that: The upper flexible material wafer (3) and the lower flexible material wafer (4) are stacked on the upper surface of the rigid glass-based wafer (2) and the lower surface of the bottom rigid silicon-based wafer (1) respectively by wafer-level bonding.

5. The rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to claim 1, characterized in that: The form of the interconnect structure (11) includes solder balls, solder pillars or bumps.

6. The rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to claim 1, characterized in that: The rigid glass-based wafer (2) is provided with an air cavity structure (13), which, combined with the upper flexible material wafer (3), can realize a low dielectric constant, low loss, ultra-thin flexible conformal antenna of the air cavity structure (13).

7. The rigid-flexible hybrid three-dimensional wafer architecture millimeter-wave on-chip array according to claim 1, characterized in that: The coefficient of thermal expansion of the lower flexible material wafer (4) is between that of silicon and PCB.

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