Power stage controller

Abstract

The invention relates to a power stage controller. A controller for controlling a power stage having one or more phases is presented. The controller includes: a reference circuit that generates a reference signal; a ramp generator that generates a feedback ramp signal based on a feedback signal of the power stage; and a modulator that generates a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses, where each pulse is associated with a corresponding phase of the power stage.

Description

Technical Field

[0001] The present disclosure relates to controllers for controlling a power stage. In particular, the present disclosure relates to controllers for controlling a constant on-time (COT) converter. Background Art

[0002] Constant on-time switching converters exhibit several advantages over other types of switching converters, including fast transient response, high efficiency at light loads, and smooth transition from continuous conduction mode (CCM) to discontinuous conduction mode (DCM) of operation.

[0003] COT converters can also be implemented with multiple phases, however conventional multi-phase COTs require complex routing signals. This increases the footprint of the power supply and limits system integration. The present disclosure aims to address one or more of the above-mentioned limitations. Summary of the invention

[0004] According to a first aspect of the present disclosure, a controller for controlling a power stage having one or more phases is provided, the controller comprising: a reference circuit suitable for generating a reference signal; a ramp generator suitable for generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator suitable for generating a control signal for controlling at least one phase of the power stage.

[0005] Optionally, the frequency of the feedback ramp signal varies depending on the number of active phases of the power stage.

[0006] Optionally, the control signal comprises a series of pulses, each pulse being associated with a corresponding phase of the power level.

[0007] Optionally, each pulse is associated with an on-time of the corresponding phase.

[0008] Optionally, the modulator comprises: a comparator adapted to compare the feedback ramp signal with a reference signal to obtain a modulation signal;

[0009] a sampling circuit configured to sample the modulation signal and generate a digital modulation signal; a logic circuit configured to generate a control signal based on the digital modulation signal; and an oscillator coupled to the sampling circuit and the logic circuit.

[0010] For example, the sampling circuit may include a first memory device coupled in series to a second memory device. The memory device may be a D flip-flop.

[0011] Optionally, the logic circuit comprises a counter configured to count the duration between consecutive pulses of the control signal.

[0012] Optionally, the logic circuit is configured to encode the digital modulated signal for a specific protocol.

[0013] Optionally, the logic circuit is a state machine. For example, the state machine may be a finite state machine FSM.

[0014] Optionally, the ramp generator includes: a capacitor; a first transconductance amplifier coupled to the capacitor via a first switch; a second transconductance amplifier coupled to the capacitor via a second switch; and a timer configured to control the first switch and the second switch.

[0015] Optionally, the controller comprises a closed-loop operational amplifier.

[0016] Optionally, the controller further comprises a duty cycle estimator configured to estimate a duty cycle of the power stage and a ramp amplitude adjuster configured to adjust the amplitude of the feedback ramp signal based on the estimated duty cycle.

[0017] According to a second aspect of the present disclosure, there is provided a power supply according to the first aspect coupled to a power stage having one or more phases.

[0018] Optionally, the controller is coupled to the power stage via a single-wire interface. For example, the single-wire interface may be a single-wire modulated transmission interface.

[0019] Optionally, the power stage comprises a plurality of phases, each phase comprising a high-side power switch coupled to a low-side power switch at a switching node.

[0020] Optionally, wherein for each phase, the power stage comprises a driver; and wherein the driver comprises a decoder for decoding the control signal.

[0021] Optionally, the decoder is configured to measure a pulse width of each pulse of the control signal and compare the measured pulse width with a predefined pulse width value.

[0022] Optionally, the power supply is a constant on-time converter.

[0023] According to a third aspect of the present disclosure, there is provided a method of controlling a power stage having one or more phases, the method comprising:

[0024] generating a reference signal;

[0025] generating a feedback ramp signal based on a feedback signal of the power stage; and

[0026] A control signal is generated for controlling at least one phase of the power stage.

[0027] Optionally, the control signal is a single control signal.

[0028] Optionally, the method comprises: calculating a duration between consecutive pulses of the control signal; and activating one or more phases if the duration is less than a first threshold; or deactivating one or more phases if the duration is greater than a second threshold.

[0029] The first threshold may be a minimum duration value, and the second threshold may be a maximum duration value. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0031] Figure 1 is a diagram of a conventional constant on-time buck converter;

[0032] Figure 2 is a graph of a ramp voltage varying over time, showing Figure 1 Operation of the converter;

[0033] Figure 3 is a diagram of a conventional multiphase converter;

[0034] Figure 4 It is a diagram for Figure 3 A diagram of a feedback ramp voltage, a reference voltage, a control signal and a state of a high-side power switch for each phase of a multi-phase converter;

[0035] Figure 5 is a flow chart of a method for controlling a power stage according to the present disclosure;

[0036] Figure 6 is a diagram of a power supply according to the present disclosure;

[0037] Figure 7 It's a picture. Figure 6 A diagram of the operation of a power supply;

[0038] Fig. 8A yes Figure 6 A diagram of an exemplary implementation of a controller of;

[0039] Figure 8B is used for Fig. 8A Schematic diagram of an alternative implementation of a ramp generator in a circuit of;

[0040] Figure 8C is used for Fig. 8A A diagram of yet another alternative implementation of a ramp generator in a circuit of;

[0041] Fig.8D is a functional diagram of a state machine used to generate control signals;

[0042] Fig. 8E It's a picture. Fig.8D A graph of the operation of a state machine;

[0043] Fig. 9 The diagram shows Fig. 8A An exemplary implementation of a power stage with two phases for use with a controller of;

[0044] Fig.10 It's a picture. Figure 6 A waveform diagram of the operation of the system;

[0045] Fig.11 is a waveform diagram showing a feedback ramp voltage having two different amplitudes;

[0046] Fig.12 is a graph of normalized ramp amplitude as a function of duty cycle obtained with and without scaling;

[0047] Fig.13 is an exemplary implementation of a duty cycle estimator;

[0048] Fig.14 is a graphic representation of the load transient conditions during Figure 6 A diagram of the operation of the circuit;

[0049] Fig.15 is shown during a load transient Figure 6 A graph of the output voltage, the inductor current of each phase and the switching period of the circuit;

[0050] Fig.16 It shows Figure 6 Graphs of the feedback ramp signal, sampling clock signal, modulation signal, and control signal of the circuit. DETAILED DESCRIPTION

[0051] Figure 1 1 is a diagram of a conventional constant on-time (CoT) buck converter. The converter 100 includes a high-side power switch S1, a low-side power switch S2, an inductor L, a driver 110, and an output regulation loop for regulating the output voltage of the converter. The output regulation loop includes a circuit for generating a feedback ramp signal V RAMP The ramp generator 120 and the pulse modulation PWM comparator 130 are provided. The pulse modulation PWM comparator 130 has a first input terminal for receiving a reference signal Vref, a first input terminal for receiving a feedback ramp voltage V RAMP and coupled to an output terminal of the driver 110.

[0052] Figure 2 It's a picture. Figure 1The top waveform shows the feedback reference voltage, and the bottom waveform shows the state of switch S1 (on or off). In operation, when the feedback ramp voltage V RAMP When (=Vout+ramp) reaches Vref, comparator 130 sends a logic high to driver 110. Driver 110 then turns on high-side switch S1 for a fixed duration D*T (where D is the duty cycle and T is the switching period), hence the name "constant on-time switching converter". When the fixed duration ends, driver 110 turns off switch S1 and turns on switch S2. The output voltage is regulated to D*Vin, where Vin is the supply voltage. The on-time of S1 is predetermined and it turns off once the predetermined time is reached. To handle larger output loads, a common technique is to use multiple power stages in parallel.

[0053] Figure 3 3 is a diagram of a conventional multiphase converter. Multiphase converter 300 illustrates a four-phase buck converter having four phases coupled in parallel. For clarity, only two phases, labeled 310 and 340, are presented.

[0054] Each phase includes a high-side power switch coupled to a low-side power switch at a switch node, an inductor coupled to the switch node, and a driver U for driving the high-side power switch and the low-side power switch. Each phase includes independent control and feedback. A controller 305 is provided to generate four control signals CNTL1-CNTL4 for controlling the drivers U1-U4 respectively. Therefore, for each phase, there is a separate ramp signal V RAMP 1-V RAMP 4 derived separate control signals.

[0055] A further controller (not shown) is required to ensure proper operation, for example for providing load balancing and phase control.Each converter of the multi-phase converter may be implemented as a CoT buck converter.

[0056] Figure 4 It is a diagram for Figure 3 Graph of the feedback ramp voltage, reference voltage, control signal, and state of the high-side power switch for each phase of a multi-phase converter.

[0057] The four phases are operated out of phase with each other, although under dynamic load (transient) conditions, the phases can be operated in phase. Each phase is controlled by a separate ramp signal that determines the ON and OFF states of the power switch. When the ramp voltage is equal to the reference voltage, a control signal is generated to turn on the power transistor. Once in the on state, the power transistor will remain on for a predefined fixed on time (CoT).

[0058] Figure 3 The converter requires a separate control signal for each phase (to turn each phase on and off) and a separate feedback ramp signal. This increases the system footprint (e.g., routing signal traces) and susceptibility to noise and reduces system integration.

[0059] Figure 3 Converters can also be limited by thermal instability. Using different control and feedback signals for each phase poses challenges to on-time balancing of each phase as well as load balancing. If the output current in each phase is unbalanced, this can lead to thermal instability and reduced reliability.

[0060] Figure 5 4 is a flow chart of a method for controlling a power level according to the present disclosure. The method includes steps 510 to 530.

[0061] At step 510, a reference signal is generated. The reference signal Vref may be selected to be the desired output voltage, ie, the converter operates such that Vout = Vref.

[0062] At step 520, a feedback ramp signal is generated based on a feedback signal of the power stage. At step 530, a control signal for controlling at least one phase of the power stage is generated.

[0063] For example, the power stage may include multiple phases, and the control signal is configured to control all phases of the power stage.

[0064] Figure 6 6 is a diagram of a power supply according to the present disclosure. The power supply or converter 600 includes a controller 605 coupled to a power stage including four phases coupled in parallel. For clarity, only two phases, labeled 610 and 640, are presented. It should be understood that the number of phases may be increased or decreased depending on the application. The controller 605 is coupled to each phase of the power stage via a single connection divided into several branches (one branch for each phase of the power stage).

[0065] Each phase includes a high-side power switch coupled to a low-side power switch at a switch node, an inductor coupled to the switch node, and a driver U for driving the high-side power switch and the low-side power switch. Each driver also includes a decoder for decoding a control signal. For example, the driver U1 of phase 610 includes a decoder D1. Similarly, the driver U4 of phase 640 includes a decoder D4.

[0066] The controller 605 is adapted to provide a single feedback ramp signal V RAMP Therefore, no separate feedback ramp signal is required for each phase.

[0067] The architecture of Power Supply 600 is scalable from single phase to multi-phase. It can be used to increase power density and simplify system integration.

[0068] Figure 7 It's a picture. Figure 6 A diagram of the operation of a power supply. Figure 7 A ramp voltage 710, a reference voltage 720, and a control signal 730 are shown. The state of the high-side power switch of each phase (on or off) is also presented. The state of the high-side power switch S1 of the first phase is represented by a waveform 740. The state of the high-side power switch S3 of the second phase is represented by a waveform 750. The state of the high-side power switch S5 of the third phase is represented by a waveform 760. The state of the high-side power switch S7 of the fourth phase is represented by a waveform 770.

[0069] In operation, the controller 605 generates a single control signal 730 to start the conduction state of all phases (1 to n, in this example, n=4). The control signal 730 is formed by a plurality of pulses. In this example, pulses T1, T3, T5, and T7 are used to switch high-side power switches S1, S3, S5, and S7, respectively. The pulses directed to a specific phase may have a specific pulse width. Therefore, pulses T1, T3, T5, and T7 may have different pulse widths.

[0070] Each driver receives the same control signal 730, and then the decoder present in the driver decodes the control signal to pass only the relevant pulses. For example, decoder D1 passes pulse T1 directed to power switch S1 and blocks other pulses T3, T5 and T7. Similarly, decoder D4 passes pulse T7 directed to power switch S7 and blocks other pulses T1, T3 and T5.

[0071] To identify relevant pulses, the decoder can measure the pulse width of each pulse received and then compare the measured pulse width with a predefined pulse width value. If the pulse width is equal to the predefined value, the pulse is passed, otherwise the pulse is blocked. The decoder can be implemented in various ways using analog or digital circuit systems.

[0072] For n (n is any possible number) phase n drivers, power converter 600 uses a single-wire modulation transmission interface (SWMTI) to transmit control signals through a single wire. This method minimizes the need for other communications between controller 605 and the driver. Controller 605 only needs to be connected to the power input voltage and output voltage of the converter, without being connected to the switch node. Power converter 600 automatically optimizes its operation for any possible operating duty cycle. For example, the slope of the ramp can be adjusted for operating conditions.

[0073] Fig. 8A Picture shows Figure 6An exemplary implementation of a controller of . The controller 800 has several input ports for receiving an input voltage VIN, a feedback signal FB from a power converter, and optionally a total average current from all phases. It also includes an output port for communicating with a multi-phase power stage via a single-wire modulation transmission interface (SWMTI). The signal FB can be equal to VOUT. Alternatively, the feedback signal can vary depending on VOUT, for example, FB can be defined as FB=Vout-X or FB=Vout / X, where X is a constant value.

[0074] The controller 800 includes a reference circuit 810 for generating a reference signal, a ramp generator 820 for generating a feedback ramp signal, and a modulator 830 adapted to generate control signals for controlling a plurality of drivers of a multi-phase power stage.

[0075] Reference circuit 810 includes feedback circuit 812 coupled to compensator circuit 814. Feedback circuit 812 has a DAC for generating a compensated reference signal Vref_comp. Compensator circuit 814 includes a transconductance amplifier having a first input for receiving signal Vref_comp and a second input for receiving feedback signal FB. The output of reference circuit 810 is a reference voltage Vref.

[0076] The modulator 830 includes a comparator 832, two D flip-flops 833a and 833b coupled in series, an oscillator 834, and a logic circuit 835 for generating a control signal. The comparator 832 has a first input terminal for receiving a reference signal Vref, a second input terminal for receiving a feedback ramp signal V RAMP and for providing a modulated signal V to the D input terminal of the first flip-flop 833a. MOD When Vref>V RAMP When V MOD is high (logic 1), otherwise V MOD is low (logic 0).

[0077] Comparing the ramp signal Vramp directly to Vref can cause some inaccuracy in the DC output voltage. Therefore, a small correction is added using the transconductance amplifier and the Rc Cc network of circuit 814 to compensate for this small error. However, this is not always necessary and Vref can be fed directly at the Vcomp node.

[0078] D flip-flops 833a and 833b form a sampling circuit. It is used to sample the modulated signal V MODThe digital modulated signal is sampled and provided at the input of the logic circuit 835. The logic circuit 835 may be a state machine configured to encode a digital version of the modulated signal for a particular protocol. Different protocols may be associated with different algorithms implemented by the state machine. The logic circuit 835 may also include a cycle counter (not shown) to count the control signal (see Figure 7 The duration or period between successive pulses of the control signal 730).

[0079] The counter measures the time between two switchings of the comparator output signal Vmod. The output of the logic circuit 835 is the control signal S_cont.

[0080] The ramp generator 820 includes two transconductance amplifiers gm1 and gm2. Each transconductance amplifier is coupled to a common node A via corresponding switches M1 and M2, respectively. The first transconductance amplifier gm1 receives an input voltage VIN and a feedback voltage FB. The second transconductance amplifier gm2 receives the feedback voltage FB and ground. A capacitor Cf having a first terminal coupled to the feedback voltage FB and a second terminal coupled to the node A is provided.

[0081] A closed loop operational amplifier 822 is provided having a non-inverting input coupled to the feedback shifter of circuit 810 and an inverting input coupled in a closed loop manner to the amplifier output. The output of amplifier 822 is coupled to node A via resistor Rf.

[0082] The output impedance of the closed loop amplifier 822 can be high, but less than Rf. A fast feedback path is provided by Cf. The closed loop amplifier 822 is used to place the feedback ramp average voltage at a desired level. The closed loop amplifier 822 is used to set the average voltage of the ramp. If the range of the ramp is between Va (valley) and Vb (peak), the peak to peak is Vb-Va. The amplitude can refer to peak to peak, and the average value or average amplitude can refer to (Vb-Va) / 2. Therefore, the desired level of the feedback ramp average voltage is referred to here as the average value (Va+Vb) / 2.

[0083] The ramp generator 820 also includes a timer 824 for controlling the switches M1 and M2.

[0084] Figure 8B is used for Fig. 8A Another ramp generator in the circuit.

[0085] This is a simpler implementation that provides a fast feedback path, but in this case the ramp average voltage is close to the output voltage.

[0086] Figure 8C Shown for Fig. 8AA closed loop amplifier allows the ramp average voltage to be placed where desired. However, the closed loop amplifier has a low output impedance.

[0087] In operation, the logic circuit 835 sends a signal to the timer 824, which in turn controls the operation of the switches M1 and M2. When M1 is turned on and M2 is turned off, the first transconductance amplifier gm1 is activated and the capacitor Cf is charged. When M2 is turned on and M1 is turned off, the second transconductance amplifier gm2 is activated and the capacitor Cf is discharged. The charging and discharging of the capacitor Cf causes the feedback ramp voltage V RAMP .

[0088] The timer circuit 824 is configured to calculate the on-time of the power supply for all phases: TON_ideal. For example, if the power supply has four phases, TON_ideal = TON_phase1 = TON_phase2 = TON_phase3 = TON_phase4. The TON of each independent phase can be different, but in most cases, they will be the same or similar. TON_ideal is based on the input voltage VIN and output voltage VOUT of the power supply that satisfy the following equation: TON_ideal = Tsw VOUT / VIN, where Tsw is the desired switching period of the power switch. The switching period of M1 and M2 is determined by TON_ideal divided by the number of active phases of the power supply. For example, if TON_ideal = 100ns and the power supply has 1 phase, the switching period is 100ns. If the power supply has 4 phases that are all activated, the switching period is 25ns. If the power supply has 4 phases but only two are activated, the switching period is 50ns. The on-time of the ramp is TON_Ideal / the number of phases.

[0089] Thus, the feedback ramp voltage is fed back N times faster than in the prior art, where N represents the number of phases (in this numerical example, 4 times faster). This allows a single control signal to be used to control all phases.

[0090] Optionally, the logic circuit 835 can be connected to a current measurement circuit 860 having an input for receiving the total output average current I_avg_total of all phases. The provided current measurement circuit 860 can be implemented in different ways, for example as an analog-to-digital converter or a set of comparators.

[0091] Optionally, the controller 800 may further include a ramp amplitude adjuster 840 coupled to the duty cycle estimator 850 for adaptively adjusting the amplitude of the feedback ramp signal. In operation, the ramp amplitude adjuster 840 receives the duty cycle from the duty cycle estimator 850 and changes the transconductances gm1 and gm2 to adjust the amplitude of the ramp signal.

[0092] Fig.8D 8 is a functional diagram of a state machine for generating control signals. As mentioned above, the logic circuit 835 can be implemented as a state machine (such as a finite state machine FSM). Verilog is used as a hardware description language for reference. For example, 3'b010 means binary 010 (using 3 bits).

[0093] Fig. 8E It's a picture. Fig.8D 834, the modulation signal VMOD provided by the comparator 832, the output of the D flip-flops 833a and 833b, the FSM state, the control signal S_cont and the waveform of the phase (0, 1, 2 or 3).

[0094] Fig. 9 The diagram shows Fig. 8A The power stage 900 is also referred to as a dual power stage DPU.

[0095] The first phase is provided with a driver 910 and the second phase is provided with a driver 920. Each driver is implemented in a similar manner. Driver 910 includes a logic circuit 912, which is coupled to an oscillator OSC, a zero current detector ZCD, a low-side sensor LS: Isns, a conduction time calculator Ton and optionally an average current sensor Iavg. The conduction time calculator can be configured to generate a slope for charging capacitor C with current (Vin-Vout) / R. The slope starts from 0 at the beginning of the conduction time, and the slope reaches Vout at the ideal Ton. The voltage comparator can compare the slope with Vout and will switch at the end of the conduction time.

[0096] The low-side sensor LS: Isns is configured to measure the current through the low-side switch. The logic circuit 910 includes a decoder (not shown) for decoding the control signal received via the single-wire modulation transmission interface (SWMTI). The output of each average current sensor is combined to generate the total average current I_avg_total. It should be understood that the topology of the circuit 900 can be extended to N (any number) phases.

[0097] Fig.10 It's a picture. Figure 6 The operating waveform of the power supply. Fig.10 The inductor currents 1011, 1012, 1013 and 1014 of the first phase, the second phase, the third phase and the fourth phase are shown respectively; the control signals with pulses: 1021 for the first phase, 1022 for the second phase, 1023 for the third phase and 1024 for the fourth phase; the feedback ramp signal 1030; the reference signal 1040 (the positive input received by the comparator 832) and the modulation signal VMOD 1050.

[0098] The control signal 1020 shows that the on-time of each phase can be equally divided based on the number of phases, thus improving the stability and reliability of the power converter. Using a single control signal for all phases helps with phase balancing.

[0099] Fig.11 is a graph showing the feedback ramp voltage V before and after amplitude adjustment RAMP The duty cycle has a significant effect on the ramp voltage. Different applications have different duty cycle ranges. A small ramp amplitude voltage provides better transient performance but increases noise sensitivity. The converter may also become unstable when the ramp amplitude voltage is too small. When the ramp amplitude voltage is large, the converter is stable but may become noisy. By adaptively adjusting the ramp amplitude signal based on the duty cycle, the performance of the converter can be improved.

[0100] Fig.12 12 is a graph of normalized ramp amplitude as a function of duty cycle obtained without scaling (waveform 1210) and with scaling (waveform 1220). The peak-to-peak value of the ramp normalized to a 0.5 duty cycle gives a value of 1. By varying gm1 and gm2 according to the ideal duty cycle of the converter, the ramp amplitude is maintained within a relatively small range around the desired amplitude level. Different duty cycle threshold levels are used at points 1-8 to adjust gm1 and gm2. The amplitude adjuster can be a state machine configured to adjust gm1 and gm2 at different duty cycle threshold levels. Both transconductances gm1 and gm2 are changing at the same ratio, i.e., a change of 0.5 would mean gm1 is divided by 2 and gm2 is divided by 2.

[0101] Fig.13 An exemplary embodiment of a duty cycle estimator for estimating an ideal duty cycle of a converter is provided.

[0102] Circuit 1300 is an integrator 1310 coupled to a comparator 1320, a sampling circuit 1330, and a DAC 1340. In operation, the integrator 1310 integrates the error between the output voltage Vout and the modulation average. The comparator 1320 compares the changes, and the output of 1320 is sampled via 1330 and fed back to the DAC 1340. The 1-bit wide sampled comparator output also feeds a digital low pass filter 1350, which accumulates the 1-bit modulation and gives an 8-bit value.

[0103] Fig.14 is a graphic representation of the load transient conditions during Figure 6 Schematic diagram of the operation of a circuit. In steady state, one phase operates out of phase with the other phases. When a load transient occurs, for example, when the load changes from minimum load to maximum load, multiple phases may be turned on simultaneously and instantaneously in response to the increased load. However, Figure 6 The circuit uses a single control signal that turns on the phases in series, such as Figure 7 As shown in the figure.

[0104] Fig.14 835. A flow chart of a method for improving transient response using a single control signal. A cycle counter of logic circuit 835 counts the duration (or period) between consecutive pulses of the control signal. If the period / duration is too short (e.g., less than a first threshold), all phases are activated. If the period / duration is too long (e.g., greater than a second threshold), only one phase is maintained and the other phases are deactivated. If the period / duration is within a desired range (e.g., between a first threshold and a second threshold), a fast reaction is not required. Information for activating or deactivating one or more phases may be encoded in control signal 730 by logic 835.

[0105] Fig.15 It shows the load transient period. Figure 6 A graph of the operation of the circuit. Fig.15 The output voltage Vout 1510 of the converter; the inductor currents 1521 , 1522 , 1523 , 1524 for the first phase, the second phase, the third phase, and the fourth phase, respectively; and the counted number of switching cycles Tsw 1530 are shown.

[0106] Prior to time t1, the converter operates in steady state using a single phase (Phase 3) with an associated stable phase switching cycle. After time t1, the converter enters a transient load condition. The switching cycle decreases and becomes shorter than the steady state switching cycle. In turn, the other phases are sequentially activated (Phase 4, then Phase 1, then Phase 2) such that all phases are activated.

[0107] Fig.16 It's a picture. Figure 6Another waveform diagram of the operation of the system. Fig.16 A feedback ramp signal 1610 , a reference signal 1620 , a sampling clock signal 1630 , a modulation signal VMOD 1640 , and a control signal 1650 are shown.

[0108] The modulation signal VMOD is sampled by D flip-flops 833a and 833b so that the switching frequency is known with an accuracy defined by the sampling period (i.e., the duration of pulses T1, T3, T5, T7 of 730). High frequency sampling (oversampling) of the voltage difference between the compensation signal Vcomp=Vref and the ramp signal Vramp prevents bus congestion and allows proper bus arbitration.

[0109] The controller of the present specification has been described for use with a buck COT converter, however, it should be understood that the controller may also be used with a boost COT converter.

[0110] The skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the present disclosure. Therefore, the above description of specific embodiments is provided by way of example only and not for the purpose of limitation. The skilled person should be aware that minor modifications may be made without significantly changing the described operations.

Claims

1. A controller for controlling a power stage, the power stage having one or more phases, the controller comprising: a reference circuit adapted to generate a reference signal; a ramp generator adapted to generate a feedback ramp signal based on a feedback signal of the power stage; as well as A modulator is adapted to generate a control signal for controlling at least one phase of the power stage. 2 . The controller of claim 1 , wherein a frequency of the feedback ramp signal varies depending on the number of active phases of the power stage.

3. The controller of claim 1, wherein the control signal comprises a series of pulses, each pulse being associated with a corresponding phase of the power stage.

4. The controller of claim 3, wherein each pulse is associated with an on-time of the corresponding phase.

5. The controller of claim 1 , wherein the modulator comprises: a comparator, the comparator being adapted to compare the feedback ramp signal with the reference signal to obtain a modulation signal; a sampling circuit, the sampling circuit being configured to sample the modulation signal and generate a digital modulation signal; a logic circuit configured to generate the control signal based on the digital modulation signal; as well as An oscillator is coupled to the sampling circuit and the logic circuit. 6 . The controller of claim 5 , wherein the logic circuit comprises a counter configured to count the duration between successive pulses of the control signal.

7. The controller of claim 5, wherein the logic circuit is configured to encode the digital modulated signal for a specific protocol.

8. The controller of claim 1, wherein the logic circuit is a state machine.

9. The controller of claim 1 , wherein the ramp generator comprises: Capacitors; a first transconductance amplifier coupled to the capacitor via a first switch; a second transconductance amplifier coupled to the capacitor via a second switch; as well as A timer is configured to control the first switch and the second switch.

10. A controller according to claim 9, comprising a closed loop operational amplifier.

11. The controller of claim 1 , further comprising a duty cycle estimator configured to estimate a duty cycle of the power stage and a ramp amplitude adjuster configured to adjust an amplitude of the feedback ramp signal based on the estimated duty cycle.

12. A power supply comprising the controller of claim 1 coupled to a power stage having one or more phases.

13. The power supply of claim 12, wherein the controller is coupled to the power stage via a single-wire interface.

14. The power supply of claim 12, wherein the power stage comprises a plurality of phases, each phase comprising a high-side power switch coupled to a low-side power switch at a switch node.

15. The power supply of claim 14, wherein for each phase, the power stage comprises a driver; and wherein the driver comprises a decoder for decoding the control signal. 16 . The power supply of claim 15 , wherein the decoder is configured to measure a pulse width of each pulse of the control signal and compare the measured pulse width with a predefined pulse width value.

17. The power supply of claim 12, wherein the power supply is a constant on-time converter.

18. A method of controlling a power stage, the power stage having one or more phases, the method comprising: generating a reference signal; generating a feedback ramp signal based on a feedback signal of the power stage; as well as A control signal is generated for controlling at least one phase of the power stage. The method of claim 18 , wherein the control signal is a single control signal.

20. The method according to claim 18, comprising: calculating the duration between consecutive pulses of the control signal; as well as If the duration is less than a first threshold, activating one or more phases; or If the duration is greater than a second threshold, one or more phases are deactivated.

Images