A charge amplifier structure and method of using the same

Abstract

The application relates to the field of charge detection reading, and discloses a charge amplifier structure and a use method thereof, which comprises: an amplification unit for receiving a to-be-identified charge signal output by a detector and amplifying the received to-be-identified charge signal to obtain an amplified signal of the to-be-identified charge signal; a peak sampling and holding circuit for collecting a peak voltage signal of the amplified signal output by the amplification unit and storing the peak voltage signal in a capacitor; a feedback circuit for feeding back the peak voltage signal collected by the peak sampling and holding circuit to a reference voltage end of the amplification unit to form a new baseline of the amplification unit; and a reset signal unit for obtaining a trigger signal of the charge signal after processing the amplified signal output by the amplification unit, and obtaining a reset signal of the amplification unit and the peak sampling and holding circuit after processing the trigger signal. The application solves the problems that a traditional charge amplifier cannot continuously integrate a slowly-drifting charge and cannot continuously superimpose collected charge peaks.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of charge detection readout, in particular to a novel charge amplifier structure for readout of continuous integration input charge and a method of using the same. BACKGROUND

[0002] In the application of nuclear detectors, the main function of the detector is to detect radioactive substances and their physical properties through interaction with radiation, particles or other radiation. These interactions will produce different types of signals in the sensitive material of the detector, usually in the form of electric charge, which may be electron-hole pairs or ion charges, depending on the material and working principle of the detector. For example, in semiconductor detectors, particles passing through the material will excite electrons and holes, and because the electron mobility of the semiconductor material is high, these charge carriers can quickly drift in the electric field, thus producing a signal with a fast rise time, while in gas detectors, the interaction will produce slow-drifting ions and free electrons. These different types of charge signals reflect key information such as particle energy and position, and are the basis for subsequent signal processing. In the weak signals produced by the detector, the amount of charge produced by nuclear radiation is usually very small, and the signal is easily disturbed by noise, and direct processing of these signals will face significant challenges. At this time, the charge amplifier, especially the charge amplifier, plays a key role as the first stage in the signal chain. Its main function is to convert the weak charge signal produced by the detector into a voltage signal that is easy to measure and process, while maintaining the integrity and accuracy of the signal as much as possible. The charge amplifier needs to have very high sensitivity and low noise characteristics to ensure that these important physical information can be accurately extracted and amplified, laying a solid foundation for subsequent signal analysis.

[0003] The signal width of different nuclear detectors is quite different, and the integration time of the charge amplifier is different. The existing charge amplifier integration time is not more than a few milliseconds, which cannot meet the demand of extremely slow charge signal, especially in the case of long-time integration of slow drift ion charge, there are many limitations. The existence of this problem seriously limits the reliability and applicability of the charge amplifier in high-precision nuclear detection applications. Based on this, the present application proposes a new type of charge amplifier, which is specially used for continuous integration of input charge. The charge amplifier can dynamically adjust the baseline of the charge amplifier according to the peak value of the collected signal by introducing an adaptive feedback control mechanism, realizes the function of continuously superimposing and self-resetting the collected charge peak value, thereby effectively solving the limitation problem that the integration time of the existing charge sensitive amplifier can only reach a few milliseconds. In addition, the new type of charge amplifier can not only accurately amplify the instantaneous electron-hole pair signal, but also effectively process the slower drift ion signal. These technical improvements greatly improve the ability of the charge amplifier to deal with different types of signals in the nuclear detector, and the integrity and accuracy of the signal are significantly improved. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a charge amplifier structure and its use method, which effectively solves the difficulty that the traditional charge amplifier cannot continuously integrate the charge with slow drift speed and cannot continuously superimpose the collected charge peak value.

[0005] To achieve the above purpose, the present application adopts the following technical scheme: a charge amplifier structure, comprising:

[0006] An amplification unit is used to receive the to-be-identified charge signal output by the detector, and amplify the received to-be-identified charge signal to obtain an amplified signal of the to-be-identified charge signal;

[0007] A peak sampling and holding circuit is used to collect the peak voltage signal of the amplified signal output by the amplification unit and store it in a capacitor;

[0008] A feedback circuit is used to feed back the peak voltage signal collected by the peak sampling and holding circuit to the reference voltage end of the amplification unit to form a new baseline of the amplification unit;

[0009] A reset signal unit is used to process the amplified signal output by the amplification unit to obtain a trigger signal of the charge signal, and process the trigger signal to obtain a reset signal of the amplification unit and the peak sampling and holding circuit.

[0010] Further, the amplification unit includes a first amplifier AMP1, a feedback capacitor C f , a feedback field effect tube Q1, a baseline holder and a first reset switch S1;

[0011] The output end of the detector is connected with the input end of the first amplifier AMP1, and the charge signal to be identified is input into the first amplifier AMP1. The input end of the first amplifier AMP1 is also connected with the first end of the feedback capacitor C f , the drain of the feedback field effect transistor Q1, the output end of the baseline holder, and the first end of the first reset switch S1. The output end of the first amplifier AMP1 is connected with the second end of the feedback capacitor C f , the source of the feedback field effect transistor Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit, and the input end of the reset signal unit.

[0012] Further, the peak sampling and holding circuit comprises a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2, and a voltage buffer.

[0013] The non-inverting terminal of the second amplifier AMP2 is connected with the output end of the first amplifier AMP1 in the amplifying unit. The output end of the second amplifier AMP2 is connected with the anode of the diode. The cathode of the diode is connected with the inverting terminal of the second amplifier AMP2, so as to lift the voltage drop caused by the diode.

[0014] The cathode of the diode is also connected with one end of the second reset switch S2, one end of the first capacitor C1, and the input end of the voltage buffer. When the diode is turned on, the peak voltage is collected.

[0015] The other end of the first capacitor C1 is connected with the other end of the second reset switch S2 in parallel and then grounded. The first capacitor C1 is used for storing the collected peak voltage. The second reset switch S2 is used for discharging the voltage stored in the first capacitor C1.

[0016] The output end of the voltage buffer is connected with the feedback circuit and outputs a voltage signal, which is used for maintaining the signal output by the peak sampling and holding circuit and enhancing the driving capability of the circuit.

[0017] Further, the second amplifier AMP2 adopts a two-stage operational amplifier or a folded common-source and common-gate amplifier.

[0018] Further, the reset signal unit comprises a comparator, an integration circuit, and a monostable circuit.

[0019] The non-inverting terminal of the comparator is used for receiving the output signal of the amplifying unit. The inverting terminal of the comparator is provided with a threshold voltage by an off-chip DAC. The output end of the comparator is connected with the input end of the monostable circuit and the input end of the integration circuit.

[0020] The output end of the integration circuit is connected with the monostable circuit, which is used for outputting a voltage signal proportional to the pulse width of the trigger signal.

[0021] The output signal of the monostable circuit is used for switching reset of the amplification unit and the peak sampling and holding circuit.

[0022] Further, the monostable circuit comprises a NOR gate, an inverter, a second field effect transistor Q2 and a second capacitor C2.

[0023] The first input terminal of the NOR gate is connected with the output terminal of the comparator, the output terminal of the NOR gate is connected with the second capacitor C2 and the input terminal of the inverter in sequence, and the second input terminal of the NOR gate is connected with the output terminal of the inverter in parallel as the output terminal of the monostable circuit.

[0024] The gate of the second field effect transistor Q2 is connected with the output terminal of the integration circuit, the drain of the second field effect transistor Q2 is connected in parallel between the second capacitor C2 and the input terminal of the inverter, and the source is connected to the analog power supply.

[0025] Further, the baseline holder comprises a third capacitor C3 and seven field effect transistors: a third field effect transistor Q3 to a ninth field effect transistor Q9.

[0026] The third field effect transistor Q3 is a bias current source, the source of which is connected to the analog power supply AVDD, the gate of which receives a bias voltage Vbias, and the drain of which is connected with the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5.

[0027] The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected to form a pair of differential pairs, the gate of the fourth field effect transistor Q4 is connected with the output terminal of the feedback circuit as the reference voltage terminal CSA_Vref of the baseline holder, the drain of the fourth field effect transistor Q4 is connected with the input terminal of the amplification unit, and the gate of the fifth field effect transistor Q5 is connected with the output terminal of the amplification unit as the input terminal of the baseline holder.

[0028] The drain of the sixth field effect transistor Q6 is connected with the drain of the fourth field effect transistor Q4, the source is grounded, and the gate is connected to the drain of the fifth field effect transistor Q5 in parallel with one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded.

[0029] The seventh to ninth field effect transistors Q7-Q9 are connected as a current mirror, and the drain current of the fifth field effect transistor Q5 is integrated to the third capacitor C3 to generate a voltage to control the gate of the sixth field effect transistor Q6.

[0030] Further, the feedback circuit is a resistor, one end of which is connected with the output terminal of the peak sampling and holding circuit, and the other end of which is connected to the reference voltage terminal of the baseline holder.

[0031] Further, the feedback circuit is a unit gain voltage buffer; the non-inverting terminal of the unit gain voltage buffer is connected to the output terminal of the peak sample and hold circuit, and the inverting terminal and the output terminal are connected to the reference voltage terminal of the baseline holder.

[0032] A use method based on the charge amplifier structure, comprising:

[0033] Transmit the to-be-identified charge signal output by the detector to the amplification unit to obtain an amplified signal of the to-be-identified charge signal;

[0034] Input the amplified signal into the peak sample and hold circuit to obtain a peak voltage signal, and feed back the peak voltage signal to the reference voltage terminal of the amplification unit by the feedback circuit to form a new baseline of the amplification unit;

[0035] Input the amplified signal output by the amplification unit into the reset signal unit to obtain a reset signal of the amplification unit and the peak sample and hold circuit.

[0036] The present application has the following advantages due to the above technical solutions:

[0037] 1. The present application adopts a feedback circuit, an integration circuit and a monostable circuit, can adaptively adjust the integration time, and the integration time range can be from tens of nanoseconds to several seconds, thereby meeting the physical experiment requirements.

[0038] 2. The amplification unit of the present application is used for amplifying the charge signal from the detector. The peak voltage signal collected by the peak sample and hold circuit is fed back to the reference voltage terminal of the amplification unit through the feedback circuit, can superimpose and generate the amplitude information representing the energy on the continuously integrated charge peak value. Then, the reset signal of the amplification unit and the peak sample and hold circuit is obtained through the reset signal unit. The problem that the traditional charge amplifier cannot continuously integrate the slowly drifting charge and cannot continuously superimpose the collected charge peak value is effectively solved. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is the overall structure schematic diagram of the charge amplifier structure in the embodiment of the present application;

[0040] Figure 2 is the peak sample and hold circuit structure schematic diagram in the embodiment of the present application;

[0041] Figure 3 is the reset signal unit structure schematic diagram in the embodiment of the present application;

[0042] Figure 4 is the baseline holder structure schematic diagram in the embodiment of the present application;

[0043] Figure 5 is the feedback circuit structure schematic diagram in the embodiment of the present application;

[0044] Figure 6 is a readout timing diagram in an embodiment of the present application;

[0045] Figure 7 is a flow chart of a method for using the charge amplifier structure in an embodiment of the present application. DETAILED DESCRIPTION

[0046] A charge amplifier is a key electronic device used in the fields of nuclear physics, particle physics, medical imaging, and other radiation detection. Its main role is to amplify the weak charge signals output by the detector (such as semiconductor detectors, gas detectors, scintillators, etc.) so that the subsequent electronic system can more effectively process these signals. The charge signals generated by the detector after receiving radiation are usually very weak and insufficient to be directly processed by the subsequent electronic system. The charge amplifier converts these weak charge signals into larger voltage signals through gain action. The signal width of nuclear detectors varies greatly among different types of detectors, mainly depending on the working principle of the detector and their response mode to nuclear radiation, so the requirements for the integration time of the charge amplifier are very different. At the same time, the integration time of the charge amplifier cannot exceed a few milliseconds, which cannot meet the measurement of extremely slow signals represented by ion time projection chamber.

[0047] For example, the time projection chamber gas detector can measure the three-dimensional position information and energy information of the charged particles at the same time. It contains a cylindrical chamber, which is filled with a specific working gas. In the middle of the chamber, there is a high-voltage electrode plate, and at both ends, there are end caps. When the charged particles pass through the chamber, ionization tracks are formed in the gas, generating ionization electrons. These electrons drift towards the end cap under the push of the electric field force. By measuring the drift time and velocity of the charge through the readout electronics located at the end cap, the position of the particle along the cylindrical direction can be determined. If the time projection chamber is filled with non-electrically negative gas, such as argon or helium, when the particle passes through the detector, it interacts with the gas molecules to produce electron-ion pairs. Since the electrons are not quickly captured by the gas molecules, they can freely drift in the electric field, forming a particle track, and the integration time of the charge signal requires microsecond level. If the time projection chamber uses electrically negative gas as the working medium, such as sulfur hexafluoride (SF6) or its mixture with rare gas, this type of TPC shows great potential in the neutrinoless double beta decay experiment, for example, in NvDEx (Neutrinoless Double Beta Decay Experiment), it uses the characteristics of electrically negative gas to improve the performance of the detector. In the electrically negative gas TPC, due to the affinity of the electrically negative gas to the electron, when the charged particle interacts with the gas molecules to produce electrons, it will quickly combine with the gas molecules to form negative ions. This feature enables the electrically negative gas TPC to integrate the charge signal for a long time, which is very useful for measuring low-energy particles or applications that require long-time integration, and the time width of the charge integration reaches hundreds of milliseconds to several seconds.

[0048] In order to meet the requirements of different detector signals from tens of nanoseconds to several seconds of integration time, while solving the limitation that the existing charge sensitive amplifier integration time can only reach several milliseconds, the present application provides a charge amplifier structure and its use method to support integration time from tens of nanoseconds to several seconds, which includes: an amplification unit for receiving a charge signal and amplifying the received to-be-identified charge signal to obtain an amplified signal of the to-be-identified charge signal; a peak sampling and holding circuit for collecting the peak signal of the amplification unit and storing it in a capacitor; a feedback circuit for feeding back the peak voltage signal collected by the peak sampling and holding circuit to the reference voltage end of the amplification unit to form a new baseline of the amplification unit; and a reset signal unit for processing the signal output by the amplification unit to obtain a trigger signal of the charge signal, and processing the trigger signal to obtain a reset signal of the readout circuit. The present application can be applied in the field of charge detection.

[0049] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the described embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0050] It should be noted that the terms used herein are only intended to describe specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise, and furthermore, it should be understood that when the terms "comprise" and / or "include" are used in the specification, there is a presence of the features, steps, operations, devices, components and / or combinations thereof.

[0051] In one embodiment of the present application, a charge amplifier structure is provided. In the embodiment, as shown in FIG. 1, the charge amplifier structure comprises: Figure 1

[0052] an amplification unit, configured to receive a to-be-identified charge signal output by a detector, and amplify the received to-be-identified charge signal to obtain an amplified signal of the to-be-identified charge signal;

[0053] a peak sampling and holding circuit, configured to collect a peak voltage signal of the amplified signal output by the amplification unit, and store the peak voltage signal in a capacitor;

[0054] a feedback circuit, configured to feed back the peak voltage signal collected by the peak sampling and holding circuit to a reference voltage end of the amplification unit, to form a new baseline of the amplification unit;

[0055] a reset signal unit, configured to obtain a trigger signal of the charge signal after processing the amplified signal output by the amplification unit, and obtain a reset signal of the amplification unit and the peak sampling and holding circuit after processing the trigger signal.

[0056] In the above embodiment, the amplification unit comprises a first amplifier AMP1, a feedback capacitor C f , a feedback field effect transistor Q1, a baseline holder and a first reset switch S1. The first amplifier AMP1 can be a single-ended folded common-gate amplifier.

[0057] The detector output end is connected with an input end of the first amplifier AMP1, and the to-be-identified charge signal is input into the first amplifier AMP1. The input end of the first amplifier AMP1 is also connected with the feedback capacitor C f ​The first end of the feedback circuit, the drain of the feedback field effect transistor Q1, the output end of the baseline holder, and the first end of the first reset switch S1 are connected, and the output end of the first amplifier AMP1 is connected with the second end of the feedback capacitor C f , the source of the feedback field effect transistor Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit, and the input end of the reset signal unit.

[0058] In the embodiment, the output end of the feedback circuit is connected with the reference voltage end CSA_Vref of the baseline holder, and the output reset signal of the reset signal unit is input to the first reset switch S1 of the amplification unit and the switch of the peak sampling and holding circuit.

[0059] As shown in the above embodiment, Figure 2 the peak sampling and holding circuit includes a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2, and a voltage buffer.

[0060] The non-inverting terminal of the second amplifier AMP2 is connected with the output end of the first amplifier AMP1 in the amplification unit, the output end of the second amplifier AMP2 is connected with the anode of the diode, and the cathode of the diode is connected with the inverting terminal of the second amplifier AMP2, so as to lift the voltage drop caused by the diode; in the embodiment, the second amplifier AMP2 usually adopts a two-stage operational amplifier or a folded cascode amplifier;

[0061] The cathode of the diode is also connected with one end of the second reset switch S2, one end of the first capacitor C1, and the input end of the voltage buffer, respectively, and the diode is turned on to collect the peak voltage, and is turned off after the collection is completed;

[0062] The other end of the first capacitor C1 is connected with the other end of the second reset switch S2 in parallel and then grounded, the first capacitor C1 is used for storing the collected peak voltage, and the second reset switch S2 is used for discharging the voltage stored in the first capacitor C1; in the embodiment, the second reset switch S2 usually adopts an NMOS field effect transistor, and the gate electrode thereof is connected with a high-level reset.

[0063] The output end of the voltage buffer is connected with the feedback circuit and outputs a voltage signal, which is used for maintaining the signal output by the peak sampling and holding circuit and enhancing the driving capability of the circuit.

[0064] As shown in the above embodiment, Figure 3 the reset signal unit includes a comparator, an integration circuit, and a monostable circuit. The monostable circuit includes a NOR gate, an inverter, a second field effect transistor, and a second capacitor.

[0065] The non-inverting input of the comparator is used to receive the output signal of the amplification unit, the inverting input is provided with a threshold voltage by an external DAC, and the output of the comparator is connected to the input of the monostable circuit and the input of the integrator circuit.

[0066] The output of the integrator circuit is connected to the gate of the second field-effect transistor Q2, and is used to output a voltage signal that is proportional to the pulse width of the trigger signal.

[0067] The output signal of the monostable circuit is used to reset the switches of the amplification unit and the peak sample-and-hold circuit.

[0068] In the monostable circuit, the first input terminal of the NOR gate is connected to the output terminal of the comparator, the output terminal of the NOR gate is connected in sequence to the second capacitor C2 and the input terminal of the inverter INV, and the second input terminal of the NOR gate is connected in parallel with the output terminal of the inverter INV to serve as the output terminal of the monostable circuit.

[0069] The drain of the second field-effect transistor Q2 is connected in parallel between the second capacitor C2 and the input terminal of the inverter INV, and the source is connected to the analog power supply AVDD.

[0070] In use, the equivalent resistance R of the second field-effect transistor Q2 and the second capacitor C2 constitute the time constant of the monostable circuit, which is used to determine the extended voltage-controlled time of the reset signal. The gate of the second field-effect transistor Q2 receives the voltage signal output from the integrating circuit to change the value of the equivalent resistance R in real time.

[0071] Although specific embodiments have been described in this invention, the invention is not limited to these specific embodiments, and any other equivalent embodiments are within the scope of protection of this invention.

[0072] In the above embodiments, such as Figure 4 As shown, the baseline hold includes a third capacitor C3 and seven field-effect transistors: the third field-effect transistor Q3 to the ninth field-effect transistor Q9.

[0073] The third field-effect transistor Q3 is a bias current source. Its source is connected to the analog power supply AVDD, and its gate receives the bias voltage Vbias. The drain of the third field-effect transistor Q3 is connected to the source of the fourth field-effect transistor Q4 and the source of the fifth field-effect transistor Q5.

[0074] The sources of the fourth field-effect transistor Q4 and the fifth field-effect transistor Q5 are connected to form a differential pair. The gate of the fourth field-effect transistor Q4 serves as the reference voltage terminal CSA_Vref of the baseline hold and is connected to the output terminal of the feedback circuit. The drain of the fourth field-effect transistor Q4 is connected to the input terminal of the amplifier unit. The gate of the fifth field-effect transistor Q5 serves as the input terminal of the baseline hold and is connected to the output terminal of the amplifier unit.

[0075] The drain of the sixth field effect transistor Q6 is connected with the drain of the fourth field effect transistor Q4, the source is grounded, and the gate is connected with one end of the third capacitor C3 in parallel and then connected to the drain of the fifth field effect transistor Q5, and the other end of the third capacitor C3 is grounded;

[0076] The seventh to ninth field effect transistors Q7-Q9 are connected as a current mirror, the drain current of the fifth field effect transistor Q5 is integrated to the third capacitor C3, and the generated voltage controls the gate of the sixth field effect transistor Q6.

[0077] In use, the baseline holder can also compensate the influence of the leakage current of the detector. When there is a voltage difference between the reference voltage end CSA_Vref and the output of the amplification unit, the channel current of the sixth field effect transistor Q6 will increase, thereby compensating the leakage current of the detector and stabilizing the output baseline.

[0078] Although specific embodiments are described in the present application, the present application is not limited to these specific embodiments, and any other equivalent embodiments are within the protection scope of the present application.

[0079] As shown in the above embodiments, Figure 5 the feedback circuit can adopt two structural forms. The first feedback circuit is realized by a resistor. One end of the resistor is connected with the output end Vout of the peak value sampling and holding circuit, and the other end is connected to the reference voltage end CSA_Vref of the baseline holder. The resistor provides a stable feedback path in the feedback loop, helping the baseline of the charge amplifier to keep the accurate peak voltage. In addition, the resistor can adjust the time constant of the circuit, and selecting a suitable resistance value can adjust the response speed and stability of the circuit.

[0080] As shown in the above embodiments, Figure 5 the second feedback circuit is realized by a unit gain voltage buffer. The non-inverting end of the unit gain voltage buffer is connected with the output end Vout of the peak value sampling and holding circuit, and the inverting end and the output end are connected to the reference voltage end CSA_Vref of the baseline holder.

[0081] Although specific embodiments are described in the present application, the present application is not limited to these specific embodiments, and any other equivalent embodiments are within the protection scope of the present application.

[0082] As shown in the above embodiments, Figure 6 the readout working timing is as follows:

[0083] After the integration of the different pulse width input charge signals slowly drifting to the first peak, the peak voltage feedback from the back-stage peak sampling holding circuit to the reference voltage end of the amplifier unit adjusts the baseline in real time (the feedback time can be up to tens of nanoseconds), the peak sampling holding circuit superimposes the second integrated charge peak on the basis of the first peak, and so on, and finally the peak sampling holding circuit continuously superimposes the peak to obtain the energy information of the final slowly drifting charge.

[0084] The amplified signal output by the amplifier unit generates a trigger signal through the comparator, and then generates a reset signal for the amplifier unit and the peak sampling holding circuit through the monostable circuit. The reset signal starts sampling when the falling edge comes and resets when the rising edge comes. Each reset signal can adaptively prolong the voltage control time according to the trigger signal of the different pulse width input signal.

[0085] The voltage signal proportional to the pulse width of the trigger signal is input to the monostable circuit to change the prolonged voltage control time. In addition to the system self-reset function realized by the reset unit, the reset of the readout circuit can also be reset in real time by an external pulse signal.

[0086] In an embodiment of the present application, a method for using the charge amplifier structure is provided, which is based on the charge amplifier structure in the above embodiments. As shown in FIG. 8, the method comprises the following steps: Figure 7

[0087] 1) transmitting the to-be-identified charge signal output by the detector to the amplifier unit to obtain an amplified signal of the to-be-identified charge signal;

[0088] 2) inputting the amplified signal into the peak sampling holding circuit to obtain a peak voltage signal, and feeding back the peak voltage signal to the reference voltage end of the amplifier unit by the feedback circuit to form a new baseline of the amplifier unit;

[0089] 3) inputting the amplified signal output by the amplifier unit into the reset signal unit to obtain a reset signal of the amplifier unit and the peak sampling holding circuit.

[0090] In the above embodiments, the amplifier unit comprises a first amplifier AMP1, a feedback capacitor C f , a feedback field effect transistor Q1, a baseline holder, and a first reset switch S1.

[0091] The output end of the detector is connected with the input end of the first amplifier AMP1, and the to-be-identified charge signal is input into the first amplifier AMP1. The input end of the first amplifier AMP1 is also connected with the first end of the feedback capacitor C f , the drain of the feedback field effect transistor Q1, the output end of the baseline holder, and the first end of the first reset switch S1, respectively. The output end of the first amplifier AMP1 is connected with the second end of the feedback capacitor C​f The second terminal is connected to the source of the feedback field-effect transistor Q1, the input terminal of the baseline hold, the second terminal of the first reset switch S1, the input terminal of the peak sample-and-hold circuit, and the input terminal of the reset signal unit.

[0092] In the above embodiments, the peak sample-and-hold circuit includes: a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2, and a voltage buffer;

[0093] The second amplifier AMP2 has its non-inverting input connected to the output of the first amplifier AMP1 in the amplification unit. The output of the second amplifier AMP2 is connected to the positive terminal of the diode, and the negative terminal of the diode is connected to the inverting input of the second amplifier AMP2 to increase the voltage drop caused by the diode.

[0094] The negative terminal of the diode is also connected to one end of the second reset switch S2, one end of the first capacitor C1, and the input terminal of the voltage buffer. The peak voltage is collected when the diode is turned on.

[0095] The other end of the first capacitor C1 is connected in parallel with the other end of the second reset switch S2 and then grounded. The first capacitor C1 is used to store the collected peak voltage, and the second reset switch S2 is used to discharge the voltage stored in the first capacitor C1.

[0096] The output of the voltage buffer is connected to the feedback circuit and outputs a voltage signal to maintain the signal output by the peak sample-and-hold circuit and enhance the driving capability of the circuit.

[0097] In this embodiment, the second amplifier AMP2 is a two-stage operational amplifier or a folded common-source cascode amplifier.

[0098] In the above embodiments, the reset signal unit includes a comparator, an integrator circuit, and a monostable circuit;

[0099] The non-inverting input of the comparator is used to receive the output signal of the amplification unit, the inverting input is provided with a threshold voltage by an external DAC, and the output of the comparator is connected to the input of the monostable circuit and the input of the integrator circuit.

[0100] The output of the integrator circuit is connected to the monostable circuit to output a voltage signal that is proportional to the pulse width of the trigger signal.

[0101] The output signal of the monostable circuit is used to reset the switches of the amplification unit and the peak sample-and-hold circuit.

[0102] In this embodiment, the monostable circuit includes a NOR gate, an inverter INV, a second field-effect transistor Q2, and a second capacitor C2.

[0103] The first input end of the NOR gate is connected with the output end of the comparator, the output end of the NOR gate is connected with the second capacitor C2 and the input end of the inverter INV in sequence, and the second input end of the NOR gate is connected with the output end of the inverter INV in parallel and then serves as the output end of the monostable circuit.

[0104] The gate of the second field effect transistor Q2 is connected with the output end of the integration circuit, the drain of the second field effect transistor Q2 is connected in parallel between the second capacitor C2 and the input end of the inverter INV, and the source is connected with the analog power supply.

[0105] In the above embodiment, the baseline holder includes a third capacitor C3 and seven field effect transistors: a third field effect transistor Q3 to a ninth field effect transistor Q9.

[0106] The third field effect transistor Q3 is a bias current source, the source of which is connected with the analog power supply AVDD, the gate of which receives a bias voltage Vbias, and the drain of which is connected with the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5.

[0107] The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected in parallel to form a pair of differential pairs, the gate of the fourth field effect transistor Q4 serves as a reference voltage end CSA_Vref of the baseline holder and is connected with the output end of the feedback circuit, the drain of the fourth field effect transistor Q4 is connected with the input end of the amplification unit, and the gate of the fifth field effect transistor Q5 serves as an input end of the baseline holder and is connected with the output end of the amplification unit.

[0108] The drain of the sixth field effect transistor Q6 is connected with the drain of the fourth field effect transistor Q4, the source is grounded, and the gate is connected with one end of the third capacitor C3 in parallel and then connected with the drain of the fifth field effect transistor Q5, and the other end of the third capacitor C3 is grounded.

[0109] The seventh to ninth field effect transistors Q7-Q9 are connected as a current mirror, the drain current of the fifth field effect transistor Q5 is integrated to the third capacitor C3, and the generated voltage controls the gate of the sixth field effect transistor Q6.

[0110] In the above embodiment, the feedback circuit is a resistor, one end of the resistor is connected with the output end of the peak value sampling and holding circuit, and the other end is connected with the reference voltage end of the baseline holder.

[0111] In the above embodiment, the feedback circuit is a unit gain voltage buffer, the non-inverting end of the unit gain voltage buffer is connected with the output end of the peak value sampling and holding circuit, and the inverting end and the output end are connected with the reference voltage end of the baseline holder.

[0112] The use method provided in the embodiment is realized based on the above-mentioned embodiments of the charge amplifier structure, and the specific implementation method and detailed content are referred to the above-mentioned embodiments, which will not be described here.

[0113] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features therein can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A charge amplifier structure, characterized by, include: The amplification unit is used to receive the charge signal to be identified output by the detector and amplify the received charge signal to obtain the amplified signal of the charge signal to be identified. The peak sample-and-hold circuit is used to acquire the peak voltage signal of the amplified signal output by the amplification unit and store it in a capacitor; The feedback circuit is used to feed back the peak voltage signal acquired by the peak sample-and-hold circuit to the reference voltage terminal of the amplifier unit, forming a new baseline for the amplifier unit; The reset signal unit is used to process the amplified signal output by the amplification unit to obtain the trigger signal of the charge signal, and to process the trigger signal to obtain the reset signal of the amplification unit and the peak sample-and-hold circuit. The amplification unit comprises a first amplifier AMP1, a feedback capacitor C f , a feedback field effect transistor Q1, a baseline holder and a first reset switch S1; The output end of the detector is connected with the input end of the first amplifier AMP1, and the charge signal to be identified is input into the first amplifier AMP1. The input end of the first amplifier AMP1 is also connected with the first end of the feedback capacitor C f , the drain of the feedback field effect tube Q1, the output end of the baseline holder and the first end of the first reset switch S1. The output end of the first amplifier AMP1 is connected with the second end of the feedback capacitor C f , the source of the feedback field effect tube Q1, the input end of the baseline holder, the second end of the first reset switch S1, the input end of the peak sampling and holding circuit and the input end of the reset signal unit. The output end of the feedback circuit is connected with the reference voltage end CSA_Vref of the baseline holder.

2. The charge amplifier structure of claim 1, wherein, The peak sample-and-hold circuit includes: a second amplifier AMP2, a diode, a first capacitor C1, a second reset switch S2, and a voltage buffer; The second amplifier AMP2 has its non-inverting input connected to the output of the first amplifier AMP1 in the amplification unit. The output of the second amplifier AMP2 is connected to the positive terminal of the diode, and the negative terminal of the diode is connected to the inverting input of the second amplifier AMP2 to increase the voltage drop caused by the diode. The negative terminal of the diode is also connected to one end of the second reset switch S2, one end of the first capacitor C1, and the input terminal of the voltage buffer. The peak voltage is collected when the diode is turned on. The other end of the first capacitor C1 is connected in parallel with the other end of the second reset switch S2 and then grounded. The first capacitor C1 is used to store the collected peak voltage, and the second reset switch S2 is used to discharge the voltage stored in the first capacitor C1. The output of the voltage buffer is connected to the feedback circuit and outputs a voltage signal to maintain the signal output by the peak sample-and-hold circuit and enhance the driving capability of the circuit.

3. The charge amplifier structure of claim 2, wherein, The second amplifier, AMP2, is either a two-stage operational amplifier or a folded common-source cascode amplifier.

4. The charge amplifier structure of claim 1, wherein, The reset signal unit includes a comparator, an integrator, and a monostable circuit; The non-inverting input of the comparator is used to receive the output signal of the amplification unit, the inverting input is provided with a threshold voltage by an external DAC, and the output of the comparator is connected to the input of the monostable circuit and the input of the integrator circuit. The output of the integrator circuit is connected to the monostable circuit to output a voltage signal that is proportional to the pulse width of the trigger signal. The output signal of the monostable circuit is used to reset the switches of the amplification unit and the peak sample-and-hold circuit.

5. The charge amplifier structure of claim 4, wherein, The monostable circuit includes a NOR gate, an inverter INV, a second field-effect transistor Q2, and a second capacitor C2; The first input terminal of the NOR gate is connected to the output terminal of the comparator. The output terminal of the NOR gate is connected in sequence to the second capacitor C2 and the input terminal of the inverter INV. The second input terminal of the NOR gate is connected in parallel with the output terminal of the inverter INV and serves as the output terminal of the monostable circuit. The gate of the second field-effect transistor Q2 is connected to the output of the integrator circuit, the drain of the second field-effect transistor Q2 is connected in parallel between the second capacitor C2 and the input of the inverter INV, and the source is connected to the analog power supply.

6. The charge amplifier structure of claim 1, wherein, The baseline hold circuit includes a third capacitor C3 and seven field-effect transistors: the third field-effect transistor Q3 to the ninth field-effect transistor Q9; The third field effect transistor Q3 is a bias current source, the source of which is connected to the analog power supply AVDD, the gate of which receives a bias voltage Vbias, and the drain of which is connected to the source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5; The source of the fourth field effect transistor Q4 and the source of the fifth field effect transistor Q5 are connected to form a pair of differential pairs, the gate of the fourth field effect transistor Q4 is used as a reference voltage end CSA_Vref of the baseline holder and is connected to the output end of the feedback circuit, and the drain of the fourth field effect transistor Q4 is connected to the input end of the amplification unit; the gate of the fifth field effect transistor Q5 is used as an input end of the baseline holder and is connected to the output end of the amplification unit; The drain of the sixth field effect transistor Q6 is connected to the drain of the fourth field effect transistor Q4, the source of the sixth field effect transistor Q6 is grounded, and the gate of the sixth field effect transistor Q6 is connected to the drain of the fifth field effect transistor Q5 after being connected in parallel with one end of the third capacitor C3, and the other end of the third capacitor C3 is grounded; The seventh to ninth field effect transistors Q7-Q9 are connected to form a current mirror, and the drain current of the fifth field effect transistor Q5 is integrated to the third capacitor C3 to generate a voltage for controlling the gate of the sixth field effect transistor Q6.

7. The charge amplifier structure of claim 1, wherein, The feedback circuit is a resistor; one end of the resistor is connected to the output end of the peak sampling and holding circuit, and the other end of the resistor is connected to the reference voltage end of the baseline holder.

8. The charge amplifier structure of claim 1, wherein, The feedback circuit is a unit gain voltage buffer; the non-inverting input end of the unit gain voltage buffer is connected to the output end of the peak sampling and holding circuit, and the inverting input end and the output end of the unit gain voltage buffer are connected to the reference voltage end of the baseline holder.

9. A method of use based on the charge amplifier structure according to any one of claims 1 to 8, characterized in that, The method comprises the following steps: transmitting the to-be-identified charge signal output by the detector to the amplification unit to obtain an amplified signal of the to-be-identified charge signal; inputting the amplified signal into the peak sampling and holding circuit to obtain a peak voltage signal, and feeding back the peak voltage signal to the reference voltage end of the amplification unit by the feedback circuit to form a new baseline of the amplification unit; inputting the amplified signal output by the amplification unit into the reset signal unit to obtain a reset signal of the amplification unit and the peak sampling and holding circuit.

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