Detection circuit of phase-locked loop, phase-locked loop circuit and electronic equipment

Abstract

The invention provides a phase-locked loop detection circuit, a phase-locked loop circuit and electronic equipment, and belongs to the technical field of integrated circuits. The detection circuit comprises a locking detection module and a clock detection module. The locking detection module can reliably detect whether the phase-locked loop is locked or not based on the locking indication signal, and outputs the unlocking indication signal when detecting that the phase-locked loop is unlocked; the clock detection module can reliably detect whether a clock signal generated by the phase-locked loop has frequency offset based on a reference clock signal and a to-be-detected clock signal, and outputs a frequency offset indication signal when detecting that the clock signal has frequency offset. Therefore, the external controller can adjust the work of the phase-locked loop in time based on the unlocking indication signal and the frequency offset indication signal, and the situation that a circuit working based on the clock signal cannot work normally due to the influence of various factors such as the fact that the phase-locked loop cannot be locked or the clock signal generated by the phase-locked loop generates frequency offset is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a phase-locked loop detection circuit, a phase-locked loop circuit and an electronic device. Background Art

[0002] A phase-locked loop (PLL) is a circuit used to generate a clock signal.

[0003] In the related art, PLL generally includes a phase comparator (phase detector, PD), a loop filter (loop filter, LF) and a voltage-controlled oscillator (voltage-controlled oscillator, VCO). The PD is used to compare the input signal and the output signal (also called the feedback signal) to generate an error signal representing the phase difference, and the LF is used to use the error signal to adjust the frequency of the VCO so that it gradually approaches the frequency of the input signal, thereby minimizing the phase difference. When the PLL is in a locked state, the phase difference between the input signal and the output signal can be kept constant, and it can be considered that the PLL generates a stable clock signal.

[0004] However, due to the influence of noise or other interference in the circuit, the PLL may fail to unlock or lose lock, and the generated clock signal may jitter or have a frequency deviation, thereby causing the circuit based on the clock signal to fail to work properly. Summary of the invention

[0005] The embodiment of the present application provides a phase-locked loop detection circuit, a phase-locked loop circuit and an electronic device, which can solve the problem in the related art that the circuit based on the clock signal cannot work normally due to the influence of PLL being unable to lock, losing lock, jitter or frequency deviation of the generated clock signal. The technical solution is as follows:

[0006] In one aspect, a detection circuit of a phase-locked loop is provided, the detection circuit comprising: a lock detection module and a clock detection module, the lock detection module and the clock detection module are both connected to the phase-locked loop;

[0007] The lock detection module is used to: receive the lock indication signal output by the phase-locked loop, and after the phase-locked loop generates a clock signal, if it is detected that the lock indication signal does not meet the lock requirement, output an unlock indication signal;

[0008] The clock detection module is used to: receive a reference clock signal input to the phase-locked loop and a clock signal to be measured output by the phase-locked loop, and obtain a first count value by counting the reference clock signal based on a first counting reference, and obtain a second count value by counting the clock signal to be measured based on a second counting reference, and output a frequency deviation indication signal if it is detected that the difference between the first count value and the second count value is greater than a first difference threshold.

[0009] Optionally, the unlock indication signal includes: an unlock interrupt signal and an unlock alarm signal; the lock detection module includes: a first lock monitoring unit and an unlock interrupt generating unit connected to each other, and the unlock interrupt generating unit is also used to connect to the controller and the register;

[0010] The first lock monitoring unit is used to: receive the lock indication signal, and after the phase-locked loop generates a clock signal, if it is detected that the lock indication signal does not meet the lock requirement, output an unlock exception signal to the unlock interrupt generating unit;

[0011] The unlock interrupt generating unit is used to generate the unlock interrupt signal and the unlock alarm signal based on the unlock abnormal signal, and output the unlock interrupt signal to the controller and output the unlock alarm signal to the register.

[0012] Optionally, the lock detection module further comprises: an unlock synchronization unit; the unlock synchronization unit is connected to the unlock interrupt generation unit;

[0013] The unlocked synchronization unit is used to: receive an unlocked interrupt mask signal and an unlocked interrupt clear signal, synchronize the unlocked interrupt mask signal and the unlocked interrupt clear signal, and output the synchronized unlocked interrupt mask signal and the unlocked interrupt clear signal to the unlocked interrupt generation unit;

[0014] The unlocked interrupt generating unit is used to generate the unlocked interrupt signal and the unlocked alarm signal based on the unlocked abnormal signal and the synchronized unlocked interrupt masking signal and the unlocked interrupt clearing signal.

[0015] Optionally, the lock detection module is further configured to: after detecting that the lock indication signal meets the lock requirement, if a transition edge of the lock indication signal is detected, output a lock loss indication signal.

[0016] Optionally, the lock-out indication signal includes: a lock-out interrupt signal and a lock-out alarm signal; the lock detection module includes: a second lock monitoring unit and a lock-out interrupt generation unit connected to each other, and the lock-out interrupt generation unit is also used to connect with the controller and the register;

[0017] The second lock monitoring unit is used to: receive the lock indication signal, and after the phase-locked loop generates a clock signal, if it is detected that the lock indication signal meets the lock requirement, then when a transition edge of the lock indication signal is detected, output a lock exception signal to the lock interrupt generation unit;

[0018] The loss-of-lock interrupt generating unit is used to generate the loss-of-lock interrupt signal and the loss-of-lock alarm signal based on the loss-of-lock abnormal signal, and output the loss-of-lock interrupt signal to the controller and output the loss-of-lock alarm signal to the register.

[0019] Optionally, the lock detection module further includes: a lock-out synchronization unit; the lock-out synchronization unit is connected to the lock-out interrupt generation unit;

[0020] The loss-of-lock synchronization unit is used to: receive a loss-of-lock interrupt masking signal and a loss-of-lock interrupt clearing signal, synchronize the loss-of-lock interrupt masking signal and the loss-of-lock interrupt clearing signal, and output the synchronized loss-of-lock interrupt masking signal and the loss-of-lock interrupt clearing signal to the loss-of-lock interrupt generating unit;

[0021] The loss-of-lock interrupt generating unit is used to generate the loss-of-lock interrupt signal and the loss-of-lock alarm signal based on the loss-of-lock abnormal signal and the synchronized loss-of-lock interrupt masking signal and the loss-of-lock interrupt clearing signal.

[0022] Optionally, the second locking monitoring unit is shared with the first locking monitoring unit included in the locking detection module; and / or the loss-of-lock synchronization unit is shared with the unlocking synchronization unit included in the locking detection module.

[0023] Optionally, the lock detection module is also used to: receive the phase-lock enable signal and the reference clock signal input to the phase-locked loop, and in response to the phase-lock enable signal, count according to the reference clock signal, and determine that the phase-locked loop has generated a clock signal when the count reaches a phase-lock count reference; wherein the phase-lock count reference is related to a standard clock period for the phase-locked loop to generate a clock signal.

[0024] Optionally, the clock detection module is also used to: obtain a third count value by counting the reference clock signal based on a third counting reference, obtain a fourth count value by counting the clock signal to be measured based on a fourth counting reference, and output a jitter indication signal if it is detected that the difference between the third count value and the fourth count value is greater than a second difference threshold.

[0025] Optionally, the clock detection module is also used to: receive a detection enable signal, and in response to the detection enable signal, obtain the first count value by counting the reference clock signal based on the first count reference, and obtain the second count value by counting the clock signal to be measured based on the second count reference; and / or, in response to the detection enable signal, obtain the third count value by counting the reference clock signal based on the third count reference, and obtain the fourth count value by counting the clock signal to be measured based on the fourth count reference.

[0026] Optionally, the clock detection module includes: a frequency detection module and a jitter detection module;

[0027] The frequency detection module is used to: receive the reference clock signal and the clock signal to be measured, and obtain the first count value by counting the reference clock signal based on the first count reference, and obtain the second count value by counting the clock signal to be measured based on the second count reference, and output the frequency deviation indication signal if it is detected that the difference between the first count value and the second count value is greater than the first difference threshold;

[0028] The jitter detection module is used to: receive the reference clock signal and the clock signal to be measured, and obtain the third count value by counting the reference clock signal based on the third count reference, and obtain the fourth count value by counting the clock signal to be measured based on the fourth count reference, and output the jitter indication signal if it is detected that the difference between the third count value and the fourth count value is greater than the second difference threshold.

[0029] Optionally, the frequency deviation indication signal includes: a frequency abnormality interrupt signal and a frequency abnormality alarm signal; the frequency detection module includes: a frequency monitoring unit and a frequency abnormality interrupt generation unit connected to each other, and the frequency abnormality interrupt generation unit is also used to connect with the controller and the register;

[0030] The frequency monitoring unit is used to: receive the reference clock signal and the clock signal to be measured, and obtain the first count value by counting the reference clock signal based on the first count reference, and obtain the second count value by counting the clock signal to be measured based on the second count reference, and output a frequency abnormality signal to the frequency abnormality interrupt generation unit if it is detected that the difference between the first count value and the second count value is greater than the first difference threshold;

[0031] The frequency abnormality interrupt generating unit is used to generate the frequency abnormality interrupt signal and the frequency abnormality alarm signal based on the frequency abnormality signal, and output the frequency abnormality interrupt signal to the controller and output the frequency abnormality alarm signal to the register.

[0032] Optionally, the frequency detection module further includes: a frequency abnormality synchronization unit; the frequency abnormality synchronization unit is connected to the frequency abnormality interruption generation unit;

[0033] The frequency abnormality synchronization unit is used to: receive a frequency abnormality interruption shielding signal and a frequency abnormality interruption clearing signal, synchronize the frequency abnormality interruption shielding signal and the frequency abnormality interruption clearing signal, and output the synchronized frequency abnormality interruption shielding signal and the frequency abnormality interruption clearing signal to the frequency abnormality interruption generating unit;

[0034] The frequency abnormality interruption generating unit is used to generate the frequency abnormality interruption signal and the frequency abnormality alarm signal based on the synchronized frequency abnormality signal, and the synchronized frequency abnormality interruption shielding signal and the frequency abnormality interruption clearing signal.

[0035] Optionally, the frequency monitoring unit is further used to connect to the register; the frequency monitoring unit is further used to: determine frequency deviation information, and output the frequency deviation information to the register;

[0036] And / or, the frequency monitoring unit is also used to connect to the frequency abnormal interrupt generating unit; the frequency monitoring unit is also used to: determine the frequency deviation information, and output the frequency deviation information to the frequency abnormal interrupt generating unit; the frequency abnormal interrupt generating unit is used to: generate the frequency abnormal interrupt signal and the frequency abnormal alarm signal based on the synchronized frequency abnormal signal and the frequency deviation information.

[0037] Optionally, the jitter indication signal includes: a jitter abnormality interrupt signal and a jitter abnormality alarm signal; the jitter detection module includes: a jitter monitoring unit and a jitter abnormality interrupt generation unit connected to each other, and the jitter abnormality interrupt generation unit is also used to connect with the controller and the register;

[0038] The jitter monitoring unit is used to: receive the reference clock signal and the clock signal to be measured, and obtain the third count value by counting the reference clock signal based on the third count reference, and obtain the fourth count value by counting the clock signal to be measured based on the fourth count reference, and output a jitter abnormality signal to the jitter abnormality interrupt generation unit if it is detected that the difference between the third count value and the fourth count value is greater than the second difference threshold;

[0039] The jitter abnormal interrupt generating unit is used to generate the jitter abnormal interrupt signal and the jitter abnormal alarm signal based on the jitter abnormal signal, and output the jitter abnormal interrupt signal to the controller and output the jitter abnormal alarm signal to the register.

[0040] Optionally, the jitter detection module further includes: a jitter abnormality synchronization unit; the jitter abnormality synchronization unit is connected to the jitter abnormality interruption generation unit;

[0041] The jitter abnormality synchronization unit is used to: receive a jitter abnormality interruption shielding signal and a jitter abnormality interruption clearing signal, synchronize the jitter abnormality interruption shielding signal and the jitter abnormality interruption clearing signal, and output the synchronized jitter abnormality interruption shielding signal and the jitter abnormality interruption clearing signal to the jitter abnormality interruption generating unit;

[0042] The jitter abnormal interrupt generating unit is used to generate the jitter abnormal interrupt signal and the jitter abnormal alarm signal based on the synchronized jitter abnormal signal, and the synchronized jitter abnormal interrupt masking signal and the jitter abnormal interrupt clearing signal.

[0043] On the other hand, a phase-locked loop circuit is provided, the phase-locked loop circuit comprising: a phase-locked loop, and the detection circuit as described in the above aspect;

[0044] The detection circuit is connected to the phase-locked loop and is used to detect the operation of the phase-locked loop.

[0045] In another aspect, an electronic device is provided, the electronic device comprising: a controller, a register, and the phase-locked loop circuit as described in the above another aspect;

[0046] The detection circuit in the phase-locked loop circuit is connected to the controller and the register respectively, and is used to output the detection result of the phase-locked loop to the controller and the register.

[0047] In summary, the technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0048] Provided are a detection circuit for a phase-locked loop, a phase-locked loop circuit, and an electronic device. The detection circuit includes a lock detection module and a clock detection module. Since the lock detection module can reliably detect whether the phase-locked loop is locked based on a lock indication signal, and output an unlock indication signal when the phase-locked loop is detected to be unlocked; the clock detection module can reliably detect whether a clock signal generated by the phase-locked loop has a frequency deviation based on a reference clock signal and a clock signal to be measured, and output a frequency deviation indication signal when the clock signal is detected to have a frequency deviation. Therefore, an external controller can adjust the operation of the phase-locked loop in a timely manner based on the unlock indication signal and the frequency deviation indication signal, so as to avoid the circuit based on the clock signal from being unable to work properly due to various factors such as the phase-locked loop being unable to lock or the clock signal generated by the phase-locked loop having a frequency deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 is a schematic diagram of the structure of a phase-locked loop provided in an embodiment of the present application;

[0051] Figure 2 It is a structural schematic diagram of a phase-locked loop detection circuit provided in an embodiment of the present application;

[0052] Figure 3 It is a structural schematic diagram of another phase-locked loop detection circuit provided in an embodiment of the present application;

[0053] Figure 4 It is a structural schematic diagram of another phase-locked loop detection circuit provided in an embodiment of the present application;

[0054] Figure 5 is a structural schematic diagram of another phase-locked loop detection circuit provided in an embodiment of the present application;

[0055] Figure 6 is a structural schematic diagram of another phase-locked loop detection circuit provided in an embodiment of the present application;

[0056] Figure 7 is a schematic diagram of the structure of a phase-locked loop circuit provided in an embodiment of the present application;

[0057] Figure 8 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0059] The clock signal is an important component in digital chip design. It is the basis of sequential logic and is a signal with a fixed period and operating rules independent of the circuit function. The operating speed of the hardware can usually be controlled by controlling the period and frequency of the clock signal. In circuits (such as digital circuits), the following are usually used: Figure 1 The PLL shown is used to generate the required clock signal to trigger the register in the circuit to work or change the working state of the circuit. Figure 1 It can be seen that the PLL can be connected to the voltage input terminal Vin, and the voltage input terminal Vin can provide an input voltage to the analog circuit inside the PLL to control the operation of the analog circuit. Figure 1Based on this, refer to Figure 2 It can be seen that PLL generally includes PD, LF and VCO connected in sequence to form a loop. In addition, PLL can also receive a reference clock signal rf_clk, a phase-locked enable signal pll_en and a reset signal rst. Among them, PLL can be reset or initialized based on the reset signal rst. PLL can start working under the control of the phase-locked enable signal pll_en. And, after the PLL starts working, the PD therein can compare the received reference clock signal rf_clk and the feedback signal fed back by the VCO and generate an error signal Vpd representing the phase difference. LF can generate a control voltage Vcont based on the error signal Vpd to adjust the frequency of the VCO so that a constant phase difference is maintained between the feedback signal output by the VCO and the input signal (ie, the reference clock signal rf_clk), that is, the output signal h_clk of the PLL is synchronized with the input signal rf_clk. At this time, it can be considered that the PLL is in a locked state. On the contrary, if the output signal cannot be synchronized with the input signal, it can be considered that the PLL is not locked or is out of lock. Among them, PLL unlocked may mean that the PLL fails to lock successfully; PLL lost lock may mean that the PLL loses lock again after being successfully locked. Figure 1 and Figure 2 It can also be seen that the PLL can also output a lock indication signal locked to indicate the lock state of the PLL.

[0060] As mentioned above, noise interference may cause the PLL to be unlocked or lost. In addition, it may cause abnormal jitter or abnormal frequency deviation (also known as frequency deviation) of the clock signal generated by the PLL. Generally, the greater the noise, the greater the frequency deviation, and the clock signal is prone to overclocking. That is, the clock signal generated by the PLL is unstable. Since the clock signal generally determines the operating speed of the circuit based on the clock signal, the instability is likely to cause the circuit to fail to work properly, resulting in an increase in the data transmission error rate of the circuit or a decrease in signal integrity. Especially for some circuits that require high-quality clock signals (such as microprocessors, digital signal processors or wireless communication devices), that is, the instability of the clock signal generated by the PLL is generally not allowed. Based on this, it is urgent to provide a detection circuit to continuously monitor the clock signal generated by the PLL, so as to detect abnormal problems such as unlocking, losing lock, jitter or frequency deviation in time, so as to avoid the circuit based on the clock signal generated by the PLL from failing to work properly.

[0061] In some embodiments, the main focus is on the frequency detection of the clock signal. For example, a frequency counter or an oscilloscope is used to detect the frequency of the clock signal generated by the PLL, or the output signal of the PLL is compared with a reference signal and the frequency of the clock signal generated by the PLL is detected in combination with a counter and an oscilloscope. However, this not only depends on the design of the PLL, but also cannot perform a complete and comprehensive test on the clock signal generated by the PLL, such as being unable to detect whether the PLL is unlocked, whether it is unlocked, and whether the clock signal generated by the PLL is jittering. In addition, in this embodiment, the detection results are mostly stored in registers for the controller to call through polling or other mechanisms, and the operation of the PLL is adjusted based on the detection results so that the PLL can generate a stable clock signal. However, this calling method cannot guarantee timely and accurate feedback of the detection results, and thus cannot timely and reliably control the PLL to generate a stable clock signal. The controller can be, for example, a central processing unit (CPU).

[0062] Based on this, an embodiment of the present application provides a detection circuit to achieve timely and accurate detection of the clock signal generated by the PLL, so that the PLL can timely and reliably generate a stable clock signal, ensuring that the circuit operating based on the clock signal can operate normally. Figure 2 Schematic diagram of a detection circuit of a phase-locked loop provided in an embodiment of the present application. Figure 2 As shown, the detection circuit 00 includes: a lock detection module 01 and a clock detection module 02. The lock detection module 01 and the clock detection module 02 are both connected to a phase-locked loop PLL.

[0063] The lock detection module 01 is used to receive the lock indication signal locked output by the phase-locked loop PLL, and after the phase-locked loop PLL generates a clock signal, if it is detected that the lock indication signal locked does not meet the lock requirement, then output an unlock indication signal. That is, the lock detection module 01 can be used to detect whether the phase-locked loop PLL is locked.

[0064] Combination Figure 1 It can be seen that the phase-locked loop PLL can output a lock indication signal locked to indicate the lock state of the phase-locked loop PLL. Accordingly, the lock indication signal locked can also be called a lock state indication signal. The lock detection module 01 can be connected to the phase-locked loop PLL to receive the lock indication signal locked, and after the phase-locked loop PLL generates a clock signal, it can determine whether the phase-locked loop PLL is locked by detecting whether the lock indication signal locked meets the lock requirement. For example, Figure 2 The lock indication signal locked output to the lock detection module 01 is also identified as pll_lock.

[0065] Optionally, the phase-locked loop PLL normally generates a clock signal generally after N standard clock cycles, where N is an integer greater than 1, such as N can generally be 3. Accordingly, the lock detection module 01 can start to detect whether the lock indication signal locked (i.e., pll_lock) output by the phase-locked loop PLL meets the lock requirement after at least 3 standard clock cycles.

[0066] Moreover, in combination with the foregoing records, it can be known that meeting the locking requirements may mean that the output signal of the phase-locked loop PLL and the input signal are synchronized within a certain period of time, and the phase-locked loop PLL can generate a stable clock signal. Conversely, not meeting the locking requirements may mean that the output signal of the phase-locked loop PLL and the input signal cannot be stably synchronized within a certain period of time. Moreover, in general, if the phase-locked loop PLL is successfully locked, the level of the locking indication signal locked outputted by it is a high level (e.g., logic 1), that is, the level of the locking indication signal locked reflecting that the phase-locked loop PLL is in a locked state is a high level. If the phase-locked loop PLL is not locked, the level of the locking indication signal locked outputted by it is a low level (e.g., logic 0), that is, the level of the locking indication signal locked reflecting that the phase-locked loop PLL is in an unlocked state is a low level. Accordingly, the locking detection module 01 can reliably and quickly determine whether the phase-locked loop PLL is locked by detecting the level of the locking indication signal locked.

[0067] For example, after the phase-locked loop PLL works for N standard clock cycles, if the locking detection module 01 detects that the level of the locking indication signal locked is low level 0, it can be determined that the locking indication signal locked does not meet the locking requirement, that is, it can be determined that the phase-locked loop PLL is not locked. At this time, the locking detection module 01 can output an unlocked indication signal to indicate that the phase-locked loop PLL is not locked. Of course, if the level of the locking indication signal locked is detected to be high level 1, it can be determined that the locking indication signal locked meets the locking requirement, that is, it can be determined that the phase-locked loop PLL has been successfully locked. At this time, the locking detection module 01 may not output an unlocked indication signal, or may also output a locked indication signal to indicate that the phase-locked loop PLL is reliably locked. Optionally, the locking indication signal and the unlocked indication signal can be two signals with different levels, such as the level of the unlocked indication signal can be high level 1, and the level of the locked indication signal can be low level 0.

[0068] Optionally, the lock detection module 01 can be connected to a controller (such as a CPU) and can output an unlock indication signal to the controller to instruct the controller to adjust the parameters in the phase-locked loop PLL or control the phase-locked loop PLL to stop working in time when the phase-locked loop PLL cannot be locked, so as to avoid the circuit that works based on the clock signal generated by the phase-locked loop PLL from malfunctioning normally.

[0069] The clock detection module 02 is used to: receive the reference clock signal rf_clk input to the phase-locked loop PLL and the clock signal h_clk to be measured output by the phase-locked loop PLL, and obtain a first count value by counting the reference clock signal rf_clk based on a first count reference, and obtain a second count value by counting the clock signal h_clk to be measured based on a second count reference, and output a frequency deviation indication signal if it is detected that the difference between the first count value and the second count value is greater than a first difference threshold. That is, the clock detection module 02 can be used to detect whether the frequency of the clock signal generated by the phase-locked loop PLL is abnormally offset, that is, whether a frequency deviation occurs.

[0070] Combination Figure 1 It can also be seen that the phase-locked loop PLL can also receive a reference clock signal rf_clk to ensure that the internal oscillation signal and the external reference signal maintain the consistency of phase and frequency based on the reference clock signal rf_clk, thereby outputting a stable clock signal, which is referred to as the clock signal to be measured h_clk. The clock detection module 02 can be connected to the phase-locked loop PLL to receive the reference clock signal rf_clk and the clock signal to be measured h_clk. Then, the clock detection module 02 can count the reference clock signal rf_clk and the clock signal to be measured h_clk to obtain a first count value and a second count value, respectively, and determine whether the clock signal generated by the phase-locked loop PLL has a frequency deviation based on the magnitude relationship between the first count value and the second count value.

[0071] It is understandable that when the frequency of the clock signal h_clk to be measured does not deviate or deviates slightly, the first count value and the second count value should be close; and when the frequency of the clock signal h_clk to be measured deviates abnormally and greatly, the first count value and the second count value differ greatly. Accordingly, the clock detection module 02 can determine whether the frequency of the clock signal generated by the phase-locked loop PLL deviates abnormally (that is, whether frequency deviation occurs, such as overclocking) by detecting whether the difference between the first count value and the second count value is large.

[0072] If the difference between the first count value and the second count value is large, the clock detection module 02 can determine that the clock signal h_clk to be measured has a frequency deviation. At this time, the clock detection module 02 can output a frequency deviation indication signal to indicate that the frequency of the clock signal generated by the phase-locked loop PLL has an abnormal deviation. Of course, if the difference between the first count value and the second count value is small or 0, the clock detection module 02 can determine that the frequency of the clock signal h_clk to be measured is normal. At this time, the clock detection module 02 may not output a frequency deviation indication signal, or may also output a normal frequency indication signal to indicate that the frequency of the clock signal generated by the phase-locked loop PLL has not undergone an abnormal deviation. Optionally, the frequency deviation indication signal and the normal frequency indication signal can be two signals with different levels, such as the level of the frequency deviation indication signal is a high level 1, and the level of the normal frequency indication signal is a low level 0. It can be understood that an abnormal frequency deviation may refer to a large frequency deviation, and the deviation here may refer to a deviation from an ideal value.

[0073] Optionally, a first difference threshold value may be pre-set to measure whether the first count value differs greatly from the second count value, and the clock detection module 02 may detect whether the absolute value of the difference between the first count value and the second count value is greater than the first difference threshold value. Also, a first counting reference and a second counting reference may be pre-set so that the clock detection module 02 counts based on the first counting reference when counting according to the reference clock signal rf_clk, that is, counting stops when counting reaches the first counting reference. Accordingly, the first counting reference may also be referred to as the counting reference of the reference clock; when counting according to the clock signal h_clk to be measured, counting is performed based on the second counting reference, that is, counting stops when counting reaches the second counting reference. Accordingly, the second counting reference may also be referred to as the counting reference of the clock to be measured. Furthermore, the first counting reference and the second counting reference may be flexibly designed according to the specifications of the phase-locked loop PLL, such as the first counting reference and the second counting reference may be the same to ensure counting according to different clock signals at the same duration. In addition, the first counting reference, the second counting reference, the first difference threshold, etc. can be pre-stored in the clock detection module 02 by configuring register parameters for the clock detection module 02 to call, which belongs to parameter configuration signals.

[0074] Optionally, together with the lock detection module 01, the clock detection module 02 can also be connected to the controller and output a frequency deviation indication signal to the controller to instruct the controller to promptly adjust the parameters in the phase-locked loop PLL or control the phase-locked loop PLL to stop working when the frequency of the clock signal generated by the phase-locked loop PLL is abnormally offset, so as to avoid the circuit that works based on the clock signal generated by the phase-locked loop PLL from malfunctioning.

[0075] Based on the above records, it can be known that the detection circuit 00 provided in the embodiment of the present application can not only detect whether the phase-locked loop PLL is locked, but also detect whether the clock signal generated by the phase-locked loop PLL has a frequency deviation, and the detection is relatively comprehensive. On this basis, by promptly informing the controller of the detection result, it is convenient for the controller to adjust the operation of the phase-locked loop PLL in a timely manner to avoid the circuit working based on the clock signal output by the phase-locked loop PLL from failing to work properly. That is, it can ensure that the circuit working based on the clock signal generated by the phase-locked loop PLL can always be in a normal working state without being affected by the abnormal operation of the phase-locked loop PLL.

[0076] In summary, an embodiment of the present application provides a detection circuit for a phase-locked loop. The detection circuit includes a lock detection module and a clock detection module. Since the lock detection module can reliably detect whether the phase-locked loop is locked based on the lock indication signal, and output an unlock indication signal when it is detected that the phase-locked loop is not locked; the clock detection module can reliably detect whether the clock signal generated by the phase-locked loop has a frequency deviation based on the reference clock signal and the clock signal to be measured, and output a frequency deviation indication signal when it is detected that the clock signal has a frequency deviation. Therefore, the external controller can adjust the operation of the phase-locked loop in time based on the unlock indication signal and the frequency deviation indication signal, so as to avoid the circuit based on the clock signal from being unable to work properly due to various factors such as the phase-locked loop being unable to lock or the clock signal generated by the phase-locked loop having a frequency deviation.

[0077] Optionally, continue to refer to Figure 2 It can also be seen that the unlock indication signal may include: an unlock interrupt signal and an unlock alarm signal. Figure 3 As shown, the lock detection module 01 may include: a first lock monitoring unit 011 and an unlock interrupt generating unit 012 connected to each other, and the unlock interrupt generating unit 012 may also be used to connect with a controller and a register. Figure 3 The controller and the register are not shown, and belong to external devices independent of the detection circuit 00.

[0078] The first lock monitoring unit 011 can be used to: receive the lock indication signal locked (i.e., pll_lock), and after the phase-locked loop PLL generates a clock signal, if it is detected that the lock indication signal locked does not meet the lock requirement, output an unlock exception signal to the unlock interrupt generating unit 012. That is, the first lock monitoring unit 011 can detect whether the lock indication signal locked meets the lock requirement.

[0079] Optionally, combined Figure 3When the first locking monitoring unit 011 detects that the locking indication signal locked does not meet the locking requirements, the level of the signal pll_unlock output to the unlocking interrupt generating unit 012 can be pulled up from the initial low level to the high level, that is, the high-level signal pll_unlock is output to the unlocking interrupt generating unit 012 to indicate that the locking indication signal locked does not meet the locking requirements, that is, the phase-locked loop PLL is not locked. In other words, the unlocking abnormal signal output by the first locking monitoring unit 011 to the unlocking interrupt generating unit 012 can refer to the high-level signal pll_unlock. Of course, it is not limited to the level-pulling process, such as it can also be pulled down from the initial high level to the low level, and the embodiment of the present application does not limit this.

[0080] The unlock interrupt generating unit 012 can be used to generate an unlock interrupt signal and an unlock alarm signal based on the unlock abnormal signal (i.e., the high-level signal pll_unlock), and output the unlock interrupt signal to the controller and the unlock alarm signal to the register. That is, the unlock interrupt generating unit 012 can generate and output the unlock indication signal based on the unlock abnormal signal output by the first lock monitoring unit 011.

[0081] Optionally, the unlocked interrupt generating unit 012 can output the generated unlocked interrupt signal and unlocked alarm signal to the controller and register through different output channels, respectively, so that the controller can timely adjust the operation of the phase-locked loop PLL based on the unlocked interrupt signal to avoid the abnormality of the phase-locked loop PLL causing the circuit based on the clock signal generated by the phase-locked loop PLL to fail to work properly, and the controller can also call the unlocked alarm signal from the register through polling or other mechanisms to determine whether the phase-locked loop PLL is working properly. Compared with the above embodiment, which can only be called by polling from the register, the detection can be more timely and accurate.

[0082] Optionally, the unlocked interrupt signal / unlocked alarm signal generated by the unlocked interrupt generation unit 012 can be a pulse signal, and the high-level pulse width of the pulse signal can be equal to the high-level pulse width of a reference clock signal rf_clk. In some embodiments, an external signal processing circuit can also be set between the lock detection module 01 and the controller to convert the pulse into a level to adapt the controller for easy processing by the controller. Among them, the external signal processing circuit generally operates in a configuration clock domain, and the clock signal used in the configuration clock domain and the reference clock signal rf_clk are mostly asynchronous. In this way, the clock signal used by the external signal processing circuit and the reference clock signal rf_clk received by the phase-locked loop PLL need to be asynchronously processed to ensure that the external signal processing circuit samples the signal (such as an alarm signal) correctly.

[0083] Optionally, continue to refer to Figure 3 It can also be seen that the lock detection module 01 may further include: an unlock synchronization unit 013. The unlock synchronization unit 013 may be connected to the unlock interrupt generation unit 012.

[0084] The unlocked synchronization unit 013 can be used to: receive the unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr, synchronize the unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr, and output the synchronized unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr to the unlocked interrupt generation unit 012.

[0085] Optionally, the unlocked interrupt mask signal and the unlocked interrupt clear signal may come from an external circuit independent of the detection circuit, also called the outside world. That is, the unlocked synchronization unit 013 may synchronize the unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr received from the outside world.

[0086] Among them, synchronization may refer to synchronizing the unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr under the same reference clock to prevent erroneous processing due to signal asynchrony. The reference clock here may refer to the reference clock signal rf_clk received by the phase-locked loop PLL. The unlocked interrupt mask signal unlock intr mask may refer to temporarily masking some less urgent interrupts to avoid interfering with the instructions of the main process. In an embodiment of the present application, the main process may refer to the unlocked judgment process. The unlocked interrupt clear signal unlockintr clr may refer to clearing an interrupt that has occurred so that the system can continue to operate normally to prepare for processing new interrupt signals.

[0087] Optionally, the unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr may both have a high level 1 and a low level 0. For example, the unlocked interrupt mask signal unlock intr mask of a low level 0 may be used to indicate a masking signal, whereas the unlocked interrupt mask signal unlock intr mask of a high level 1 may be used to indicate a release of the masking signal.

[0088] The unlock interrupt generating unit 012 may be configured to generate an unlock interrupt signal and an unlock alarm signal based on the unlock exception signal, and the synchronized unlock interrupt mask signal unlock intr mask and unlock interrupt clear signal unlock intr clr.

[0089] Optionally, after receiving the synchronized unlocked interrupt masking signal unlockintr mask and unlocked interrupt clearing signal unlock intr clr, the unlocked interrupt generating unit 012 can select whether to mask the unlocked interrupt signal and unlocked alarm signal generated based on the unlocked exception signal based on the unlocked interrupt masking signal unlock intr mask, and select whether to clear the unlocked interrupt signal and unlocked alarm signal generated based on the unlocked exception signal based on the unlocked interrupt clearing signal unlock intr clr, thereby flexibly generating the unlocked interrupt signal and unlocked alarm signal based on the unlocked exception signal and the synchronized unlocked interrupt masking signal unlock intr mask and unlocked interrupt clearing signal unlock intr clr.

[0090] Optionally, the lock detection module 01 can also be used to: after detecting that the lock indication signal locked (i.e., pll_lock) meets the lock requirement, if a transition edge of the lock indication signal locked is detected, then an unlock indication signal is output. That is, the lock detection module 01 can also be used to detect whether the phase-locked loop PLL loses lock again after being locked. In this way, the detection function can be further enriched.

[0091] Optionally, after the phase-locked loop PLL is in a locked state, the locking indication signal locked can be maintained at a high level for a certain period of time. Once the high level is powered off to a low level, it can be considered that the phase-locked loop PLL is unlocked. Correspondingly, the transition edge of the locking indication signal locked can refer to a falling edge that jumps from a high level to a low level. Correspondingly, it can be known that the locking detection module 01 can continue to detect the falling edge of the locking indication signal locked in real time to determine whether the phase-locked loop PLL is unlocked after detecting that the locking indication signal locked meets the locking requirements, such as after detecting that the level of the locking indication signal locked is a high level 1. For example, once the locking detection module 01 detects that the locking indication signal locked has a falling edge, it can be determined that the phase-locked loop PLL is unlocked. At this time, the locking detection module 01 can output an unlock indication signal to indicate that the phase-locked loop PLL is unlocked.

[0092] Optionally, the lock detection module 01 can also output the unlock indication signal to the controller to instruct the controller to promptly adjust the parameters in the phase-locked loop PLL or control the phase-locked loop PLL to stop working when the phase-locked loop PLL loses lock, so as to avoid the circuit that works based on the clock signal generated by the phase-locked loop PLL from malfunctioning.

[0093] Optionally, continue to refer to Figure 2 It can also be seen that the lock-out indication signal may include: a lock-out interrupt signal and a lock-out alarm signal. Figure 3 As shown, the lock detection module 01 may include: a second lock monitoring unit 014 and a lock-loss interrupt generating unit 015 connected to each other, and the lock-loss interrupt generating unit 015 may also be used to connect with a controller and a register.

[0094] The second lock monitoring unit 014 may be configured to: receive the lock indication signal locked (i.e., pll_lock), and after the phase-locked loop PLL generates a clock signal, if it is detected that the lock indication signal locked meets the lock requirement, then when a transition edge (e.g., a falling edge) of the lock indication signal is detected, output a lock exception signal to the lock interrupt generating unit 015. That is, the second lock monitoring unit 014 may detect whether the lock indication signal locked has a falling edge.

[0095] Optionally, combined Figure 3 When the second lock monitoring unit 014 detects the falling edge of the lock indication signal locked, it can pull up the level of the signal pll_locklose output to the lock-out interrupt generating unit 015 from the initial low level to the high level, that is, output the high-level signal pll_locklose to the lock-out interrupt generating unit 015 to indicate that the lock indication signal locked has a falling edge, that is, indicates that the phase-locked loop PLL is locked. In other words, the lock-out abnormal signal output by the second lock monitoring unit 014 to the lock-out interrupt generating unit 015 can refer to the high-level signal pll_locklose. Of course, it is not limited to the level-pulling process, such as it can also be pulled down from the initial high level to the low level, and the embodiment of the present application does not limit this.

[0096] The lock-loss interrupt generation unit 015 can be used to generate a lock-loss interrupt signal and a lock-loss alarm signal based on the lock-loss abnormal signal (i.e., the high-level signal pll_locklose), and output the lock-loss interrupt signal to the controller and the lock-loss alarm signal to the register. That is, the lock-loss interrupt generation unit 015 can generate and output a lock-loss indication signal based on the lock-loss abnormal signal output by the second lock monitoring unit 014.

[0097] Optionally, the lock-loss interrupt generation unit 015 can also output the generated lock-loss interrupt signal and lock-loss alarm signal to the controller and the register through different output channels, so that the controller can timely adjust the operation of the phase-locked loop PLL based on the lock-loss interrupt signal to avoid the abnormality of the phase-locked loop PLL causing the circuit based on the clock signal generated by the phase-locked loop PLL to fail to work properly, and the controller can also call the lock-loss alarm signal from the register through polling or other mechanisms to determine whether the phase-locked loop PLL is working properly. Compared with the method of only being able to poll and call from the register in the above embodiment, the detection can be more timely and accurate.

[0098] Optionally, continue to refer to Figure 3 It can also be seen that the lock detection module 01 may further include: a lock-out synchronization unit 016 . The lock-out synchronization unit 016 may be connected to the lock-out interrupt generation unit 015 .

[0099] The loss-of-lock synchronization unit 016 can be used to: receive the loss-of-lock interrupt mask signal lock lose intr mask and the loss-of-lock interrupt clear signal lock lose intr clr, synchronize the loss-of-lock interrupt mask signal lock lose intr mask and the loss-of-lock interrupt clear signal lock lose intr clr, and output the synchronized loss-of-lock interrupt mask signal lock lose intrmask and the loss-of-lock interrupt clear signal lock lose intr clr to the loss-of-lock interrupt generation unit 015.

[0100] The lock-loss interrupt generating unit 015 may be configured to generate a lock-loss interrupt signal and a lock-loss alarm signal based on the synchronized lock-loss exception signal, and the synchronized lock-loss interrupt mask signal lock-lose-int mask and the lock-lose-interrupt clear signal lock-lose-int clr.

[0101] That is, together with the unlocked synchronization unit 013, the lost synchronization unit 016 can be set to synchronize the lost interrupt masking signal lock lose intr mask and the lost interrupt clearing signal lock lose intr clr received from the outside, so that when the lost interrupt generating unit 015 generates the lost interrupt signal and the lost alarm signal, it also refers to the synchronized lost interrupt masking signal lock lose intr mask and the lost interrupt clearing signal lock lose intr clr, so as to flexibly and reliably generate the lost interrupt signal and the lost alarm signal.

[0102] It can be understood that, with regard to the lost synchronization unit 016, the lost interrupt masking signal lock lose intr mask and the lost interrupt clearing signal lock lose intr clr, etc., reference can be made to the previous records regarding the unlocked synchronization unit 013, the unlocked interrupt masking signal unlock intr mask and the unlocked interrupt clearing signal unlock intr clr, and no further details will be given.

[0103] Optionally, continue to refer to Figure 3 It can be seen that the second lock monitoring unit 014 can be shared with the first lock monitoring unit 011 included in the lock detection module 01. That is, in the lock detection module 01, the lock monitoring unit for monitoring whether the lock indication signal locked meets the lock requirements and the lock monitoring unit for monitoring whether the lock indication signal locked has a falling edge can be the same lock monitoring unit. And / or, the lock-out synchronization unit 016 can be shared with the unlocked synchronization unit 013 included in the lock detection module 01. That is, in the lock detection module 01, the synchronization unit for synchronizing the unlocked abnormal signal and the synchronization unit for synchronizing the lock-out abnormal signal can be the same synchronization unit. In this way, the circuit structure can be simplified and the cost can be saved.

[0104] Optionally, continue to refer to Figure 3 It can be seen that the lock detection module 01 can also be used to: receive the phase-locked enable signal pll_en and the reference clock signal rf_clk input to the phase-locked loop PLL, and respond to the phase-locked enable signal pll_en, count according to the reference clock signal rf_clk, and determine that the phase-locked loop PLL has generated a clock signal when the count reaches the phase-locked count reference pll_locknum. The phase-locked count reference pll_locknum is related to the standard clock cycle for the phase-locked loop PLL to generate a clock signal. For example, the phase-locked count reference pll_locknum can be greater than or equal to the standard clock cycle.

[0105] Optionally, continue to refer to Figure 1It can be seen that the phase-locked loop PLL can also receive a phase-locked enable signal pll_en to start working based on the phase-locked enable signal pll_en. For example, the phase-locked loop PLL can be connected to the phase-locked enable terminal to receive the phase-locked enable signal pll_en provided by the phase-locked enable terminal. In addition, the phase-locked enable signal pll_en can refer to a high-level signal provided by the phase-locked enable terminal. Conversely, if the phase-locked enable terminal provides a low-level signal, it can represent a de-enabling signal. That is, the level of the signal provided by the phase-locked enable terminal can be raised to represent the phase-locked enable signal pll_en. The phase-locked loop PLL can start working after receiving the high-level phase-locked enable signal pll_en. The phase-locked enable signal pll_en can also be called the start signal of the phase-locked loop PLL. Accordingly, the lock detection module 01 can count based on the phase-lock count reference pll_locknum according to the reference clock signal rf_clk when receiving the high-level phase-lock enable signal pll_en, or when the level of the phase-lock enable signal pll_en is pulled high, until the count is stopped when the phase-lock count reference pll_locknum is counted, and the lock indication signal locked is started to detect whether it meets the lock requirement. That is, the lock detection module 01 can count after the phase-locked loop PLL starts working. In this way, the problem of wasting power consumption when the lock detection module 01 starts detecting before the phase-locked loop PLL starts working can be avoided.

[0106] Optionally, the phase-locked count reference pll_locknum can be flexibly set according to the standard clock cycle of a clock signal generated by the phase-locked loop PLL and pre-stored in the lock detection module 01. That is, the phase-locked count reference pll_locknum also belongs to the parameter configuration signal. Figure 3 In the embodiment of the present application, the lock monitoring unit included in the lock detection module 01 receives the phase lock enable signal pll_en and the reference clock signal rf_clk, and counts according to the reference clock signal rf_clk in response to the phase lock enable signal pll_en.

[0107] That is, if Figure 3As shown, the lock detection circuit 01 recorded in the embodiment of the present application may include four units to realize two detections of unlock and lock lose, and the core unit may be a lock monitoring unit. The lock monitoring unit may count based on the phase-lock count reference pll_locknum according to the reference clock signal rf_clk after the level of the phase-lock enable signal pll_en is pulled high, until the count is stopped when the phase-lock count reference pll_locknum is counted, and further checks whether the lock indication signal locked (that is, pll_lock) meets the lock requirement, and if not, pulls up the level of the signal pll_unlock. Moreover, after the lock indication signal locked meets the lock requirement, the lock monitoring unit may also detect the falling edge of pll lock, so as to pull up the signal pll_locklose when the falling edge is detected. The synchronization unit may synchronize the unlock interrupt mask signal unlock intr mask and the unlock interrupt clear signal unlockintr clr from the outside, and synchronize the lock interrupt mask signal lock lose intr mask and the lock interrupt clear signal lock lose intr clr from the outside. The synchronized signals are connected to the interrupt generation unit to instruct the interrupt generation unit to generate an unlocked interrupt signal and an alarm signal, and a lost-lock interrupt signal and an alarm signal, respectively.

[0108] Optionally, the clock detection module 02 can also be used to: obtain a third count value by counting the reference clock signal rf_clk based on a third count reference, obtain a fourth count value by counting the clock signal h_clk to be measured based on a fourth count reference, and output a jitter indication signal if it is detected that the difference between the third count value and the fourth count value is greater than a second difference threshold. That is, the clock detection module 02 can also be used to detect whether the clock signal generated by the phase-locked loop PLL has jitter abnormality. In this way, the detection function can be further enriched.

[0109] It can be understood that when the clock signal h_clk to be measured generated by the phase-locked loop PLL does not jitter or jitters less, the third count value and the fourth count value should be close; and when the clock signal h_clk to be measured generated by the phase-locked loop PLL has abnormally large jitter (such as long-term jitter), the third count value and the fourth count value are greatly different. Correspondingly, it can be known that the clock detection module 02 can determine whether the clock signal h_clk to be measured generated by the phase-locked loop PLL has abnormal jitter by detecting whether the difference between the third count value and the fourth count value is large. If the difference between the third count value and the fourth count value is large, the clock detection module 02 can determine that the clock signal h_clk to be measured has abnormal jitter. At this time, the clock detection module 02 can output a jitter indication signal to indicate that the clock signal generated by the phase-locked loop PLL jitters. Of course, if the difference between the third count value and the fourth count value is small or 0, the clock detection module 02 can determine that the clock signal h_clk to be measured does not have abnormal jitter. At this time, the clock detection module 02 may not output a jitter indication signal, or may also output a non-jitter indication signal to indicate that the clock signal generated by the phase-locked loop PLL does not jitter. Optionally, the jitter indication signal and the non-jitter indication signal may be two signals with different levels, such as the level of the jitter indication signal may be a high level 1, and the level of the non-jitter indication signal may be a low level 0. It is understandable that abnormal frequency jitter may refer to larger jitter or longer jitter duration.

[0110] Optionally, a second difference threshold value may be pre-set to measure whether the third count value differs greatly from the fourth count value, and the clock detection module 02 may detect whether the absolute value of the difference between the third count value and the fourth count value is greater than the second difference threshold value. Also, a third counting reference and a fourth counting reference may be pre-set so that the clock detection module 02 counts based on the third counting reference when counting according to the reference clock signal rf_clk, that is, counting stops when counting reaches the third counting reference. Accordingly, the third counting reference may also be referred to as the counting reference of the reference clock; when counting according to the clock signal h_clk to be measured, counting is performed based on the fourth counting reference, that is, counting stops when counting reaches the fourth counting reference. Accordingly, the fourth counting reference may also be referred to as the counting reference of the clock to be measured. Furthermore, the third counting reference and the fourth counting reference may be flexibly designed according to the specifications of the phase-locked loop PLL, such as the third counting reference and the fourth counting reference may be the same to ensure counting according to different clock signals at the same duration. In addition, the third counting reference, the fourth counting reference and the second difference threshold etc. can also be pre-stored in the clock detection module 02 by configuring register parameters for the clock detection module 02 to call, which are parameter configuration signals.

[0111] Furthermore, it can be understood that the third counting reference, the fourth counting reference and the second difference threshold can be determined based on the frequency of the clock signal h_clk to be measured, that is, they can be related to the clock signal h_clk to be measured, rather than being set arbitrarily. This is different from the counting reference and difference threshold used in frequency deviation detection. In other words, the clock detection module 02 detects whether the frequency and jitter of the clock signal h_clk to be measured occur in the same principle, and the difference lies in the setting of the counting reference and the difference threshold.

[0112] For example, if it is necessary to detect whether a 100 MHz clock signal h_clk to be tested has a jitter exceeding 30 seconds (s), then at least the counting reference of the reference clock (i.e., the third counting reference) needs to be set to 10000 cycles, and the counting reference of the clock to be tested (i.e., the fourth reference: 100Mhz / 0.025MHz) × the counting reference of the reference clock = 12000cycles needs to be set, and the second difference threshold needs to be set to 30ps*12000cycles = 36. That is, under this setting, if the clock detection module 02 detects that the difference between the third count value and the fourth count value exceeds 36, a jitter indication signal can be output to reliably indicate the jitter of the clock signal generated by the phase-locked loop PLL.

[0113] Optionally, similarly, the clock detection module 02 can also output a jitter indication signal to the controller to instruct the controller to promptly adjust the parameters in the phase-locked loop PLL or control the phase-locked loop PLL to stop working when the clock signal generated by the phase-locked loop PLL has abnormal jitter, so as to avoid the circuit that works based on the clock signal generated by the phase-locked loop PLL from malfunctioning.

[0114] Optionally, refer to Figure 4 The clock detection module 02 may also be used to: receive a detection enable signal check_en, and in response to the detection enable signal check_en, count the reference clock signal rf_clk based on the first counting reference to obtain a first count value, and count the clock signal h_clk to be measured based on the second counting reference to obtain a second count value. And / or, in response to the detection enable signal check_en, count the reference clock signal rf_clk based on the third counting reference to obtain a third count value, and count the clock signal h_clk to be measured based on the fourth counting reference to obtain a fourth count value.

[0115] Optionally, the clock detection module 02 can be connected to the detection enable terminal, and the detection enable signal check_en can be a high level signal provided by the detection enable terminal, and conversely, the low level signal provided by the detection enable terminal can refer to a detection disable signal. That is, the level of the signal provided by the detection enable terminal can be pulled up to indicate the detection enable signal check_en. The clock detection module 02 can start working after receiving the high level detection enable signal check_en. The detection enable signal check_en can also be called a start signal for clock detection. That is, a switch can be set to indicate that the clock detection module 02 is working or stopping working.

[0116] It is understandable that for some circuits with low clock quality requirements, the frequency deviation or jitter of the clock signal generated by the phase-locked loop PLL may have little effect on the operation of the circuit, and in this case, the clock detection module 02 may not be required to detect whether the clock signal has frequency deviation or jitter. In this way, by setting the detection enable signal check_en to indicate that the clock detection module 02 is working, the clock detection module 02 can be controlled not to work in some scenarios, thereby reducing the working power consumption of the clock detection module 02.

[0117] Alternatively, if Figure 4 As shown, the clock detection module 02 may include: a frequency detection module 021 and a jitter detection module 022 .

[0118] The frequency detection module 021 can be used to: receive a reference clock signal and a clock signal to be measured, and obtain a first count value by counting the reference clock signal based on a first count reference, and obtain a second count value by counting the clock signal to be measured based on a second count reference, and output a frequency deviation indication signal if it is detected that the difference between the first count value and the second count value is greater than a first difference threshold. That is, the frequency detection module 021 can detect whether the clock signal generated by the phase-locked loop PLL has an abnormal frequency deviation.

[0119] The jitter detection module 022 can be used to: receive a reference clock signal and a clock signal to be measured, and obtain a third count value by counting the reference clock signal based on a third count reference, and obtain a fourth count value by counting the clock signal to be measured based on a fourth count reference, and output a jitter indication signal if it is detected that the difference between the third count value and the fourth count value is greater than a second difference threshold. That is, the jitter detection module 022 can detect whether the clock signal generated by the phase-locked loop PLL has abnormal jitter.

[0120] Optionally, continue to refer to Figure 2 It can be seen that the frequency deviation indication signal may include: a frequency anomaly interrupt signal and a frequency anomaly alarm signal. Figure 5As shown, the frequency detection module 021 may include: a frequency monitoring unit 0211 and a frequency abnormal interrupt generation unit 0212 which are connected to each other, and the frequency abnormal interrupt generation unit 0212 may also be used to connect with a controller and a register.

[0121] The frequency monitoring unit 0211 can be used to: receive a reference clock signal rf_clk and a clock signal to be measured h_clk, and obtain a first count value by counting the reference clock signal rf_clk based on a first count reference, obtain a second count value by counting the clock signal to be measured h_clk based on a second count reference, and if it is detected that the difference between the first count value and the second count value is greater than a first difference threshold, output a frequency abnormality signal to the frequency abnormality interrupt generating unit 0212. That is, the frequency monitoring unit 0211 can detect whether the clock signal generated by the phase-locked loop PLL has a frequency deviation.

[0122] Optionally, combined Figure 5 When the frequency monitoring unit 0211 detects that the difference between the first count value and the second count value is greater than the first difference threshold, the level of the signal hclk_err output to the frequency abnormal interrupt generation unit 0212 can be pulled up from the initial low level to the high level, that is, the high-level signal hclk_err is output to the frequency abnormal interrupt generation unit 0212 to indicate that the first count value differs greatly from the second count value, that is, the frequency of the clock signal generated by the phase-locked loop PLL is abnormally offset. In other words, the frequency abnormality signal output by the frequency monitoring unit 0211 to the frequency abnormal interrupt generation unit 0212 may refer to the high-level signal hclk_err. Of course, it is not limited to the level-pulling process, such as it can also be pulled down from the initial high level to the low level, and the embodiment of the present application does not limit this.

[0123] Optionally, the frequency monitoring unit 0211 may include two counters. When the detection enable signal check_en is detected, one of the counters may count according to the reference clock signal rf_clk, and the other counter may be started to count according to the clock signal h_clk to be measured, and then the two count values ​​obtained may be compared, and once the difference between the two count values ​​is greater than the difference threshold, a frequency abnormality signal may be output.

[0124] The frequency abnormal interrupt generation unit 0212 can be used to: generate a frequency abnormal interrupt signal and a frequency abnormal alarm signal based on the frequency abnormal signal (i.e., the high-level signal hclk_err), and output the frequency abnormal interrupt signal to the controller, and output the frequency abnormal alarm signal to the register. That is, the frequency abnormal interrupt generation unit 0212 can generate and output a frequency deviation indication signal based on the frequency abnormal signal output by the frequency monitoring unit 0211.

[0125] Optionally, the frequency abnormal interrupt generation unit 0212 can also output the generated frequency abnormal interrupt signal and frequency abnormal alarm signal to the controller and register through different output channels, so that the controller can timely adjust the operation of the phase-locked loop PLL based on the frequency abnormal interrupt signal to avoid the abnormal clock signal generated by the phase-locked loop PLL causing the circuit based on the clock signal generated by the phase-locked loop PLL to fail to work properly, and the controller can also call the frequency abnormal alarm signal from the register through polling or other mechanisms to determine whether the clock signal generated by the phase-locked loop PLL is normal. Compared with the method of only being able to poll and call from the register in the above embodiment, the detection can be more timely and accurate.

[0126] Optionally, the frequency monitoring unit 0211 may also be used to connect to a register. On this basis, the frequency monitoring unit 0211 may also be used to: determine frequency deviation information hclk_ppm, and output the frequency deviation information to the register.

[0127] Among them, the frequency deviation information hclk_ppm may refer to a specific frequency deviation parameter, that is, the size of the frequency deviation. The register can reliably determine whether the clock signal generated by the phase-locked loop PLL has a frequency deviation in combination with the frequency deviation information and the frequency anomaly alarm information. Of course, in some embodiments, the frequency monitoring unit 0211 can also output the frequency deviation information hclk_ppm to the loss-of-lock interrupt generation unit 015, so that the loss-of-lock interrupt generation unit 015 can reliably generate a frequency anomaly interrupt signal and a frequency anomaly alarm signal in combination with the frequency anomaly signal and the frequency deviation information hclk_ppm.

[0128] Optionally, continue to refer to Figure 5 It can be seen that the frequency detection module may further include: a frequency abnormality synchronization unit 0213. The frequency abnormality synchronization unit 0213 is connected to the frequency abnormality interruption generation unit 0212.

[0129] The frequency abnormality synchronization unit 0213 can be used to: receive the frequency abnormality interrupt mask signal freq_hlck inrtmask and the frequency abnormality interrupt clear signal freq_hlck inrt clr, synchronize the frequency abnormality interrupt mask signal freq_hlck inrt mask and the frequency abnormality interrupt clear signal freq_hlck inrt clr, and output the synchronized frequency abnormality interrupt mask signal freq_hlck inrt mask and the frequency abnormality interrupt clear signal freq_hlck inrt clr to the frequency abnormality interrupt generating unit 0212.

[0130] The frequency abnormality interrupt generating unit 0212 may be configured to generate a frequency abnormality interrupt signal and a frequency abnormality alarm signal based on the synchronized frequency abnormality signal, and the synchronized frequency abnormality interrupt masking signal freq_hlck inrt mask and the frequency abnormality interrupt clearing signal freq_hlck inrtclr.

[0131] That is, together with the unlocked synchronization unit 013, the frequency abnormality synchronization unit 0213 can be set to synchronize the frequency abnormality interrupt masking signal freq_hlck inrt mask and the frequency abnormality interrupt clearing signal freq_hlck inrtclr received from the outside world, so that the frequency abnormality interrupt generating unit 0212, when generating the frequency abnormality interrupt signal and the frequency abnormality alarm signal, also refers to the synchronized frequency abnormality interrupt masking signal freq_hlck inrt mask and the frequency abnormality interrupt clearing signal freq_hlck inrt clr, so as to flexibly and reliably generate the frequency abnormality interrupt signal and the frequency abnormality alarm signal.

[0132] It can be understood that regarding the frequency abnormal synchronization unit 0213, the frequency abnormal interrupt masking signal freq_hlckinrt mask and the frequency abnormal interrupt clearing signal freq_hlck inrt clr, etc., reference can be made to the previous records regarding the unlocked synchronization unit 013, the unlocked interrupt masking signal unlock intr mask and the unlocked interrupt clearing signal unlock intr clr, and no further details will be given.

[0133] Optionally, continue to refer to Figure 2 It can be seen that the jitter indication signal may include: a jitter abnormality interrupt signal and a jitter abnormality alarm signal. Figure 6 As shown, the jitter detection module 022 may include: a jitter monitoring unit 0221 and a jitter abnormal interrupt generation unit 0222 connected to each other, and the jitter abnormal interrupt generation unit 0222 may also be used to connect with a controller and a register.

[0134] The jitter monitoring unit 0221 can be used to: receive a reference clock signal rf_clk and a clock signal to be measured h_clk, and obtain a third count value by counting the reference clock signal rf_clk based on a third count reference, obtain a fourth count value by counting the clock signal to be measured h_clk based on a fourth count reference, and if it is detected that the difference between the third count value and the fourth count value is greater than a second difference threshold, output a jitter abnormality signal to the jitter abnormality interrupt generating unit 0222. That is, the jitter monitoring unit 0221 can detect whether the clock signal generated by the phase-locked loop PLL has jitter abnormality.

[0135] Optionally, combined Figure 6 , the same frequency monitoring unit 0211, the jitter monitoring unit 0221 can also pull up the level of the signal hclk_jitter output to the jitter abnormal interrupt generation unit 0222 from the initial low level to the high level when it is detected that the difference between the third count value and the fourth count value is greater than the second difference threshold, that is, output a high-level signal hclk_jitter to the jitter abnormal interrupt generation unit 0222 to indicate that the third count value and the fourth count value differ greatly, that is, indicate that the clock signal generated by the phase-locked loop PLL is abnormally jittered. In other words, the jitter abnormality signal output by the jitter monitoring unit 0221 to the jitter abnormal interrupt generation unit 0222 can refer to a high-level signal hclk_jitter. Of course, it is not limited to the level-pulling process, such as it can also be pulled down from the initial high level to the low level, and the embodiment of the present application does not limit this.

[0136] Optionally, the frequency monitoring unit 0211 and the jitter monitoring unit 0221 may also include two counters. When the detection enable signal check_en is detected, one of the counters may count according to the reference clock signal rf_clk, and the other counter may be started to count according to the clock signal h_clk to be measured, and then the two count values ​​obtained may be compared, and once the difference between the two count values ​​is greater than the difference threshold, a jitter abnormality signal may be output.

[0137] The jitter abnormal interrupt generation unit 0222 can be used to: generate a jitter abnormal interrupt signal and a jitter abnormal alarm signal based on the jitter abnormal signal (i.e., the high-level signal hclk_jitter), and output the jitter abnormal interrupt signal to the controller, and output the jitter abnormal alarm signal to the register. That is, the jitter abnormal interrupt generation unit 0222 can generate and output a jitter indication signal based on the jitter abnormal signal output by the jitter monitoring unit 0221.

[0138] Optionally, the jitter abnormal interrupt generation unit 0222 may also output the generated jitter abnormal interrupt signal and jitter abnormal alarm signal to the controller and register through different output channels, so that the controller can timely adjust the operation of the phase-locked loop PLL based on the jitter abnormal interrupt signal to avoid the abnormal clock signal generated by the phase-locked loop PLL causing the circuit based on the clock signal generated by the phase-locked loop PLL to fail to work properly, and the controller may also call the jitter abnormal alarm signal from the register through polling or other mechanisms to determine whether the clock signal generated by the phase-locked loop PLL is normal. Compared with the above embodiment, which can only be called by polling from the register, the detection can be more timely and accurate.

[0139] Optionally, continue to refer to Figure 6It can be seen that the jitter detection module 022 may further include: a jitter abnormality synchronization unit 0223. The jitter abnormality synchronization unit 0223 is connected to the jitter abnormality interruption generation unit 0222.

[0140] The jitter abnormality synchronization unit 0223 can be used to: receive the jitter abnormality interrupt masking signal jitter_hlck inrtmask and the jitter abnormality interrupt clearing signal jitter_hlck inrt clr, synchronize the jitter abnormality interrupt masking signal jitter_hlck inrt mask and the jitter abnormality interrupt clearing signal jitter_hlck inrt clr, and output the synchronized jitter abnormality interrupt masking signal jitter_hlck inrt mask and the jitter abnormality interrupt clearing signal jitter_hlckinrt clr to the jitter abnormality interrupt generating unit 0222.

[0141] The jitter abnormal interrupt generating unit 0222 may be configured to generate a jitter abnormal interrupt signal and a jitter abnormal alarm signal based on the synchronized jitter abnormal signal, and the synchronized jitter abnormal interrupt masking signal jitter_hlckinrt mask and the jitter abnormal interrupt clearing signal jitter_hlckinrt clr.

[0142] That is, together with the unlocked synchronization unit 013, the jitter abnormality synchronization unit 0223 can be set to synchronize the jitter abnormality interrupt masking signal jitter_hlck inrt mask and the jitter abnormality interrupt clearing signal jitter_hlckinrt clr received from the outside, so that when the jitter abnormality interrupt generation unit 0222 generates the jitter abnormality interrupt signal and the jitter abnormality alarm signal, it also refers to the synchronized jitter abnormality interrupt masking signal jitter_hlck inrt mask and the jitter abnormality interrupt clearing signal jitter_hlck inrt clr, so as to flexibly and reliably generate the jitter abnormality interrupt signal and the jitter abnormality alarm signal.

[0143] It can be understood that, regarding the jitter abnormal synchronization unit 0223, the jitter abnormal interrupt mask signal jitter_hlckinrt mask and the jitter abnormal interrupt clear signal jitter_hlck inrt clr, etc., reference can be made to the above-mentioned records regarding the unlocked synchronization unit 013, the unlocked interrupt mask signal unlock intr mask and the unlocked interrupt clear signal unlock intr clr, and no further details will be given. Figures 1 to 6It can also be seen that the phase-locked loop PLL can receive a reset signal rst to reset based on the reset signal rst. And each unit in the detection circuit 00 can receive a reset signal rst to reset based on the reset signal rst. The reset signal rst received by the phase-locked loop PLL and the reset signal rst received by the detection circuit 00 can be the same.

[0144] Optionally, based on the foregoing records, the detection circuit provided in the embodiment of the present application can realize continuous monitoring of the phase-locked loop PLL unlocking, unlocking, generated clock signal frequency deviation, and jitter, and also has an enable control to enhance the working stability of the circuit. Among them, the detection circuit mainly includes three independent detection modules: a lock detection module, a frequency detection module, and a jitter detection module. The lock detection module can realize two detections: unlock detection and unlock detection. The unlock detection is to detect whether the phase-locked loop PLL generates a stable clock signal within a certain clock cycle. Of course, when the phase-locked loop PLL needs to be reconfigured, the level of pll_en can be controlled to be a low level, and the lock indication signal locked can be detected again after waiting for the specified clock cycle. The lock detection is to detect the falling edge of the lock indication signal locked. The frequency detection module can detect any degree of frequency deviation error and generate an alarm. For the frequency detection module, the counting reference and the difference threshold can be configured according to the requirements. The principle of the jitter detection module is similar to that of the frequency detection module, and the difference lies in the setting of the counting reference. For frequency detection, the higher the counting reference, the higher the detection accuracy, but there is no need to limit the minimum value. For jitter detection, the counting reference needs to be set to a minimum value according to the frequency of the clock signal h_clk to be measured, such as 10000 cycles. In this way, the abnormality of the phase-locked loop PLL can be discovered in a timely and comprehensive manner, thereby improving the working stability of the circuit working based on the clock signal generated by the phase-locked loop PLL.

[0145] Optionally, each part of the detection circuit 00 recorded in the embodiment of the present application may include a register and a logic circuit (such as a gate circuit) to realize the above detection function. Of course, in some embodiments, the controller may directly obtain the lock indication signal locked output by the phase-locked loop PLL to determine whether the clock generated by the phase-locked loop PLL is stable, and jitter detection and frequency detection may be realized by an oscilloscope or a spectrum analyzer.

[0146] In summary, an embodiment of the present application provides a detection circuit for a phase-locked loop. The detection circuit includes a lock detection module and a clock detection module. Since the lock detection module can reliably detect whether the phase-locked loop is locked based on the lock indication signal, and output an unlock indication signal when it is detected that the phase-locked loop is not locked; the clock detection module can reliably detect whether the clock signal generated by the phase-locked loop has a frequency deviation based on the reference clock signal and the clock signal to be measured, and output a frequency deviation indication signal when it is detected that the clock signal has a frequency deviation. Therefore, the external controller can adjust the operation of the phase-locked loop in time based on the unlock indication signal and the frequency deviation indication signal, so as to avoid the circuit based on the clock signal from being unable to work properly due to various factors such as the phase-locked loop being unable to lock or the clock signal generated by the phase-locked loop having a frequency deviation.

[0147] The present application also provides a phase-locked loop circuit. Figure 7 As shown, the phase-locked loop circuit includes: a phase-locked loop PLL, and Figures 1 to 6 Any of the detection circuits 00 shown.

[0148] The detection circuit 00 is connected to the phase-locked loop PLL and is used to detect the operation of the phase-locked loop PLL.

[0149] It is understandable that, since the phase-locked loop circuit has substantially the same technical effects as the aforementioned detection circuit, the technical effects of the phase-locked loop circuit will not be repeated here for the purpose of brevity.

[0150] The present application also provides an electronic device. Figure 8 As shown, the electronic device includes: a controller 100, a register 200 and Figure 7 The phase-locked loop circuit 000 is shown.

[0151] The detection circuit 00 in the phase-locked loop circuit 000 is connected to the controller 100 and the register 200 respectively, and is used to output the detection result of the phase-locked loop PLL to the controller 100 and the register 200 .

[0152] Optionally, the electronic device described in the embodiments of the present application may include: a microprocessor, a digital signal processor or a wireless communication device, etc.

[0153] It is understandable that, since the electronic device has substantially the same technical effects as the aforementioned phase-locked loop circuit, the technical effects of the electronic device will not be repeated here for the purpose of brevity.

[0154] It is understood that the terms used in the embodiments of the present application are used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs.

[0155] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "an" do not indicate a quantitative limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0156] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A phase-locked loop detection circuit, characterized in that: The detection circuit comprises: a lock detection module and a clock detection module, wherein both the lock detection module and the clock detection module are connected to the phase-locked loop; The lock detection module is used to: receive the lock indication signal output by the phase-locked loop, and after the phase-locked loop generates a clock signal, if it is detected that the lock indication signal does not meet the lock requirement, output an unlock indication signal; The clock detection module is used to: receive a reference clock signal input to the phase-locked loop and a clock signal to be measured output by the phase-locked loop, and obtain a first count value by counting the reference clock signal based on a first counting reference, and obtain a second count value by counting the clock signal to be measured based on a second counting reference, and output a frequency deviation indication signal if it is detected that the difference between the first count value and the second count value is greater than a first difference threshold.

2. The detection circuit according to claim 1, characterized in that: The unlock indication signal includes: an unlock interrupt signal and an unlock alarm signal; the lock detection module includes: a first lock monitoring unit and an unlock interrupt generating unit connected to each other, and the unlock interrupt generating unit is also used to connect to the controller and the register; The first lock monitoring unit is used to: receive the lock indication signal, and after the phase-locked loop generates a clock signal, if it is detected that the lock indication signal does not meet the lock requirement, output an unlock exception signal to the unlock interrupt generating unit; The unlock interrupt generating unit is used to generate the unlock interrupt signal and the unlock alarm signal based on the unlock abnormal signal, and output the unlock interrupt signal to the controller and output the unlock alarm signal to the register.

3. The detection circuit according to claim 2, characterized in that: The lock detection module further comprises: an unlock synchronization unit; the unlock synchronization unit is connected to the unlock interrupt generation unit; The unlocked synchronization unit is used to: receive an unlocked interrupt mask signal and an unlocked interrupt clear signal, synchronize the unlocked interrupt mask signal and the unlocked interrupt clear signal, and output the synchronized unlocked interrupt mask signal and the unlocked interrupt clear signal to the unlocked interrupt generation unit; The unlocked interrupt generating unit is used to generate the unlocked interrupt signal and the unlocked alarm signal based on the unlocked abnormal signal and the synchronized unlocked interrupt masking signal and the unlocked interrupt clearing signal.

4. The detection circuit according to any one of claims 1 to 3, characterized in that: The lock detection module is further configured to: after detecting that the lock indication signal meets the lock requirement, if a transition edge of the lock indication signal is detected, output a lock loss indication signal.

5. The detection circuit according to claim 4, characterized in that: The lock-out indication signal includes: a lock-out interrupt signal and a lock-out alarm signal; the lock detection module includes: a second lock monitoring unit and a lock-out interrupt generation unit connected to each other, and the lock-out interrupt generation unit is also used to connect with the controller and the register; The second lock monitoring unit is used to: receive the lock indication signal, and after the phase-locked loop generates a clock signal, if it is detected that the lock indication signal meets the lock requirement, then when a transition edge of the lock indication signal is detected, output a lock exception signal to the lock interrupt generation unit; The loss-of-lock interrupt generating unit is used to generate the loss-of-lock interrupt signal and the loss-of-lock alarm signal based on the loss-of-lock abnormal signal, and output the loss-of-lock interrupt signal to the controller and output the loss-of-lock alarm signal to the register.

6. The detection circuit according to claim 5, characterized in that: The lock detection module further includes: a lock-out synchronization unit; the lock-out synchronization unit is connected to the lock-out interrupt generation unit; The loss-of-lock synchronization unit is used to: receive a loss-of-lock interrupt masking signal and a loss-of-lock interrupt clearing signal, synchronize the loss-of-lock interrupt masking signal and the loss-of-lock interrupt clearing signal, and output the synchronized loss-of-lock interrupt masking signal and the loss-of-lock interrupt clearing signal to the loss-of-lock interrupt generating unit; The loss-of-lock interrupt generating unit is used to generate the loss-of-lock interrupt signal and the loss-of-lock alarm signal based on the loss-of-lock abnormal signal and the synchronized loss-of-lock interrupt masking signal and the loss-of-lock interrupt clearing signal.

7. The detection circuit according to claim 6, characterized in that: The second locking monitoring unit is shared with the first locking monitoring unit included in the locking detection module; and / or the loss-of-lock synchronization unit is shared with the unlocking synchronization unit included in the locking detection module.

8. The detection circuit according to any one of claims 1 to 3, characterized in that: The lock detection module is also used to: receive the phase-lock enable signal and the reference clock signal input to the phase-locked loop, and in response to the phase-lock enable signal, count according to the reference clock signal, and determine that the phase-locked loop has generated a clock signal when the count reaches a phase-lock count reference; wherein the phase-lock count reference is related to a standard clock period for the phase-locked loop to generate a clock signal.

9. The detection circuit according to any one of claims 1 to 3, characterized in that: The clock detection module is also used to: obtain a third count value by counting the reference clock signal based on a third count reference, obtain a fourth count value by counting the clock signal to be measured based on a fourth count reference, and output a jitter indication signal if it is detected that the difference between the third count value and the fourth count value is greater than a second difference threshold.

10. The detection circuit according to claim 9, characterized in that: The clock detection module is also used to: receive a detection enable signal, and in response to the detection enable signal, obtain the first count value by counting the reference clock signal based on the first count reference, and obtain the second count value by counting the clock signal to be measured based on the second count reference; and / or, in response to the detection enable signal, obtain the third count value by counting the reference clock signal based on the third count reference, and obtain the fourth count value by counting the clock signal to be measured based on the fourth count reference.

11. The detection circuit according to claim 9, characterized in that: The clock detection module includes: a frequency detection module and a jitter detection module; The frequency detection module is used to: receive the reference clock signal and the clock signal to be measured, and obtain the first count value by counting the reference clock signal based on the first count reference, and obtain the second count value by counting the clock signal to be measured based on the second count reference, and output the frequency deviation indication signal if it is detected that the difference between the first count value and the second count value is greater than the first difference threshold; The jitter detection module is used to: receive the reference clock signal and the clock signal to be measured, and obtain the third count value by counting the reference clock signal based on the third count reference, and obtain the fourth count value by counting the clock signal to be measured based on the fourth count reference, and output the jitter indication signal if it is detected that the difference between the third count value and the fourth count value is greater than the second difference threshold.

12. The detection circuit according to claim 11, characterized in that: The frequency deviation indication signal includes: a frequency abnormality interrupt signal and a frequency abnormality alarm signal; the frequency detection module includes: a frequency monitoring unit and a frequency abnormality interrupt generation unit connected to each other, and the frequency abnormality interrupt generation unit is also used to connect with the controller and the register; The frequency monitoring unit is used to: receive the reference clock signal and the clock signal to be measured, and obtain the first count value by counting the reference clock signal based on the first count reference, and obtain the second count value by counting the clock signal to be measured based on the second count reference, and output a frequency abnormality signal to the frequency abnormality interrupt generation unit if it is detected that the difference between the first count value and the second count value is greater than the first difference threshold; The frequency abnormality interrupt generating unit is used to generate the frequency abnormality interrupt signal and the frequency abnormality alarm signal based on the frequency abnormality signal, and output the frequency abnormality interrupt signal to the controller and output the frequency abnormality alarm signal to the register.

13. The detection circuit according to claim 12, characterized in that: The frequency detection module further includes: a frequency abnormality synchronization unit; the frequency abnormality synchronization unit is connected to the frequency abnormality interruption generation unit; The frequency abnormality synchronization unit is used to: receive a frequency abnormality interruption shielding signal and a frequency abnormality interruption clearing signal, synchronize the frequency abnormality interruption shielding signal and the frequency abnormality interruption clearing signal, and output the synchronized frequency abnormality interruption shielding signal and the frequency abnormality interruption clearing signal to the frequency abnormality interruption generating unit; The frequency abnormality interruption generating unit is used to generate the frequency abnormality interruption signal and the frequency abnormality alarm signal based on the synchronized frequency abnormality signal, and the synchronized frequency abnormality interruption shielding signal and the frequency abnormality interruption clearing signal.

14. The detection circuit according to claim 12, characterized in that: The frequency monitoring unit is also used to connect to the register; the frequency monitoring unit is also used to: determine frequency deviation information, and output the frequency deviation information to the register; And / or, the frequency monitoring unit is also used to connect to the frequency abnormal interrupt generating unit; the frequency monitoring unit is also used to: determine the frequency deviation information, and output the frequency deviation information to the frequency abnormal interrupt generating unit; the frequency abnormal interrupt generating unit is used to: generate the frequency abnormal interrupt signal and the frequency abnormal alarm signal based on the synchronized frequency abnormal signal and the frequency deviation information.

15. The detection circuit according to claim 11, characterized in that: The jitter indication signal includes: a jitter abnormal interrupt signal and a jitter abnormal alarm signal; the jitter detection module includes: a jitter monitoring unit and a jitter abnormal interrupt generation unit connected to each other, and the jitter abnormal interrupt generation unit is also used to connect with the controller and the register; The jitter monitoring unit is used to: receive the reference clock signal and the clock signal to be measured, and obtain the third count value by counting the reference clock signal based on the third count reference, and obtain the fourth count value by counting the clock signal to be measured based on the fourth count reference, and output a jitter abnormality signal to the jitter abnormality interrupt generation unit if it is detected that the difference between the third count value and the fourth count value is greater than the second difference threshold; The jitter abnormal interrupt generating unit is used to generate the jitter abnormal interrupt signal and the jitter abnormal alarm signal based on the jitter abnormal signal, and output the jitter abnormal interrupt signal to the controller and output the jitter abnormal alarm signal to the register.

16. The detection circuit according to claim 15, characterized in that: The jitter detection module further includes: a jitter abnormality synchronization unit; the jitter abnormality synchronization unit is connected to the jitter abnormality interruption generation unit; The jitter abnormality synchronization unit is used to: receive a jitter abnormality interruption shielding signal and a jitter abnormality interruption clearing signal, synchronize the jitter abnormality interruption shielding signal and the jitter abnormality interruption clearing signal, and output the synchronized jitter abnormality interruption shielding signal and the jitter abnormality interruption clearing signal to the jitter abnormality interruption generating unit; The jitter abnormal interrupt generating unit is used to generate the jitter abnormal interrupt signal and the jitter abnormal alarm signal based on the synchronized jitter abnormal signal, and the synchronized jitter abnormal interrupt masking signal and the jitter abnormal interrupt clearing signal.

17. A phase-locked loop circuit, characterized in that: The phase-locked loop circuit comprises: a phase-locked loop, and a detection circuit as claimed in any one of claims 1 to 16; The detection circuit is connected to the phase-locked loop and is used to detect the operation of the phase-locked loop.

18. An electronic device, characterized in that: The electronic device comprises: a controller, a register, and a phase-locked loop circuit as claimed in claim 17; The detection circuit in the phase-locked loop circuit is connected to the controller and the register respectively, and is used to output the detection result of the phase-locked loop to the controller and the register.

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