Polarization decoder and polarization decoding method

Abstract

The present invention discloses a polarization decoder and a polarization decoding method, comprising: a normalization receiving module, an intermediate LLR calculation module, a decision module, a partial sum return module, a return bit storage module, an index storage module and a decoding output module; the normalization receiving module converts a received demodulated signal into a normalized channel LLR value; the intermediate LLR calculation module calculates an intermediate LLR value using the normalized channel LLR value; the decision module is used to hard-determine an estimated bit according to the intermediate LLR value; the return bit and the estimated information bit are output through the estimated bit; the index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module; the decoding output module is used to read the estimated information bit from the return bit storage module and output it serially; by first normalizing the demodulated data and then performing a decoding operation, the operation bit width is saved and the calculation complexity between fixed-point numbers is reduced.

Description

Technical Field

[0001] The invention discloses a polarization decoder and a polarization decoding method, and relates to the field of information communication. Background Art

[0002] Polar codes have been selected as the uplink and downlink short code scheme for the control channel in the 5G communication system coding standard. However, due to the relatively short development time of polar codes, there is an urgent need to test theoretical research in practice, mainly by reducing hardware resource consumption.

[0003] Due to the inherent characteristics of serial decoding, polar codes suffer from complex hardware structures and high decoding latency, leading to excessive resource consumption. When the code length is long, the number of data exchanges and computational complexity required for intermediate LLR calculations increases significantly, necessitating a more optimized architecture to increase computational parallelism and minimize computational latency while maintaining low complexity. In existing designs, the basic arithmetic unit of the intermediate LLR calculation module consists of interconnected node modules. The complexity of this structure significantly impacts the performance of the entire decoder. Although optimized in the paper "Cao Zheng. High-Speed ​​Design and FPGA Implementation of Polar Code Codec for 5G Standards [D]. Xidian University, 2022," it still suffers from inversion and redundant XOR circuits. Furthermore, due to the excessive number of cascaded units, there is a risk of asynchronous combinational logic outputs, which may lead to computational errors. Furthermore, the choice of fixed-point quantization bit width is also a significant factor affecting decoder resource consumption. The paper selected an 8-bit quantization bit width, which, while approaching floating-point performance, still wastes excessive hardware resources. Summary of the Invention

[0004] In response to the deficiencies in the above-mentioned background technology, the present invention provides a polar decoder and a polar decoding method, which first normalize the demodulated data before performing the decoding operation, thereby saving operation bit width and reducing the computational complexity between fixed-point numbers.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a polar decoder, characterized by comprising: a normalized receiving module, an intermediate LLR storage module, an intermediate LLR calculation module, a decision module, a partial sum return module, a return bit storage module, a control module, an index storage module, and a decoding output module;

[0006] The data signal output terminal of the normalized receiving module is connected to the data signal input terminal of the intermediate LLR storage module;

[0007] The control signal output terminal of the normalization receiving module is connected to the control signal input terminal of the control module;

[0008] The control signal input terminal connection part of the control module and the control signal output terminal of the return module,

[0009] The data signal output terminal of the control module is connected to the second output XOR gate input terminal and the data signal input terminal of the intermediate LLR calculation module, and its control signal output terminal is connected to the control signal input terminal of the decoding output module;

[0010] The control signal output terminal of the decoding output module is connected to the second output XOR gate input terminal, and the data signal output terminal is connected to the third output XOR gate input terminal;

[0011] The output end of the two-output XOR gate is connected to the input end of the index storage module;

[0012] The output of the three-output XOR gate is connected to the input of the return bit storage module;

[0013] The output end of the index storage module is respectively connected to the control signal input end of the intermediate LLR calculation module, the control signal input end of the decision module, the control signal input end of the partial sum return module and the control signal input end of the decoding output module;

[0014] The output end of the return bit storage module is connected to the data signal input end of the intermediate LLR calculation module, the data signal input end of the partial sum return module and the data signal input end of the decoding output module;

[0015] The data signal output terminal of the intermediate LLR storage module is connected to the data signal input terminal of the intermediate LLR calculation module;

[0016] The control signal output terminal of the intermediate LLR calculation module is connected to the control signal input terminal of the intermediate LLR storage module and the input terminal of the three-input XOR gate, and the data signal output terminal is connected to the input terminal of the decision module;

[0017] The output terminal connection part of the judgment module and the data signal input terminal of the return module;

[0018] The partial sum return module control signal output terminal is connected to the return bit storage module control signal input terminal and the control module control signal input terminal, and the data signal output terminal is connected to the three-input XOR gate input terminal;

[0019] The normalized receiving module is used to convert the received demodulated signal into a normalized channel LLR value;

[0020] The intermediate LLR calculation module is used to calculate the intermediate LLR value using the normalized channel LLR value;

[0021] The intermediate LLR storage module is used to store the normalized channel LLR value and the intermediate LLR value output by the intermediate LLR calculation module;

[0022] The decision module is used to hard-determine the estimated bit according to the intermediate LLR value;

[0023] The part and return module outputs return bits and estimated information bits through the estimated bits;

[0024] The return bit storage module receives the return bit and the estimated information bit and outputs them to the intermediate LLR calculation module for performing intermediate LLR calculation;

[0025] The control module is used to control each submodule to complete the entire process from receiving the demodulated signal to the decoding output module outputting the estimated information bits;

[0026] The index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module;

[0027] The decoding output module is used to read the estimated information bits from the return bit storage module and output them serially.

[0028] Furthermore, the normalization module includes: two equal operation units, a right shift operation unit, a two-input XOR gate, a two-to-one selector and a register; the demodulated signal first passes through the right shift operation unit to complete the bitwise right shift operation, and then the two equal operation units judge the positive and negative of the input signal, and then the two-to-one selector selectively outputs the right shift output or its corresponding complement according to the positive and negative of the input data, and finally latches and outputs it through the register; it realizes the shortening of the quantization bit width of 12bit data to the quantization bit width of 5bit data.

[0029] Furthermore, the intermediate LLR calculation module includes a node interconnection module, which includes a three-input selector, two two-input selectors, two registers, an XOR gate, an adder, a subtractor, an AND gate, and two sign-taking operations. This module implements low-complexity intermediate LLR calculation by first performing addition and subtraction operations on the two received intermediate LLR data using an adder and a subtractor, respectively, and using them as two inputs of the three-input selector. Simultaneously, an XOR operation is performed on the sign bits of the two input signals using a sign-taking unit and an XOR gate, and using them as the last input of the three-input selector. Furthermore, the input of the first two-input selector consists of the outputs of the adder and the subtractor. The output of the three-input selector and the output of the first two-input selector are then used as the inputs of the second two-input selector. Finally, the output of the second two-input selector is latched into a register and output.

[0030] A polar decoding method comprises the following steps:

[0031] Step 1: Normalize the received channel LLRs. After shifting and saturating to reduce the data quantization bit width, the normalized channel LLRs are serially output to the intermediate LLR storage module.

[0032] Step 2: The intermediate LLR calculation module reads the intermediate LLR values ​​stored in the intermediate LLR storage module and performs parallel calculations. The calculation results are stored in the intermediate LLR storage module according to the write address output by the state machine in the intermediate LLR calculation module. The state machine divides the polar code into states based on the code length. The initial state is determined by the LLR index. When the jump condition is met, the state jump is performed and the intermediate LLR of the next state is calculated. When entering the IDLE state, it indicates that the intermediate LLR calculation of the bit is completed. The sign bit of the intermediate LLR calculated in the LAYER_1 state is output for the next bit decision.

[0033] Step 3: The decision module receives the sign bit from the intermediate LLR calculation module and the frozen bit index output by the index storage module. When the decision signal output by the intermediate LLR calculation module is high, the decision is made. Finally, the decision bit is output to the partial sum return module.

[0034] Step 4: The partial sum return module receives the decision bit output by the decision module and the partial sum return index output by the index storage module to determine the number of XOR operations required in this partial sum return calculation and the number of bits for each XOR operation.

[0035] Step 5: After receiving the calculation completion signal output by the partial sum return module, the control module outputs a read address signal and a read enable signal to the index storage module. The index storage module decodes the read address signal and the read enable signal output by the output module according to the read address signal and the read enable signal output by the control module, and updates the LLR index, frozen bit index, and partial sum return index in the intermediate LLR calculation module, the decision module, and the partial sum return module respectively.

[0036] Step 6: After detecting that the decoding end flag signal output by the control module is valid, the decoding output module selectively reads the estimated information bits in parallel from the return bit storage module in groups of 4 bits based on the output of the storage module, outputs all information bits serially after parallel-to-serial conversion, and simultaneously resets all modules inside the SC decoder, enters the waiting state, and prepares for the next decoding.

[0037] Furthermore, before normalization processing, the LLR index, frozen bit index and partial return index are first imported into the index storage module of the decoder, and the reset port of the decoder is pulled high for one clock cycle to reset the data in the intermediate LLR storage module and the return bit storage module and synchronize the clock signal.

[0038] Furthermore, the decision method in step 3 is as follows: if the frozen bit index is 1, it indicates that the bit is a frozen bit and is directly decided as 0; otherwise, the bit is an information bit. For the decision of the information bit: if the input is 0, it indicates that the LLR value is non-negative and the decision is 1; otherwise, the decision is 0.

[0039] Furthermore, step 4 is specifically as follows: in an XOR operation, the partial sum return module reads 4 bits of data in the return bit storage module as input according to the read address, and outputs 4 bits of data according to the write address and stores them in the return bit storage module, wherein the initial values ​​of the read address and write address calculated each time are determined by the partial sum return index in the index storage module, and the counter is used to accumulate the count.

[0040] Beneficial Effects: This method proposes normalizing the demodulated data before decoding. Compared to unnormalized processing, the appropriate normalization coefficient has a negligible performance loss, while saving operation bit width and reducing the computational complexity between fixed-point numbers. The normalization operation is completed by a simple right shift operation, with extremely low complexity.

[0041] The present invention utilizes a time-division multiplexing design concept in both the intermediate LLR calculation module and the partial sum return module. During LLR calculation, the improved node interconnection module is reused to sequentially calculate intermediate LLR values. By analyzing resource consumption and utilization, the appropriate number of cascades in the array is calculated, achieving an optimal solution for resource consumption and utilization. During partial sum calculation, the XOR array is reused and sequentially calculated according to the standard structure of the polar code generator matrix. Compared with traditional direct reproduction operation circuits, the proposed method can save a large amount of hardware resources and reduce implementation complexity.

[0042] The present invention improves the node interconnection module in the intermediate LLR calculation module. The traditional interconnection module requires "complement code-signed number", "signed number-complement code" and absolute value circuits, and is specifically composed of two complement code units and a two-output selector. In contrast, this design utilizes the characteristics of interconnected operations and selects a simple three-input selector and a box of XOR gates, reducing the delay and complexity of each operation.

[0043] The present invention requires frequent reading of previously calculated values ​​when calculating intermediate LLRs and partial sum returns, while also requiring immediate writing of new values. Therefore, designing the storage unit to be write-first and changing the read-write bit width can simplify operations and save reading time and address storage resources. In conventional designs, the storage of return bits with a code length of 512 requires counting 1023 address units, and only single-bit output is possible during reading, which takes a lot of time for long codewords. This design is improved to store 4-bit outputs together in one storage unit, shortening the number of address units to 319 and matching the number of input bits required by the XOR array and the LLR calculation array. Data reading can be completed within one cycle, shortening the decoding delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of the hardware structure of the present invention;

[0045] Figure 2 This is a schematic diagram of the normalized receiving module structure of the present invention;

[0046] Figure 3 This is the node interconnection module structure of the present invention;

[0047] Figure 4 It is the flow chart of the algorithm of the present invention;

[0048] Figure 5 Calculate state jumps for invented LLRs;

[0049] Figure 6 Calculate array resource consumption and utilization for the invented LLR;

[0050] Figure 7 Schematic diagram of the designed decoder resource report. Implementation Method

[0051] The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are not intended to limit the scope of protection of the present invention.

[0052] like Figure 1 An embodiment shown: This embodiment provides a polar decoder, including: a normalized receiving module, an intermediate LLR storage module, an intermediate LLR calculation module, a decision module, a partial sum return module, a return bit storage module, a control module, an index storage module, and a decoding output module;

[0053] The data signal output terminal of the normalized receiving module is connected to the data signal input terminal of the intermediate LLR storage module;

[0054] The control signal output terminal of the normalization receiving module is connected to the control signal input terminal of the control module;

[0055] The control signal input terminal connection part of the control module and the control signal output terminal of the return module,

[0056] The data signal output terminal of the control module is connected to the second output XOR gate input terminal and the data signal input terminal of the intermediate LLR calculation module, and its control signal output terminal is connected to the control signal input terminal of the decoding output module;

[0057] The control signal output terminal of the decoding output module is connected to the second output XOR gate input terminal, and the data signal output terminal is connected to the third output XOR gate input terminal;

[0058] The output end of the two-output XOR gate is connected to the input end of the index storage module;

[0059] The output of the three-output XOR gate is connected to the input of the return bit storage module;

[0060] The output end of the index storage module is respectively connected to the control signal input end of the intermediate LLR calculation module, the control signal input end of the decision module, the control signal input end of the partial sum return module and the control signal input end of the decoding output module;

[0061] The output end of the return bit storage module is connected to the data signal input end of the intermediate LLR calculation module, the data signal input end of the partial sum return module and the data signal input end of the decoding output module;

[0062] The data signal output terminal of the intermediate LLR storage module is connected to the data signal input terminal of the intermediate LLR calculation module;

[0063] The control signal output terminal of the intermediate LLR calculation module is connected to the control signal input terminal of the intermediate LLR storage module and the input terminal of the three-input XOR gate, and the data signal output terminal is connected to the input terminal of the decision module;

[0064] The output terminal connection part of the judgment module and the data signal input terminal of the return module;

[0065] The partial sum return module control signal output terminal is connected to the return bit storage module control signal input terminal and the control module control signal input terminal, and the data signal output terminal is connected to the three-input XOR gate input terminal;

[0066] The normalized receiving module is used to convert the received demodulated signal into a normalized channel LLR value;

[0067] The intermediate LLR calculation module is used to calculate the intermediate LLR value using the normalized channel LLR value;

[0068] The intermediate LLR storage module is used to store the normalized channel LLR value and the intermediate LLR value output by the intermediate LLR calculation module;

[0069] The decision module is used to hard-determine the estimated bit according to the intermediate LLR value;

[0070] The part and return module outputs return bits and estimated information bits through the estimated bits;

[0071] The return bit storage module receives the return bit and the estimated information bit and outputs them to the intermediate LLR calculation module for performing intermediate LLR calculation;

[0072] The control module is used to control each submodule to complete the entire process from receiving the demodulated signal to outputting the estimated information bits;

[0073] The index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module;

[0074] The decoding output module is used to read the estimated information bits from the return bit storage module and output them serially.

[0075] like Figure 2 As shown, the normalization module includes: two equal operation units, a right shift operation unit, a two-input XOR gate, a two-to-one selector and a register;

[0076] The demodulated signal (c_llr) first passes through a right shift unit to perform a bitwise right shift operation, resulting in a 7-bit signal, N_llr. The upper three bits of N_llr (N_llr[6:4]) are then passed through two equals units to determine the positive and negative sign of the input signal. A two-or-two selector then outputs the right-shifted data (N_llr[6:0]) or the extreme value within the quantization bit width ({N_llr[6],{4{!N_llr[6]}}) based on this relationship. Finally, the data is latched and output through a register, shortening the quantization bit width from 12 bits to 5 bits.

[0077] like Figure 3 As shown, the intermediate LLR calculation module includes: a node 2 interconnection module, the node interconnection module includes: a three-input selector, two two-input selectors, two registers, an XOR gate, an adder, a subtractor, an AND gate and two sign operations, realizing low-complexity intermediate LLR calculation;

[0078] First, the two received intermediate LLR data (L1 and L2) are added (L2 + L1) and subtracted (L2 - L1) using an adder and subtractor, respectively. These are then used as two inputs to a three-input selector. Simultaneously, the sign bits of the two input signals are XORed using a sign operation unit (sign) and an XOR gate, and then used as the final input to the three-input selector. Furthermore, the inputs to the first two-input selector consist of the outputs of the adder and subtractor (L2 + L1 and L2 - L1). The output of the three-input selector (f) and the output of the first two-input selector (g) are then used as the inputs to the second two-input selector. Finally, the output of the second two-input selector is latched into a register and output.

[0079] like Figures 4 and 5 In the embodiment shown, the detailed workflow is as follows:

[0080] Step 1: Initialization

[0081] To ensure proper operation of the decoder of Example 1, the first step is to import the LLR index, frozen bit index, and partial sum return index into the decoder's index storage module. The decoder's reset port is then pulled high for one clock cycle to reset the data in the intermediate LLR storage module and the return bit storage module and synchronize the clock signal. The decoder enters a wait state and begins decoding when the decoding start flag signal is pulled high.

[0082] Step 2: Normalize the demodulator output signal

[0083] When the decoder receives the decoding start signal, the normalization receiving module normalizes the channel LLRs output by the demodulator. After shifting and saturating the data to reduce the data quantization bit width, the module serially outputs the data to the intermediate LLR storage module for the next intermediate LLR calculation.

[0084] Step 3: Calculate the bit-to-bit LLR

[0085] The intermediate LLR calculation module calculates the intermediate LLRs of bits. The calculation process is controlled by a state machine. The state machine outputs a read address and an enable signal to control the node interconnect module to read the LLR values ​​stored in the intermediate LLR storage module for parallel calculation. The calculation results are then stored in the corresponding storage cells of the intermediate LLR storage module according to the write address output by the state machine.

[0086] The state machine is divided into states based on the code length. For example, a code length of 512 has 10 states. When the llr_ctrl_in_flag signal is pulled high, the state machine enters the LATER state from the IDLE state. The number of layers is determined by the LLR index. When the jump condition signal (jump_flag) is pulled high, the state jumps to the next state and calculates the intermediate LLR for the next state. Entering the IDLE state indicates that the intermediate LLR calculation for each bit is complete. The sign bit (most significant bit) of the intermediate LLR calculated in the LAYER_1 state is output for the next bit decision.

[0087] Step 4: Decision Bit

[0088] The decision module receives the 1-bit output from the intermediate LLR calculation module and the corresponding frozen bit index. It makes a decision when the valid signal is high. If the frozen bit index is 1, the bit is frozen and the decision is 0. Otherwise, the bit is an information bit. Regarding the information bit decision, if the input is 0, indicating that the LLR value is non-negative, the decision is 1; otherwise, the decision is 0. Finally, the decision bit is output.

[0089] Step 5: Partial and Return

[0090] The partial sum return module receives the judged bits and the partial sum return index to determine the number of times the partial sum return calculation needs to be performed and the number of bits for each exclusive OR operation; 4 bits of data are read from the return bit storage module during each operation, and the result of the operation is also stored in the return bit storage module in groups of 4 bits; the address counter accumulates the count and outputs the read and write address of the return bit storage module, so that the partial sum return module can read or write the bits required for this partial sum calculation.

[0091] Step 6: Enter the bit decoding process

[0092] After receiving the current bit calculation completion signal from the partial sum return module, the control module outputs the LLR index, frozen bit index and partial sum return index of the next bit; the decoding bit counter therein increments by 1 to count the number of decoded bits and pulls up the decoding start signal to enter the bit decoding; when the decoding bit counter counts to the end, the decoding ends and the decoding end flag signal level is pulled high for one clock cycle.

[0093] Step 7: Output the results

[0094] When the decoding output module detects that the decoding end flag signal is valid, it selectively reads information bits in parallel from the return bit storage module in groups of 4 bits according to the frozen bit index, outputs all information bits serially after parallel-to-serial conversion, and simultaneously sends a signal to clear the control module counter to 0, enters the waiting state, and prepares for the next decoding.

[0095] like Figure 6 As shown in the figure, when the number of node interconnect modules integrated into the LLR calculation array is four, the normalized resource consumption of the normalized receiving module is 0.35, and the resource utilization is 0.5. Further increasing the number of node interconnect modules significantly reduces the resource utilization, but the reduction in resource consumption is not significant. Therefore, it was ultimately determined that integrating four node interconnect modules into the LLR calculation array module maximizes the balance between decoding latency and resource consumption.

[0096] like Figure 7 As shown in the figure, the hardware resource usage is obtained after synthesizing and placing and routing the decoder in Vivado software. The results after placement and routing show that the system decoder consumes few resources, meeting the requirements of low-complexity design.

[0097] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A polar decoder, characterized in that: include: Normalization receiving module, intermediate LLR storage module, intermediate LLR calculation module, decision module, partial sum return module, return bit storage module, control module, index storage module and decoding output module; The data signal output terminal of the normalized receiving module is connected to the data signal input terminal of the intermediate LLR storage module; The control signal output terminal of the normalization receiving module is connected to the control signal input terminal of the control module; The control signal input terminal connection part of the control module and the control signal output terminal of the return module, The data signal output terminal of the control module is connected to the second output XOR gate input terminal and the data signal input terminal of the intermediate LLR calculation module, and its control signal output terminal is connected to the control signal input terminal of the decoding output module; The control signal output terminal of the decoding output module is connected to the second output XOR gate input terminal, and the data signal output terminal is connected to the third output XOR gate input terminal; The output end of the two-output XOR gate is connected to the input end of the index storage module; The output of the three-output XOR gate is connected to the input of the return bit storage module; The output end of the index storage module is respectively connected to the control signal input end of the intermediate LLR calculation module, the control signal input end of the decision module, the control signal input end of the partial sum return module and the control signal input end of the decoding output module; The output end of the return bit storage module is connected to the data signal input end of the intermediate LLR calculation module, the data signal input end of the partial sum return module and the data signal input end of the decoding output module; The data signal output terminal of the intermediate LLR storage module is connected to the data signal input terminal of the intermediate LLR calculation module; The control signal output terminal of the intermediate LLR calculation module is connected to the control signal input terminal of the intermediate LLR storage module and the input terminal of the three-input XOR gate, and the data signal output terminal is connected to the input terminal of the decision module; The output terminal connection part of the judgment module and the data signal input terminal of the return module; The partial sum return module control signal output terminal is connected to the return bit storage module control signal input terminal and the control module control signal input terminal, and the data signal output terminal is connected to the three-input XOR gate input terminal; The normalized receiving module is used to convert the received demodulated signal into a normalized channel LLR value; The intermediate LLR calculation module is used to calculate the intermediate LLR value using the normalized channel LLR value; The intermediate LLR storage module is used to store the normalized channel LLR value and the intermediate LLR value output by the intermediate LLR calculation module; The decision module is used to hard-determine the estimated bit according to the intermediate LLR value; The part and return module outputs return bits and estimated information bits through the estimated bits; The return bit storage module receives the return bit and the estimated information bit and outputs them to the intermediate LLR calculation module for performing intermediate LLR calculation; The control module is used to control each submodule to complete the entire process from receiving the demodulated signal to the decoding output module outputting the estimated information bits; The index storage module is used to provide corresponding index values ​​to the intermediate LLR calculation module, the decision module, the partial sum return module and the decoding output module; The decoding output module is used to read the estimated information bits from the return bit storage module and output them serially.

2. The polar decoder according to claim 1, wherein: The normalized receiving module includes: two equal operation units, a right shift operation unit, a two-input XOR gate, a two-choose-one selector and a register; the demodulated signal first passes through the right shift operation unit to complete the bitwise right shift operation, then the two equal operation units judge the positive or negative of the input signal, and then the two-choose-one selector selectively outputs the right shift output or its corresponding complement according to the positive or negative of the input data, and finally latches and outputs it through the register.

3. The polar decoder according to claim 1, wherein: The intermediate LLR calculation module includes: a node interconnection module, the node interconnection module includes: a three-input selector, two two-input selectors, two registers, an XOR gate, an adder, a subtractor, an AND gate and two sign operations; First, the two received intermediate LLR data are added and subtracted through the adder and subtractor respectively and used as two inputs of the three-input selector. At the same time, the sign bits of the two input signals are XORed through the sign operation unit and the XOR gate, which serves as the last input of the three-input selector. In addition, the input of the first two-input selector is composed of the output of the adder and the subtractor. Then, the output of the three-input selector and the output of the first two-input selector are used as the input of the second two-input selector. Finally, the output of the second two-input selector is input to the register latch and output.

4. A polar decoding method, characterized in that: The following steps are involved: Step 1: Normalize the received channel LLRs. After shifting and saturating to reduce the data quantization bit width, the normalized channel LLRs are serially output to the intermediate LLR storage module. Step 2: The intermediate LLR calculation module reads the intermediate LLR value stored in the intermediate LLR storage module and performs parallel calculation. The calculation result is stored in the intermediate LLR storage module according to the write address output by the state machine in the intermediate LLR calculation module. The state machine divides the polar code into states based on its code length. The initial state is determined by the LLR index. When the jump condition is met, the state jump is performed and the intermediate LLR of the next state is calculated. When entering the IDLE state, the intermediate LLR calculation of the bit is completed. The sign bit of the intermediate LLR calculated in the LAYER_1 state is output for the next bit decision. Step 3: The decision module receives the sign bit from the intermediate LLR calculation module and the frozen bit index output by the index storage module. When the decision signal output by the intermediate LLR calculation module is high, the decision is made and the decision bit is output to the partial sum return module. Step 4: The partial sum return module receives the decision bit output by the decision module and the partial sum return index output by the index storage module to determine the number of XOR operations required in this partial sum return calculation and the number of bits for each XOR operation; Step 5: After receiving the calculation completion signal output by the partial sum return module, the control module outputs a read address signal and a read enable signal to the index storage module. The index storage module decodes the read address signal and the read enable signal output by the output module according to the read address signal and the read enable signal output by the control module, and updates the LLR index, frozen bit index, and partial sum return index in the intermediate LLR calculation module, the decision module, and the partial sum return module respectively. Step 6: After detecting that the decoding end flag signal output by the control module is valid, the decoding output module selectively reads the estimated information bits in parallel from the return bit storage module in groups of 4 bits based on the output of the storage module, outputs all information bits serially after parallel-to-serial conversion, and simultaneously resets all modules inside the SC decoder, enters the waiting state, and prepares for the next decoding.

5. The polar decoding method according to claim 4, wherein: Before normalization, the LLR index, frozen bit index and partial return index are imported into the index storage module of the decoder, and the reset port is pulled high for one clock cycle to reset the data in the intermediate LLR storage module and the return bit storage module and synchronize the clock signal.

6. The polar decoding method according to claim 5, wherein: The judgment method in step 3 is: if the frozen bit index is 1, it means that the bit is a frozen bit and is directly judged as 0; otherwise, the bit is an information bit. For the judgment of the information bit: if the input is 0, it means that the LLR value is non-negative and the judgment is 1; otherwise, the judgment is 0.

7. The polar decoding method according to claim 4, wherein: Step 4 is specifically as follows: in an XOR operation, the partial sum return module reads 4 bits of data in the return bit storage module as input according to the read address, and outputs 4 bits of data according to the write address and stores them in the return bit storage module, where the initial values ​​of the read address and write address calculated each time are determined by the partial sum return index in the index storage module, and the counter is used to accumulate the count.

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