Time domain performance testing of digital devices

Abstract

The invention relates to time domain performance testing of digital devices. Various embodiments of the present disclosure disclose improved BIST systems and methods for testing digital devices. A method for testing a digital device includes receiving an output signal from a device under test (DUT) based at least in part on an input signal. The output signal is processed to generate a noise signal and a recovered signal of the DUT. The controller may generate a signal-to-noise power ratio based at least in part on the noise and the recovered signal and compare the signal-to-noise power ratio to a predetermined power threshold to generate a performance metric.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 63 / 578,426, filed on August 24, 2023, entitled “Time Domain Performance Testing for Digital Devices,” the entire disclosure of which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] Example embodiments of the present disclosure relate generally to phase-independent testing of digital devices, and in particular, to built-in testing of continuous-time digital devices, such as continuous-time sigma-delta (Σ-Δ) converters. Background Art

[0004] Applicants have discovered many technical challenges and difficulties associated with testing mixed-signal intellectual property (IP) core systems. Through hard work, ingenuity and innovation, Applicants have addressed the problems associated with traditional automated test equipment (ATE) and other performance limitations of traditional testing techniques by developing solutions implemented in the present disclosure, which will be described in detail below. Summary of the invention

[0005] Various embodiments described herein relate to systems, apparatus, products, and methods for testing complex systems.

[0006] In some embodiments, a controller is configured to: receive an output signal from a device under test (DUT) based at least in part on an input signal; generate a noise signal based at least in part on the input signal and the output signal; generate a recovered signal based at least in part on the output signal and the noise signal; generate a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal; and generate a performance metric of the DUT based at least in part on a comparison between the signal-to-noise power ratio and a predetermined power threshold.

[0007] In some examples, the performance metric is a signal-to-noise ratio (SNR) metric.

[0008] In some examples, the predetermined power threshold is one of a plurality of predetermined power thresholds stored in a lookup table, and each of the plurality of predetermined power thresholds indicates a corresponding threshold SNR metric.

[0009] In some examples, generating a signal-to-noise power ratio includes: generating a signal power based at least in part on a recovered signal using a first power accumulator; generating a noise power based at least in part on a noise signal using a second power accumulator; and generating the signal-to-noise power ratio based at least in part on the signal power and the noise power.

[0010] In some examples, generating the noise signal includes extracting the noise signal from the output signal using a notch infinite impulse response (IIR) filter.

[0011] In some examples, generating the recovered signal includes subtracting the noise signal from the output signal.

[0012] In some examples, the recovered signal and the noise signal accumulation are performed for 1024 samples.

[0013] In some examples, the controller is configured to output a performance metric.

[0014] In some examples, the input signal is a sine wave, and the controller is further configured to generate the input signal by at least: generating a modulated pulse; and filtering the modulated pulse to generate the sine wave.

[0015] In some examples, the controller and the DUT are part of the same mixed-signal system, and the controller is configured to test the DUT without external control.

[0016] In some examples, the DUT is a continuous-time sigma-delta analog-to-digital converter.

[0017] In some embodiments, a method includes: receiving an output signal from a device under test (DUT) based at least in part on an input signal; generating a noise signal based at least in part on the input signal and the output signal; generating a recovered signal based at least in part on the output signal and the noise signal; generating a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal; and generating a performance metric of the DUT based at least in part on a comparison between the signal-to-noise power ratio and a predetermined power threshold.

[0018] In some examples, the performance metric is a signal-to-noise ratio (SNR) metric.

[0019] In some examples, the predetermined power threshold is one of a plurality of predetermined power thresholds stored in a lookup table, and each of the plurality of predetermined power thresholds indicates a corresponding threshold SNR metric.

[0020] In some examples, generating a signal-to-noise power ratio includes: generating a signal power based at least in part on a recovered signal using a first power accumulator; generating a noise power based at least in part on a noise signal using a second power accumulator; and generating the signal-to-noise power ratio based at least in part on the signal power and the noise power.

[0021] In some examples, generating the noise signal includes extracting the noise signal from the output signal using a notch infinite impulse response (IIR) filter.

[0022] In some embodiments, a system includes: a device under test (DUT); and a controller. The controller is configured to receive an output signal from the DUT based at least in part on an input signal; generate a noise signal based at least in part on the input signal and the output signal; generate a recovered signal based at least in part on the output signal and the noise signal; generate a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal; and generate a performance metric of the DUT based at least in part on a comparison between the signal-to-noise power ratio and a predetermined power threshold.

[0023] In some examples, the DUT is a continuous-time sigma-delta analog-to-digital converter.

[0024] In some examples, the input signal is a sine wave, and the controller is further configured to generate the input signal by at least: generating a modulated pulse; and filtering the modulated pulse to generate the sine wave.

[0025] In some examples, the system is a system on a chip (SoC) or a system in a package (SiP).

[0026] The above summary of the invention is provided only for the purpose of summarizing some example embodiments, so as to provide a basic understanding of some aspects of the present disclosure. Therefore, it should be appreciated that the above embodiments are merely examples and should not be interpreted as limiting the scope or spirit of the present disclosure in any way. It should also be appreciated that the scope of the present disclosure covers many potential embodiments in addition to the embodiments outlined here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Having generally described above certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0028] Figure 1 illustrates an example computing ecosystem according to one or more embodiments of the present disclosure;

[0029] Figure 2 illustrates a block diagram of a built-in self-test (BIST) system according to one or more embodiments of the present disclosure;

[0030] Figure 3 illustrates a block diagram of an example signal and noise separator according to one or more embodiments of the present disclosure;

[0031] Figure 4 illustrates a data flow diagram of an example signal and noise separator according to one or more embodiments of the present disclosure;

[0032] Figure 5 illustrates a circuit diagram of an example notch filter according to one or more embodiments of the present disclosure;

[0033] Figure 6 illustrates a data flow diagram of an example performance measurement process according to one or more embodiments of the present disclosure;

[0034] Figure 7 A circuit diagram illustrating an example performance measurement process according to one or more embodiments of the present disclosure;

[0035] Figure 8 A flow chart of an example method for testing a digital device according to one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0036] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. Indeed, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0037] Various example embodiments of the present disclosure relate to improved test devices and systems, devices, products and methods for testing digital devices. The present disclosure describes in some examples a BIST system that is customized for testing intellectual property (IP) cores, complex systems on chips (SoCs) and systems in packages (SiPs) to improve traditional test techniques that cannot calculate performance metrics in the time domain.

[0038] For example, traditional testing for mixed-signal IP cores relies on functional specification testing, which uses specialized automated test equipment (ATE) to apply appropriate test stimuli, obtain output responses, and process test results. However, in complex SoC / SiP architectures—where internal IP is difficult to access externally, or even impossible—these operations are challenging, costly, and ineffective for evaluating the performance of digital devices (such as analog-to-digital converters (ADCs)) in continuous time. High-performance continuous-time Sigma Delta ADC testing involves applying a clean analog input signal to the device under test (DUT) and analyzing the measured signal. Traditional techniques require phase alignment of the reference signal and the measured signal, which brings many technical disadvantages to evaluating continuous-time devices with unpredictable phase shifts (such as continuous-time Sigma Delta modulators). In this case, sine wave fitting may not be possible because the phase of the test signal may be unknown. Other techniques can be implemented to perform phase-independent testing on digital devices. However, such techniques rely on bin power computations in the frequency domain, which can be time-consuming to generate, and which can rely on multiple bin-specific variables. Some embodiments of the present disclosure overcome these technical problems by enabling phase-independent signal analysis in the time domain.

[0039] Some embodiments of the present disclosure provide a complete on-chip architecture for testing continuous-time Sigma Delta ADCs. In some examples, the architecture can provide an input signal that is smoothed by a linear finite impulse response (FIR) digital-to-analog converter (DAC) filter and applied to the DUT. In this way, a full dynamic range signal at the DUT can be ensured. The output signal of the DUT can be evaluated by a test controller using some techniques of the present disclosure to extract the performance of the DUT. For example, a noise signal can be generated at least in part based on an input signal and an output signal, a recovered signal can be generated at least in part based on the output signal and the noise signal, a noise power ratio can be generated at least in part based on a comparison between the recovered signal and the noise signal, and a performance metric of the DUT can be generated at least in part based on a comparison between the signal-to-noise power ratio and a predetermined power threshold. In this way, a test apparatus and method for testing a digital device can be provided, which is applicable to all types of converters (e.g., ADC, etc.) testing, has a small turnaround time (e.g., less than 2500 samples), is scalable for higher performance modulators, has a low area digital analyzer (e.g., for 12b ENOB 40MSPS data, <350 FFs), and meets actual performance requirements. The test apparatus and method for testing a digital device can calculate performance metrics in the time domain (such as signal-to-noise ratio (SNR)) by using the time domain calculation of the output bit stream of the digital device, thereby providing a new and efficient solution.

[0040] It should be readily appreciated that the embodiments of the systems, apparatus and methods described herein may be configured in various additional and alternative ways besides those explicitly described herein.

[0041] Figure 1 An example computing ecosystem 100 according to one or more embodiments of the present disclosure is illustrated. In general, the terms computing system, computer, system, device, entity, and / or similar words used interchangeably herein may refer to, for example, one or more BIST systems, computers, computing entities, desktops, mobile phones, tablet computers, notebooks, laptops, distributed systems, kiosks, input terminals, servers or server networks, blades, gateways, switches, processing devices, processing entities, set-top boxes, repeaters, routers, network access points, base stations, etc. and / or any combination of devices or entities suitable for performing the functions, operations, and / or processes described herein. Such functions, operations, and / or processes may include, for example, transmission, reception, operation, processing, display, storage, determination, creation / generation, monitoring, evaluation, comparison, and / or similar terms used interchangeably herein. In one embodiment, these functions, operations, and / or processes may be performed on data, content, information, and / or similar terms used interchangeably herein.

[0042] The computing ecosystem 100 may include a BIST system 110 and / or one or more computing entities 120 that may be integrated with the BIST system 110. For example, the BIST system 110 may include a controller 102, a DUT 104, and / or a memory 106. The controller 102 may be communicatively coupled to the DUT 104 and / or the memory 106. The BIST system 110 may be a SOC, a SIP, etc., and / or may be a part of a SOC, a SIP, etc. For example, the BIST system 110 may include an integrated circuit 112, an advanced driver assistance system 114, and / or a part of any other analog-to-digital system configured to convert one or more analog signals into digital outputs and / or vice versa.

[0043] In some embodiments, the BIST system 110 includes one or more mixed-signal IP cores, where access to the cores is restricted. For example, access to the DUT 104 may be restricted by the design of the cores. The controller 102 or another device of the computing ecosystem 100 may be configured with the BIST and may perform testing on the DUT 104 (as an on-system test), thereby forgoing dedicated external testing.

[0044] The DUT 104 may be a modulator or a converter, such as a continuous-time sigma-delta analog-to-digital converter (ADC), etc. The DUT 104 may receive a first signal as a continuous-time analog signal and output a second signal as a digital representation of the first signal. The BIST may determine a performance metric of the DUT 104. The performance metric may represent or reflect the performance of the DUT 104 in response to a stimulus. The performance metric may be an SNR metric and / or a total harmonic distortion of the DUT 104.

[0045] The memory 106 may be any data storage device. The memory 106 may store executable instructions that, when executed by the controller 102, cause the controller 102 to operate as described herein. The memory 106 may be a read-only memory (ROM) or a random access memory (RAM), among others. In addition to executable instructions, the memory 106 may also store data. The data may include the results of tests performed on the DUT 104.

[0046] Controller 102 can be any device configured to test DUT 104. Controller 102 can include one or more processing elements (also referred to as processors, processing circuit systems, digital circuit systems and / or similar terms used interchangeably herein), or communicate with the one or more processing elements, which can be implemented in a variety of different ways. For example, the processing element can be implemented as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, co-processing entities, application specific instruction set processors (ASIPs), and / or microcontrollers, etc. In addition, the processing element can be implemented as one or more other processing devices or circuit systems. The term "circuitry" can refer to a combination of a complete hardware embodiment or a hardware and computer program product. Therefore, the processing element can be implemented as an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, and / or a digital circuit system, etc.

[0047] Therefore, as can be understood, the controller 102 can be configured for a specific purpose, or configured to execute instructions stored in the memory 106 or otherwise accessible to the controller 102. Thus, whether configured by hardware or non-transitory computer-readable media, or by a combination thereof, the controller 102 can be capable of performing steps or operations according to embodiments of the present disclosure after being configured accordingly.

[0048] In some embodiments, the controller 102 generates and sends an input signal 130 to the DUT 104. In response to sending the input signal 130, the controller 102 may receive an output signal 132 from the DUT 104. The controller 102 may evaluate the output signal 132 to determine a performance metric of the DUT 104. For example, the controller 102 may determine the SNR, harmonic distortion, or other signal quality indicators of the DUT 104.

[0049] Example embodiments of the present disclosure describe an improved BIST system that can be integrated into a complex system to test the performance of one or more digital devices (such as DUT 104) within the complex system. One or more test techniques can be used to test the digital device, such as reference Figure 2 as described.

[0050] Figure 2A block diagram of a BIST system 110 according to one or more embodiments of the present disclosure is illustrated. In some embodiments, the BIST system 110 includes a controller 102 and / or a DUT 104. In some examples, the BIST system 110 may be a SoC and / or a SiP, and / or may be integrated with a SoC and / or a SiP. In some examples, the controller 102 and the DUT 104 may be part of the same mixed signal system, and the controller 102 may test the DUT 104 without external control (e.g., using some of the techniques described herein). For example, the controller 102 may provide an input signal 130 to the DUT 104, and receive an output signal 132 from the DUT 104 based at least in part on the input signal 130. The controller 102 may process the output signal 132 to generate a performance metric 202 of the DUT 104.

[0051] In some embodiments, the controller 102 includes a pulse density modulator 204, a first filter 206, a second filter 208, a power ratio calculation section 210 configured to generate a noise power 212 and / or a signal power 214, and / or a performance calculation section 216 configured to generate a performance metric 202 based at least in part on the noise power 212 and / or the signal power 214. For example, the controller 102 may include an output port coupled to an input port of the DUT 104 and / or an input port coupled to an output port of the DUT 104. The pulse density modulator 204 may include any type of modulator, including a one-bit ROM, etc., which is configured to generate a modulated signal representing an analog signal in a digital domain. The signal may be a sine wave having a frequency, etc.

[0052] In some embodiments, the input signal 130 is a sine wave, and the controller 102 is configured to generate the input signal 130 at least by generating a modulated pulse using a pulse density modulator 204, and filtering the modulated pulse using a first filter 206 to generate a sine wave. The pulse density modulator 204 can, for example, output a signal to the first filter 206. The first filter 206 can be a finite impulse response (FIR) digital-to-analog converter (DAC). The first filter 206 can be a low-pass filter. The first filter 206 can be configured to filter and smooth the signal and output the input signal 130 to the DUT 104. The input signal 130 can be an analog signal (e.g., a sine wave, etc.). The DUT 104 can receive the input signal 130, process the input signal 130, and output an output signal 132 based at least in part on the input signal 130.

[0053] In some embodiments, the DUT 104 generates an output signal 132 based at least in part on the input signal 130. For example, the DUT 104 may include a digitizer circuit, such as an ADC circuit. For example, the DUT 104 may include any type of ADC circuit. In some examples, the DUT 104 may include a continuous time sigma-delta ADC (CTSDM) configured to convert analog signals over a wide frequency range. For example, the DUT 104 may include an oversampling modulator followed by a digital / decimation filter configured to convert an analog signal (such as the input signal 130) into a high-resolution data stream output (such as the output signal 132). For example, the output signal 132 may be a digital signal digitized by the DUT 104.

[0054] In some embodiments, the DUT 104 outputs an output signal 132 to the controller 102. The output signal 132 may have a phase shift relative to the input signal 130. As described herein, the controller 102 may be configured to generate a phase-agnostic performance metric, whereby a phase shift of the output signal due to operation of the DUT 104 may not be known and may not have a substantial impact on the performance metric 202 of the DUT 104. The second filter 208 of the controller 102 may receive the output signal 132 and filter the output signal 132 to generate a filtered signal. For example, the second filter 208 may reduce the rate of the output signal 132.

[0055] In some embodiments, the controller 102 includes a power ratio calculation section 210 that receives the output signal 132 (and / or the filtered output signal). The power ratio calculation section 210 may include circuitry configured to generate a noise signal and a restored signal from the output signal 132. In some embodiments, the power ratio calculation section 210 includes one or more power accumulators configured to transform the noise signal and / or the restored signal into noise power 212 and / or signal power 214, respectively.

[0056] In some embodiments, controller 102 includes performance calculation section 216 that receives noise power 212 and signal power 214 (and / or their ratio). Performance calculation section 216 may include circuitry configured to generate performance metric 202 based at least in part on comparison of noise power 212, signal power 214, and / or one or more predetermined thresholds. As described herein, noise power 212 and signal power 214 may be provided to performance calculation section 216 to generate performance metric 202.

[0057] In this manner, a performance metric 202 may be generated for the DUT 104 by separating the noise signal from the recovered signal, generating a power ratio based at least in part on the noise and the recovered signal, and comparing the ratio to a predetermined threshold. Each operation may be performed by the controller 102 and / or dedicated circuitry of the controller 102. For example, the noise and recovered signal may be generated by a signal and noise separator, which will be referred to as Figure 3 Further description.

[0058] Figure 3 A block diagram 300 of a signal and noise separator of an example according to one or more embodiments of the present disclosure is illustrated. The block diagram 300 includes an output signal representation 302 for the output signal 132. The output signal 132 is provided to a signal and noise separator 304. The signal and noise separator 304 may include circuitry specifically configured to separate a noise signal 306 and a recovered signal 308 from the output signal 132. In this manner, the controller uses the signal and noise separator 304 to generate a noise signal 306 as represented by a noise signal representation 310 and / or a recovered signal 308 as represented by a recovered signal representation 312 based at least in part on the output signal 132.

[0059] The signal and noise separator 304 may include a device specifically configured to Figure 4 One or more signal processing operations are described to generate circuitry for noise signal 306 and recovered signal 308 .

[0060] Figure 4 A data flow diagram 400 of an example signal and noise separator according to one or more embodiments of the present disclosure is illustrated. The signal and noise separator 304 may be configured to receive the output signal 132 as represented by the output signal representation 302, and output a restored signal 308 as represented by the restored signal representation 312 and / or a noise signal 306 as represented by the noise signal representation 310. The signal and noise separator 304 may include a notch filter 420, a first electrical connector 408, and / or a second electrical connector 410. The output signal 132 may, for example, include an extracted signal (e.g., sine wave + noise) output from the DUT based at least in part on the input signal (e.g., at fs=40MHz, fIN=5MHz).

[0061] In some embodiments, the controller generates the noise signal 306 based at least in part on the input signal and the output signal 132. For example, the notch filter 402 may be configured at least in part based on the input signal to extract the noise signal 306 from the output signal 132. The notch filter 402 may include any type of notch filter circuit. In some examples, the notch filter 402 may include a notch infinite impulse response (IIR) filter configured specifically for a particular input signal. In some embodiments, the controller extracts the noise signal 306 from the output signal 132 using a notch IIR filter. For example, the output signal 132 may be provided to the notch filter 402 to receive the noise signal 306. In some examples, the notch filter 402 may generate an average noise signal 404 for at least 1024 cycles. The average noise signal 404 may be compared with the extracted signal at the first electrical connector 408 to generate the noise signal 306 from the output signal 132.

[0062] In some embodiments, the controller generates the restored signal 308 based at least in part on the output signal 132 and the noise signal 306. In some embodiments, the controller subtracts the noise signal 306 from the output signal 132 to generate the restored signal 308. For example, at the second electrical connector 410, the noise signal 306 can be removed from the output signal 132 to generate the restored signal 308.

[0063] Notch filter 402 may include circuitry specifically configured to generate noise signal 306, as described with reference to FIG. Figure 5 as described.

[0064] Figure 5 A circuit diagram 500 of an example notch filter design according to one or more embodiments of the present disclosure is illustrated. The circuit diagram 500 illustrates an example notch filter design for extracting the noise signal 306 from the output signal 132. The notch filter design may form a notch infinite impulse response (IIR) filter that may be configured to extract the noise signal according to the following equation:

[0065]

[0066] Where F0 can be equal to 5MHz, F s It can be equal to 40MHz and / or Q can be equal to 50.

[0067] In some embodiments, the noise signal 306 (and / or the recovered signal described herein) may be provided to one or more power accumulators to generate noise and signal power. Figure 6 One or more performance measurement operations are described that utilize noise and signal power to generate a performance metric.

[0068] Figure 6 A data flow diagram 600 of an example performance measurement process according to one or more embodiments of the present disclosure is illustrated. The performance measurement process can be performed by a controller and / or one or more circuit systems thereof. For example, the controller can include a power ratio calculation section 210, which can be configured to generate a recovered signal 308 and a noise signal 306 (e.g., using a noise and signal separator, etc.) and output a noise power 212 and a signal power 214. The noise power 212 and / or the signal power can be output to a performance calculation section 216, which can be configured to generate a performance metric 202 based at least in part on the noise power 212 and the signal power 214.

[0069] In some embodiments, the controller generates a signal-to-noise power ratio 608 based at least in part on the recovered signal 308 and the noise signal 306. For example, the controller can generate a signal power 214 based at least in part on the recovered signal 308 using the first power accumulator 602. The signal power 214 can be a power measurement that indicates an energy characteristic of the recovered signal 308. The controller can generate a noise power 212 based at least in part on the noise signal 306 using the second power accumulator 604. The noise power 212 can be another power measurement that indicates an energy characteristic of the noise signal 306.

[0070] The controller may generate a signal-to-noise power ratio 608 based at least in part on the signal power 214 and the noise power 212. For example, the signal power 214 and the noise power 212 may be provided to the division component 606 to generate the signal-to-noise power ratio 608. For example, the signal-to-noise power ratio 608 may include a measurement indicating the signal power 214 divided by the noise power 212. In some examples, the accumulation of the recovered signal 308 and / or the noise signal 306 may be performed for 1024 samples. For example, the accumulation of the recovered signal 308 and / or the noise signal 306 may be performed for 1024 samples, and then the division may be performed to calculate the signal-to-noise power ratio 608.

[0071] In some embodiments, the controller generates a performance metric 202 of the DUT based at least in part on a comparison between the signal-to-noise power ratio 608 and a plurality of predetermined power thresholds. For example, a plurality of predetermined power thresholds may be stored in a lookup table 612. Each of the plurality of predetermined power thresholds may indicate a corresponding performance metric. For example, each predetermined power threshold may indicate a threshold signal-to-noise power ratio for achieving a particular performance metric. For example, a performance metric may include an SNR metric. In this case, each of the plurality of predetermined power thresholds may indicate a corresponding threshold SNR metric corresponding to each of a plurality of different threshold signal-to-noise power ratios. In some examples, the signal-to-noise power ratio 608 may be provided to a comparator 610, which may compare the signal-to-noise power ratio 608 with a pre-stored value from a lookup table 612 to generate a performance metric 202, such as a signal-to-noise ratio achievable by the DUT.

[0072] In some embodiments, the controller outputs a performance metric. For example, the controller may initiate output of an indication (e.g., a light, a display, etc.) of performing the performance metric. For example, the indication may include a status indicator (e.g., a light, an audible sound, etc.) that may indicate the relative performance of the DUT relative to one or more compliance standards. In addition, or alternatively, the indicator may indicate a performance metric (such as an achievable SNR) and / or one or more contributing parameters of the performance metric (such as an output signal representation, a noise signal representation, a recovered signal representation, and / or a signal-to-noise power ratio, etc.).

[0073] Figure 7 A circuit diagram 700 of an example performance measurement process according to one or more embodiments of the present disclosure is illustrated. The circuit diagram 700 illustrates an example functional circuit representation of the controller circuit system described herein. For example, the circuit representation includes a first portion indicating a power ratio calculation section 210 configured to generate a signal-to-noise power ratio and a second portion indicating a performance calculation section 216 configured to generate a performance metric based at least in part on the signal-to-noise power ratio. The first portion may include a signal and noise separator 304 configured to generate noise and a recovered signal using a notch filter 402 to generate a signal-to-noise power ratio.

[0074] Figure 8A flow chart of an example method 800 for testing a digital device according to one or more embodiments of the present disclosure is illustrated. The flow chart depicts a continuous signal testing technique for testing the performance of a digital device that overcomes various performance limitations of conventional testing techniques. The technique may be implemented by one or more computing devices, entities, and / or systems described herein. For example, via the various steps / operations of method 800, a controller (such as controller 102 described herein) may implement the technique (e.g., via one or more control instructions and / or circuit systems, etc.) to overcome various limitations of conventional testing techniques by enabling phase-independent testing of continuous time signals with full-speed performance testing.

[0075] Figure 8 An example method 800 is illustrated for illustrative purposes. Although the example method 800 depicts a particular order of steps / operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the steps / operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the method 800. In other examples, different components of an example device or system implementing the method 800 may perform functions substantially simultaneously or in a particular order.

[0076] According to some examples, method 800 includes receiving an output signal from the DUT at step / operation 802. For example, the controller 102 may receive an output signal from the DUT based at least in part on an input signal. The input signal may be, for example, a sine wave, and the controller may be configured to generate the input signal by at least generating a modulated pulse and / or filtering the modulated pulse to generate a sine wave. In some examples, the controller and the DUT may be part of the same mixed-signal system, and the controller may test the DUT without external control. In some examples, the DUT may be a continuous-time sigma-delta ADC. In some examples, the controller and the DUT may include, and / or be integrated with, a SoC and / or a SiP.

[0077] According to some examples, method 800 includes generating a noise signal at step / operation 804. For example, controller 102 may generate the noise signal based at least in part on the input signal and the output signal. In some examples, the controller may generate the noise signal by extracting the noise signal from the output signal using a notch IIR filter.

[0078] According to some examples, method 800 includes generating a recovery signal at step / operation 806. For example, controller 102 may generate a recovery signal based at least in part on the output signal and the noise signal. In some examples, the controller may generate the recovery signal by subtracting the noise signal from the output signal. In some examples, the recovery signal and the noise signal may be accumulated for 1024 samples.

[0079] According to some examples, method 800 includes generating a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal at step / operation 808. For example, the controller 102 may generate the signal-to-noise power ratio based at least in part on the recovered signal and the noise signal. For example, the controller may generate the signal power based at least in part on the recovered signal using a first power accumulator, and generate the noise power based at least in part on the noise signal using a second power accumulator. In some examples, the controller may generate the signal-to-noise power ratio based at least in part on the signal power and the noise power.

[0080] According to some examples, method 800 includes generating a performance metric of the DUT based at least in part on a comparison between a signal-to-noise power ratio and a predetermined power threshold at step / operation 810. For example, the controller 102 may generate a performance metric of the DUT based at least in part on a comparison between a signal-to-noise power ratio and a predetermined power threshold. In some examples, the performance metric may be an SNR metric. The predetermined power threshold may be one of a plurality of predetermined power thresholds stored in a lookup table. Each of the plurality of predetermined power thresholds may indicate a corresponding threshold SNR metric. In some examples, the controller may output the performance metric.

[0081] in conclusion

[0082] Those skilled in the art will appreciate many modifications and other embodiments of the disclosure described herein after having benefited from the teachings presented in the above description and the associated drawings. Although the figures only show certain components of the apparatus and system described herein, it should be understood that various other components may be used in conjunction with the system. Therefore, it should be understood that the present disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, the steps in the above method do not necessarily occur in the order depicted in the drawings, and in some cases, one or more of the depicted steps may occur substantially simultaneously, or may involve additional steps. Although specific terms are employed herein, they are used only in a general and descriptive sense, and not for limiting purposes.

[0083] Although various embodiments according to the principles disclosed herein have been shown and described above, those skilled in the art may modify them without departing from the spirit and teachings of the present disclosure. The embodiments described herein are representative only and are not intended to be limiting. Many variations, combinations, and modifications are possible and within the scope of the present disclosure. The disclosed embodiments are primarily directed to BIST devices and techniques for testing digital devices, but those skilled in the art will recognize that these principles can be applied to any electrical system. Alternative embodiments produced by combining, integrating, and / or omitting the features of (one or more) embodiments are also within the scope of the present disclosure. Therefore, the scope of protection is not limited by the above description.

[0084] Additionally, section headings are used herein to provide or otherwise provide an organizational cue consistent with the recommendations under 37 CFR 1.77. Such headings shall not limit or characterize the disclosure set forth in any claims that may be issued from this disclosure.

[0085] The use of broader terms such as "including", "comprising", and "having" should be understood to provide support for narrower terms such as "consisting of", "consisting essentially of", and "consisting essentially of". The use of terms such as "optionally", "may", "perhaps", "might" and the like for any element of an embodiment means that the element is not required, or, alternatively, the element is required, both of which are within the scope of the embodiment. In addition, reference to examples is for illustrative purposes only and is not intended to be exclusive.

[0086] Although the detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, the appended claims may cover any form of semiconductor manufacturing.

[0087] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim.

Claims

1. A controller, configured to: receiving an output signal from a device under test (DUT) based at least in part on the input signal; generating a noise signal based at least in part on the input signal and the output signal; generating a recovery signal based at least in part on the output signal and the noise signal; generating a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal; as well as A performance metric of the DUT is generated based at least in part on a comparison between the signal-to-noise power ratio and a predetermined power threshold.

2. A controller as claimed in claim 1, wherein the performance metric is a signal-to-noise ratio (SNR) metric.

3. The controller of claim 2, wherein the predetermined power threshold is one of a plurality of predetermined power thresholds stored in a lookup table, and each of the plurality of predetermined power thresholds indicates a corresponding threshold SNR metric.

4. The controller of claim 1 , wherein generating a signal-to-noise power ratio comprises: generating a signal power based at least in part on the recovered signal using a first power accumulator; generating a noise power based at least in part on the noise signal using a second power accumulator; as well as A signal-to-noise power ratio is generated based at least in part on the signal power and the noise power.

5. The controller of claim 1 , wherein generating a noise signal comprises: A notch infinite impulse response (IIR) filter is used to extract the noise signal from the output signal.

6. The controller of claim 1 , wherein generating a resume signal comprises: Subtract the noise signal from the output signal.

7. The controller of claim 1, wherein the restored signal and the noise signal are accumulated for 1024 samples.

8. The controller of claim 1, further configured to: The performance metric is output.

9. The controller of claim 1 , wherein the input signal is a sine wave, and the controller is further configured to generate the input signal by at least: generating a modulated pulse; and The modulated pulse is filtered to generate a sine wave.

10. The controller of claim 1, wherein the controller and the DUT are part of the same mixed signal system, and the controller is configured to test the DUT without external control.

11. The controller of claim 1 , wherein the DUT is a continuous-time sigma-delta analog-to-digital converter.

12. A method comprising: receiving an output signal from a device under test (DUT) based at least in part on the input signal; generating a noise signal based at least in part on the input signal and the output signal; generating a recovery signal based at least in part on the output signal and the noise signal; generating a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal; as well as A performance metric of the DUT is generated based at least in part on a comparison between the signal-to-noise power ratio and a predetermined power threshold.

13. The method of claim 12, wherein the performance metric is a signal-to-noise ratio (SNR) metric.

14. The method of claim 13, wherein the predetermined power threshold is one of a plurality of predetermined power thresholds stored in a lookup table, and each of the plurality of predetermined power thresholds indicates a corresponding threshold SNR metric.

15. The method of claim 12, wherein generating a signal-to-noise power ratio comprises: generating a signal power based at least in part on the recovered signal using a first power accumulator; generating a noise power based at least in part on the noise signal using a second power accumulator; as well as A signal-to-noise power ratio is generated based at least in part on the signal power and the noise power.

16. The method of claim 12, wherein generating a noise signal comprises: A notch infinite impulse response (IIR) filter is used to extract the noise signal from the output signal.

17. A system comprising: Device under test DUT; as well as A controller, wherein the controller is configured to: receiving an output signal from the DUT based at least in part on the input signal; generating a noise signal based at least in part on the input signal and the output signal; generating a recovery signal based at least in part on the output signal and the noise signal; generating a signal-to-noise power ratio based at least in part on the recovered signal and the noise signal; as well as A performance metric of the DUT is generated based at least in part on a comparison between the signal-to-noise power ratio and a predetermined power threshold.

18. The system of claim 17, wherein the DUT is a continuous-time sigma-delta analog-to-digital converter.

19. The system of claim 17, wherein the input signal is a sine wave, and the controller is further configured to generate the input signal by at least: generating a modulated pulse; and The modulated pulse is filtered to generate a sine wave.

20. The system of claim 17, wherein the system is a system on chip (SoC) or a system in package (SiP).

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