Channelization processing IP core suitable for spectrum sensing

By designing a channelized processing IP core suitable for spectrum perception, the signal loss problem caused by high hardware resource consumption and cross-channel problems in the prior art is solved, and efficient and real-time spectrum-aware signal processing is achieved.

CN119519865AActive Publication Date: 2025-02-25NAT SPACE SCI CENT CAS
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Patent Information

Application Number
CN202411550962.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-01
Publication Date
2025-02-25
Estimated Expiration
2044-11-01

AI Technical Summary

Technical Problem

The prior art has problems in spectrum perception that high hardware resource consumption or easy to cause cross-channel problems, resulting in signal loss.

Method used

A channelized processing IP core suitable for spectrum perception is designed, including a data preprocessing module, a serial-parallel conversion module, a subband analysis filter, a constant alarm detection module and a subband integrated filter. Through the coordinated work of these modules, spectrum-aware channelized processing without prior information is realized.

Benefits of technology

This technology can effectively avoid cross-channel problems without consuming a large amount of hardware resources, improve signal reception accuracy and real-time performance, and achieve more efficient spectrum perception.

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Abstract

The invention provides a channelized processing IP core suitable for spectrum sensing, and the core comprises a data preprocessing module which is used for receiving broadband spectrum data, generating a high-speed serial data stream, and transmitting the high-speed serial data stream to a serial-to-parallel conversion module; the serial-to-parallel conversion module is used for dividing the high-speed serial data stream into parallel multi-path signals to realize multi-path output of specific bits; the sub-band analysis filter is used for carrying out narrowband division on the multi-channel data and dividing a high-speed broadband signal into a narrowband low-speed signal; the constant false alarm detection module is used for carrying out signal detection on a narrow-band low-speed channel and judging whether a signal exists in the channel or not; and the sub-band synthesis filter is used for combining the data of the sub-channels with the signals. The method has the advantages that the problems of lack of prior information, large data transmission quantity, high resource occupancy rate, difficulty in real-time processing and broadband signal cross-channel in current actual spectrum monitoring can be solved; the method has the advantages of high operation efficiency, good transplantable effect and high reliability.
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Description

Technical Field

[0001] The present application belongs to the field of electromagnetic signal processing, and specifically relates to a channelized processing IP core suitable for spectrum sensing. Background Art

[0002] With the continuous improvement of the informatization level of modern warfare, a large number of communication electronic equipment has been widely used in the military field, making modern military communications show a trend of software-based, intelligent, broadband and networked development. This has led to the diversification of communication systems and communication standards, high-speed transmission rates, and the emergence of an endless stream of communication technologies with anti-interference and low probability of interception.

[0003] With the increase of various communication and radar electronic equipment, the modern electromagnetic space environment is becoming more and more complex. Spectrum sensing scenarios need to face a variety of unfavorable situations such as large instantaneous bandwidth, different carrier frequencies, and low signal-to-noise ratio (SNR). In the actual battlefield environment, more and more military radio stations and detection equipment using different modulation methods and communication protocols are used, which makes the electromagnetic environment increasingly complex, and therefore the requirements for spectrum sensing have become more stringent. In the complex electromagnetic environment of the modern battlefield, higher requirements are placed on the performance of spectrum sensing. RF receivers must have large instantaneous bandwidth, real-time signal reception, large dynamic range, high sensitivity, and strong signal resolution and processing capabilities.

[0004] Digital channelization technology has important research significance in spectrum sensing. Spectrum sensing refers to the real-time full-band scanning and monitoring of the radio spectrum in order to effectively manage and allocate radio spectrum resources, which is crucial for the optimization of radio communication systems, the improvement of spectrum utilization, and the fair allocation of spectrum resources. Digital channelization technology can process the received signals in multiple channels to improve the quality and stability of the signals. Its advantages lie in its high precision, high sensitivity, reconfigurability and easy implementation. These characteristics make it have great potential in spectrum sensing. Its parallel processing method also improves the efficiency of spectrum sensing. In addition, digital channelization technology can also realize adaptive frequency selection and adaptive gain control, so as to better adapt to the signal characteristics of different frequency bands and improve the accuracy and stability of spectrum sensing.

[0005] In terms of implementation, programmable logic devices FPGA or other dedicated computing devices are used to meet the requirements of real-time processing, and can reduce the cost, size and power consumption of the system to a certain extent. Among them, FPGA has greater advantages in development cycle, development difficulty, flexibility, real-time computing, etc.

[0006] FPGA makes it possible to process high-speed data streams in parallel, among which digital channelization technology is the key to solving the contradiction between input bandwidth and real-time signal processing. The essence of digital channelization is to use filter banks in the frequency domain to separate signals of different frequency bands, and then independently complete the signal processing algorithm in each channel.

[0007] Since spectrum sensing is a non-cooperative signal, it needs to be monitored in the entire frequency domain, which puts tremendous pressure on subsequent hardware processing. High data rates will inevitably put higher requirements on hardware cache and real-time processing capabilities, and also bring challenges to chip clock domain design and hardware interface management. Digital channelization technology divides the received broadband signal into multiple sub-bands and processes each sub-band separately, which can divide the broadband signal into narrowband signals, reduce the signal rate, reduce the subsequent hardware processing pressure, and achieve higher reception accuracy and real-time performance.

[0008] In current actual channelization projects, for broadband sparse signals, the amount of data directly processed is huge, which consumes a lot of hardware resources; while uniform channelization is prone to cross-channel problems, resulting in signal loss. In the absence of prior information for spectrum sensing scenarios, direct channel division is prone to cross-channel problems. Summary of the invention

[0009] The purpose of this application is to overcome the defects of the prior art that the hardware resources are consumed high or cross-channel problems are easily generated, resulting in signal loss.

[0010] In order to achieve the above-mentioned purpose, the present application proposes a channelized IP core suitable for spectrum sensing, wherein the IP core comprises a data preprocessing module 1, a serial-to-parallel conversion module 2, a sub-band analysis filter 3, a constant false alarm detection module 4 and a sub-band synthesis filter 5 connected in sequence; wherein:

[0011] The data preprocessing module 1 is used to receive broadband spectrum data, realize data cross-clock domain transmission through FIFO buffer, realize low-speed clock processing of high-speed data between different clock frequencies, and then send the high-speed serial data stream to the serial-to-parallel conversion module 2;

[0012] The serial-to-parallel conversion module 2 is used to divide the high-speed serial data stream into parallel multi-channel signals, and use the LUT lookup table unit inside the FPGA to achieve multi-channel output of a specific bit number;

[0013] The sub-band analysis filter 3 is used to divide the multi-channel data output by the serial-to-parallel conversion module 2 into narrowband, so as to divide the high-speed broadband signal into narrowband low-speed signals;

[0014] The constant false alarm detection module 4 is used to perform signal detection on the narrowband low-speed channel to determine whether there is a signal in the channel, and if so, output yes, and send the data of the sub-channel to the sub-band synthesis filter 5;

[0015] The sub-band synthesis filter 5 is used to merge the data of the sub-channels where signals exist. If a broadband signal is divided into two adjacent sub-channels, that is, there is cross-channel data, then the two channels are merged and output.

[0016] As an improvement of the above-mentioned IP core, the processing process of the subband analysis filter 3 is as follows: determine the number of sub-channels that need to be divided for the input data, and arrange the coefficients into a two-dimensional structure of multi-phase filtering according to the coefficients of the FIR prototype filter, where the number of two-dimensional rows corresponds to the number of sub-channels that need to be divided; then perform an inverse discrete Fourier transform on the output of the multi-phase filtering structure, convolve the signal with the coefficients, and output multiple narrowband sub-channels.

[0017] As an improvement of the above IP core, the process of the constant false alarm detection module 4 detecting the signal in the sub-channel includes: firstly calculating the signal amplitude through square detection, then selecting 2N data points, selecting a unit to be detected D in the middle of the data points, and the left and right sides of the unit to be detected are protection units respectively; then calculating the summed average value of the N points Xn on the left side of the unit to be detected and the summed average value of the N points Yn on the right side of the detection unit, taking the average value as the background noise in the sub-channel, obtaining the noise level nt, and then multiplying the two according to the set detection factor a to obtain the detection threshold, and judging whether there is a signal in the sub-channel by comparing the detection threshold with the unit to be detected.

[0018] As an improvement of the above IP core, the processing process of the sub-band synthesis filter 5 is: according to the operation result of the constant false alarm detection module 4, the sub-channel with the signal is obtained, and all the sub-channels with the signal are subjected to comprehensive filtering. The comprehensive filtering and the analysis filtering are inversely related in structure, and the divided multiple sub-channels are merged into a complete broadband signal.

[0019] Compared with the prior art, the advantages of this application are:

[0020] 1. A channelization processing IP core suitable for spectrum sensing of the present invention is implemented based on FPGA and can perform spectrum sensing without prior information.

[0021] 2. A channelized processing IP core suitable for spectrum sensing of the present invention performs spectrum splicing according to the sensing results to solve the problem of cross-channel occurrence in uniform division.

[0022] 3. A channelized processing IP core suitable for spectrum sensing of the present invention is based on modularization implementation, and constant false alarm detection achieves low false alarm probability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The figure shows a schematic diagram of the structure of a channelization processing IP core suitable for spectrum sensing;

[0024] Figure 2 The figure shows the functional diagram of the sub-band analysis filter of the channelization processing IP core suitable for spectrum sensing;

[0025] Figure 3 Shown is a functional diagram of the constant false alarm detection of the channelized processing IP core suitable for spectrum sensing;

[0026] Figure 4 Shown is a functional diagram of the sub-band synthesis filter of the channelization processing IP core suitable for spectrum sensing. DETAILED DESCRIPTION

[0027] The technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0028] The present application provides a channelization IP core suitable for spectrum sensing. In the absence of prior information, a preliminary uniform channel division is first performed, and then a constant false alarm threshold is calculated based on the signal amplitude in the sub-channel. The cross-channel signal is obtained through threshold detection, and then the cross-channel sub-signal is subjected to a sub-band synthesis filter to obtain a complete reconstructed signal, thereby realizing spectrum sensing channelization processing without prior information.

[0029] The channelized IP core for spectrum sensing provided by the present application includes: a data preprocessing module 1, a serial-to-parallel conversion module 2, a sub-band analysis filter 3, a constant false alarm detection module 4 and a sub-band synthesis filter 5 connected in sequence; wherein:

[0030] The data preprocessing module 1 is used to receive broadband spectrum data from the ADC, realize data transmission across clock domains through FIFO buffer, realize low-speed clock processing of high-speed data between different clock frequencies, and then send it to the serial-to-parallel conversion module 2.

[0031] The serial-to-parallel conversion module 2 is used to divide the high-speed serial data stream output by the data preprocessing module 1 into parallel multi-channel signals, and use the LUT lookup table unit inside the FPGA to achieve multi-channel output of a specific bit number.

[0032] The sub-band analysis filter 3 is used to divide the multi-channel data output by the serial-to-parallel conversion module 2 into narrow-band signals, thereby dividing the high-speed broadband signal into narrow-band low-speed signals.

[0033] The subband analysis filter 3 needs to determine the number of subchannels that the input data needs to be divided into, and arranges the coefficients into a two-dimensional structure of polyphase filtering according to the coefficients of the designed FIR prototype filter, and the number of two-dimensional rows corresponds to the number of subchannels that need to be divided. Then, the output of the polyphase filtering structure is subjected to inverse discrete Fourier transform, the signal is convolved with the coefficients, and multiple narrowband subchannels are output.

[0034] The constant false alarm detection module 4 is used to perform signal detection on the sub-channel output by the sub-band analysis filter 3 to determine whether there is a signal in the channel. If so, it outputs yes and sends the data of the sub-channel to the sub-band synthesis filter 5.

[0035] The constant false alarm detection module 4 needs to detect the signal in the sub-channel. First, the signal amplitude is calculated by square detection, and then 2N data points are selected. A unit D to be detected is selected in the middle of the data points. The left and right sides of the unit to be detected D are protection units respectively. Then, the summed average value of the N points Xn on the left side of the unit to be detected and the summed average value of the N points Yn on the right side of the detection unit are calculated. The average value is used as the background noise in the sub-channel to obtain the noise level nt. Then, according to the set detection factor a, the two are multiplied to obtain the detection threshold. By comparing the detection threshold with the unit to be detected, it is determined whether there is a signal in the sub-channel.

[0036] The sub-band synthesis filter 5 is used to merge the data in the sub-channels output by the constant false alarm detection module 4. If a broadband signal is divided into two adjacent sub-channels, that is, there is cross-channel data, then the two channels are merged and output.

[0037] The sub-band synthesis filter 5 obtains the sub-channels with signals according to the calculation results of the constant false alarm detection, and performs comprehensive filtering on all the sub-channels with signals. The comprehensive filtering and the analysis filtering are inversely related in structure, so that the divided multiple sub-channels can be combined into a complete broadband signal.

[0038] like Figure 1 As shown, the sampled spectrum data first enters the data preprocessing module 1, and then enters the serial-to-parallel conversion module 2 after data cross-clock domain transmission. The data is converted into multiple parallel channels and then sent to the sub-band analysis filter 3. The sub-channel output of the analysis filter is then sent to the constant false alarm detection module 4, and the cross-channel data obtained after the constant false alarm detection is sent to the sub-band synthesis filter 5.

[0039] like Figure 2As shown, the subband analysis filter 3 of the channelization processing IP core suitable for spectrum sensing divides the data into K subchannels. First, the serial-to-parallel converted signal x(n) passes through the delay unit Z to obtain the signal x(nk) at each moment, where n represents the input signal sampling point, and its value is 0, 1…, N; k represents the number of divided channels, and its value is 0, 1,…, K. Then, through the extraction unit, M points are extracted at intervals, and then a prototype low-pass FIR filter h(n) is designed according to the required narrowband bandwidth, and the filter coefficients are converted into a multi-phase filtering structure. The multi-phase structure is to rearrange the filter coefficients from 1 to n, and arrange the FIR filter coefficients from a one-dimensional form to a two-dimensional form. The number of rows of the two-dimensional filter coefficients is equal to the number of divided subchannels. The operation of the filter coefficient and the input signal is essentially a convolution operation. The convolution operation is to perform weighted summation of the data and the coefficients at each moment. Through the formula derivation, in mathematical operations, this weighted summation operation can be quickly implemented through IFFT operation. Through the above operation of the sub-band analysis filter 3, the broadband signal can be divided into a plurality of narrow-band sub-channels.

[0040] like Figure 3 As shown, after the analysis of the subband analysis filter 3, Vk[n] is output, and the output signal is sent to the constant false alarm detection module 4. The constant false alarm detection module 4 first obtains the amplitude value through square detection to obtain a data sequence with a length of 2n+3, selects the middle data point as the unit to be detected D, and the left and right sides of the detection unit are used as protection units, and then selects n data from the left and right sides of the detection unit respectively, and sums xn and yn respectively and takes the average X and Y (X=(x0+x1+…+xn) / n; Y=(y0+y1+…+yn) / n), and then takes the sum of the mean values ​​of X and Y as the background noise to obtain the noise level nt. According to the required constant false alarm detection probability, the detection factor a is designed, and then the noise level is multiplied by the detection factor a to obtain the detection threshold Th, and the detection threshold Th and the unit to be detected D are sent to the comparator for comparison to determine whether there is a signal in the subchannel, and the judgment result is output.

[0041] like Figure 4 As shown, from a structural point of view, the sub-band synthesis filter 5 and the sub-band analysis filter 3 are inversely related, and mainly complete the reconstruction and output of the sub-channel with the signal, ensure the integrity of the broadband signal, and avoid the cross-channel situation. After the constant false alarm detection, the sub-channel with the signal in the result is input into the sub-band synthesis filter 5, and the convolution operation of the signal and the filter coefficient is first realized through DFT, and then the result is sent to the FIR filter of the K-way multi-phase filtering structure. After passing through the filter, the data is interpolated M times, and finally through the delay unit Z, all the data are added and the result of the combined signal is output.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application and are not intended to limit it. Although the present application is described in detail with reference to the embodiments, a person skilled in the art should understand that any modification or equivalent replacement of the technical solution of the present application does not depart from the spirit and scope of the technical solution of the present application and should be included in the scope of the claims of the present application.

Claims

1. A channelized IP core suitable for spectrum sensing, characterized in that: The IP core comprises a data preprocessing module (1), a serial-to-parallel conversion module (2), a sub-band analysis filter (3), a constant false alarm detection module (4) and a sub-band synthesis filter (5) which are connected in sequence; wherein: The data preprocessing module (1) is used to receive broadband spectrum data, realize data cross-clock domain transmission through FIFO buffer, realize low-speed clock processing of high-speed data between different clock frequencies, and then send the high-speed serial data stream to the serial-to-parallel conversion module (2); The serial-to-parallel conversion module (2) is used to divide the high-speed serial data stream into parallel multi-channel signals, and use the LUT lookup table unit inside the FPGA to achieve multi-channel output of a specific bit number; The sub-band analysis filter (3) is used to perform narrow-band division on the multi-channel data output by the serial-to-parallel conversion module (2), thereby dividing the high-speed broadband signal into a narrow-band low-speed signal; The constant false alarm detection module (4) is used to perform signal detection on the narrowband low-speed channel to determine whether there is a signal in the channel, and if so, output a yes signal, and send the data of the sub-channel to the sub-band synthesis filter (5); The sub-band synthesis filter (5) is used to merge the data of the sub-channels where the signals exist. If a broadband signal is divided into two adjacent sub-channels, that is, there is cross-channel data, then the two channels are merged and output.

2. The channelized IP core suitable for spectrum sensing according to claim 1, characterized in that: The processing process of the subband analysis filter (3) is as follows: determining the number of subchannels to be divided of the input data, arranging the coefficients into a two-dimensional structure of polyphase filtering according to the coefficients of the FIR prototype filter, wherein the number of two-dimensional rows corresponds to the number of subchannels to be divided; and then performing inverse discrete Fourier transform on the output of the polyphase filtering structure, convolving the signal with the coefficients, and outputting a plurality of narrowband subchannels.

3. The channelized IP core suitable for spectrum sensing according to claim 1, characterized in that: The process of the constant false alarm detection module (4) detecting the signal in the sub-channel comprises: firstly calculating the signal amplitude through square detection, then selecting 2N data points, selecting a unit to be detected D in the middle of the data points, the left and right sides of the unit to be detected are protection units respectively; then calculating the summed average value of N points Xn on the left side of the unit to be detected and the summed average value of N points Yn on the right side of the detection unit, taking the average value as the background noise in the sub-channel, obtaining the noise level nt, and then multiplying the two according to the set detection factor a to obtain the detection threshold, and judging whether there is a signal in the sub-channel by comparing the detection threshold with the unit to be detected.

4. The channelized IP core suitable for spectrum sensing according to claim 1, characterized in that: The processing process of the sub-band synthesis filter (5) is as follows: according to the operation result of the constant false alarm detection module (4), the sub-channel with the signal is obtained, and all the sub-channels with the signal are subjected to synthesis filtering, the synthesis filtering and the analysis filtering are mutually inverse in structure, and the divided multiple sub-channels are combined into a complete broadband signal.

Citation Information

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