Simulator-based os network data processing mechanism simulation system and simulation method

Abstract

The application provides an emulator-based OS network data processing mechanism simulation system and simulation method, wherein the simulation system comprises nodes, network devices, channels, application programs, protocol stacks, data packet structures, hardware resource management modules and processing simulation modules; the hardware resource management modules are used for providing hardware resources and corresponding hardware parameters for the processing simulation modules; the processing simulation modules generate simulation models of OS network data under preset processing mechanisms based on functions of functions in the emulator, and generate simulation instances according to the simulation models, the hardware resources and the corresponding hardware parameters; the hardware resources, the network devices, the application programs, the data packet structures, the protocol stacks and the simulation instances are included in the nodes, and the nodes are connected through the channels. The simulation process of the application has strong flexibility and scalability for network data processing.

Description

Technical Field

[0001] This invention relates to the field of network simulation, specifically to a simulation system and method for OS network data processing mechanism based on a simulator. Background Technology

[0002] With the development of IoT technology, various smart terminals need to connect to the network, and these smart terminals have high requirements for the real-time performance of network data. The operating systems on existing smart terminals have incorporated various new network technologies to improve network performance. To verify the performance improvements of these technologies and to make further improvements, testing in a network environment is necessary. However, testing in a real-world environment is costly; for example, building a smart industrial robot platform requires significant resources and manpower. Therefore, to reduce testing costs and improve efficiency, network simulators are needed for simulation testing.

[0003] There are many network simulation simulators available, such as ns-3, OPNET, GloMoSim, and SSFNet. However, existing simulators still suffer from inaccurate modeling, especially when processing OS network data. This results in simulation results that differ significantly from those of real network environments, thus reducing the accuracy and efficiency of testing. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a simulator-based OS network data processing mechanism simulation system and method.

[0005] According to a first aspect, the present invention provides a simulator-based OS network data processing mechanism simulation system, comprising: nodes, network devices, channels, applications, protocol stacks, and data packet structures, and further comprising a hardware resource management module and a processing simulation module; the hardware resource management module is used to provide hardware resources and corresponding hardware parameters to the processing simulation module; the processing simulation module generates a simulation model of OS network data under the preset processing mechanism based on a preset processing mechanism and the functions in the simulator, and generates a simulation instance according to the simulation model, the hardware resources, and the corresponding hardware parameters; each node includes the hardware resources, the network devices, the applications, the data packet structures, the protocol stack, and the simulation instance, and the nodes are connected through the channels.

[0006] Preferably, the hardware resource management module includes a resource unit, a resource management unit, and a resource processing unit; the resource unit includes hardware resources and their corresponding hardware parameters; the resource management unit is used to manage the total amount of various types of hardware resources and their current availability; the resource processing unit is used to request hardware resources and their corresponding hardware parameters from the resource management unit.

[0007] Preferably, the hardware resources include a processor, a cache memory, memory, a network interface card (NIC), and a bus; the hardware parameters include cache line size, bus bandwidth, memory bandwidth, memory space, and processor processing speed.

[0008] Preferably, the processing simulation module includes a processing function simulation unit and a storage function simulation unit; the processing function simulation unit includes several sub-units with different processing functions; according to the working principle of the preset processing mechanism, the sub-units are selected and combined, and the functions in the selected sub-units are generated based on the function settings in the simulator to simulate the processing functions in the preset processing mechanism; the storage function simulation unit includes: a control structure and a storage space block; according to the working principle of the preset processing mechanism, the combination and interaction form of the control structure and the storage space block are determined to generate a simulation model simulating the storage functions in the preset processing mechanism; the simulation model of the processing function and the simulation model of the storage function constitute the simulation model of OS network data under the preset processing mechanism.

[0009] Preferably, the processing functional unit includes: a network interface card (NIC) processing subunit, an interrupt processing subunit, a polling processing subunit, a data copying processing subunit, a protocol stack processing subunit, and an application processing subunit; the NIC processing subunit is used to pass data packets to the data copying processing subunit; the interrupt processing subunit is used to simulate the interrupt handling process triggered after data packets are transmitted to the buffer; the polling processing subunit is used to simulate the process of polling and reading data packets from the buffer after the interrupt handling is completed; the data copying subunit is used to simulate the process of data packets being transmitted from the NIC to memory, or from the NIC to a cache memory, or from memory to a cache memory; the protocol stack processing subunit is used to simulate the protocol stack processing process; and the application processing subunit is used to simulate the application processing process.

[0010] According to a second aspect, the present invention provides a method for managing hardware resources in a simulation system as described in the first aspect, comprising: the resource processing unit sending a hardware resource request to the resource management unit, the hardware resource request including the required hardware resources, their demand quantity, and their corresponding hardware parameters; the resource management module allocating the hardware resources to the resource processing module according to the demand quantity based on the current available quantity of the hardware resources in the hardware resource request, and updating the current available quantity of the hardware resources; and reading the hardware parameters of the hardware resources from the resource module and returning them to the resource processing module.

[0011] Preferably, the method further includes: if the resource processing module holds excess hardware resources, it sends a release signal to the resource management module and releases the currently held excess hardware resources; after receiving the release signal, the resource management module reclaims the released excess hardware resources and updates the current available quantity of the hardware resources.

[0012] According to a third aspect, the present invention provides a method for the simulation system of the first aspect, comprising: selecting and combining the sub-units and their functions according to the processing function simulation unit, determining the hardware resources required by the simulation model of the processing function, their demand and corresponding hardware parameters, generating a hardware resource request for the processing function simulation, and sending it to the resource processing unit; determining the combination and interaction form of the control structure and storage space block according to the storage function simulation unit, determining the hardware resources required by the simulation model of the storage function, their demand and corresponding hardware parameters, generating a hardware resource request for the storage function simulation, and sending it to the resource processing unit; the resource processing unit interacts with the resource management unit and the resource unit to provide hardware resources and corresponding hardware parameters for the processing simulation module.

[0013] According to a fourth aspect, the present invention provides a simulation method for an OS network data processing mechanism simulation system based on a simulator, comprising: generating a simulation instance using the hardware resource management module and the processing simulation module according to a preset processing mechanism; adding the simulation instance into a simulator network topology structure composed of the node, the network device, the application program, the data packet structure, the protocol stack, and the channel; and running the simulation instance.

[0014] According to a fifth aspect, the present invention provides a storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the steps of the method as described in any of the second to fourth aspects.

[0015] This invention realizes a complete simulation process for network data processing. Based on the original simulator, it adds modeling of hardware resources and network data processing mechanisms, which improves the reliability of the simulation. It can simulate various hardware environments and network data processing mechanisms, and has strong flexibility and scalability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the module structure of the ns-3 simulator.

[0017] Figure 2 This is a schematic diagram of the network topology of the ns-3 simulator.

[0018] Figure 3 This is a flowchart illustrating the simulation process of network data processing in the simulator under the NAPI mechanism.

[0019] Figure 4 This is an architecture diagram of a hardware resource management module according to an embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram illustrating an implementation method of a hardware resource management module according to an embodiment of the present invention.

[0021] Figure 6 This is a module architecture diagram for simulating an OS network data processing mechanism according to an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram illustrating the interaction between the processing simulation module and the hardware resource module according to an embodiment of the present invention.

[0023] Figure 8 This invention relates to a simulator-based OS network data processing mechanism simulation system according to an embodiment of the present invention.

[0024] Figure 9 This invention relates to a simulation method for a simulator-based OS network data processing mechanism simulation system according to an embodiment of the present invention.

[0025] Figure 10 This is a flowchart illustrating the network data processing process after adding an OS network data processing mechanism to the simulation architecture in this embodiment of the invention. Detailed Implementation

[0026] Specific embodiments of the present invention will now be described in detail. It should be noted that these embodiments are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known procedures, materials, or methods have not been specifically described to avoid obscuring the invention.

[0027] Figure 1 The diagram shows the module structure of the existing network simulator ns-3, including nodes, network devices, channels, applications, protocol stacks, and packet structures. Figure 2 The diagram shows the network topology of the ns-3 simulator. The computer is modeled as a node, and network devices, protocol stacks, and applications are added to the node. Finally, several nodes are connected through channels to form a complete network topology.

[0028] In a real network environment, after data packets arrive at the network interface card (NIC), they need to be processed by an OS-based network data processing mechanism. Commonly used mechanisms include NAPI, Netmap, and DPDK. Taking NAPI as an example, the processing is roughly as follows: After the data packet arrives at the NIC, it is transferred to a circular buffer in memory via DMA. Then, a hardware interrupt is triggered to notify the CPU that a new data packet has arrived. The CPU responds to the interrupt and performs polling, retrieving the data packet from the buffer and performing subsequent protocol stack processing. Finally, the data packet is copied to user space to await application processing. To better understand this invention, the network data processing process in a real network environment is described in detail below using the NAPI mechanism as an example.

[0029] First, after system startup, the network card driver registers information. The system allocates an RX (receive data) ring structure and a TX (transmit data) ring structure, along with corresponding memory areas for storing data packets. It also allocates an skb (socket buffer) structure for protocol stack processing. The network card driver writes the bus addresses (i.e., descriptors) of the memory areas corresponding to the RX and TX rings into the network card register. When a data packet arrives at the network card, it is written into the network card's receive queue. DMA (Direct Memory Access) searches for the next available descriptor in the RX ring and then transfers the data packet from the receive queue to the data buffer pointed to by the descriptor in memory via the I / O bus. The network card triggers a hardware interrupt, notifying the CPU that a data packet has arrived. The hardware interrupt handler places the interrupt request corresponding to the RX ring into a processor core's polling queue and then calls the software interrupt handler. The software interrupt handler calls the `net_rx_action()` function to retrieve the first item from the polling queue, then calls the `poll()` function to retrieve the data packet from the data area corresponding to the RX ring and send it to the kernel network stack handler. After processing, the packet is copied to the corresponding process's buffer (in user space), allowing the user process to process the data packet content. If there are no more data packets in the data area corresponding to the RX ring, the `poll()` function returns, and `net_rx_action()` calls the `napi_complete()` function to remove the first item from the polling queue before returning. If there are still items in the polling queue, `net_rx_action()` continues to retrieve the current first item and then calls `poll()` again. If the number of data packets processed by `poll()` has reached the set weight value, it returns, and `net_rx_action()` adds the item corresponding to the RX ring back to the tail of the polling queue to await the next access. The weight value represents the maximum number of data packets in one RX ring that can be processed at a time. When the weight value is exceeded, data packets on the next RX ring are processed. This is done to ensure that data packets on each RX ring are processed promptly, rather than processing data packets on a single RX ring indefinitely. If the net_rx_action() function has processed the preset number of packets or the processing time exceeds the set value, it returns and exits the soft interrupt procedure to wait for the next scheduling.

[0030] When simulating data processing under the NAPI mechanism in existing simulators (such as the ns-3 simulator), the data packet directly calls a function to trigger protocol stack processing after arriving at the network card, without simulating the above operating system-based processing. Specifically, as follows... Figure 3As shown: After a data packet arrives at the channel, the network interface card (NIC) is notified of the arrival of a new data packet. The NIC's receive function is called to process the corresponding packet header. The data packet is then passed to the protocol stack handler added to the node for processing. The processed data packet is placed in the socket buffer, and the application is notified to read and process the data packet from the socket buffer. Therefore, directly simulating in a simulator cannot completely reproduce the real network environment, and the simulation results may differ significantly from those in the real environment.

[0031] The inventors discovered that in real-world network environments, the computer's hardware itself significantly impacts the speed and results of network data processing. For example, the CPU's processing speed can cause latency in accessing memory devices. The hardware involved in network data processing primarily includes the processor, cache, memory, network interface card (NIC), and bus. Existing simulators focus on protocol stack processing but do not consider the impact of hardware parameters under different environments, nor do they simulate the network data processing mechanisms based on the operating system (OS, a computer program that manages computer hardware and software resources). This leads to significant differences between the overall simulation performance and the performance in the real environment. Therefore, fully considering the impact of computer hardware parameters during simulation will result in more accurate simulation results.

[0032] Based on the above analysis, the inventors proposed a simulator-based OS network data processing mechanism simulation architecture to solve the problem of the lack of hardware resource simulation function and network data processing mechanism simulation function in existing simulators.

[0033] According to one embodiment of the present invention, the hardware resources involved in OS network data processing are modeled as resource units; in order to manage the aforementioned hardware resources, a resource management unit and a resource processing unit are designed, thereby proposing a hardware resource management module. The architecture of the hardware resource management module is as follows: Figure 4As shown, the system includes a resource unit, a resource management unit, and a resource processing unit. The resource unit contains the required hardware resources and the hardware parameters for each type of hardware resource. In some embodiments, the hardware resources include a processor, cache, memory, network interface card (NIC), and bus. In other embodiments, the hardware parameters include cache line size, bus bandwidth, memory bandwidth, memory space, and processor speed. The resource management unit manages the usage of hardware resources, i.e., the total amount and current availability of each type of hardware resource. The resource processing unit requests hardware resources and obtains their corresponding hardware parameters. This unit contains a list of required hardware resources and a list of currently available resources. Specifically, according to one embodiment of the present invention, the resource unit is provided with five types of hardware resources, including processor, cache, memory, network card, and bus. Each hardware resource is implemented by a C++ class, namely, processor resource class cpu_core_resource, cache resource class cache_resource, memory resource class memory_resource, network card resource class nic_resource, and bus resource class bu_resource. Each class sets a specific parameter list for the hardware resource, which is implemented through a structure. It also sets two public member functions, Init() and get_parameter(). Users can set specific parameter values ​​through the Init() function, while the get_parameter() function is used to obtain the parameters of the hardware resource and is called by the resource management unit. The resource management unit is implemented by a C++ class `Resource Manager`. It first sets up a member variable `resource`, implemented as a structure, which contains the total quantity and currently available quantity of five types of hardware resources. It also sets up three member functions: `AllocateResource()`, `RecycleResource()`, and `Getparameter()`. `AllocateResource()` is responsible for allocating resources to the resource management unit; `RecycleResource()` is responsible for reclaiming resources released by the resource management unit; and `Getparameter()` is responsible for handling parameter requests from the resource management unit.The resource processing unit is implemented by a C++ class `process_unit`, which mainly contains four functions: `RequestBufferResource()`, `RequestResource()`, `ReleaseResource()`, and `get_xx_para()`. `RequestBufferResource()` is used to request buffer resources, that is, to request memory or a portion of the cache space according to the required space. `RequestResource()` is used to request other hardware resources, such as CPU, network card, and bus. `ReleaseResource()` is used to release hardware resources. `get_xx_para()` is used to request the required hardware parameters, where `xx` represents the hardware type, such as `get_cpu_para()`, `get_cache_para()`, etc.

[0034] Based on the aforementioned hardware resource management module, this embodiment of the invention proposes an implementation method for the hardware resource management module (i.e., the interaction process between various units within the hardware resource management module), such as... Figure 5 As shown, the process includes: the resource processing unit sending a hardware resource request to the resource management unit, the hardware resource request including the required hardware resources, their demand quantity, and their corresponding hardware parameters (i.e., the requested resources and parameters); the resource management unit allocating hardware resources to the resource processing unit according to the current availability of various types of hardware resources, modifying the current availability of various types of hardware resources, and reading the hardware parameters from the resource unit and returning them to the resource processing unit. In some embodiments, if the resource processing unit holds excess hardware resources (i.e., hardware resources that are not currently in use), it sends a release signal to the resource management unit and releases the excess hardware resources currently held by the resource processing unit (i.e., releasing resources); after receiving the release signal, the resource management unit reclaims the released hardware resources and modifies the current availability of various types of hardware resources. Specifically, according to one embodiment of the present invention, when the resource processing unit needs to request hardware resources, it calls...

[0035] The RequestBufferResource(int flag, int size) or RequestResource(int flag) function is used, and the flag parameter is passed into the function to represent the type of hardware resource required. When requesting storage resources, size needs to be given to represent the size of the required storage space. However, when requesting CPU, network card, or bus resources, only one can be requested at a time, and it is not necessary to specify the number of resources.

[0036] The `RequestBufferResource` and `RequestResource` functions call the `AllocateResource()` function in `ResourceManager`. `AllocateResource()` searches the resource list based on the required hardware resource type (`flag`) and quantity (`num`), and determines if the currently available resources meet the demand (i.e., whether the current available quantity of that type of hardware resource is greater than or equal to the requested quantity `num`). If so, it allocates the resource, updates the current available quantity, and returns `true` to indicate successful allocation; otherwise, it returns `false` to indicate insufficient resources. When the resource processing unit no longer needs a hardware resource, it calls the `ReleaseResource(int flag, int size)` function to release that type of hardware resource. The input parameters `flag` and `size` represent the type and quantity of the hardware resource, respectively. This function calls the `RecycleResource()` function in `ResourceManager`. `RecycleResource()` determines the hardware resources and quantity to return based on `flag` and `size`, and updates the current available quantity of that type of hardware resource. When the resource processing unit needs parameters for a certain type of hardware resource, it calls the get_xx_parameter() function, such as get_cache_parameter(). get_xx_parameter() calls Getparameter() in ResourceManager(). Getparameter() determines which type of hardware resource parameter is needed based on the function name. For example, based on get_cache_parameter(), it knows that the current requirement is for cache parameters, so it calls get_parameter() in cache_resource to obtain the corresponding parameter list.

[0037] To address the lack of hardware resource simulation functionality, this invention models various hardware resources involved in network data processing and manages each hardware resource and its parameters. Based on different hardware environments, different parameters are assigned to the hardware resources, thereby simulating various real-world environments and providing good flexibility.

[0038] According to an embodiment of the present invention, a module for simulating OS network data processing mechanisms (hereinafter referred to as the processing simulation module) is proposed, such as... Figure 6As shown, it includes a processing function simulation unit and a storage function simulation unit. The processing function simulation unit contains several sub-units with different functions. The combination of sub-units and the functional functions within each sub-unit are determined according to the working principle of the preset processing mechanism to completely simulate the process of processing OS network data by the preset processing mechanism. In some embodiments, the several sub-units with different functions are determined according to the processing objectives of each stage in the OS network data processing process, including a network card processing sub-unit, an interrupt processing sub-unit, a polling processing sub-unit, a data copying processing sub-unit, a protocol stack processing sub-unit, and an application processing sub-unit. In some embodiments, the data copying processing sub-unit includes at least one of the following functions: copying data from the network card to memory, copying data from the network card to a buffer, and copying data from memory to a buffer. The specific functions of each processing unit are shown in Table 1.

[0039] Table 1 Functions of each processing unit in the data processing system

[0040]

[0041]

[0042] The storage function simulation unit designs the storage structure required for data processing based on the working principle of the preset processing mechanism. Functionally, it can be divided into a control structure and storage space blocks. The control structure determines whether a storage space block has storage space; if so, the data packet is stored in the corresponding storage space block. The specific form of the control structure and storage space blocks is determined by the preset processing mechanism. The hardware resources and parameters required by the storage module include memory space and memory bandwidth. Specifically, the storage structure mainly contains three structures: RX_Ring, descriptor, and buffer, as detailed in the table below:

[0043]

[0044]

[0045]

[0046]

[0047] Each descriptor represents the control structure of a data packet and corresponds to a buffer. Multiple descriptors are managed by an RX_Ring. When a data packet arrives, the RX_Ring's use_count is checked first to see if there is a free descriptor. If so, NextToUse is used to find the required descriptor, and then the data packet is stored in the corresponding buffer.

[0048] Since the processing function simulation unit and the storage function simulation unit require hardware resources and corresponding hardware parameters during the simulation process, this embodiment of the invention provides an interaction method between the hardware management module and the processing simulation module, namely, the interaction between the processing function simulation unit, the storage function simulation unit, and the resource processing unit. For example... Figure 7 As shown, the processing function simulation unit and the storage function simulation unit each contain a list of required hardware resources and required hardware parameters. Based on the list of required hardware resources and required hardware parameters, a hardware resource request is generated and sent to the resource processing unit. The resource processing unit interacts with the resource unit and the resource management unit in the hardware resource management module according to the implementation method of the hardware resource management module, so as to apply for resources, release resources and request parameters, thereby achieving the purpose of interaction.

[0049] To address the lack of simulation functionality for network data processing mechanisms, this paper breaks down the complete workflow into several sub-units based on the working principle of the processing mechanism. These sub-units are then combined according to a preset processing mechanism, and a storage function simulation unit is designed for this preset mechanism. Furthermore, the interaction between the processing function simulation unit, the storage function simulation unit, and the resource processing unit is designed to improve the realism of the simulation. Users can set the mechanism to be used in the application, i.e., the input parameter `mechanism`. After the system starts running, it will determine the value of `mechanism`. Each value represents a mechanism, such as 0 for the NAPI mechanism, 1 for the Netmap mechanism, etc. The system then creates an instance corresponding to the mechanism (each mechanism is implemented by a class, such as `class NAPI`, `class Netmap`, each class containing its unique storage structure and initialization function. The C++ program will instantiate the class into an object during runtime).

[0050] According to one embodiment of the present invention, a simulator-based OS network data processing mechanism simulation system is proposed, such as... Figure 8 As shown, it includes nodes, network devices, channels, applications, protocol stacks, packet structures, hardware resource management modules, and processing simulation modules. Figure 8This is a topology structure connecting two interconnected nodes, primarily intended to demonstrate the main components of this topology (corresponding to the real environment). The mechanism within this structure is the processing simulation module, and the CPU and other components represent hardware resources. The hardware resource management module is not shown in this diagram. The processing simulation module generates a simulation model of the OS network data under the preset processing mechanism based on the functions in the simulator. It then generates simulation instances based on the simulation model, the hardware resources, and the corresponding hardware parameters. This part involves generating instance objects of the corresponding mechanism based on the `mechanism` value set by the user in the application, including the mechanism's processing functions (such as `Init` and `Receive`) and its unique data structures. Simultaneously, instance objects of all hardware resources and all processing units need to be generated; the specific process will not be elaborated here.

[0051] Each node represents a computer. Hardware resources, network devices, applications, packet structures, protocol stacks, and simulation instances are added to each node, and the nodes are connected by the channel to form a simulator-based OS network data processing mechanism simulation architecture.

[0052] According to an embodiment of the present invention, a simulation method for an OS network data processing mechanism simulation system based on a simulator is proposed, such as... Figure 9As shown, the process includes: modeling hardware resources and establishing a hardware resource management module, which is implemented according to the aforementioned method; establishing a processing simulation module, which is implemented according to the aforementioned method; generating a simulation instance using the hardware resource management module and the processing simulation module according to a preset processing mechanism; adding the simulation instance to a simulator network topology consisting of the node, the network device, the application, the data packet structure, the protocol stack, and the channel, and running the simulation instance. This part has been explained in the preceding content. The mechanism itself is a class containing corresponding processing functions (the processing flow of the mechanism is linked together by a series of processing units), such as `class NAPI`. During runtime, corresponding instance objects are created, containing their unique storage structure and processing functions. A pointer to the mechanism class can also be added to the existing node. By pointing this pointer to the instantiated mechanism object, the mechanism can be added to the node. This paper describes a simulation method for an OS network data processing mechanism simulation architecture based on the ns-3 simulator. The required processing mechanism is obtained from the application (i.e., the preset processing mechanism is determined). The data processing module in the data processing simulation model determines the combination of processing units based on the function functionality in the ns-3 simulator and the preset processing mechanism. Taking the NAPI mechanism as an example, the combination of processing units includes a network interface card (NIC) processing unit, an interrupt processing unit, a polling processing unit, a protocol stack processing unit, an application processing unit, and a data copying processing unit. Taking the Netmap mechanism as an example, unlike NAPI, it does not require a protocol stack processing unit, and its polling process also differs from NAPI, requiring the setting of functions corresponding to the Netmap mechanism within the polling processing unit. The storage module determines the storage structure based on the preset processing mechanism. Based on the combination of processing units, the storage structure, and the hardware management module, an instance corresponding to the preset processing mechanism is created and added to the network topology of the ns-3 simulator for data processing.

[0053] Taking the NAPI mechanism as an example, the simulation process of the simulation architecture for OS network data processing mechanism based on the simulator is as follows: Figure 10 As shown, the process includes: after a data packet is transmitted from the sending end to the receiving end network card, the network card processing unit transmits the data packet from the network card to the buffer in memory via the bus and triggers the interrupt processing unit; the interrupt processing unit adds the current buffer to the waiting queue and then triggers the polling processing unit; the polling processing unit retrieves the data packet from the buffer and transmits it to the protocol stack processing unit; after the protocol stack processing unit processes the data packet, it transmits it to the application processing unit.

[0054] The various embodiments in this specification are described in a progressive manner, with each embodiment illustrating the differences from other embodiments or implementation methods. Similar or identical parts between the various embodiments of the present invention can be referred to mutually. The implementation principles and technical effects surrounding the inventive concept can be referred to mutually, and will not be repeated here. Where there is no conflict, the various embodiments or implementation methods in this invention can be combined with each other.

[0055] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0056] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0057] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can be, for example, including but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0058] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A simulator-based OS network data processing mechanism simulation system, comprising: The system comprises nodes, network devices, channels, applications, protocol stacks, and data packet structures, and is characterized by further including a hardware resource management module and a processing simulation module. The hardware resource management module is used to provide hardware resources and corresponding hardware parameters for the processing simulation module; The processing simulation module includes a processing function simulation unit and a storage function simulation unit. The processing function simulation unit includes several sub-units with different processing functions. Based on the working principle of the preset processing mechanism, the sub-units are selected and combined, and the functions in the selected sub-units are set based on the function settings in the simulator to generate a simulation model simulating the processing function in the preset processing mechanism. The storage function simulation unit includes a control structure and a storage space block. Based on the working principle of the preset processing mechanism, the combination and interaction form of the control structure and the storage space block are determined to generate a simulation model simulating the storage function in the preset processing mechanism. The simulation models of the processing function and the storage function constitute a simulation model of OS network data under the preset processing mechanism, and a simulation instance is generated based on the simulation model, the hardware resources, and the corresponding hardware parameters. The node includes the hardware resources, the network devices, the application, the data packet structure, the protocol stack, and the simulation instance, and the nodes are connected to each other through the channel.

2. The simulation system according to claim 1, characterized in that, The hardware resource management module includes a resource unit, a resource management unit, and a resource processing unit; The resource unit includes hardware resources and their corresponding hardware parameters; The resource management unit is used to manage the total amount of various hardware resources and their current availability; The resource processing unit is used to request hardware resources and their corresponding hardware parameters from the resource management unit.

3. The simulation system according to claim 2, characterized in that, The hardware resources include a processor, a cache memory, memory, a network interface card (NIC), and a bus. The hardware parameters include cache line size, bus bandwidth, memory bandwidth, memory space, and processor processing speed.

4. The simulation system according to claim 1, characterized in that, The processing functional units include: network card processing subunit, interrupt processing subunit, polling processing subunit, data copying processing subunit, protocol stack processing subunit, and application processing subunit. The network interface card (NIC) processing subunit is used to transmit data packets to the data copying processing unit; The interrupt handling subunit is used to simulate the interrupt handling process triggered after a data packet is transmitted to the buffer; The polling processing subunit is used to simulate the process of reading data packets from the buffer after the interrupt handling is completed; The data copying subunit is used to simulate the process of data packets being transferred from the network card to the memory, or the process of data packets being transferred from the network card to the cache memory, or the process of data packets being transferred from the memory to the cache memory. The protocol stack processing subunit is used to simulate the processing of the protocol stack; The application processing subunit is used to simulate the application's processing procedure.

5. A method for managing hardware resources in the simulation system of claim 2, characterized in that, include: The resource processing unit sends a hardware resource request to the resource management unit. The hardware resource request includes the required hardware resources, their quantity, and their corresponding hardware parameters. The resource management unit allocates the hardware resources to the resource processing unit according to the demand based on the current availability of the hardware resources in the hardware resource request, and updates the current availability of the hardware resources. After reading the hardware parameters of the hardware resources from the resource unit, the data is returned to the resource processing unit.

6. The method according to claim 5, characterized in that, Also includes: If the resource processing unit holds excess hardware resources, it sends a release signal to the resource management unit and releases the excess hardware resources it currently holds. After receiving the release signal, the resource management unit will reclaim the released excess hardware resources and update the current available quantity of the hardware resources.

7. A method for the simulation system of claim 2, characterized in that, include: Based on the sub-units and their functions selected and combined by the processing function simulation unit, the hardware resources required for the simulation model of the processing function, their demand and their corresponding hardware parameters are determined, a hardware resource request for processing function simulation is generated and sent to the resource processing unit. The storage function simulation unit determines the combination and interaction form of the control structure and storage space block, determines the hardware resources required for the simulation model of the storage function, their demand and corresponding hardware parameters, generates a hardware resource request for storage function simulation, and sends it to the resource processing unit. The resource processing unit interacts with the resource management unit and the resource unit to provide hardware resources and corresponding hardware parameters to the processing simulation module.

8. A simulation method for a simulator-based OS network data processing mechanism simulation system according to any one of claims 1-4, characterized in that, include: According to the preset processing mechanism, simulation instances are generated using the hardware resource management module and the processing simulation module; The simulation instance is added to the simulator network topology consisting of the node, the network device, the application, the packet structure, the protocol stack, and the channel, and the simulation instance is run.

9. A storage medium, characterized in that, The storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the steps of the method as described in any one of claims 5 to 8.

Images