Backboard bus address automatic distribution circuit and distribution method
By designing a backplane bus address automatic allocation circuit including coupler and slave module, and using components such as frequency division multiple access modules and op amp modules, the problems of poor fault tolerance and multiple slaves requesting addresses in the prior art are solved, and efficient and fault-tolerant automatic allocation is achieved.
Patent Information
- Application Number
- CN202411656398.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-25
AI Technical Summary
The existing backplane bus address automatic allocation circuit has poor fault tolerance during automatic allocation, and cannot effectively handle the situation where multiple slaves request addresses at the same time. It will affect the address allocation of other modules when the module CPU crashes or 3V3 short-circuits.
A backplane bus address automatic allocation circuit including a coupler and slave module is designed, and components such as frequency division multiple access modules and op amp modules are used to power up and allocate addresses to the slave module through the frequency division multiple access module, and in abnormal situations, the transistor is activated using the delay output of the op amp module to skip the fault module.
It realizes automatic allocation effect with fast allocation speed, fewer bus lines occupies backplane and strong fault tolerance. Even if the module CPU crashes or 3V3 short circuit, the address allocation of other modules will not be affected.
Smart Images
Figure CN119520477A_ABST
Abstract
Description
Technical Field
[0001] The invention mainly relates to the technical field of backplane bus address allocation, and in particular to a backplane bus address automatic allocation circuit and allocation method. Background Art
[0002] In the bus communication system, how to automatically assign addresses to slaves is always an important issue. At present, the address setting of slaves is done by hardware, i.e., DIP switches. With the development of intelligence, the host scanning method is gradually used to automatically assign addresses to slaves. With the continuous development of science and technology, people have higher and higher requirements for the manufacturing process of the backplane bus automatic address assignment circuit.
[0003] The existing backplane bus address automatic allocation circuit has certain drawbacks when used. First, when performing automatic allocation, a large number of backplane buses are used, and the fault tolerance is poor; after power-on, when multiple slaves send address allocation requests to the host at the same time, it cannot be processed very conveniently, which is not conducive to people's use; in addition, the allocation structure is relatively simple. In the case of a module CPU freeze or even 3V3 short circuit, it will affect the address allocation of other modules, which will bring certain adverse effects to the actual use process. Summary of the invention
[0004] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a backplane bus address automatic allocation circuit and allocation method with fast allocation speed, small number of backplane buses occupied, and strong fault tolerance.
[0005] In order to solve the above technical problems, the technical solution proposed by the present invention is:
[0006] A backplane bus address automatic allocation circuit comprises a coupler and a plurality of slave modules, wherein the coupler and the plurality of slave modules are sequentially connected via the same backplane bus; the coupler and the slave modules both comprise a power supply unit, a main control module, an operational amplifier module, a frequency division multiple access module and a switch module; the main control module is respectively connected to the operational amplifier module, the switch module and the frequency division multiple access module; the power supply unit comprises an input power supply and an output power supply, the frequency division multiple access module is located between the input power supply and the output power supply; the operational amplifier module and the main control module are both connected to the switch module for controlling the switch of the switch module.
[0007] Preferably, the switch module includes switch tubes Q2 and Q3, the base of Q3 is connected to the main control module, the emitter is grounded, and the collector is connected to the input end of the frequency division multiple access module Q1; the base of Q2 is connected to the operational amplifier module, the emitter is grounded, and the collector is connected to the input end of the frequency division multiple access module Q1.
[0008] Preferably, the switch tubes Q2 and Q3 are both triodes.
[0009] Preferably, the backplane bus includes two differential signal lines and two power lines.
[0010] Preferably, the input power supply and the output power supply are both 5V power supplies.
[0011] The present invention also discloses an automatic allocation method based on the backplane bus address automatic allocation circuit as described above, comprising the steps of:
[0012] During normal power-on, when the coupler is powered on and ready to assign addresses, the slave module is powered on through the frequency division multiple access module. After the slave module is powered on, it actively sends the module type to the coupler. After receiving the slave module type, the coupler assigns an address to the slave module. After the slave module receives its own address, it powers the next slave module through the master control module.
[0013] During abnormal power-on, the output of the operational amplifier module activates the transistor Q2 and the frequency division multiple access module Q1, thereby skipping the slave module to power on and assign addresses to the subsequent slave modules.
[0014] Preferably, during normal power-on, the bus is connected to the switch tube Q3.
[0015] Preferably, when power is turned on abnormally, an operational amplifier module is used to enable a delayed power-on loop, and a signal is output to activate Q1 and Q2 after a short delay.
[0016] Compared with the prior art, the advantages of the present invention are:
[0017] The present invention has the advantages of fast allocation speed, small number of backplane bus lines occupied, and strong fault tolerance. It only needs two differential signal lines and two power lines. Even if a module CPU crashes or even a 3V3 short circuit occurs, it still does not affect the address allocation of other modules, and better automatic allocation processing is performed. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 It is a circuit schematic diagram of a coupler and a slave module in an embodiment of the present invention.
[0019] Figure 2 It is a topological structure diagram of the distribution circuit in an embodiment of the present invention.
[0020] Figure 3 It is a schematic diagram of the state of the distribution circuit of the present invention when it is normally powered on.
[0021] Figure 4 It is a schematic diagram of the state of the distribution circuit of the present invention when it is abnormally powered on. DETAILED DESCRIPTION
[0022] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.
[0023] like Figure 1-Figure 2 As shown, the backplane bus address automatic allocation circuit provided by the embodiment of the present invention includes a coupler and a slave module, wherein the coupler and the slave module both include a main power module (5V input module and 5V output module), an LM321 operational amplifier module, an FDMA frequency division multiple access module Q1, an MCU main control module, a switch module and a backplane bus;
[0024] The coupler and the slave modules are connected by the same backplane bus; the backplane bus includes two differential signal lines and two power lines; the coupler provides power input for the slave modules, and the power supply of the latter slave modules comes from the former slave modules. All slave modules and the coupler are located on the same bus;
[0025] The switch module includes a transistor Q2 and a transistor Q3, the base of the transistor Q3 is connected to the main control module, the emitter is grounded, and the collector is connected to the input end of the frequency division multiple access module Q1; the base of the transistor Q2 is connected to the operational amplifier module, the emitter is grounded, and the collector is connected to the input end of the frequency division multiple access module Q1;
[0026] After the slave module is powered on, it actively sends the information to the host module. After receiving the slave module type, the host module assigns an address to the slave module through the FDMA frequency division multiple access module. After receiving its own address, the slave module supplies power to the next slave module through the MCU main control module.
[0027] When the MCU master module cannot start normally, the LM321 op amp module sets up a delayed output, and delays for a period of time to power on the next slave module and continue to allocate other slave modules;
[0028] The main power supply module is connected to the 5V input module and outputs a 5V voltage. After the coupler is powered on, it powers on the slave module through the FDMA frequency division multiple access module. It has the advantages of fast allocation speed, small number of backplane buses occupied, and strong fault tolerance. It only requires two differential signal lines and two power lines. In the case of a slave module CPU crash or even a 3V3 short circuit, it will not affect the address allocation of other modules, and better automatic allocation processing can be performed.
[0029] In specific applications, the main power supply is connected through the Pmos tube. After the coupler is powered on and ready to assign addresses, the slave module is powered on through Pmos. After the slave module is powered on, it actively sends the module type to the host. After receiving the module type, the host gives the slave module an address. After receiving its own address, the slave module powers the next module through the MCUDO pin.
[0030] When the MCU cannot start normally, the delayed output built by the operational amplifier module LM321 will delay for a period of time to power on the next module and continue to allocate other slave modules. The entire backplane bus address automatic allocation circuit has a simple structure and is easy to operate. The effect of use is better than the traditional method.
[0031] The present invention has the advantages of fast allocation speed, small number of backplane bus lines occupied, and strong fault tolerance. It only needs two differential signal lines and two power lines. Even if a module CPU crashes or even a 3V3 short circuit occurs, it still does not affect the address allocation of other modules, and better automatic allocation processing is performed.
[0032] like Figure 3-Figure 4 As shown, the automatic allocation method of the backplane bus address of the embodiment of the present invention includes two automatic allocation methods, namely normal power-on and abnormal power-on;
[0033] The power supply circuit is connected by the backplane bus, and the bus is connected to Q3 (BC817-40LT1G) when powered on normally;
[0034] In the abnormal power-on circuit, the LM321 op amp module output is used to activate transistor Q2 (BC817-40LT1G) and connected;
[0035] The main power supply is connected through the Pmos tube Q1 (FDMA530PZ). When the coupler is powered on and ready to assign addresses, the slave module is powered on through the Pmos tube Q1 (FDMA530PZ). After the slave module is powered on, it actively sends the module type to the host. After receiving the module type, the host gives the slave module an address. After receiving its own address, the slave module powers the next slave module through the MCUDO pin. Specifically, Figure 3 As shown in the figure, in the normal power-on circuit, the 5V power supply is output from the coupler to the first slave module 1. After the slave module 1 is powered on, it sends the module type to the coupler through the communication bus. The coupler assigns an address to the slave module 1. After the slave module 1 receives the module address, it sends the module type to the coupler through the communication bus. Figure 1 The MCUDO signal of the MCU master module activates transistors Q3 (BC817-40LT1G) and Q1 (FDMA530PZ) to power on the next slave module.
[0036] like Figure 4 As shown, in the abnormal power-on circuit (such as when the MCU cannot start normally), when the previous slave module 1 is abnormal, the LM321 op amp module is used to enable the delayed power-on circuit. After a short delay, the output of the LM321 op amp module activates transistors Q2 (BC817-40LTG) and Q1 (FDMA530PZ), thereby skipping slave module 1 to power on the subsequent slave modules and assign addresses.
[0037] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.
Claims
1. A backplane bus address automatic allocation circuit, characterized in that: It includes a coupler and a plurality of slave modules, wherein the coupler and the plurality of slave modules are connected in sequence through the same backplane bus; the coupler and the slave modules both include a power supply unit, a main control module, an operational amplifier module, a frequency division multiple access module and a switch module; the main control module is respectively connected to the operational amplifier module, the switch module and the frequency division multiple access module; the power supply unit includes an input power supply and an output power supply, and the frequency division multiple access module is located between the input power supply and the output power supply; the operational amplifier module and the main control module are both connected to the switch module for controlling the switch of the switch module.
2. The backplane bus address automatic allocation circuit according to claim 1, characterized in that: The switch module includes switch tubes Q2 and Q3, the base of Q3 is connected to the main control module, the emitter is grounded, and the collector is connected to the input end of the frequency division multiple access module Q1; the base of Q2 is connected to the operational amplifier module, the emitter is grounded, and the collector is connected to the input end of the frequency division multiple access module Q1.
3. The backplane bus address automatic allocation circuit according to claim 2, characterized in that: The switch tubes Q2 and Q3 are both triodes.
4. The backplane bus address automatic allocation circuit according to claim 1, 2 or 3, characterized in that: The backplane bus includes two differential signal lines and two power lines.
5. The backplane bus address automatic allocation circuit according to claim 1, 2 or 3, characterized in that: The input power supply and the output power supply are both 5V power supplies.
6. An automatic allocation method based on the backplane bus address automatic allocation circuit according to any one of claims 2 to 5, characterized in that: Includes steps: During normal power-on, when the coupler is powered on and ready to assign addresses, the slave module is powered on through the frequency division multiple access module. After the slave module is powered on, it actively sends the module type to the coupler. After receiving the slave module type, the coupler assigns an address to the slave module. After the slave module receives its own address, it powers the next slave module through the master control module. During abnormal power-on, the output of the operational amplifier module activates the transistor Q2 and the frequency division multiple access module Q1, thereby skipping the slave module to power on and assign addresses to the subsequent slave modules.
7. The automatic allocation method of the backplane bus address automatic allocation circuit according to claim 6, characterized in that: During normal power-on, the bus is connected to the switch tube Q3.
8. The automatic allocation method of the backplane bus address automatic allocation circuit according to claim 6, characterized in that: In case of abnormal power-on, the operational amplifier module is used to enable the delayed power-on circuit, and then the output signal activates Q1 and Q2 after a short delay.