Semiconductor device

Abstract

The invention relates to a semiconductor device. The semiconductor device may include: a bit line extending in a third direction; a plurality of active layers extending in the first direction and contacting the bit lines; a plurality of word lines extending in the second direction, each word line disposed at a top surface or a bottom surface of each of the plurality of active layers; a plurality of capacitors contacting the plurality of active layers; and a contact formed in at least one active layer disposed at an uppermost portion of the bit line among the plurality of active layers. The bit line and the contact may be electrically connected or separated by using a word line disposed in a top surface or a bottom surface of at least one active layer among the plurality of word lines as a control line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0112026, filed on August 25, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to integrated circuit technology, and more particularly, to semiconductor device technology and applications thereof. Background Art

[0004] Recently, as the market demand for more functional electronic devices with reduced size, lower power consumption and higher performance continues to grow, there is a need for improved semiconductor devices that can reliably store information. Semiconductor devices can be used as storage devices for a variety of electronic devices (such as computers, smart watches, laptops, digital cameras, tablet computers, portable communication devices, and many other portable or non-portable smart devices).

[0005] Generally, in two-dimensional semiconductor devices, various technologies have been developed for reducing the size of semiconductor devices and increasing their data storage capacity, which allow more memory cells to be integrated into an area of ​​a given size by reducing the metal line width. Recently, since the cost, investment cost, and development cycle associated with manufacturing equipment for reducing the metal line width in two-dimensional semiconductor devices have increased exponentially, various methods for manufacturing semiconductor devices having three-dimensional structures have been proposed. Summary of the invention

[0006] In an embodiment of the present disclosure, a semiconductor device may include: a bit line extending in a third direction; a plurality of active layers extending in a first direction and contacting the bit line; a plurality of word lines extending in a second direction, each word line being disposed at a top surface or a bottom surface of each of the plurality of active layers; a plurality of capacitors contacting the plurality of active layers; and a contact formed in at least one active layer disposed at an uppermost portion of the bit line among the plurality of active layers. The bit line and the contact may be electrically connected or separated by using a word line disposed in a top surface or a bottom surface of at least one active layer among the plurality of word lines as a control line.

[0007] In an embodiment of the present disclosure, a semiconductor device may include: a plurality of transistors including a plurality of active layers connected between a bit line and a plurality of capacitors; and a plurality of word lines, each word line being disposed in at least one of a top surface and a bottom surface of each of the plurality of active layers. A transistor disposed at the uppermost portion of a bit line among the plurality of transistors may be used as a bit line selection switch.

[0008] In an embodiment of the present disclosure, a semiconductor device may include: a plurality of transistors including a plurality of active layers connected between a bit line and a plurality of capacitors; and a plurality of word lines, each word line being disposed in at least one of a top surface and a bottom surface of each of the plurality of active layers. A transistor disposed at the uppermost portion of a bit line among the plurality of transistors may be used as a bit line precharge switch.

[0009] These and other features and advantages of the present invention will become better understood from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a simplified schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is a simplified schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3 is a simplified schematic diagram illustrating a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4 is a simplified schematic diagram showing a bit line selection switch of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5 is a simplified schematic diagram showing a bit line precharge switch of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 6 and Figure 7 is a simplified schematic diagram showing connections between a semiconductor device and another semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments according to the technical concept of the present disclosure are described with reference to the accompanying drawings.

[0017] Various embodiments of the present disclosure provide a semiconductor device having a three-dimensional structure, the semiconductor device including a capacitor and a unit transistor arranged in a three-dimensional structure (also referred to as a stack).

[0018] Figure 1 and Figure 2 is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. The third direction III may be a direction orthogonal to a plane defined by the first direction I and the second direction II.

[0019] Now refer to Figure 1 and Figure 2 , a semiconductor device according to an embodiment of the present disclosure may include a bit line BL, an active layer ACT, a word line WL, and a capacitor CAP.

[0020] The bit line BL may have a columnar shape extending along a third direction III. The third direction may be a vertical direction. For example, the bit line BL may be vertically oriented along the third direction III. Therefore, the bit line BL may be represented as a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The bit line BL may include a conductive material. The bit line BL may include, for example, a silicon-based material, a metal-based material, or a combination of a silicon-based material and a metal-based material. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination of polysilicon, a metal, a metal nitride, and a metal silicide. The bit line BL may include polysilicon, titanium, nitrogen, tungsten, or a combination of polysilicon, titanium, nitrogen, and tungsten. For example, the bit line BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities.

[0021] The active layer ACT may contact the bit line BL and may have a strip shape extending in the first direction I. The active layer ACT may include a semiconductor material or an oxide semiconductor material. For example, the active layer ACT may include silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The active layer ACT may include a channel (not shown), a first source / drain region (not shown), and a second source / drain region (not shown).

[0022] The word line WL may extend in the second direction II and may be disposed in at least one of the top surface and the bottom surface of the active layer ACT. The word line WL may be disposed in each of the top surface and the bottom surface of the active layer ACT. In addition, the word line WL may be disposed in one of the top surface and the bottom surface of the active layer ACT. The word line WL may include a metal, a metal mixture, a metal alloy, or a semiconductor material. For example, the word line WL may include titanium nitride, tungsten, polysilicon, or a combination of titanium nitride, tungsten, and polysilicon.

[0023] The capacitor CAP may contact the active layer ACT and may be horizontally disposed along the first direction I. For example, the capacitor CAP may have one end contacting the active layer ACT and may have the other end contacting the plate line PL. The configuration of the capacitor CAP is described later.

[0024] In a semiconductor device according to an embodiment of the present disclosure, a memory cell MC including a word line WL disposed in each of the top surface and the bottom surface of an active layer ACT is described. In the embodiment, a bit line selection switch BLSS and a bit line precharge switch BLPS are described, each including a control line CL disposed below the bottom surface of the active layer ACT in contact with the uppermost portion of the bit line BL (in the direction in which the bit line BL extends). The word line WL and the control line CL may be formed identically, except that the word line WL and the control line CL may provide different functions and be disposed at different positions. In this case, a contact CT extending in a third direction III may have an active layer ACT located between a capacitor CAP and the control line CL of the bit line selection switch BLSS. In addition, the bit line precharge switch BLPS may include a plate line PL contacting the active layer ACT between the capacitor CAP and the control line CL.

[0025] The semiconductor device according to the embodiment of the present disclosure may be formed to include: a bit line BL extending in a vertical direction (i.e., a third direction III); a plurality of active layers ACT contacting the bit line BL and extending in a horizontal direction (i.e., a first direction I); a capacitor CAP contacting each of the plurality of active layers ACT; and a word line WL extending in a second direction II between the bit line BL and each capacitor CAP and disposed in at least one of the top surface and the bottom surface of the active layer ACT. In this case, the contact CT may have an active layer ACT disposed at the uppermost portion of the bit line BL, so that the transistor of the memory cell MC is used as a bit line selection switch BLSS. In addition, by connecting the plate line PL to the active layer ACT disposed at the uppermost portion of the bit line BL, the transistor of the memory cell MC may be used as a bit line precharge switch BLPS. In this case, each word line WL disposed below the bottom surface of the active layer ACT disposed at the uppermost portion of the bit line BL may be referred to as a control line CL.

[0026] Figure 3 is a simplified schematic diagram illustrating a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0027] Reference Figure 3 , the memory cell MC may include a transistor TR and a capacitor CAP.

[0028] The transistor TR may include an active layer ACT arranged in a first direction and a word line WL as a gate of the transistor TR. In this case, the memory cell MC according to an embodiment of the present disclosure may include a word line pair WL1 and WL2 respectively disposed in top and bottom surfaces of the active layer ACT.

[0029] The active layer ACT may include a first source / drain region SR, a channel CH, and a second source / drain region DR. The same conductive impurities may be doped into the first source / drain region SR and the second source / drain region DR. N-type impurities or P-type impurities may be doped into the first source / drain region SR and the second source / drain region DR. A first side of the first source / drain region SR may contact the bit line BL. A second side of the first source / drain region SR may contact the channel CH. A first side of the second source / drain region DR may contact the channel CH. A second side of the second source / drain region DR may contact the storage node SN of the capacitor CAP. Therefore, the channel CH may be disposed between the first source / drain region SR and the second source / drain region DR.

[0030] The word line pair WL1 and WL2 may include a first word line WL1 disposed above the top surface of the active layer ACT and a second word line WL2 disposed below the bottom surface of the active layer ACT. In this case, the first word line WL1 and the second word line WL2 may be disposed to cover the channel CH and may partially overlap the first source / drain region SR and the second source / drain region DR. The word line pair WL1 and WL2 may be represented as a double word line DWL.

[0031] When the difference between the voltage levels of the bit line BL and the word line pair WL1 and WL2 is greater than the threshold voltage, the transistor TR of the memory cell MC constructed as above may be turned on, and thus the bit line BL and the capacitor CAP may be electrically connected. When the difference between the voltage levels of the bit line BL and the word line pair WL1 and WL2 is less than the threshold voltage, the transistor TR of the memory cell MC may be turned off, and thus the bit line BL and the capacitor CAP may be electrically separated.

[0032] The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The capacitor CAP may be disposed adjacent to the transistor TR in a first direction I. The storage node SN may extend horizontally from the active layer ACT in the first direction I. The dielectric layer DE and the plate node PN may be disposed on the storage node SN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged horizontally along the first direction I. The storage node SN may have a horizontally oriented cylindrical shape. The dielectric layer DE may conformally cover the inner and outer walls of the cylinder of the storage node SN. The plate node PN may have a shape extending into the inner and outer walls of the cylinder of the storage node SN on the dielectric layer DE. The plate node PN may contact the plate line PL. The storage node SN may electrically contact the second source / drain region DR.

[0033] The storage node SN may have a three-dimensional structure. The storage node SN may have a horizontal three-dimensional structure oriented along the first direction I. For example, the storage node SN may have a cylindrical shape.

[0034] The plate node PN may include an internal node N1 and external nodes N2, N3 and N4. The internal node N1 and the external nodes N2, N3 and N4 may contact each other. The internal node N1 may be arranged in the tube of the storage node SN. The external nodes N2 and N3 may be arranged outside the tube of the storage node SN, and the dielectric layer DE is inserted between the external nodes N2 and N3. The external node N4 may connect the internal node N1 with the external nodes N2 and N3. The external nodes N2 and N3 may be arranged as the outer wall of the tube surrounding the storage node SN. The external node N4 may play the role of the plate line PL.

[0035] The storage node SN and the plate node PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a noble metal oxide, a metal carbide, a metal silicide, or a combination of a metal, a noble metal, a metal nitride, a conductive metal oxide, a noble metal oxide, a metal carbide, and a metal silicide. For example, the storage node SN and the plate node PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacking or tungsten nitride / tungsten (WN / W) stacking. The plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the plate node PN may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stacking. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the barrel of the storage node SN. Titanium nitride (TiN) may function as a plate node PN of the capacitor CAP. Tungsten nitride may be a low resistance material.

[0036] The dielectric layer DE may include silicon oxide, silicon nitride, a high dielectric constant (high-k) material, or a combination of silicon oxide, silicon nitride and high-k material. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9. The dielectric layer DE may include a high-k material having a dielectric constant of 4 or more. The high-k material may have a dielectric constant of about 20 or more. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanate (SrTiO3). In another embodiment, the dielectric layer DE may include a composite layer including two or more layers of the aforementioned high-k material.

[0037] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO2). The stacked structure including zirconium oxide (ZrO2) may include a ZrO2 / Al2O3 (ZA) stack or a ZrO2 / Al2O3 / ZrO2 (ZAZ) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may be expressed as a zirconium oxide (ZrO2)-based layer. In another embodiment, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO2). The stacked structure including hafnium oxide (HfO2) may include a HfO2 / Al2O3 (HA) stack or a HfO2 / Al2O3 / HfO2 (HAH) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may be expressed as a hafnium oxide (HfO2)-based layer. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a larger band gap than each of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than each of zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0038] In an embodiment, if the capacitor CAP has a metal-insulator-metal (MIM) structure, the storage node SN and the plate node PN may each include a metal-based material.

[0039] In another embodiment, the capacitor CAP may be replaced with another data storage material. For example, the data storage material may include a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0040] The memory cell MC constructed as above may electrically connect or separate the bit line BL and the capacitor CAP by the difference between the voltage levels of the bit line BL and the double word line DWL. In an embodiment, after a read operation or a write operation starts, the bit line BL and the capacitor CAP may be electrically connected.

[0041] Figure 4 is a simplified schematic diagram showing a bit line selection switch of a semiconductor device according to an embodiment of the present disclosure.

[0042] Reference Figure 1 and Figure 2, the bit line selection switch BLSS of the semiconductor device according to the embodiment of the present disclosure may include a control line CL and an uppermost active layer ACT contacting the bit line BL.

[0043] Reference Figure 4 , the active layer ACT included in the bit line selection switch BLSS and contacting the uppermost portion of the bit line BL may include a first source / drain region SR, a channel CH, and a second source / drain region DR. A first side of the first source / drain region SR may contact the bit line BL. A second side of the first source / drain region SR may contact the channel CH. A first side of the second source / drain region DR may contact the channel CH. A second side of the second source / drain region DR may contact the capacitor CAP. In this case, a contact CT extending in the third direction III may be formed in the second source / drain region DR.

[0044] The control line CL may be disposed under the bottom surface of the active layer ACT formed at the uppermost portion of the bit line BL. In this case, the control line CL may be formed to cover the channel CH and may partially overlap the first and second source / drain regions SR and DR.

[0045] The capacitor CAP may have Figure 3 The capacitor CAP shown has the same construction.

[0046] The contact CT may be formed on the source / drain region of the contact capacitor CAP among the first source / drain region SR and the second source / drain region DR of the active layer ACT. The contact CT may extend in the same direction (third direction III) as the bit line BL. The contact CT may contact the conductive line and a local bit line (not shown) extending in a direction different from the third direction III. That is, the contact CT may be connected between the second source / drain region DR and the local bit line extending in a direction different from the third direction III.

[0047] The bit line selection switch BLSS constructed as above can be turned on or off by the difference between the voltage levels of the first source / drain region SR and the control line CL. When the bit line selection switch BLSS is turned on, the bit line selection switch BLSS can electrically connect the bit line BL and the contact CT. Therefore, the local bit line connected to the contact CT can be electrically connected to the bit line BL. As a result, the turned-on bit line selection switch BLSS can electrically connect the vertically oriented bit line BL with the local bit line. The turned-off bit line selection switch BLSS can electrically separate the vertically oriented bit line BL from the local bit line.

[0048] Figure 5 is a simplified schematic diagram showing a bit line precharge switch of a semiconductor device according to an embodiment of the present disclosure.

[0049] Reference Figure 1 and Figure 2 , the bit line precharge switch BLPS of the semiconductor device according to the embodiment of the present disclosure may include a control line CL and an uppermost active layer ACT connected to the bit line BL.

[0050] Reference Figure 5 , the active layer ACT included in the bit line precharge switch BLPS and connected to the uppermost portion of the bit line BL may include a first source / drain region SR, a channel CH, and a second source / drain region DR. A first side of the first source / drain region SR may contact the bit line BL. A second side of the first source / drain region SR may contact the channel CH. A first side of the second source / drain region DR may contact the channel CH. A second side of the second source / drain region DR may contact the capacitor CAP. In this case, the second source / drain region DR may be electrically connected to the plate line PL. That is, the second source / drain region DR and the plate line PL may partially overlap each other.

[0051] The control line CL may be disposed under the bottom surface of the active layer ACT formed at the uppermost portion of the bit line BL. In this case, the control line CL may be formed to cover the channel CH and may partially overlap the first and second source / drain regions SR and DR.

[0052] The capacitor CAP may include a storage node SN, a dielectric layer DE, and a plate node PN. The capacitor CAP may be arranged horizontally along a first direction I. The storage node SN may extend horizontally in the first direction I from the active layer ACT. The dielectric layer DE and the plate node PN may be arranged on the storage node SN. The storage node SN, the dielectric layer DE, and the plate node PN may be arranged horizontally along the first direction I. The storage node SN may have a horizontally oriented cylindrical shape. The dielectric layer DE may conformally cover the inner and outer walls of the cylinder of the storage node SN. The plate node PN may have a shape on the dielectric layer DE in which the plate node PN extends to the inner and outer walls of the cylinder of the storage node SN. In addition, the plate node PN may extend along the first direction I and contact the second source / drain region DR. The plate node PN may contact the plate line PL and the second source / drain region DR. Therefore, the second source / drain region DR of the active layer ACT may be electrically connected to the plate line PL through the plate node PN.

[0053] The bit line precharge switch BLPS constructed as above can be turned on or off by the difference between the voltage levels of the first source / drain region SR and the control line CL. When the bit line precharge switch BLPS is turned on, the bit line precharge switch BLPS can electrically connect the bit line BL and the plate line PL. Therefore, the turned-on bit line precharge switch BLPS can precharge the bit line BL using the cell plate voltage VCP provided to the plate line PL. The bit line precharge switch BLPS can electrically separate the bit line BL and the plate line PL when it is turned off.

[0054] Figure 6 and Figure 7 is a schematic diagram for describing connection between a semiconductor device according to an embodiment of the present disclosure and another semiconductor device.

[0055] Reference Figure 6 and Figure 7 , the first semiconductor device CW may be a first wafer CW including a plurality of memory cells MC.

[0056] The second semiconductor device PW may be a second wafer PW including at least one peripheral circuit such as a sense amplifier SA.

[0057] The first wafer CW may include a bit line BL that has been vertically oriented, and a memory cell MC, a word line WL, and at least one local bit line LBL that contact the vertically oriented bit line BL. As described above, the first wafer CW may include a bit line selection switch BLSS and a bit line precharge switch BLPS, each of which includes an active layer ACT formed at the uppermost portion of the vertically oriented bit line BL and a control line CL formed under the bottom surface of the active layer ACT. The bit line selection switch BLSS may be connected to the local bit line LBL through a contact CT. In addition, the bit line precharge switch BLPS may be connected to a plate line PL, and the second source / drain region DR is provided with a cell plate voltage VCP through the plate line PL. Therefore, the bit line selection switch BLSS may selectively connect the local bit line LBL and the bit line BL that has been vertically oriented. In addition, the bit line precharge switch BLPS may selectively precharge the bit line BL that has been vertically oriented. In this case, the bit line precharge switch BLPS may precharge the level of the bit line BL that has been vertically oriented to the level of the cell plate voltage VCP.

[0058] The first wafer CW and the second wafer PW may be joined via at least one bonding pad (not shown). The local bit line LBL of the first wafer CW may contact the global bit line GBL via the bonding pad. The global bit line GBL may contact the sense amplifier SA. If there is no bit line selection switch BLSS that selectively connects the local bit line LBL and the already vertically oriented bit line BL, the already vertically oriented bit line BL of the first wafer CW may contact the sense amplifier SA of the second wafer PW by using a large number of bonding pads, and a switch that performs the function of the bit line selection switch BLSS needs to be formed in the second wafer PW. However, the semiconductor device according to an embodiment of the present disclosure may require a small number of bonding pads when the first wafer CW and the second wafer PW are joined, because the semiconductor device includes a bit line selection switch BLSS that selectively connects the already vertically oriented bit line BL to the local bit line LBL.

[0059] As a result, the semiconductor device according to the embodiment of the present disclosure can use a transistor disposed in at least one memory cell formed at the uppermost portion of the already vertically oriented bit line BL as a bit line selection switch BLSS that selectively connects the vertically oriented bit line BL to the local bit line LBL.

[0060] In addition, the semiconductor device according to the embodiment of the present disclosure can use a transistor arranged in at least one memory cell formed at the uppermost portion of the vertically oriented bit line BL as a bit line precharge switch BLPS for selectively precharging the vertically oriented bit line BL with the cell plate voltage VCP.

[0061] exist Figure 6 In the above, a structure has been described in which the second wafer PW is disposed on the first wafer CW. Figure 7 As shown, in the embodiments of the present disclosure, even a structure in which the first wafer CW is disposed on the second wafer PW can be used. In one embodiment, Figure 7 It can be one of Figure 6 A structure in which parts or structures have been turned upside down.

[0062] Although the embodiments according to the technical concept of the present disclosure have been described above with reference to the accompanying drawings, these embodiments are provided only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical concept of the present disclosure defined in the attached claims, the technical personnel in the field to which the present disclosure belongs can replace, modify and change the embodiments in various ways. It can be said that these replacements, modifications and changes all belong to the scope of the present disclosure. In addition, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: a bit line extending along a third direction; a plurality of active layers extending along a first direction and contacting the bit lines; a plurality of word lines extending along a second direction, each word line being disposed at a top surface or a bottom surface of each of the plurality of active layers; a plurality of capacitors contacting the plurality of active layers; as well as a contact formed in at least one active layer disposed at an uppermost portion of the bit line among the plurality of active layers, The bit line and the contact are electrically connected or separated by using a word line disposed above the top surface or below the bottom surface of the at least one active layer among the plurality of word lines as a control line.

2. The semiconductor device according to claim 1, wherein Each of the plurality of active layers comprises: a first source / drain region contacting the bit line; a second source / drain region contacting each of the plurality of capacitors; and A channel is disposed between the first source / drain region and the second source / drain region.

3. The semiconductor device according to claim 2, wherein: The contact is formed in the second source / drain region of the at least one active layer among the plurality of active layers, and The contact contacts the local bit line.

4. The semiconductor device according to claim 1, wherein: The third direction is a direction orthogonal to a plane defined by the first direction and the second direction.

5. The semiconductor device according to claim 3, wherein: Each of the plurality of capacitors includes a storage node, a dielectric layer, and a plate node, and The storage node has a cylindrical shape and horizontally contacts the active layer, the dielectric layer is formed to cover inner and outer walls of the cylinder of the storage node, and the plate node extends to the inner and outer walls of the cylinder on the dielectric layer.

6. The semiconductor device according to claim 3, wherein: The local bit line is electrically connected to the global bit line, and The local bit lines and the global bit lines are formed in different wafers.

7. The semiconductor device according to claim 2, wherein: Each of the plurality of word lines covers the channel and partially overlaps the first source / drain region and the second source / drain region.

8. A semiconductor device comprising: a plurality of transistors including a plurality of active layers connected between the bit lines and the plurality of capacitors; as well as a plurality of word lines, each word line being disposed in at least one of a top surface and a bottom surface of each of the plurality of active layers, Among the plurality of transistors, a transistor disposed at an uppermost portion of the bit line is used as a bit line selection switch.

9. The semiconductor device according to claim 8, wherein: Each of the plurality of active layers comprises: a first source / drain region contacting the bit line; a second source / drain region contacting each of the plurality of capacitors; and A channel is disposed between the first source / drain region and the second source / drain region.

10. The semiconductor device according to claim 9, wherein A contact connected to a local bit line contacts the second source / drain region of the bit line selection switch.

11. The semiconductor device according to claim 9, wherein: Each of the plurality of word lines covers the channel and partially overlaps the first source / drain region and the second source / drain region.

12. A semiconductor device comprising: a plurality of transistors including a plurality of active layers connected between the bit lines and the plurality of capacitors; as well as a plurality of word lines, each word line being disposed in at least one of a top surface and a bottom surface of each of the plurality of active layers, Among the plurality of transistors, a transistor disposed at the uppermost portion of the bit line is used as a bit line precharge switch.

13. The semiconductor device according to claim 12, wherein: Each of the plurality of active layers comprises: a first source / drain region contacting the bit line; a second source / drain region contacting each of the plurality of capacitors; and A channel is disposed between the first source / drain region and the second source / drain region.

14. The semiconductor device according to claim 13, wherein: A plate line contacts the second source / drain region of the bit line precharge switch.

15. The semiconductor device according to claim 14, wherein: Each of the plurality of capacitors includes a storage node, a dielectric layer, and a plate node, and The storage node has a cylindrical shape and horizontally contacts the active layer, the dielectric layer is formed to cover the inner and outer walls of the cylinder of the storage node, and the plate node has a shape on the dielectric layer in which the plate node extends to the inner and outer walls of the cylinder.

16. The semiconductor device according to claim 15, wherein: The plate node contacts the plate line and the second source / drain region of the bit line precharge switch.

17. The semiconductor device according to claim 13, wherein: Each of the plurality of word lines covers the channel and partially overlaps the first source / drain region and the second source / drain region.

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