Semiconductor device and method for manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a bit line; a plurality of first semiconductor pillars disposed over the bit lines; a plurality of first cell contact plugs disposed between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first cell contact plugs; a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; and a plurality of capacitors coupled to the second semiconductor pillars and the second cell contact plugs, respectively.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0111117, filed on August 24, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a vertical transistor and a method for manufacturing the semiconductor device. Background Art

[0004] For high integration of semiconductor devices, a transistor having a vertical channel (hereinafter, which may be simply referred to as a "vertical transistor") has been proposed.

[0005] Vertical transistors using single crystal silicon as a channel have limitations in terms of integration. Moreover, electrical characteristics may be degraded due to gate induced drain leakage (GIDL) and junction leakage of the PN junction occurring in the overlap region between the source / drain and the gate. Therefore, an improved structure for improving integration and performance is needed. Summary of the invention

[0006] Embodiments of the present invention relate to a highly integrated semiconductor device and a method for manufacturing the semiconductor device.

[0007] According to one embodiment of the present invention, a semiconductor device includes: a bit line; a plurality of first semiconductor pillars arranged above the bit line; a plurality of first unit contact plugs arranged between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first unit contact plugs; a plurality of second unit contact plugs arranged between the second semiconductor pillars and coupled to the first semiconductor pillars; and a plurality of capacitors coupled to the second semiconductor pillars and the second unit contact plugs, respectively.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a bit line above a substrate; forming a first semiconductor column above the bit line; forming a plurality of first unit contact plugs coupled to the bit line between the first semiconductor columns; forming a second semiconductor column above the first unit contact plug; forming a plurality of second unit contact plugs disposed between the second semiconductor columns and coupled to the first semiconductor column; and forming a plurality of capacitors respectively coupled to the second semiconductor column and the second unit contact plug. The method also includes: forming a first interlayer dielectric layer covering the bit line between the first semiconductor columns; forming a first contact hole in the first interlayer dielectric layer exposing the bit line; forming a first contact spacer on the sidewall of the first contact hole; and filling the first contact hole with a conductive layer to form the first unit contact plug above the first contact spacer. The method also includes: forming a second interlayer dielectric layer between the second semiconductor columns; forming a second contact hole in the second interlayer dielectric layer exposing the upper surface of the first semiconductor column; forming a second contact spacer on the sidewall of the second contact hole; and filling the second contact hole with a conductive layer to form a second unit contact plug above the second contact spacer. The method also includes before forming the first unit contact plug: forming a first gate dielectric layer on the sidewall of the first semiconductor column; and forming a first vertical gate of a dual structure above the first gate dielectric layer, the first vertical gate being disposed on both sidewalls of each first semiconductor column in the first semiconductor column. The method also includes before forming the second unit contact plug: forming a second gate dielectric layer on the sidewall of the second semiconductor column; and forming a second vertical gate of a dual structure above the second gate dielectric layer, the second vertical gate being disposed on the sidewall of the second semiconductor column. Forming a bit line and forming a first semiconductor column include: forming a conductive layer above a substrate; forming an oxide semiconductor stack above the conductive layer; forming an oxide semiconductor line by etching the oxide semiconductor stack; etching the conductive layer to form a bit line; and etching the oxide semiconductor line in a direction intersecting the bit line to form a first semiconductor column. The method also includes: forming a tapered dual vertical gate on both sidewalls of each first semiconductor column in the first semiconductor column and on both sidewalls of each second semiconductor column in the second semiconductor column.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a horizontal conductive line; a first level including a first semiconductor column and a first contact plug disposed above the horizontal conductive line; a second level including a second semiconductor column and a second contact plug disposed above the first level; and a third level disposed above the second level, wherein the second contact plug is vertically stacked above the first semiconductor column, and the second semiconductor column is vertically stacked above the first contact plug. The first semiconductor column and the first contact plug may be spaced apart from each other, and the second semiconductor column and the second contact plug may be spaced apart from each other. The first level may include an array of a plurality of first vertical channel transistors. The second level may include an array of a plurality of second vertical channel transistors. The third level may include an array of a plurality of capacitors. The semiconductor device may also include a first-level vertical conductive line of a dual structure disposed on both sidewalls of each first semiconductor column in the first semiconductor column. The semiconductor device may also include a second-level vertical conductive line of a dual structure disposed on both sidewalls of each second semiconductor column in the second semiconductor column.

[0010] These and other features and advantages will become better understood from the following drawings and detailed description of embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

[0012] Figure 2A is along Figure 1 Schematic plan view taken along line A1 - A1 ′ shown in FIG.

[0013] Figure 2B is along Figure 1 Schematic plan view taken along line A2-A2' shown in FIG.

[0014] Figure 2C is along Figure 1 Schematic cross-sectional view taken along line A3-A3' shown in FIG.

[0015] Figure 2D is along Figure 2C A schematic cross-sectional view taken along line A4-A4' is shown in FIG.

[0016] Figure 3A is a cross-sectional view illustrating a first vertical transistor.

[0017] Figure 3B is a cross-sectional view illustrating a second vertical transistor.

[0018] Figures 4 to 32 A method for manufacturing a semiconductor device according to one embodiment of the present invention is illustrated.

[0019] Figure 33 to Figure 35 A method for manufacturing a semiconductor device according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout the present disclosure, throughout the various drawings and embodiments of the present invention, similar reference numerals refer to similar parts.

[0021] The drawings are not necessarily to scale, and in some instances, the proportions may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, this refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0022] Figure 1 is a schematic cross-sectional view illustrating the semiconductor device 100 . Figure 2A is along Figure 1 Schematic plan view taken along line A1 - A1 ′ shown in FIG. Figure 2B is along Figure 1 Schematic plan view taken along line A2-A2' shown in FIG. Figure 2C is along Figure 1 Schematic cross-sectional view taken along line A3-A3' shown in FIG. Figure 2D is along Figure 2C A schematic cross-sectional view taken along line A4-A4' is shown in FIG. Figure 3A is a detailed cross-sectional view illustrating a first vertical transistor. Figure 3B is a detailed cross-sectional view illustrating a second vertical transistor.

[0023] Reference now Figure 1 , Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 3A and Figure 3B, the semiconductor device 100 may include a horizontal conductive line 110 and a first, second and third level. The first level includes a first semiconductor column 120 and a first cell contact plug CT1 disposed above the horizontal conductive line 110. The second level is disposed above the first level and includes a second semiconductor column 130 and a second cell contact plug CT2 disposed above the first level. The third level is disposed above the second level. The second cell contact plug CT2 may be vertically stacked above the first semiconductor column 120, and the second semiconductor column 130 may be vertically stacked above the first cell contact plug CT1. The first semiconductor column 120 and the first cell contact plug CT1 may be spaced apart from each other. The second semiconductor column 130 and the second cell contact plug CT2 may be spaced apart from each other. The first level may include an array VTA1 of a plurality of first vertical transistors VT1. The second level may include an array VTA2 of a plurality of second vertical transistors VT2. The third level may include an array of a plurality of data storage elements CAP1 and CAP2. A first level-vertical conductive line 122 of a dual structure may be disposed on both sidewalls of the first semiconductor column 120. A second level-vertical conductive line 132 of a dual structure may be disposed on both sidewalls of the second semiconductor pillar 130. The first level-vertical conductive line 122 and the second level-vertical conductive line 132 may extend in the second direction D2.

[0024] Hereinafter, the first horizontal conductive line 110 may be simply referred to as a “bit line 110 .” The first tier-vertical conductive line 122 and the second tier-vertical conductive line 132 may be simply referred to as a “first vertical gate 122 and a second vertical gate 132 ,” respectively.

[0025] The semiconductor device 100 may include a substrate 101, a buried conductive multilayer line structure BBL, a first vertical transistor array VTA1, a second vertical transistor array VTA2, and a data storage element array CAP. The semiconductor device 100 may include a memory cell array.

[0026] The buried conductive multilayer line structure BBL may include a stack of a bit line 110 and a barrier layer 111 disposed above the bit line 110. The buried conductive multilayer line structure BBL may be disposed above a substrate 101, and a buffer layer 102 may be disposed between the substrate 101 and the buried conductive multilayer line structure BBL. Figure 2A , the buried conductive multilayer line structure BBL may extend in a first direction D1. In some embodiments, the first direction D1 may be a horizontal direction.

[0027] The first vertical transistor array VTA1 may include a three-dimensional array of a plurality of first vertical transistors VT1. Each of the first vertical transistors VT1 may include a first semiconductor pillar 120, a first gate dielectric layer 121 formed on both sidewalls of the first semiconductor pillar 120, and a first vertical gate 122 formed above the first gate dielectric layer 121. The first vertical gate 122 may include a pair of a first tapered gate WL1 and a second tapered gate WL2. Each of the first vertical transistors VT1 may also include a first pillar pad 123 disposed above the first semiconductor pillar 120. Figure 2A , the first tapered gate WL1 and the second tapered gate WL2 may extend in the second direction D2. The first vertical gate 122 may be referred to as a “first vertical word line”, and the first tapered gate WL1 and the second tapered gate WL2 may be referred to as a “first tapered word line” and a second tapered word line, respectively.

[0028] The second vertical transistor array VTA2 may include a three-dimensional array of a plurality of second vertical transistors VT2. Each second vertical transistor VT2 may include a second semiconductor pillar 130, a second gate dielectric layer 131 formed on both sidewalls of the second semiconductor pillar 130, and a second vertical gate 132 formed above the second gate dielectric layer 131. The second vertical gate 132 may include a pair of a first tapered gate WL11 and a second tapered gate WL12. Each second vertical transistor VT2 may also include a second column pad 133 disposed above the corresponding second semiconductor pillar 130. Reference Figure 2B , the first tapered gate WL11 and the second tapered gate WL12 may extend in the second direction D2. The second vertical gate 122 may be referred to as a "second vertical word line", and the first tapered gate WL11 and the second tapered gate WL12 may be referred to as a "first tapered word line" and a "second tapered word line", respectively.

[0029] The first semiconductor pillar 120 and the second semiconductor pillar 130 may extend vertically in the third direction D3. The first semiconductor pillar 120 and the second semiconductor pillar 130 may be referred to as active pillars or channel pillars.

[0030] The data storage element array CAP may include a landing pad 141 disposed above the second vertical transistor array VTA2, a first electrode SN above the landing pad 141, a plurality of support members SUP1 and SUP2 supporting the outer wall of the first electrode SN, a dielectric layer DE formed above the first electrode SN and the support members SUP1 and SUP2, and a second electrode PN formed above the dielectric layer DE. The data storage element array CAP may include a capacitor array. For example, the data storage element array CAP may include: a first capacitor array including a plurality of first capacitors CAP1, and a second capacitor array including a plurality of second capacitors CAP2. The individual first capacitors CAP1 and the individual second capacitors CAP2 may have the same structure and may include a first electrode SN, a dielectric layer DE, and a second electrode PN, wherein the dielectric layer DE is disposed between the first electrode SN and the second electrode PN. The first electrodes SN of the individual first capacitors CAP1 and the individual second capacitors CAP2 may have a columnar structure. The first electrodes SN of the first capacitor CAP1 and the second capacitor CAP2 may include a cylindrical electrode SN1 and a columnar electrode SN2 filling the interior of the cylindrical electrode SN1. Return to reference Figure 2C , adjacent first electrodes SN may be arranged in a zigzag arrangement to form an array of a honeycomb structure.

[0031] The landing pads 141 may be spaced apart from each other at regular intervals in the interlayer dielectric layer 142 and may pass through the interlayer dielectric layer 142 to contact the corresponding second contact plugs CT2 and second spacers SP2 at their bottom ends and contact the tubular electrode SN1 at their top ends. An etch stop layer 143 may be disposed over the interlayer dielectric layer 142 .

[0032] The first vertical transistor array VTA1 may further include a first cell contact plug CT1. The first cell contact plug CT1 may be disposed between the first vertical transistors VT1. The first cell contact plug CT1 may be disposed between the first vertical gates 122 of the first vertical transistors VT1.

[0033] The first contact spacer SP1 may be disposed on an outer wall of the first cell contact plug CT1. The first contact spacer SP1 may surround an outer wall of the first cell contact plug CT1. The first contact spacer SP1 may include a dielectric material, and the first cell contact plug CT1 may include a conductive material. The first cell contact plug CT1 may be electrically connected to the bit line 110 and the second semiconductor pillar 130. The first cell contact plug CT1 may extend vertically from the bit line 110 in the third direction D3, and the second semiconductor pillar 130 may extend vertically from the first cell contact plug CT1 in the third direction D3.

[0034] The second vertical transistor array VTA2 may further include a second cell contact plug CT2 disposed between the second vertical transistors VT2. A second contact spacer SP2 may be disposed on an outer wall of the second cell contact plug CT2. The second contact spacer SP2 may surround an outer wall of the second cell contact plug CT2. The second contact spacer SP2 may include a dielectric material, and the second cell contact plug CT2 may include a conductive material. Return to Reference Figure 2D , the second cell contact plug CT2 may be electrically connected to the first semiconductor pillar 120 through the first pillar pad 123. The first semiconductor pillar 120 may vertically extend from the bit line 110 in the third direction D3. The second cell contact plug CT2 may also vertically extend from the first semiconductor pillar 120 in the third direction D3.

[0035] The first vertical structure VS1 indicated by one vertical arrow includes the bit line 110, the first semiconductor pillar 120, the second cell contact plug CT2, and the landing pad 141 (which are stacked in the order mentioned), and may be coupled to the first capacitor CAP1. The second vertical gate 132 and the second cell contact plug CT2 may be isolated from each other by the second contact spacer SP2.

[0036] The second vertical structure VS2 indicated by another vertical arrow includes the bit line 110, the first cell contact plug CT1, the second semiconductor pillar 130, and the landing pad 141 (which are stacked in the order mentioned), and can be coupled to the second capacitor CAP2. The first vertical gate 122 and the first cell contact plug CT1 can be isolated from each other by the first contact spacer SP1.

[0037] The substrate 101 may be a material suitable for semiconductor processing. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of a material containing silicon. The substrate 101 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 101 may also include another semiconductor material, such as germanium. The substrate 101 may include a III / V semiconductor substrate, for example a compound semiconductor substrate, such as GaAs. The substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0038] The buffer layer 102 may include silicon oxide, silicon nitride, or a combination thereof. To reduce parasitic capacitance, the buffer layer 102 may be formed of silicon oxide. For example, the buffer layer 102 may include tetraethyl orthosilicate (TEOS).

[0039] The bit line 110 may extend horizontally in the first direction D1 above the buffer layer 102. The bit line 110 may include a metal-based material. The bit line 110 may include a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line 110 may have a thickness of about 100 nm. arrive The bit line 110 may include a tungsten layer.

[0040] The barrier layer 111 may include a metal, a metal nitride, a metal silicide, or a combination thereof. The barrier layer 111 may include titanium nitride, molybdenum, or ruthenium. The barrier layer 111 may have a thickness of about arrive For example, the barrier layer 111 may include a titanium nitride layer.

[0041] Return to reference Figure 3A and Figure 3B , the first semiconductor pillar 120 may include a first lower interface layer 120L, a first upper interface layer 120U, and a first channel layer 120P between the first lower interface layer 120L and the first upper interface layer 120U. The second semiconductor pillar 130 may be formed in the same structure as the first semiconductor pillar 120. The second semiconductor pillar 130 may include a second lower interface layer 130L, a second upper interface layer 130U, and a second channel layer 130P between the second lower interface layer 130L and the second upper interface layer 130U.

[0042] The first semiconductor pillar 120 and the second semiconductor pillar 130 may include an oxide semiconductor layer. The first semiconductor pillar 120 and the second semiconductor pillar 130 may be oxide semiconductor pillars. The first lower interface layer 120L, the first upper interface layer 120U, and the first channel layer 120P may include an oxide semiconductor layer. The second lower interface layer 130L, the second upper interface layer 130U, and the second channel layer 130P may include an oxide semiconductor layer.

[0043] The first vertical gate 122 and the second vertical gate 132 may have a tapered vertical word line structure.

[0044] The first lower interface layer 120L and the second lower interface layer 130L and the first upper interface layer 120U and the second upper interface layer 130U may include an oxide semiconductor material having a lower resistance than the first channel layer 120P and the second channel layer 130P. The first lower interface layer 120L and the second lower interface layer 130L and the first upper interface layer 120U and the second upper interface layer 130U may include a metal-rich oxide semiconductor material, and the first channel layer 120P and the second channel layer 130P may include an oxygen-rich oxide semiconductor material. For example, the first channel layer 120P and the second channel layer 130P may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (IZTO) or zinc tin oxide (ZTO), and the first lower interface layer 120L and the second lower interface layer 130L and the first upper interface layer 120U and the second upper interface layer 130U may include indium-rich IGZO. Indium-rich IGZO may refer to a material having a higher indium content than gallium (Ga) and zinc (Zn) in IGZO, for example, the indium content may be 40% or more.

[0045] The first channel layer 120P and the second channel layer 130P may include an oxide semiconductor material. The first channel layer 120P and the second channel layer 130P may contain indium. The first channel layer 120P and the second channel layer 130P may include IGZO. The first channel layer 120P and the second channel layer 130P may be formed to have approximately arrive Thickness.

[0046] The first lower interface layer 120L and the second lower interface layer 130L may include an oxide semiconductor material. The first lower interface layer 120L and the second lower interface layer 130L may contain indium. The first lower interface layer 120L and the second lower interface layer 130L may include an indium-rich oxide semiconductor material. For example, the first lower interface layer 120L and the second lower interface layer 130L may include indium-rich IGZO. The first lower interface layer 120L and the second lower interface layer 130L may be formed to have a thickness of about arrive Thickness.

[0047] The first upper interface layer 120U and the second upper interface layer 130U may include an oxide semiconductor material. The first upper interface layer 120U and the second upper interface layer 130U may contain indium. The first upper interface layer 120U and the second upper interface layer 130U may include an indium-rich oxide semiconductor material. For example, the first upper interface layer 120U and the second upper interface layer 130U may include indium-rich IGZO. The first upper interface layer 120U and the second upper interface layer 130U may be formed to have a thickness of about arrive Thickness.

[0048] The first semiconductor pillar 120 and the second semiconductor pillar 130 may extend vertically in the third direction D3 above the bit line 110. The first semiconductor pillar 120 and the second semiconductor pillar 130 may include a first lower interface layer 120L and a second lower interface layer 130L, a first channel layer 120P and a second channel layer 130P, and a first upper interface layer 120U and a second upper interface layer 130U (which are vertically stacked in the order mentioned). The first lower interface layer 120L and the second lower interface layer 130L, the first channel layer 120P and the second channel layer 130P, and the first upper interface layer 120U and the second upper interface layer 130U may all include an oxide semiconductor material. The first lower interface layer 120L and the second lower interface layer 130L, the first channel layer 120P and the second channel layer 130P, and the first upper interface layer 120U and the second upper interface layer 130U may all include IGZO, and the first lower interface layer 120L and the second lower interface layer 130L and the first upper interface layer 120U and the second upper interface layer 130U may have a greater indium concentration than the first channel layer 120P and the second channel layer 130P. The first channel layer 120P and the second channel layer 130P may be IGZO, and the first lower interface layer 120L and the second lower interface layer 130L and the first upper interface layer 120U and the second upper interface layer 130U may be indium-rich IGZO. The first semiconductor pillar 120 and the second semiconductor pillar 130 may be referred to as an active pillar.

[0049] The first vertical gate 122 may be disposed on the sidewall of the first semiconductor column 120. The first vertical gate 122 may have a dual structure of a first tapered gate WL1 and a second tapered gate WL2. The first vertical gate 122 and the bit line 110 may extend in directions intersecting each other. The first vertical gate 122 may have an inverted tapered shape. The inverted tapered shape may refer to a shape in which the width of the bottom portion becomes smaller than the width of the top portion. The first vertical gate 122 may include a first lower level portion 122L disposed adjacent to the bottom portion of the first semiconductor column 120 and a first upper level portion 122U disposed adjacent to the top portion of the first semiconductor column 120. The thickness of the first lower level portion 122L in the first direction D1 may be thinner than the thickness of the first upper level portion 122U. The first lower level portion 122L may be disposed adjacent to the first lower interface layer 120L, and the first upper level portion 122U may be disposed adjacent to the first upper interface layer 120U. The first lower-level portion 122L and the first upper-level portion 122U may be formed of the same material and may have an integrated structure.

[0050] The first vertical gate 122 may include a metal-based material. The first vertical gate 122 may include a metal, a metal nitride, or a combination thereof. The first vertical gate 122 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof.

[0051] The first gate dielectric layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The first gate dielectric layer 121 may be disposed between the first semiconductor pillar 120 and the first vertical gate 122. The first gate dielectric layer 121 may include a flat portion extending to be disposed between a lower level portion of the first vertical gate 122 and the bit line 110, and the flat portion of the first gate dielectric layer 121 may directly contact the barrier layer 111. The first vertical gate 122 may be referred to as a first tapered vertical gate or a first tapered vertical word line.

[0052] The second vertical gate 132 may be disposed on the sidewall of the second semiconductor column 130. The second vertical gate 132 may have a dual structure of a first tapered gate WL11 and a second tapered gate WL12. The second vertical gate 132 and the bit line 110 may extend in directions intersecting each other. The second vertical gate 132 may have an inverted tapered shape. The term "inverted tapered shape" as used herein refers to a shape in which the width of the bottom portion becomes smaller than the width of the top portion. The second vertical gate 132 may include a second lower level portion 132L disposed adjacent to the bottom portion of the second semiconductor column 130 and a second upper level portion 132U disposed adjacent to the top portion of the second semiconductor column 130. The thickness of the second lower level portion 132L in the first direction D1 may be thinner than the thickness of the second upper level portion 132U. The second lower level portion 132L may be disposed adjacent to the second lower interface layer 130L, and the second upper level portion 132U may be disposed adjacent to the second upper interface layer 130U. The second lower-level portion 132L and the second upper-level portion 132U may be formed of the same material and may have an integrated structure.

[0053] The second vertical gate 132 may include a metal-based material. The second vertical gate 132 may include a metal, a metal nitride, or a combination thereof. The second vertical gate 132 may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof.

[0054] The second gate dielectric layer 131 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The second gate dielectric layer 131 may be disposed between the second semiconductor pillar 130 and the second vertical gate 132. The second gate dielectric layer 131 may include a flat portion extending to be disposed between the lower level portion of the second vertical gate 132 and the bit line 110, and the flat portion of the second gate dielectric layer 131 may directly contact the first contact spacer SP1 and / or the first interlayer dielectric layer 124. The second vertical gate 132 may be referred to as a second tapered vertical gate or a second tapered vertical word line.

[0055] The first cell contact plug CT1 and the second cell contact plug CT2 may include a metal-based material. The first cell contact plug CT1 and the second cell contact plug CT2 may include a metal, a metal nitride, or a combination thereof. The first cell contact plug CT1 and the second cell contact plug CT2 may be formed of the same metal-based material. According to another embodiment of the present invention, the first cell contact plug CT1 and the second cell contact plug CT2 may be formed of different metal-based materials.

[0056] The first contact spacer SP1 and the second contact spacer SP2 may include a dielectric material. For example, the first contact spacer SP1 and the second contact spacer SP2 may include silicon oxide, silicon nitride, or a combination thereof.

[0057] The first column pad 123 and the second column pad 133 may include a metal-based material. The first column pad 123 and the second column pad 133 may include a metal, a metal nitride, or a combination thereof. The first column pad 123 and the second column pad 133 may be formed of the same metal-based material. According to another embodiment of the present invention, the first column pad 123 and the second column pad 133 may be formed of different metal-based materials. The sidewall of the first column pad 123 may be surrounded by the first gate dielectric layer 121. The sidewall of the second column pad 133 may be surrounded by the second gate dielectric layer 131.

[0058] The landing pad 141 may include a metal-based material. The landing pad 141 may include a metal, a metal nitride, or a combination thereof. The landing pad 141 and the second cell contact plug CT2 may partially overlap. The landing pad 141 and the second column pad 133 may partially overlap.

[0059] Figures 4 to 32 An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is illustrated. Hereinafter, a view in the direction of A11-A11' is a cross-sectional view in a direction crossing a bit line, and a view in the direction of A12-A12' is a cross-sectional view in a direction extending a bit line. For example, a view in the direction of A11-A11' is a cross-sectional view in a direction crossing a bit line. Figure 1 The cross-sectional view taken in the second direction D2 shown in FIG. 1 and the view in the direction A12-A12' are Figure 1 A cross-sectional view taken in the first direction D1 is shown in FIG.

[0060] refer to Figure 4, a buffer layer 12 may be formed over the substrate 11. The substrate 11 may be a material suitable for semiconductor processing. The substrate 11 may include a semiconductor substrate. The substrate 11 may be formed of a material containing silicon. The substrate 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 11 may also include other semiconductor materials, such as germanium. The substrate 11 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate, such as GaAs. The substrate 11 may include a silicon-on-insulator (SOI) substrate. The buffer layer 12 may include a dielectric material. The buffer layer 12 may include silicon oxide, silicon nitride, or a combination thereof.

[0061] A conductive layer 13A may be formed over the buffer layer 12. The conductive layer 13A may include a metal-based material. The conductive layer 13A may include a metal, a metal nitride, a metal silicide, or a combination thereof. The conductive layer 13A may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). The conductive layer 13A may be formed to have a thickness of about 100 nm. arrive For example, a tungsten layer may be deposited to a thickness of about The conductive layer 13A is formed with a thickness of . In order to reduce the parasitic capacitance between the substrate 11 and the conductive layer 13A, the buffer layer 12 may be formed of silicon oxide. For example, the buffer layer 12 may include tetraethyl orthosilicate (TEOS).

[0062] The barrier material layer 14A may be formed over the conductive layer 13A. The barrier material layer 14A may include a metal-based material. The barrier material layer 14A may include a metal, a metal nitride, a metal silicide, or a combination thereof. The barrier material layer 14A may include titanium nitride, molybdenum, or ruthenium. The barrier material layer 14A may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). The barrier material layer 14A may be formed to have a thickness of about 100 nm. arrive For example, titanium nitride may be deposited to a thickness of about The barrier material layer 14A is formed with a thickness of .

[0063] A first oxide semiconductor stack 15A may be formed over the barrier material layer 14A. The first oxide semiconductor stack 15A may include Figure 3A and Figure 3B The stack of the lower interface layer, the channel layer and the upper interface layer is shown in FIG.

[0064] The first oxide semiconductor stack 15A may include a conductive material. The first oxide semiconductor stack 15A may include an oxide semiconductor material. The first oxide semiconductor stack 15A may include an indium-rich oxide semiconductor material, IGZO, or a combination thereof. For example, the first oxide semiconductor stack 15A may include a first indium-rich IGZO, IGZO, and a second indium-rich IGZO stacked in sequence.

[0065] Subsequently, a first sacrificial layer 16A may be formed over the first oxide semiconductor stack 15A. The first sacrificial layer 16A may include silicon nitride. The first sacrificial layer 16A may include a stack of different materials.

[0066] Reference now Figure 5 , a first sacrificial line 16 may be formed over the first oxide semiconductor stack 15A. The first sacrificial line 16 may be formed by etching the first sacrificial layer 16A. The first sacrificial line 16 may be used to protect the first oxide semiconductor stack 15A from subsequent processes. For example, the first sacrificial line 16 may be used as an etching barrier during the etching process of the first oxide semiconductor stack 15A.

[0067] The first sacrificial lines 16 may include silicon nitride. The etching process for forming the first sacrificial layer 16A of the first sacrificial lines 16 may include a double patterning process. Each of the first sacrificial lines 16 may include a stack of different materials.

[0068] Subsequently, the first oxide semiconductor stack 15A may be etched using the first sacrificial line 16 as an etch barrier, and then the barrier material layer 14A and the conductive layer 13A may be etched.

[0069] A plurality of line structures LS and first trenches T1 may be formed over the buffer layer 12 through the above-described series of etching processes. Each of the line structures LS may include a stack of a bit line 13, a bit line barrier layer 14, an oxide semiconductor line 15B, and a sacrificial line 16. The bit line barrier layer 14 may be formed by etching the barrier material layer 14A, and the bit line 13 may be formed by etching the conductive layer 13A. The oxide semiconductor line 15B may be formed by etching the oxide semiconductor stack 15A. The first trench T1 may be provided between the line structures LS.

[0070] refer to Figure 6, a first dielectric wire 17 may be formed between the line structures LS. The first dielectric wire 17 may include a dielectric material. For example, the first dielectric wire 17 may include silicon oxide, silicon nitride, silicon carbide oxide (SiCO), a spin-on dielectric layer, or a combination thereof. After depositing a dielectric material to fill the first trenches T1 between the line structures LS to form the first dielectric wire 17, a planarization process of the dielectric material may be performed. The first dielectric wire 17 may fill the first trenches T1, respectively. In order to form the first dielectric wire 17, silicon nitride, silicon carbide oxide, and a spin-on dielectric layer may be sequentially formed, and then a planarization process may be performed.

[0071] refer to Figure 7 , a portion of the line structure LS may be selectively etched to form a first column structure VP. The first column structure VP may include a stack of a first oxide semiconductor column 15P and a first sacrificial column 16P. The bit line barrier layer 14 and the bit line 13 may be disposed below the first oxide semiconductor column 15P. The first sacrificial column 16P may be formed above the first oxide semiconductor column 15P.

[0072] In the A12-A12' direction, a second trench T2 may be formed between the first oxide semiconductor pillars 15P. The lower surface of the second trench T2 may expose the upper surface of the bit line barrier layer 14. The first trench T1 and the second trench T2 may intersect each other. The first trench T1 may be deeper than the second trench T2. In the A11-A11' direction, the dielectric line 17 may be cut by the second trench T2. Hereinafter, the first dielectric line 17 may be referred to as "first dielectric pillar 17P". The first dielectric pillar 17P may be disposed between the first oxide semiconductor pillars 15P in the A11-A11' direction.

[0073] Each of the first oxide semiconductor pillars 15P may include first to fourth side walls SW1 to SW4. The first side wall SW1 and the second side wall SW2 of each of the first oxide semiconductor pillars 15P may be exposed through the second trench T2, and the third side wall SW3 and the fourth side wall SW4 of each of the first oxide semiconductor pillars 15P may not be exposed through the dielectric pillar 17P. The first sacrificial pillar 16P may also include exposed side walls and unexposed side walls in the same manner as the first oxide semiconductor pillars 15P.

[0074] refer to Figure 8, a first gate dielectric layer 18 may be formed over the first column structure VP. A first gate dielectric layer 18 may be formed over the exposed first sidewall SW1 and second sidewall SW2 of the first oxide semiconductor column 15P. The first gate dielectric layer 18 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof. The high-k material may include a material having a dielectric constant greater than that of silicon oxide. For example, the high-k material may include a material having a dielectric constant greater than about 3.9. For another example, the high-k material may include a material having a dielectric constant greater than 10. For yet another example, the high-k material may include a material having a dielectric constant of about 10 to 30. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. With respect to the high-k material, other known high-k materials may be selectively used. The first gate dielectric layer 18 may include a metal oxide. The first gate dielectric layer 18 may be conformally formed over the first and second sidewalls SW1 and SW2 of the first oxide semiconductor pillar 15P. The first gate dielectric layer 18 may conformally cover the exposed sidewalls and upper surface of the first sacrificial pillar 16P.

[0075] A gate conductive layer 19A may be formed over the first gate dielectric layer 18. The gate conductive layer 19A may be conformally formed over the first gate dielectric layer 18. The gate conductive layer 19A may include a metal-based material. The gate conductive layer 19A may include a metal, a metal nitride, or a combination thereof. The gate conductive layer 19A may include tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or a combination thereof.

[0076] refer to Fig. 9 , a sacrificial spacer 20 may be formed over the gate conductive layer 19A. The sacrificial spacer 20 may include an oxide. To form the sacrificial spacer 20, silicon oxide may be deposited over the gate conductive layer 19A, and then an etch-back process may be performed. The upper surface of the sacrificial spacer 20 may be disposed at a level lower than the upper surface of the sacrificial column 16P. The lower surface of the sacrificial spacer 20 may be disposed at a level lower than the lower surface of the sacrificial column 16P.

[0077] refer to Fig.10, a first vertical gate 19 may be formed. In order to form the first vertical gate 19, the gate conductive layer 19A may be selectively etched using a sacrificial spacer 20 as an etching barrier. The sacrificial spacer 20 may be used to protect the first vertical gate 19 during the etching process of the gate conductive layer 19A. The process of etching the gate conductive layer 19A may include an etch-back process and a wet etching process performed sequentially. The non-tapered shape of the first vertical gate 19 may be formed due to the etch-back process, and the tapered shape of the first vertical gate 19 may be formed due to the subsequent wet etching process. Due to the wet etching process, the bottom portion of the first vertical gate 19 may be thinned. The first vertical gate 19 may correspond to Figure 3A The first vertical gate 122 shown in FIG. 1 and the bottom portion of the first vertical gate 19 may correspond to the first vertical gate 122 also shown in FIG. Figure 3A The first lower level portion 122L is shown in FIG.

[0078] refer to Fig.11 , the sacrificial spacer 20 may be removed. Each of the first vertical gates 19 has a dual structure and may be formed on each of the first sidewall and the second sidewall of the first oxide semiconductor column 15P. Figure 2A As illustrated in FIG. 1 , the first vertical gate 19 may extend in the second direction D2, and the bit line 13 may extend in the first direction D1. The first oxide semiconductor pillars 15P and the first dielectric pillars 17P may be alternately disposed in the second direction D2, and the first vertical gate 19 may extend along the exposed sidewalls of the first oxide semiconductor pillars 15P and the first dielectric pillars 17P.

[0079] Through the above series of processes, a first vertical transistor array VTA1 may be formed. The first vertical transistor array VTA1 may include a plurality of first vertical transistors VT1.

[0080] refer to Fig.12 , a first interlayer dielectric layer 21 may be formed over the first vertical gate 19. The first interlayer dielectric layer 21 may be planarized to expose the upper surface of the first sacrificial pillar 16P. The first interlayer dielectric layer 21 may include silicon oxide, such as a spin-on dielectric (SOD) layer. The first sacrificial pillar 16P may be used as a stop layer during the planarization process of the first interlayer dielectric layer 21.

[0081] refer to Fig.13 , a first contact hole 22 may be formed by selectively etching a portion of the first interlayer dielectric layer 21. The first contact hole 22 may be formed to be self-aligned on the sidewall of the first vertical gate 19. The first contact hole 22 may be enlarged by etching the bit line barrier layer 14 below the first contact hole 22. The first contact hole 22 may expose the surface of the bit line 13.

[0082] refer to Fig.14 , a first contact spacer 23 may be formed on a sidewall of the first contact hole 22. The first contact spacer 23 may include a dielectric material. The first contact spacer 23 may include silicon oxide, silicon nitride, or a combination thereof. The first contact spacer 23 may expose a surface of the bit line 13.

[0083] refer to Fig.15 , a first cell contact plug 24 may be formed to fill the first contact hole 22. The first cell contact plug 24 may be electrically connected to the bit line 13. The first cell contact plug 24 may extend vertically from a surface of the bit line 13.

[0084] As described above, the first cell contact plug 24 may be disposed between adjacent first vertical transistors VT1 . The first cell contact plug 24 may be disposed between adjacent first vertical gates 19 .

[0085] refer to Fig.16 , the first sacrificial column 16P may be selectively removed. As a result, a first hole-type recess 16H may be formed. The first hole-type recess 16H may selectively expose the upper surface of the first oxide semiconductor column 15P. The first sacrificial column 16P may be removed by a wet etching process.

[0086] refer to Fig.17 , a first column pad 25 may be formed to fill the first hole-shaped recess 16H. The first column pad 25 may directly contact the first oxide semiconductor column 15P. The first column pad 25 may be formed of a material including a metal, a metal nitride, or a combination thereof. For example, the first column pad 25 may be formed by first depositing titanium nitride to fill the first hole-shaped recess 16H and then planarizing the titanium nitride to expose the surface of the first cell contact plug 24.

[0087] The first vertical transistor array VTA1 may further include first cell contact plugs 24 and first pillar pads 25 .

[0088] refer to Fig.18 , a second oxide semiconductor stack 26A may be formed over the first vertical transistor array VTA1 and the first cell contact plug 24. A second sacrificial layer 27A may be formed over the second oxide semiconductor stack 26A. The second oxide semiconductor stack 26A may be the same as the first oxide semiconductor stack 15A. The second sacrificial layer 27A may be the same as the first sacrificial layer 16A.

[0089] Then, you can execute Figures 5 to 7 As a result, Fig.19As illustrated in FIG. 1 , a stack of second pillar structures VP2 (ie, second oxide semiconductor pillars 26P and second sacrificial pillars 27P) may be formed. A third trench 28 may be formed between adjacent second pillar structures VP2.

[0090] Then, you can execute Figures 8 to 11 A series of processes illustrated in FIG. 1 to form a second gate dielectric layer 29 above the second pillar structure VP2, as shown in FIG. Fig. 20 , and the second vertical gate 31 is formed by using a sacrificial spacer 30. The second gate dielectric layer 29 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material, or a combination thereof.

[0091] The second vertical gate 31 may correspond to Figure 3B The second vertical gate 132 is shown in FIG.

[0092] refer to Fig.21 , the sacrificial spacer 30 may be removed. Each of the second vertical gates 31 may have a dual structure and may be formed on the sidewall of the second oxide semiconductor pillar 26P. Figure 2B As illustrated in FIG. 1 , the second vertical gate 31 may extend in the second direction D2, and the bit line 13 may extend in the first direction D1. The second oxide semiconductor pillars 26P may be disposed in the second direction D2.

[0093] Through the above series of processes, the second vertical transistor array VTA2 may be formed. The second vertical transistor array VTA2 may include a plurality of second vertical transistors VT2. The second oxide semiconductor pillar 26P and the first cell contact plug 24 may be electrically connected to each other.

[0094] refer to Fig. 22 , a second interlayer dielectric layer 32 may be formed between the second vertical transistors VT2. The second interlayer dielectric layer 32 may be disposed between the second vertical gates 31.

[0095] Subsequently, the second sacrificial column 27P may be selectively removed. As a result, a second hole-type recess 33 may be formed. The second hole-type recess 33 may selectively expose the upper surface of the second oxide semiconductor column 26P. The second sacrificial column 27P may be removed by a wet etching process.

[0096] refer to Fig.23 , a second column pad 34 may be formed to fill the second hole-shaped recess 33 and directly contact the second oxide semiconductor column 26P. The second column pad 34 may include a metal, a metal nitride, or a combination thereof. For example, the second column pad 34 may be formed by first depositing titanium nitride to fill the second hole-shaped recess 33 and then planarizing the titanium nitride to expose the surface of the second interlayer dielectric layer 32.

[0097] refer to Fig.24 , a second contact hole 35 may be formed by selectively etching a portion of the second interlayer dielectric layer 32. The second contact hole 35 may be formed to be self-aligned with the sidewall of the second vertical gate 31. The second contact hole 35 may be enlarged by etching the lower surface of the second gate dielectric layer 29 below the second contact hole 35. The second contact hole 35 may expose the surface of the first column pad 25.

[0098] refer to Fig.25 , a second contact spacer 36 may be formed on the sidewall of the second contact hole 35. The second contact spacer 36 may include a dielectric material. The second contact spacer 36 may include silicon oxide, silicon nitride, or a combination thereof. The second contact spacer 36 may expose the surface of the first column pad 25.

[0099] Subsequently, a second cell contact plug 37 may be formed to fill the second contact hole 35, as shown in FIG. Fig.25 The second cell contact plug 37 may be electrically connected to the first pillar pad 25 . The second cell contact plug 37 may extend vertically from a surface of the first pillar pad 25 .

[0100] The second vertical transistor array VTA2 may further include second cell contact plugs 37 and second pillar pads 34 .

[0101] As described above, the first vertical transistor array VTA1 may be disposed above the bit line 13, and the second vertical transistor array VTA2 may be disposed above the first vertical transistor array VTA1. The first cell contact plug 24 may be disposed between adjacent first vertical transistors VT1. The first vertical transistors VT1 and the first cell contact plug 24 may be alternately arranged in the direction A12-A12' in which the bit line 13 extends. The second cell contact plug 37 may be disposed between adjacent second vertical transistors VT2. The second vertical transistors VT2 and the second cell contact plug 37 may be alternately arranged in the direction A12-A12' in which the bit line 13 extends. The first cell contact plug 24 may be electrically connected to the second oxide semiconductor pillar 26P, and the second cell contact plug 37 may be electrically connected to the first oxide semiconductor pillar 15P.

[0102] refer to Fig.26 , a pad material layer 38A may be formed over the second vertical transistor array VTA2 and the second cell contact plugs 37. The pad material layer 38A may include a metal-based material, a semiconductor material, or a combination thereof.

[0103] refer to Fig. 27 , a landing pad 38 may be formed by etching the pad material layer 38A. The landing pad 38 may be coupled to the second cell contact plug 37 and the second pillar pad 34, respectively.

[0104] According to another embodiment of the present invention, the second cell contact plug 37 and the landing pad 38 may be formed simultaneously.

[0105] refer to Fig.28 After forming the pad dielectric layer 39 to fill the space between the landing pads 38, an etch stop layer 40 may be formed over the pad dielectric layer 39 and the landing pads 38. A first molding layer 41, a first support layer 42, a second molding layer 43, and a second support layer 44 may be sequentially formed over the etch stop layer 40.

[0106] The etch stop layer 40 may be formed of a material having an etching selectivity relative to the first mold layer 41. The etch stop layer 40 may include silicon nitride or silicon oxynitride. The first mold layer 41 may include a dielectric material. The first mold layer 41 may be silicon oxide (SiO2). The first mold layer 41 may be formed to be thicker than the first support layer 42. The first mold layer 41 may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). The first mold layer 41 may include phosphorus-doped silicon oxide or boron-doped silicon oxide. The first mold layer 41 may include USG, PSG, BSG, BPSG, FSG or a combination thereof. Due to the fast etching rate of phosphorus-doped silicon oxide and boron-doped silicon oxide with respect to the etching solution, they can be easily removed in subsequent processes.

[0107] The first support layer 42 may be formed of a material having an etching selectivity with respect to the first mold layer 41 and the second mold layer 43. The first support layer 42 may include silicon nitride or silicon carbonitride (SiCN).

[0108] The second molding layer 43 may include a dielectric material. The second molding layer 43 may be silicon oxide (SiO2). The second molding layer 43 may be formed to be thicker than the first support layer 42. The second molding layer 43 may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). The second molding layer 43 may include phosphorus-doped silicon oxide or boron-doped silicon oxide. The second molding layer 43 may include USG, PSG, BSG, BPSG, FSG or a combination thereof. The first molding layer 41 and the second molding layer 43 may be the same material or different materials.

[0109] According to another embodiment of the present invention, the first mold layer 41 and the second mold layer 43 may be formed of a silicon material such as amorphous silicon or polycrystalline silicon.

[0110] The second support layer 44 may be formed of a material having an etching selectivity with respect to the second mold layer 43. The second support layer 44 may include silicon nitride or silicon carbonitride (SiCN).

[0111] The first support member layer 42 and the second support member layer 44 can be the same material or different materials. Both the first support member layer 42 and the second support member layer 44 can be formed of silicon nitride. According to another embodiment of the present invention, the first support member layer 42 can be formed of silicon nitride, and the second support member layer 44 can be formed of silicon carbonitride. The second support member layer 44 can be thicker than the first support member layer 42.

[0112] According to another embodiment of the present invention, another support member layer may be formed. For example, the support member structure may have a multi-level support member layer structure.

[0113] refer to Fig.29 , an opening 45 may be formed. To form the opening 45, the second support layer 44, the second molding layer 43, the first support layer 42, and the first molding layer 41 may be sequentially etched by using a mask layer (not shown) as an etching barrier. The etching process for forming the opening 45 may stop at the etching stop layer 40. The opening 45 may be formed by using a dry etching process, a wet etching process, or a combination thereof. The opening 45 may be referred to as a hole in which the lower electrode (or storage node) is to be formed.

[0114] Subsequently, etch stop layer 40 may be etched to expose the upper surface of landing pad 38 below opening 45 .

[0115] refer to Fig.30 , a lower electrode SN may be formed in the opening 45. The lower electrode SN may fill the interior of the opening 45. The lower electrode SN may include polysilicon, metal, metal nitride, conductive metal oxide, metal silicide, noble metal, or a combination thereof. The lower electrode SN may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or a combination thereof. The lower electrode SN may include titanium nitride (TiN). The lower electrode SN may include titanium nitride (ALD-TiN) formed by atomic layer deposition (ALD). The lower electrode SN may include a stack of a cylindrical electrode 46 and a columnar electrode 47. According to another embodiment of the present invention, the lower electrode SN may include a hybrid structure of a titanium nitride cylinder and a polysilicon column.

[0116] refer to Fig.31 , the second support member layer 44, the second mold layer 43, and the first support member layer 42 may be sequentially etched. As a result, a support member opening 48 exposing the first mold layer 41 may be formed, and an upper-level support member 44S and a lower-level support member 42S may be formed.

[0117] The upper and lower level supports 44S and 42S may contact the outer wall of the lower electrode SN. The upper and lower level supports 44S and 42S may prevent the lower electrode SN from collapsing during a subsequent process of removing the second and first mold layers 43 and 41 .

[0118] Subsequently, the second mold layer 43 and the first mold layer 41 may be removed through the support opening 48. The first mold layer 41 and the second mold layer 43 may be removed by a wet immersion process. The wet immersion process for removing the first mold layer 41 and the second mold layer 43 may be performed using an etching solution capable of selectively removing the first mold layer 41 and the second mold layer 43. When the first mold layer 41 and the second mold layer 43 include silicon oxide, the first mold layer 41 and the second mold layer 43 may be removed by a wet etching process using hydrofluoric acid (HF).

[0119] refer to Fig.32 , a dielectric layer 49 may be formed over the lower electrode SN and the lower level support member 42S and the upper level support member 44S. The dielectric layer 49 may include a high-k material having a higher dielectric constant than silicon oxide. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer 49 may be formed by a composite layer including two or more layers of the aforementioned high-k materials. According to this embodiment of the present invention, the dielectric layer 49 may be formed by a zirconium oxide-based material having excellent leakage current characteristics while fully reducing the equivalent oxide thickness (EOT). For example, it may include a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. According to another embodiment of the present invention, the dielectric layer 49 may include a TiO2 / ZrO2 / Al2O3 / ZrO2 stack, a TiO2 / HfO2 / Al2O3 / HfO2 stack, a Ta2O5 / ZrO2 / Al2O3 / ZrO2 stack, or a Ta2O5 / HfO2 / Al2O3 / HfO2 stack.

[0120] Subsequently, an upper electrode 50 may be formed over the dielectric layer 49. The upper electrode 50 may fill the space between adjacent lower electrodes SN. The upper electrode 50 may extend to cover the upper portion of the lower electrode SN. The upper electrode 50 may include a conductive material. The upper electrode 50 may include titanium nitride, silicon germanium, tungsten, tungsten nitride, or a combination thereof.

[0121] As described above, the first vertical transistor array VTA1 may be disposed above the bit line 13, and the second vertical transistor array VTA2 may be disposed above the first vertical transistor array VTA1. The capacitor array CAP may be disposed above the second vertical transistor array VTA2.

[0122] The first cell contact plug 24 may be disposed between adjacent first vertical transistors VT1. The first vertical transistors VT1 and the first cell contact plug 24 may be alternately arranged in the direction A12-A12' in which the bit line 13 extends. The second cell contact plug 37 may be disposed between adjacent second vertical transistors VT2. The second vertical transistors VT2 and the second cell contact plug 37 may be alternately arranged in the direction A12-A12' in which the bit line 13 extends. The first cell contact plug 24 may be electrically connected to the second oxide semiconductor pillar 26P, and the second cell contact plug 37 may be electrically connected to the first oxide semiconductor pillar 15P.

[0123] Figure 33 to Figure 35 A method for manufacturing a semiconductor device according to another embodiment of the present invention is shown. Figure 33 to Figure 35 A method of simultaneously forming a second cell contact plug and a landing pad is illustrated.

[0124] You can execute Figures 4 to 26 The second contact hole 35 is formed through a series of processes illustrated in FIG.

[0125] Then, refer to Fig.33 , a second contact spacer 36 may be formed on a sidewall of the second contact hole 35 .

[0126] refer to Fig.34 , a contact material 51 may be formed to fill the second contact hole 35. The contact material 51 may include a metal-based material.

[0127] refer to Fig.35 , the contact material 51 may be etched to simultaneously form the second cell contact plug 37 and the landing pad 38 .

[0128] Then, you can execute Figure 28 to Figure 32 A series of processes illustrated in the figure.

[0129] According to the above-described embodiments of the present invention, by arranging the first vertical transistor and the second vertical transistor in a two-layer structure, the area of ​​the cell can be reduced without scaling the vertical transistors.

[0130] Therefore, cost can be reduced by adding net die without degrading unit performance.

[0131] Also, since the bit line and the transistor are sequentially formed by using a depositable channel material, process difficulty can be reduced.

[0132] Furthermore, by using a metal oxide (particularly IGZO) as a channel material, gate induced drain leakage and junction leakage can be suppressed, and thus retention characteristics can be improved.

[0133] According to an embodiment of the present invention, a cell area can be reduced without scaling the vertical transistor by providing the vertical transistor in a multi-layer structure (eg, a two-layer structure).

[0134] Therefore, cost can be reduced by adding net die without degrading unit performance.

[0135] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: bit line; a plurality of first semiconductor pillars disposed above the bit lines; a plurality of first unit contact plugs disposed between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first cell contact plugs; a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; as well as A plurality of capacitors are coupled to the second semiconductor pillars and the second cell contact plugs, respectively.

2. The semiconductor device according to claim 1, further comprising: A first vertical gate having a double structure, wherein the first vertical gate is disposed on two side walls of each of the first semiconductor pillars; as well as A second vertical gate having a dual structure is disposed on two side walls of each of the second semiconductor pillars. 3 . The semiconductor device according to claim 2 , wherein each of the first vertical gate and the second vertical gate has a tapered shape.

4. The semiconductor device according to claim 2, wherein each of the first vertical gate and the second vertical gate comprises: The upper level part, and A lower level portion that is thinner than the upper level portion.

5. The semiconductor device according to claim 1, wherein each of the first semiconductor pillar and the second semiconductor pillar comprises: Oxide semiconductor materials.

6. The semiconductor device according to claim 5, wherein each of the first semiconductor pillar and the second semiconductor pillar comprises: Lower interface layer; Upper interface layer; as well as A channel layer is between the lower interface layer and the upper interface layer.

7. The semiconductor device according to claim 6, wherein the channel layer comprises IGZO, IZTO or ZTO, and The lower interface layer and the upper interface layer include indium-rich IGZO, and The indium-rich IGZO includes IGZO in which the indium content is greater than the gallium content and the zinc content. The semiconductor device according to claim 1 , wherein the bit line comprises a metal material.

9. The semiconductor device according to claim 1, further comprising: a substrate disposed below the bit line, and A buffer layer is disposed between the bit line and the substrate. 10 . The semiconductor device of claim 1 , wherein each of the first semiconductor pillar and the second semiconductor pillar comprises IGZO, IZTO, ZTO, Indium-rich IGZO, or a combination thereof.

11. The semiconductor device according to claim 1, wherein each of the capacitors comprises a first electrode, a dielectric layer, and a second electrode, wherein the first electrode comprises a cylindrical electrode, and The columnar electrode is arranged inside the cylindrical electrode. 12 . The semiconductor device of claim 11 , wherein the capacitor further comprises a multi-layered hierarchical support supporting an outer wall of the first electrode. 13 . The semiconductor device of claim 1 , wherein the first cell contact plug and the second cell contact plug include a metal-based material.

14. A method for manufacturing a semiconductor device, the method comprising: forming a bit line over the substrate; forming a first semiconductor pillar above the bit line; forming a plurality of first cell contact plugs coupled to the bit lines between the first semiconductor pillars; forming a second semiconductor pillar over the first cell contact plug; forming a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; as well as A plurality of capacitors respectively coupled to the second semiconductor pillars and the second cell contact plugs are formed.

15. The method according to claim 14, further comprising: forming a first interlayer dielectric layer covering the bit lines between the first semiconductor pillars; forming a first contact hole in the first interlayer dielectric layer to expose the bit line; forming a first contact spacer on a sidewall of the first contact hole; as well as The first contact hole is filled with a conductive layer to form the first cell contact plug over the first contact spacer.

16. The method according to claim 14, further comprising: forming a second interlayer dielectric layer between the second semiconductor pillars; forming a second contact hole in the second interlayer dielectric layer to expose the upper surface of the first semiconductor pillar; forming a second contact spacer on a sidewall of the second contact hole; as well as The second contact hole is filled with a conductive layer to form the second cell contact plug over the second contact spacer.

17. The method according to claim 14, further comprising: Before forming the first cell contact plug, forming a first gate dielectric layer on the sidewalls of the first semiconductor pillar; as well as A first vertical gate of a dual structure is formed over the first gate dielectric layer, and the first vertical gate is disposed on two sidewalls of each of the first semiconductor pillars.

18. The method according to claim 14, further comprising: Before forming the second cell contact plug, forming a second gate dielectric layer on the sidewalls of the second semiconductor pillar; as well as A second vertical gate with a dual structure is formed above the second gate dielectric layer, and the second vertical gate is disposed on the sidewall of the second semiconductor column.

19. The method according to claim 14, wherein forming the bit line and forming the first semiconductor pillar comprises: forming a conductive layer over the substrate; forming an oxide semiconductor stack over the conductive layer; forming an oxide semiconductor line by etching the oxide semiconductor stack; etching the conductive layer to form the bit line; as well as The oxide semiconductor line is etched in a direction intersecting the bit line to form the first semiconductor pillar.

20. The method of claim 14, further comprising: A tapered double vertical gate is formed on both sidewalls of each of the first semiconductor pillars and on both sidewalls of each of the second semiconductor pillars.

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