Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device may include: a first active pattern and a second active pattern each including a central portion and an edge portion, the central portion of the first active pattern and the edge portion of the second active pattern being adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a bit line node contact on a central portion of the first active pattern; a bit line on the bit line node contact; a storage node contact on an edge portion of the second active pattern; a bit line spacer between the bit line and the storage node contact; and a gap filling insulating pattern between a lower portion of the bit line spacer and the storage node contact. A central portion of the first active pattern may include a central oxide region in an upper portion thereof.

Description

Technical Field

[0001] Various example embodiments relate to semiconductor devices, and in particular, to semiconductor devices and / or methods of manufacturing the same. Background Art

[0002] Semiconductor devices are considered important elements in the electronics industry due to their small size, multifunctionality and / or low cost characteristics. Semiconductor devices can be classified into memory devices for storing data, logic devices for processing data, and hybrid devices including both memory elements and logic elements.

[0003] As the demand for electronic devices with fast speed and / or low power consumption has increased recently, semiconductor devices require fast operation speed and / or low operation voltage. In order to meet or help meet these requirements, the integration density of semiconductor devices is increasing, and many studies are being conducted. Summary of the invention

[0004] Various example embodiments provide semiconductor devices and / or methods of manufacturing semiconductor devices that may be manufactured with a low failure rate and / or an improved yield.

[0005] Alternatively or additionally, various example embodiments may provide a semiconductor device having improved electrical characteristics and / or reliability characteristics and / or a method of manufacturing a semiconductor device.

[0006] According to some example embodiments, a semiconductor device may include: a first active pattern and a second active pattern, each including a central portion and an edge portion, the central portion of the first active pattern and the edge portion of the second active pattern being adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a bit line node contact on the central portion of the first active pattern; a bit line on the bit line node contact; a storage node contact on the edge portion of the second active pattern; a bit line spacer between the bit line and the storage node contact; and a gap filling insulating pattern between a lower portion of the bit line spacer and the storage node contact. The central portion of the first active pattern may include a central oxide region in an upper portion thereof.

[0007] Alternatively or additionally, according to various example embodiments, a semiconductor device may include: a first active pattern and a second active pattern adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a recessed region defined by the first active pattern and the device isolation pattern; a bit line node contact on the first active pattern; a gap filling insulating pattern provided on a side surface of the bit line node contact to fill the recessed region; a bit line spacer between the side surface of the bit line node contact and the gap filling insulating pattern; and an intermediate material between the gap filling insulating pattern and the device isolation pattern. The intermediate material may include at least one of a halogen element and carbon.

[0008] Alternatively or additionally, according to various example embodiments, a semiconductor device may include: a first active pattern and a second active pattern, each including a central portion and an edge portion, the central portion of the first active pattern and the edge portion of the second active pattern being adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a bit line node contact on the central portion of the first active pattern; a bit line on the bit line node contact; a gap filling insulating pattern on a side surface of the bit line node contact; and a bit line spacer covering a side surface of the bit line and extending to a region between the side surface of the bit line node contact and the gap filling insulating pattern. The gap filling insulating pattern may contact the device isolation pattern and may vertically and partially overlap an edge portion of the second active pattern.

[0009] Alternatively or additionally, according to various example embodiments, a method of manufacturing a semiconductor device may include: forming a recessed region on a central portion of a first active pattern and an edge portion of a second active pattern, the first active pattern and the second active pattern being adjacent to each other, the recessed region exposing a portion of the edge portion of the second active pattern; forming a bit line node contact on the central portion of the first active pattern; forming a bit line on the bit line node contact; oxidizing the exposed portion of the edge portion of the second active pattern to form an edge oxide region; selectively forming sub-spacers on side surfaces of the bit line node contact and side surfaces of the bit line; and forming a gap-filling insulating pattern to fill the recessed region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a plan view illustrating a semiconductor device according to various example embodiments.

[0011] Figure 2A and 2B Along Figure 1 A cross-sectional view taken along lines AA' and BB'.

[0012] Figure 3 is corresponding to Figure 2A An enlarged cross-sectional view of portion P1.

[0013] Figures 4 to 6 is along Figure 1 A cross-sectional view taken along line AA'.

[0014] Figures 7 to 22 are diagrams illustrating a method of manufacturing a semiconductor device according to various example embodiments.

[0015] Fig.23 and Fig.24 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments.

[0016] Fig.25 and Fig.26 is a flow chart illustrating a method of manufacturing a first sub-spacer. DETAILED DESCRIPTION

[0017] Various example features and embodiments will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0018] Figure 1 is a plan view illustrating a semiconductor device according to various example embodiments. Figure 2A and 2B are respectively along Figure 1 A cross-sectional view taken along lines AA' and BB'. Figure 3 is corresponding to Figure 2A An enlarged cross-sectional view of portion P1.

[0019] refer to Figures 1 to 3 , a substrate 100 may be provided. The substrate 100 may be or may include, for example, one or more of a silicon substrate, a germanium substrate, or a silicon germanium substrate, or may be included in, for example, one or more of a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0020] The device isolation pattern STI may be disposed on the substrate 100. The device isolation pattern STI may define an active pattern ACT in the substrate 100. Each active pattern ACT may include a central portion CA and a pair of edge portions EA, the central portion CA being provided between a pair of word lines WL to be described below, the pair of edge portions EA being spaced apart from each other and the central portion CA being interposed therebetween. The paired edge portions EA may be opposite ends of the active pattern ACT. The central portion CA and the paired edge portions EA may include an impurity region doped with impurities (e.g., n-type and / or p-type impurities).

[0021] The active patterns ACT may be adjacent to each other in a first direction D1 and a second direction D2 that are parallel to the bottom surface of the substrate 100 and are not parallel to each other, and may be orthogonal to each other in some example embodiments. As described herein, the expression “a pair of active patterns ACT are adjacent to each other in the first direction D1” may indicate that a center portion CA of one of the pair of active patterns ACT is adjacent to an edge portion EA of the other active pattern ACT in the first direction D1. Figure 1 As shown, the first active pattern ACT1 and the second active pattern ACT2 may be adjacent to each other in the first direction D1. As described herein, the expression "a pair of active patterns ACT are adjacent to each other in the second direction D2" may indicate that central portions CA of the pair of active patterns ACT are adjacent to each other in the second direction D2.

[0022] Each active pattern ACT may have a shape protruding in a third direction D3 perpendicular to the bottom surface of the substrate 100. In some example embodiments, the device isolation pattern STI may be disposed in the substrate 100 or at least partially disposed in the substrate 100, and the active pattern ACT may be or may include a portion of the substrate 100 surrounded by the device isolation pattern STI, or be included in a portion of the substrate 100 surrounded by the device isolation pattern STI. For ease of explanation, unless otherwise specified or clear from the context, the term "substrate 100" may refer to the remaining portion of the substrate 100, excluding the active pattern ACT.

[0023] The active pattern ACT may be a separate strip pattern that is spaced apart from each other and is elongated in the fourth direction D4. The fourth direction D4 may be parallel to the bottom surface of the substrate 100 and may not be parallel to the first direction D1 and the second direction D2. The fourth direction may form an angle, such as an acute angle, with either or both of the first direction D1 and the second direction D2. The paired edge portions EA of the active pattern ACT may be spaced apart from each other in the fourth direction D4, with the center portion CA interposed therebetween.

[0024] The central portion CA of the active pattern ACT may include a central oxide region Oc and a central non-oxide region NOc, and the edge portion EA may include an edge oxide region Oe and an edge non-oxide region NOe. The central oxide region Oc may be or may include or be included in an oxidized region of the central portion CA, and the central non-oxide region Noc may be or may include or be included in an unoxidized region of the central portion CA. The edge oxide region Oe may be or may include or be included in an oxidized region of the edge portion EA, and the edge non-oxide region NOe may be or may include or be included in an unoxidized region of the edge portion EA. The central oxide region Oc and the edge oxide region Oe may be provided adjacent to the first recessed region RS1, which will be described below.

[0025] The central oxide region Oc may be provided on the central portion CA of the active pattern ACT. Each central portion CA may include a pair of central oxide regions Oc spaced apart from each other in the first direction D1. When viewed in a plan view, a pair of central oxide regions Oc may be provided at both sides of the bit line node contact DC, which will be described below.

[0026] The device isolation pattern STI may include an insulating material. As an example, the device isolation pattern STI may be formed of or include at least one of silicon oxide or silicon nitride. The device isolation pattern STI may be a single layer made of one of the above materials, or a composite layer made of at least two of the above materials. The device isolation pattern STI may include a shallow trench isolation process or be formed using a shallow trench isolation process; example embodiments are not limited thereto.

[0027] The word line WL may be disposed to cross the active pattern ACT. As an example, the word line WL may cross the active pattern ACT and the device isolation pattern STI in the first direction D1. In some example embodiments, a plurality of word lines WL may be provided. The word lines WL may be spaced apart from each other in the second direction D2. In some example embodiments, a pair of word lines WL adjacent to each other in the second direction D2 may be provided to cross the active pattern ACT.

[0028] In some example embodiments, each word line WL may include a gate electrode GE, a gate insulation pattern GI, and a gate capping pattern GC. The gate electrode GE may be provided to cross the active pattern ACT and the device isolation pattern STI in the first direction D1. The gate insulation pattern GI may be interposed between the gate electrode GE and the active pattern ACT. The gate capping pattern GC may cover the top surface of the gate electrode GE.

[0029] The buffer pattern BP may be disposed on the substrate 100. The buffer pattern BP may cover the active pattern ACT, the device isolation pattern STI, and the word line WL. The buffer pattern BP may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The buffer pattern BP may be a single layer made of a single material, or a composite layer including two or more materials.

[0030] The bit line node contact DC may be provided on each active pattern ACT, and in some example embodiments, a plurality of bit line node contacts DC may be provided. The bit line node contacts DC may be provided on the central portion CA of the active pattern ACT, respectively, and electrically connected to the central portion CA of the active pattern ACT, respectively. The bit line node contacts DC may be spaced apart from each other in the first direction D1 and the second direction D2. The bit line node contacts DC may be interposed between the active pattern ACT and the bit line BL, which will be described below. Each of the bit line node contacts DC may electrically connect a corresponding one of the bit lines BL to a central portion CA of a corresponding one of the active patterns ACT. In some example embodiments, the bit line node contacts DC may be formed of doped polysilicon or may include doped polysilicon; example embodiments are not limited thereto.

[0031] The bit line node contacts DC may be disposed in the first recess regions RS1, respectively. The first recess regions RS1 may be provided in an upper portion of the active pattern ACT and an upper portion of the device isolation pattern STI adjacent to the upper portion of the active pattern ACT. In some example embodiments, the first recess regions RS1 may be defined by the active pattern ACT and the device isolation pattern STI.

[0032] The bit line BL may be provided on the bit line node contact DC. The bit line BL may be provided on the bit line node contact DC, and the bit line node contact DC is linearly arranged in the second direction D2. In some example embodiments, a plurality of bit lines BL may be provided. The bit lines BL may be spaced apart from each other in the first direction D1. The bit line BL may include a metallic material. The bit line BL may be formed of at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag) or include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0033] The polysilicon pattern PP may be interposed between the bit line BL and the buffer pattern BP. A top surface of the polysilicon pattern PP may be located at substantially the same height as a top surface of the bit line node contact DC. The polysilicon pattern PP may be formed of or include doped polysilicon.

[0034] The ohmic pattern OP may be interposed between the bit line BL and the bit line node contact DC and between the bit line BL and the polysilicon pattern PP. The ohmic pattern OP may be formed of or include at least one of metal silicide materials (e.g., silicide materials including one or more of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). A barrier pattern (not shown) may be further interposed between the bit line BL and the bit line node contact DC and between the bit line BL and the polysilicon pattern PP. The blocking pattern may be formed of or include at least one of conductive metal nitride materials (e.g., nitride materials containing one or more of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0035] A bit line cover pattern BCP may be provided on the bit line BL. In various example embodiments, the bit line cover patterns BCP may be provided on the top surfaces of the bit lines BL, respectively. The bit line cover patterns BCP may extend along the corresponding bit lines BL and in the second direction D2, and may be spaced apart from each other in the first direction D1. Each of the bit line cover patterns BCP may overlap vertically with a corresponding one of the bit lines BL. The bit line cover pattern BCP may be composed of a single layer or a plurality of layers. In some example embodiments, the bit line cover pattern BCP may include a first cover pattern (not shown), a second cover pattern (not shown), and a third cover pattern (not shown) stacked sequentially. In some example embodiments, each of the first to third cover patterns may be formed of or include silicon nitride. As another example, the bit line cover pattern BCP may further include additional cover patterns (e.g., fourth and fifth cover patterns (not shown)).

[0036] The gap-filling insulating pattern BI may fill each first recessed region RS1. The gap-filling insulating pattern BI may fill the inner space of the first recessed region RS1. In various example embodiments, the gap-filling insulating pattern BI may cover or at least partially cover the inner surface of the first recessed region RS1 and the side surface DCs of the bit line node contact DC. In the first recessed region RS1, the gap-filling insulating pattern BI may contact the device isolation pattern STI. The gap-filling insulating pattern BI may vertically overlap the central portion CA and the edge portion EA of the active pattern ACT. The gap-filling insulating pattern BI may vertically overlap a portion of the edge portion EA of the active pattern ACT. In the first recessed region RS1, the gap-filling insulating pattern BI may further contact the edge portion EA of the active pattern ACT.

[0037] The gap-filling insulating pattern BI may include an outer gap-filling pattern Ba conformally covering the inner surface of the first recessed region RS1, and an inner gap-filling pattern Bb provided on the outer gap-filling pattern Ba to fill the first recessed region RS1. The outer gap-filling pattern Ba may be in contact with a first sub-spacer SS1 and a device isolation pattern STI to be described below. In some example embodiments, the outer gap-filling pattern Ba may further be in contact with the central oxide region Oc and the edge oxide region Oe.

[0038] The outer gap-filling pattern Ba may include oxygen, and may or may not include nitrogen in some example embodiments. The inner gap-filling pattern Bb may include nitrogen, and may or may not include oxygen in some example embodiments. As an example, the outer gap-filling pattern Ba may be made of SiO 2 Forming or including SiO 2 , and the inner gap-filling pattern Bb may be formed of or include SiN.

[0039] The bit line spacer SPC may be provided on the side surface DCs of the bit line node contact DC, the side surface BLs of the bit line BL, and the side surface of the bit line cover pattern BCP. The bit line spacer SPC may cover the side surface DCs of the bit line node contact DC, the side surface BLs of the bit line BL, and the side surface of the bit line cover pattern BCP. The bit line spacer SPC may extend along the side surface BLs of the bit line BL and in the second direction D2. The bit line spacer SPC may be inserted between the bit line BL and the storage node contact BC to be described below, and may separate them from each other. The lowermost surface of the bit line spacer SPC (for example, the lowermost surface of the first sub-spacer SS1 to be described below) may be substantially coplanar with the bottom surface of the gap filling insulating pattern BI.

[0040] The bit line spacer SPC may include a plurality of sub-spacers. In some example embodiments, each of the bit line spacers SPC may include a first sub-spacer SS1, a second sub-spacer SS2, and a third sub-spacer SS3 sequentially provided on the side surface BLs of the bit line BL. Each of the first to third sub-spacers SS1, SS2, and SS3 may be formed of or include at least one of SiN, SiON, SiOCN, or SiOCH. In some example embodiments, at least a portion of the first to third sub-spacers SS1, SS2, and SS3 may include an empty space (e.g., an air gap) having an air layer (such as a clean dry air layer that may or may not be in a vacuum).

[0041] The first subspacer SS1 may cover the side surface DCs of the bit line node contact DC, the side surface BLs of the bit line BL, and the side surface of the bit line capping pattern BCP, and may extend continuously along the side surface toward the inner bottom surface of the first recessed region RS1. The first subspacer SS1 may extend into a region between the gap-filling insulating pattern BI and the side surface DCs of the bit line node contact DC. The first subspacer SS1 may separate the gap-filling insulating pattern BI from the bit line node contact DC.

[0042] The first subspacer SS1 may not extend to the inner surface of the first recessed region RS1. The first subspacer SS1 may be spaced apart from the storage node contact BC, which will be described below. In some example embodiments, the lower portion of the first subspacer SS1 may be spaced apart from the storage node contact BC. The first subspacer SS1 may not be inserted between the gap filling insulating pattern BI and the device isolation pattern STI (e.g., between the external gap filling pattern Ba and the device isolation pattern STI), and may not extend to the area on the device isolation pattern STI. The first subspacer SS1 may separate the second subspacer SS2 from the side surface BLs of the bit line BL.

[0043] The first subspacer SS1 may include a first region R1 adjacent to the second subspacer SS2 and a second region R2 disposed between the first region R1 and the bit line BL. The second region R2 may separate the first region R1 from the bit line BL and the bit line node contact DC. Each of the first region R1 and the second region R2 may contain nitrogen. The first region R1 may also contain oxygen, and the second region R2 may not contain oxygen. As an example, the first region R1 and the second region R2 may be formed of or include SiON and SiN, respectively, but example embodiments are not limited thereto. The oxygen in the first region R1 may be generated by diffusion from the second subspacer SS2 or the external gap fill pattern Ba. In some example embodiments, the second subspacer SS2 may contain oxygen, or may be formed using an oxygen-containing material, even when its final structure does not contain oxygen. As an example, the second subspacer SS2 may be formed of SiO 2 Forming or including SiO 2 In some example embodiments, the second subspacer SS2 may be an air gap between the first subspacer SS1 and the third subspacer SS3. In some example embodiments, the third subspacer SS3 may be formed of or include a nitrogen-containing material (eg, SiN).

[0044] If the bit line node contact DC is adjacent to oxygen, a failure, such as a failure based on oxygen diffusion, may occur during a subsequent heat treatment step performed as part of the manufacturing process. However, since the first subspacer SS1 is formed to have a sufficiently large thickness, a second region R2 in which oxygen is not diffused may be formed. The second region R2 may separate the bit line node contact DC from oxygen, and therefore, the possibility of such a failure that may occur when the bit line node contact DC contacts oxygen may be prevented or reduced.

[0045] In some example embodiments, the capping spacer CS may cover a side surface of an upper portion of the bit line capping pattern BCP. The capping spacer CS may also be provided on at least a portion of a top surface of the bit line spacer SPC.

[0046] The intermediate material IM may be placed between the gap filling insulating pattern BI (e.g., the outer gap filling pattern Ba) and the device isolation pattern STI. In some example embodiments, the intermediate material IM may be further placed between the gap filling insulating pattern BI and the central oxide region Oc and / or between the gap filling insulating pattern BI and the edge oxide region Oe. As described herein, the expression "intermediate material IM is positioned between element A and element B" should be understood to include the intermediate material IM being positioned in an inner portion of element B adjacent to element A or in an inner portion of element A adjacent to element B. In some example embodiments, the intermediate material IM may be positioned along the inner surface of the first recessed region RS1.

[0047] The intermediate material IM may include at least one of a halogen element and carbon. In some example embodiments, the intermediate material IM may be an unremoved portion or residue of a material used to form the first sub-spacer SS1. In some example embodiments, the intermediate material IM may be a residue of an etchant, which will be described below, and may contain a halogen element such as at least one of fluorine, chlorine, bromine, or iodine. In some example embodiments, the intermediate material IM may be a residue of an inhibitor, which will be described below, and may contain carbon.

[0048] A storage node contact BC may be provided between adjacent bit lines in the bit line BL. In some example embodiments, a plurality of storage node contacts BC may be provided, and the storage node contacts BC may be spaced apart from each other in the first direction D1 and the second direction D2. The storage node contact BC may be spaced apart from the bit line BL, and a bit line spacer SPC is interposed between the storage node contact BC and the bit line BL. The storage node contact BC may fill a second recessed region RS2 formed on an edge portion EA of the active pattern ACT. The storage node contact BC may be electrically connected to the edge portion EA. In some example embodiments, the storage node contact BC may contact the edge oxide region Oe and the edge non-oxide region NOe, and may be electrically connected to the edge non-oxide region NOe.

[0049] The storage node contact BC may include a conductive material. In some example embodiments, the storage node contact BC may be formed of or include at least one of doped polysilicon or a metallic material (e.g., at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0050] On the word line WL, the fence pattern FN may separate the storage node contacts BC from each other in the second direction D2. In some example embodiments, the fence patterns FN may be spaced apart from each other in the second direction D2 with the storage node contacts BC interposed therebetween. In some example embodiments, the fence pattern FN may be formed of or include silicon nitride.

[0051] The diffusion barrier layer DP may conformally cover the storage node contact BC and the bit line spacer SPC. The diffusion barrier layer DP may be formed of or include a conductive metal nitride material (e.g., containing at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, or Ag). A metal silicide layer may be further interposed between the diffusion barrier layer DP and the storage node contact BC.

[0052] A landing pad LP may be provided on the storage node contact BC. In some example embodiments, a plurality of landing pads LP may be provided, and the plurality of landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the landing pads LP may be connected to a corresponding one of the storage node contacts BC. The landing pad LP may cover the top surface of the bit line cover pattern BCP. In some example embodiments, the lower portion of the landing pad LP may overlap vertically with the storage node contact BC, and the upper portion of the landing pad LP may be offset from the lower portion in the second direction D2 or in the opposite direction thereof. The landing pad LP may be formed of at least one of a metallic material (e.g., one or more of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag) or include at least one of a metallic material (e.g., one or more of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0053] A filler pattern FI may be provided to surround the landing pad LP. The filler pattern FI may be inserted between the landing pads LP adjacent to each other. When viewed in a plan view, the filler pattern FI may be provided in a grid shape having holes, and in this case, the landing pad LP may be provided in the hole to penetrate the filler pattern FI. In some example embodiments, the filler pattern FI may be formed of or include at least one of silicon nitride, silicon oxide, or silicon oxynitride. In some example embodiments, the filler pattern FI may include an empty space having an air layer (e.g., an air gap).

[0054] A data storage pattern DSP may be provided on the landing pad LP. In some example embodiments, a plurality of data storage patterns DSP may be provided. The data storage patterns DSP may be spaced apart from each other in the first direction D1 and the second direction D2. Each of the data storage patterns DSP may be electrically connected to a corresponding one of the edge portions EA of the active pattern ACT through a corresponding one of the landing pads LP and a corresponding one of the storage node contacts BC.

[0055] In some example embodiments, the data storage pattern DSP may be or may include a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device according to some example embodiments of the present inventive concept may be or may include a dynamic random access memory (DRAM) device or be included in a dynamic random access memory (DRAM) device. Alternatively or additionally, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor memory device may be or may include a magnetic random access memory (MRAM) device or be included in a magnetic random access memory (MRAM) device. Alternatively or additionally, the data storage pattern DSP may be formed of a phase change material and / or a variable resistance material or include a phase change material and / or a variable resistance material. In this case, the semiconductor memory device may be a phase change random access memory (PRAM) device and / or a resistive random access memory (ReRAM) device, or may include a phase change random access memory (PRAM) device and / or a resistive random access memory (ReRAM) device, or may be included in a phase change random access memory (PRAM) device and / or a resistive random access memory (ReRAM) device. However, example embodiments are not limited to these examples, and the data storage pattern DSP may include various structures and / or materials that may be used to store data.

[0056] In the following, reference will be made to Figures 4 to 6 Some additional example embodiments are described. In the following description, for the sake of brevity, previously described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0057] Figures 4 to 6 is along Figure 1 A cross-sectional view taken along line AA'.

[0058] refer to Figure 4, a third recessed area RS3 may be provided below the second recessed area RS2. The third recessed area RS3 may be connected to the second recessed area RS2, and when viewed in a cross-sectional view, the third recessed area RS3 may have a width smaller than that of the second recessed area RS2. The inner surface of the second recessed area RS2 and the inner surface of the third recessed area RS3 may be connected to each other. The inner surface of the third recessed area RS3 may be defined by the edge portion EA (e.g., edge non-oxide area NOe) of the gap-filling insulating pattern BI and the active pattern ACT.

[0059] The storage node contact BC may include a protruding portion BCp. The protruding portion BCp of the storage node contact BC may fill the third recess region RS3. The protruding portion BCp may protrude toward the edge oxide region Oe.

[0060] refer to Figure 5 , the edge oxide region Oe may not be provided. The third recessed region RS3 may extend to the upper portion of the device isolation pattern STI to expose the side surface of the upper portion of the device isolation pattern STI. The protruding portion BCp of the storage node contact BC may fill the upper portion of the third recessed region RS3. The lower portion of the third recessed region RS3 may include an empty space (e.g., a void VD) that may or may not be in a vacuum.

[0061] refer to Figure 6 , the edge oxide region Oe may not be provided, such as Figure 5 However, Figure 5 Unlike the structure of the storage node contact BC, the protruding portion BCp of the storage node contact BC may be provided to completely fill the third recess region RS3. Therefore, the void VD may not be provided in the third recess region RS3.

[0062] Figures 7 to 22 is a diagram illustrating a method of manufacturing a semiconductor device according to various example embodiments. More specifically, Figure 7 , 10 , 13 , 16 , and 20 are cross-sectional plan views illustrating a method of manufacturing a semiconductor device according to various example embodiments. Figure 8 , 11 , 14, 15, 17, 19, 21 and 22 are respectively along Figure 7 , 10 , 13, 16 and 20 are cross-sectional views taken along line AA′. Fig. 9 and Fig.12 It is along Figure 7 and Fig.10 A cross-sectional view taken along line BB'. Fig.18 It is shown Fig.17 Hereinafter, reference will be made to the "P1" section of Figures 7 to 22 Manufacturing methods according to some example embodiments of the inventive concepts are described in more detail.

[0063] refer to Figures 7 to 9 , a substrate 100 may be prepared. A device isolation pattern STI and an active pattern ACT may be formed on the substrate 100. The formation of the device isolation pattern STI and the active pattern ACT may include performing a patterning process to form a trench region in the substrate 100, and filling the trench region with an insulating material to form the device isolation pattern STI. The active pattern ACT may be a portion of the substrate 100 where the trench region is not formed.

[0064] The word lines WL may be formed to cross the active pattern ACT and the device isolation pattern STI in the first direction D1. The formation of the word lines WL may include forming a mask pattern on the active pattern ACT and the device isolation pattern STI, performing an anisotropic etching process using the mask pattern to form a trench region, and filling the trench region with the word lines WL. The word lines WL may be spaced apart from each other in the second direction D2.

[0065] The paired word lines WL may be provided to cross the active pattern ACT, and a central portion CA of the active pattern ACT may be defined between the paired word lines WL. An opposing portion of the active pattern ACT, which is spaced apart from the central portion CA with each of the paired word lines WL interposed therebetween, may be defined as an edge portion EA.

[0066] refer to Figures 10 to 12 , a buffer layer BFL and a polysilicon layer PL may be formed on the device isolation pattern STI and the active pattern ACT. Next, a first recessed area RS1 may be formed on the central portion CA of the active pattern ACT. As a result of forming the first recessed area RS1, an upper portion of the device isolation pattern STI, an upper portion of the central portion CA of the active pattern ACT, and an upper portion of the edge portion EA of the active pattern ACT may be recessed. The first recessed area RS1 may vertically overlap the central portion CA and the edge portion EA of the active pattern ACT. In some example embodiments, the first recessed area RS1 may vertically overlap a portion of the edge portion EA of the active pattern ACT. The first recessed area RS1 may be provided to expose the central portion CA and the edge portion EA of the device isolation pattern STI and the active pattern ACT. The formation of the first recessed area RS1 may include performing etching, such as etching including an anisotropic etching process, on the polysilicon layer PL, the buffer layer BFL, the device isolation pattern STI, and the active pattern ACT.

[0067] A preliminary bit line node contact DCL may be formed to fill the first recessed region RS1. The preliminary bit line node contact DCL may be formed to cover the central portion CA of the active pattern ACT. In some example embodiments, a top surface of the preliminary bit line node contact DCL and a top surface of the polysilicon layer PL may be formed at substantially the same height and may be substantially coplanar with each other. Next, an ohmic layer OL, a bit line layer BLL, a bit line capping layer BCL, and a bit line mask pattern BM may be sequentially stacked on the preliminary bit line node contact DCL.

[0068] refer to Fig.13 and Fig.14 , an anisotropic etching process such as a dry etching process may be performed using the bit line mask pattern BM as an etching mask. The preliminary bit line node contact DCL, the polysilicon layer PL, the ohmic layer OL, the bit line layer BLL, and the bit line capping layer BCL may be etched by an anisotropic etching process to form a bit line node contact DC, a polysilicon pattern PP, an ohmic pattern OP, a bit line BL, and a bit line capping pattern BCP. During this process, the inner surface of the first recessed region RS1 and the buffer layer BFL may be exposed to the outside. In some example embodiments, the central portion CA and the edge portion EA of the active pattern ACT may be partially exposed by the inner surface of the first recessed region RS1.

[0069] refer to Fig.15 , an oxidation process may be performed on the exposed portions of the central portion CA and the edge portion EA of the active pattern ACT. As a result of the oxidation process, a central oxide region Oc of the central portion CA and an edge oxide region Oe of the edge portion EA may be formed. An unoxidized region of the central portion CA may be defined as a central non-oxide region NOc, and an unoxidized region of the edge portion EA may be defined as an edge non-oxide region NOe.

[0070] The oxidation process may occur sparsely or almost not on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. To this end, the oxidation process may include performing an anisotropic oxidation process in the third direction D3. In some example embodiments, the anisotropic oxidation process may include performing an anisotropic plasma oxidation process in the third direction D3. In some example embodiments, the anisotropic oxidation process may include an oxide deposition process in the third direction D3. In some example embodiments, the anisotropic oxidation process may include a beam line process (e.g., an ion implantation process) in the third direction D3. However, example embodiments are not limited thereto, and the oxidation process may be performed in various ways. For example, alternatively or additionally, the oxidation process may be or may include a thermal oxidation process; example embodiments are not limited thereto. In some example embodiments, during the oxidation process, the central portion CA and the edge portion EA may be partially oxidized, for example, single crystal silicon may be replaced with silicon oxide; example embodiments are not limited thereto. Steam may or may not be included in the oxidation process.

[0071] In some example embodiments, a removal process (e.g., an isotropic etching process) may be further performed to remove a small amount of an oxide layer formed on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. Even after removing the small amount of the oxide layer, both the central oxide region Oc and the edge oxide region Oe may remain.

[0072] refer to Figures 16 to 18 , the first subspacer SS1 may be formed on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. In some example embodiments, the first subspacer SS1 may be selectively formed. In some example embodiments, due to oxygen in the central oxide region Oc, the edge oxide region Oe, and the device isolation pattern STI, these portions may not have the first subspacer SS1 formed therein. For example, the first subspacer SS1 may be formed on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC, but may be formed to have little or a small amount of presence on the central oxide region Oc, the edge oxide region Oe, and the device isolation pattern STI. Therefore, after the first subspacer SS1 is formed, the central oxide region Oc and the edge oxide region Oe may be exposed to the outside. The first subspacer SS1 may even be further formed on the buffer layer BFL, but example embodiments are not limited thereto.

[0073] After forming the first sub-spacer SS1, the intermediate material IM may be left along the inner surface of the first recessed region RS1. In some example embodiments, the intermediate material IM may be or include an unremoved portion or residue of a material used to form the first sub-spacer SS1. (See Fig.25 and26 ).

[0074] refer to Fig.19 , a gap-filling insulating pattern BI may be formed in the first recessed region RS1. The gap-filling insulating pattern BI may be formed to fill the first recessed region RS1. The formation of the gap-filling insulating pattern BI may include forming an outer gap-filling pattern Ba on the substrate 100, forming an inner gap-filling pattern Bb to cover the outer gap-filling pattern Ba and fill the first recessed region RS1, and removing the outer gap-filling pattern Ba and the inner gap-filling pattern Bb from a region higher than the first recessed region RS1.

[0075] refer to Fig. 20 and Fig.21 , the second subspacer SS2 and the third subspacer SS3 may be formed on the side surface BLs of the bit line BL. The second subspacer SS2 and the third subspacer SS3 may be sequentially formed. The second recessed area RS2 may be formed by performing an etching process using the bit line capping pattern BCP as an etching mask. The second recessed area RS2 may be formed to expose the gap filling insulating pattern BI and the edge oxide area Oe. Since the first subspacer SS1 is selectively formed in the previous step, the second recessed area RS2 exposing the edge oxide area Oe may be easily or more easily formed.

[0076] refer to Fig. 22 , a removal process may be performed on the edge oxide region Oe exposed by the second recess region RS2. The removal process may include a wet etching process, such as a buffered hydrogen fluoride wet etching process; however, example embodiments are not limited thereto. As a result, the edge non-oxide region NOe may be exposed by the second recess region RS2.

[0077] Return to reference Figures 1 to 2B , a storage node contact BC and a fence pattern FN may be formed. The storage node contact BC may be formed to fill the second recessed region RS2. In the second recessed region RS2, the storage node contact BC may be electrically connected to the edge portion EA of the active pattern ACT through the edge non-oxide region NOe.

[0078] The fence pattern FN may be formed before or after forming the storage node contact BC. In some example embodiments, after forming the storage node contact BC, the fence pattern FN may be formed between the storage node contacts BC. The fence pattern FN may be formed before forming the second recess region RS2, and the storage node contact BC may be formed between the fence patterns FN.

[0079] The landing pad LP may be formed on the storage node contact BC. The formation of the landing pad LP may include sequentially forming a landing pad layer (not shown) and a mask pattern (not shown) to cover the top surface of the storage node contact BC, and performing an anisotropic etching process using the mask pattern as an etching mask to divide the landing pad layer into a plurality of landing pads LP.

[0080] Next, a filler pattern FI may be formed in a region formed by removing the landing pad layer. The filler pattern FI may be formed to surround each landing pad LP. A data storage pattern DSP may be formed on each landing pad LP.

[0081] According to some example embodiments, since the first subspacer SS1 is selectively formed, the edge oxide region Oe can be easily or more easily exposed, and therefore, the storage node contact BC can be easily or more easily electrically connected to the edge non-oxide region NOe. Optionally or additionally, the first subspacer SS1 is formed to have a sufficiently large thickness on the side surface DCs of the bit line node contact DC, and the bit line node contact DC can be separated from oxygen, and therefore, the possibility of failure that may occur when the bit line node contact DC contacts oxygen can be prevented or reduced. As a result, the failure of the semiconductor device can be reduced, and the electrical characteristics and / or reliability characteristics of the semiconductor device can be improved. For example, the yield can be increased.

[0082] Fig.23 and Fig.24 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to various example embodiments.

[0083] refer to Fig.23 , a removal process may be performed on the edge oxide region Oe exposed by the second recess region RS2. A third recess region RS3 may be further formed in the region formed by removing the edge oxide region Oe. Therefore, a storage node contact BC may be formed in a subsequent process to fill the second recess region RS2 and the third recess region RS3, and a semiconductor device may be formed to have Figure 4 The final structure is shown.

[0084] refer to Fig.24 , the edge oxide region Oe exposed by the second recessed region RS2 may be completely removed. Therefore, the third recessed region RS3 may extend to the upper portion of the device isolation pattern STI to expose the side surface of the upper portion of the device isolation pattern STI. In some example embodiments, the storage node contact BC may fill a portion of the third recessed region RS3 in a subsequent process, and in this case, the semiconductor device may be formed to have Figure 5In some example embodiments, the storage node contact BC may fill the entire third recess region RS3 in a subsequent process, and in this case, the semiconductor device may be formed to have Figure 6 The structure shown.

[0085] Fig.25 and Fig.26 is a flow chart illustrating a method of manufacturing a first sub-spacer.

[0086] refer to Fig.25 , the selective formation of the first sub-spacer SS1 may include depositing a first reactant (in S10), removing the first reactant from the central oxide region Oc and the edge oxide region Oe using an etchant (in S15), and reacting a second reactant with a remaining portion of the first reactant (in S20). In some example embodiments, steps S10, S15, and S20 may be alternately and repeatedly performed to selectively form the first sub-spacer SS1.

[0087] The depositing of the first reactant (in S10) may include selectively depositing the first reactant. The first reactant may include a precursor (e.g., including silicon (Si)). In some example embodiments, the precursor may also include a halogen element. As an example, the precursor may include DCS (SiH 2 Cl 2 )、TCS(SiCl 4 ), or DIS(SiH 2 I 2 ), but example embodiments are not limited thereto. The precursor may include a material having a deposition selectivity. As an example, the precursor may be relatively more deposited on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC, and may be sparsely or almost not on the central oxide region Oc and the edge oxide region Oe including the oxide material. For example, the first reactant may be selectively deposited on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC.

[0088] The central oxide region Oc and the edge oxide region Oe may be exposed by removing the first reactant from the central oxide region Oc and the edge oxide region Oe (in S15). Even when the removal process (S15) is performed, the first reactant may remain on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. The etchant may include a halogen element. As an example, the etchant may include a gas containing at least one of a halogen element (e.g., F and Cl).

[0089] The reaction between the first reactant and the second reactant (in S20) may include reacting the second reactant with the first reactant, the first reactant being located on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. On the central oxide region Oc and the edge oxide region Oe, the reaction between the first reactant and the second reactant may be suppressed because the etchant suppresses the reaction of the first reactant. As a result of the reaction between the first reactant and the second reactant, a first subspacer SS1 may be formed. As a result, the first subspacer SS1 may be selectively formed by forming the first reactant on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC and removing the first reactant from the central oxide region Oc and the edge oxide region Oe. In some example embodiments, the second reactant may include NH 3 , but example embodiments are not limited thereto.

[0090] Even after forming the first sub-spacer SS1, a portion of the etchant may remain along the inner surface of the first recessed region RS1 and may be located between the gap-filling insulating pattern BI and the device isolation pattern STI in a subsequent process. In this case, the intermediate material IM may include a portion of the etchant, and in some example embodiments, it may include a halogen element.

[0091] refer to Fig.26 , the selective formation of the first sub-spacer SS1 may include forming an inhibitor on the central oxide region Oc and the edge oxide region Oe (in S00), depositing a first reactant (in S10), and reacting a second reactant with the first reactant (in S20). In some example embodiments, steps S00, S10, and S20 may be alternately and repeatedly performed to selectively form the first sub-spacer SS1.

[0092] In some example embodiments, forming the inhibitor on the central oxide region Oc and the edge oxide region Oe (in S00) may include selectively forming the inhibitor on the central oxide region Oc and the edge oxide region Oe. As an example, the inhibitor may be selectively formed on the central oxide region Oc and the edge oxide region Oe containing the oxide material, but may be formed to have little or a small amount of presence on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. In some example embodiments, the inhibitor may contain carbon.

[0093] The deposition of the first reactant (in S10) may include selectively depositing the first reactant. Due to the presence of the inhibitor, the first reactant may be sparsely or almost not deposited on the central oxide region Oc and the edge oxide region Oe. Therefore, the first reactant may be selectively deposited on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC.

[0094] The reaction of the first reactant and the second reactant (in S20) may include reacting the second reactant with the first reactant on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC. Since the inhibitor inhibits the deposition of the first reactant on the central oxide region Oc and the edge oxide region Oe, the reaction between the first reactant and the second reactant may be inhibited. As a result, the first subspacer SS1 may be selectively formed on the side surface BLs of the bit line BL and the side surface DCs of the bit line node contact DC.

[0095] After forming the first subspacer SS1, the inhibitor may partially remain on the inner surface of the first recess region RS1 and may be located between the gap-filling insulating pattern BI and the device isolation pattern STI during subsequent processes. In this case, the intermediate material IM may contain a portion of the inhibitor (eg, carbon) in the final stage.

[0096] However, Fig.25 and Fig.26 Examples of various methods for forming the first sub-spacer SS1 are shown. For example, if the deposition selectivity of the first reactant is good, the first sub-spacer SS1 can be selectively formed using the deposition of the first reactant (in S10) and the reaction of the first reactant with the second reactant (in S20) without using an etchant or an inhibitor. In some example embodiments, both an etchant and an inhibitor can be used; for example, the steps of forming an inhibitor (in S00), depositing the first reactant (in S10), removing the first reactant using an etchant (in S15), and reacting the first reactant with the second reactant (in S20) can be performed in sequence.

[0097] According to some example embodiments of the present inventive concept, the first sub-spacer can be selectively formed. This can make it easy or more likely to connect the storage node contact to the edge portion of the active pattern and prevent failures that may occur when the bit line node contact contacts oxygen. As a result, failures in the semiconductor device can be reduced, and the electrical characteristics and / or reliability characteristics of the semiconductor device can be improved.

[0098] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that precision of the geometric shape is not required, but tolerance of the shape is within the scope of the present disclosure. In addition, when the words "approximately" and "substantially" are used in conjunction with a material composition, it is intended that precision of the material is not required, but tolerance of the material is within the scope of the present disclosure.

[0099] In addition, regardless of whether a value or shape is modified to be "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the value or shape. Therefore, although the terms "same", "equivalent" or "equal" are used in the description of example embodiments, it should be understood that there may be some imprecision. Therefore, when an element or a value is referred to as being the same as or equal to another value as another element, it should be understood that the element or value is the same as the other element or another value within the desired manufacturing or operating tolerance range (e.g., ±10%).

[0100] Although various example embodiments of the present invention have been specifically shown and described, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. In addition, the example embodiments are not necessarily mutually exclusive of each other. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This patent application claims the priority of Korean Patent Application No. 10-2023-0111731 filed in the Korean Intellectual Property Office on August 25, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a first active pattern and a second active pattern, each of which includes a center portion and an edge portion, the center portion of the first active pattern and the edge portion of the second active pattern being adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a bit line node contact on the central portion of the first active pattern; a bit line on the bit line node contact; a storage node contact on the edge portion of the second active pattern; a bit line spacer between the bit line and the storage node contact; as well as a gap-filling insulating pattern between a lower portion of the bit line spacer and the storage node contact, Wherein the central portion of the first active pattern includes a central oxide region provided in an upper portion thereof. 2 . The semiconductor device according to claim 1 , wherein the bit line spacer covers a side surface of the bit line and extends to a side surface of the bit line node contact.

3. The semiconductor device according to claim 1, wherein The bit line spacer includes a first sub-spacer and a second sub-spacer sequentially provided on a side surface of the bit line, and The first sub-spacer is spaced apart from the storage node contact.

4. The semiconductor device according to claim 3, wherein: The first subspacer comprises: a first region adjacent to the second subspacer; and a second region separating the first region from the bit line, The first region contains oxygen and nitrogen.

5. The semiconductor device according to claim 1, further comprising: an intermediate material between the gap-filling insulating pattern and the device isolation pattern, Wherein, the intermediate material includes at least one of halogen elements and carbon. 6 . The semiconductor device of claim 1 , wherein the gap-filling insulating pattern is spaced apart from the bit line node contact and is in contact with the device isolation pattern. 7 . The semiconductor device of claim 1 , wherein the gap-filling insulating pattern vertically and partially overlaps the edge portion of the second active pattern.

8. The semiconductor device according to claim 1, wherein The gap-filling insulating pattern includes an outer gap-filling pattern contacting the device isolation pattern, and The outer gap-filling pattern contains oxygen. 9 . The semiconductor device of claim 1 , wherein the gap-fill insulating pattern separates the lower portion of the bit line spacer from the storage node contact. 10 . The semiconductor device according to claim 1 , wherein the central oxide region comprises a pair of central oxide regions spaced apart from each other in a first direction. 11 . The semiconductor device of claim 1 , wherein the edge portion of the second active pattern comprises an edge oxide region contacting the gap-filling insulating pattern. 12 . The semiconductor device of claim 11 , wherein the edge oxide region is in contact with the storage node contact.

13. A semiconductor device comprising: a first active pattern and a second active pattern adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a recessed area defined by the first active pattern and the device isolation pattern; a bit line node contact on the first active pattern; a gap-filling insulating pattern on a side surface of the bit line node contact and filling the recessed area; a bit line spacer between the side surface of the bit line node contact and the gap-filling insulating pattern; as well as an intermediate material between the gap-filling insulating pattern and the device isolation pattern, Wherein, the intermediate material includes at least one of halogen elements and carbon. The semiconductor device according to claim 13 , wherein the intermediate material is along an inner surface of the recessed region. 15 . The semiconductor device of claim 13 , wherein the gap-filling insulating pattern is spaced apart from the bit line node contact and is in contact with the device isolation pattern. 16 . The semiconductor device of claim 13 , wherein the gap-filling insulating pattern vertically and partially overlaps an edge portion of the second active pattern, the edge portion of the second active pattern being adjacent to a central portion of the first active pattern. 17 . The semiconductor device of claim 13 , wherein the gap-filling insulating pattern is in contact with an inner surface of the recess region.

18. The semiconductor device according to claim 17, wherein The gap-filling insulating pattern includes an outer gap-filling pattern conformally covering the inner surface of the recessed region, and The outer gap-filling pattern contains oxygen.

19. A semiconductor device comprising: a first active pattern and a second active pattern, each of which includes a center portion and an edge portion, the center portion of the first active pattern and the edge portion of the second active pattern being adjacent to each other; a device isolation pattern between the first active pattern and the second active pattern; a bit line node contact on the central portion of the first active pattern; a bit line on the bit line node contact; a gap-fill insulating pattern on a side surface of the bit line node contact; as well as a bit line spacer covering a side surface of the bit line and extending to a region between the side surface of the bit line node contact and the gap-filling insulating pattern, The gap-filling insulating pattern contacts the device isolation pattern and vertically and partially overlaps the edge portion of the second active pattern. 20 . The semiconductor device of claim 19 , wherein the gap-fill insulating pattern is spaced apart from the bit line node contact by the bit line spacer.

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