Memory and manufacturing method thereof
By forming metal silicide on the first wafer of the memory, forming a ferroelectric layer or a magnetic layer on the second wafer, and then bonding, the thermal stability problem of nickel silicide in high temperature environments is solved, and the performance of the memory is improved.
Patent Information
- Application Number
- CN202311076781.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-24
- Publication Date
- 2025-02-25
AI Technical Summary
When preparing ferroelectric materials and magnetic materials, high temperature environments will lead to thermal stability problems of nickel silicide, resulting in diffusion and other defects, affecting the performance of the memory.
By forming a metal silicide on the first wafer and forming a ferroelectric or magnetic layer on the second wafer, and then bonding the two, the influence of the high temperature environment on the metal silicide is avoided.
While ensuring the advantages of metal silicides, it avoids defects that may arise at high temperatures, thereby improving the performance of the memory.
Smart Images
Figure CN119521679A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a memory and a manufacturing method thereof. Background Art
[0002] In the existing MOS transistor process, in order to improve the ohmic contact between the gate, source and drain of the transistor and the filling plug, metal silicide is usually formed on the surface of the gate, source and drain. As the device size develops towards smaller methods, the metal silicide process has become the industry's preferred choice, among which nickel metal silicide (nickel silicide, NiSi) has the advantages of low interface resistance and low silicon loss and has become the industry's favorite choice. However, the disadvantage of nickel silicide is that it has poor thermal stability at high temperatures and is prone to defects such as diffusion (piping) at high temperatures.
[0003] Compared with traditional memories, FeRAM (Ferroelectric RAM) and MRAM (Magnetoresistive Random Access Memory) have the advantages of non-volatility, higher writing speed, higher read and write endurance, lower power consumption, etc. However, the process requirements are also relatively strict, especially when it comes to the preparation process of ferroelectric materials and magnetic materials, which requires high temperature conditions, such as up to 800°C or even higher. High temperature environment will cause defects in nickel silicide or inactivate the doped ions in the active area.
[0004] Therefore, how to avoid the defects of nickel silicide caused by high temperature during the preparation of ferroelectric materials and magnetic materials is an urgent problem to be solved by those skilled in the art. Summary of the invention
[0005] The object of the present invention is to provide a memory and a method for manufacturing the same, which can avoid the defect problem of nickel silicide caused by high temperature during the preparation of ferroelectric materials and magnetic materials.
[0006] To solve the above technical problem, according to a first aspect of the present invention, a method for manufacturing a memory is provided, comprising the following steps:
[0007] Providing a first wafer, wherein a transistor is formed in the first wafer, and the transistor includes a metal silicide;
[0008] providing a second wafer, wherein a capacitor is formed in the second wafer, the capacitor comprising a ferroelectric layer or a magnetic layer; and
[0009] The first wafer is bonded to the second wafer.
[0010] Optionally, the temperature used when forming the capacitor in the second wafer is higher than the thermal stability temperature of the metal silicide.
[0011] Optionally, the first wafer includes a first substrate and a first insulating layer located on the first substrate, the transistor includes a gate located on the first substrate and a source and a drain located in the first substrate on both sides of the gate, the first insulating layer covers the gate, and the metal silicide is formed on the gate, the source and the drain.
[0012] Optionally, the metal silicide includes at least one of nickel silicide, nickel platinum silicide, titanium silicide, titanium platinum silicide, cobalt silicide, and cobalt platinum silicide.
[0013] Optionally, metal plugs electrically connected to the gate, the source and the drain respectively and a first metal layer electrically connected to the metal plugs are formed in the first insulating layer, and the first insulating layer is away from a surface of the first substrate to expose the first metal layer.
[0014] Optionally, the second wafer includes a second substrate and a second insulating layer located on the second substrate, a plurality of capacitors and a plurality of second metal layers are formed in the second insulating layer, the second metal layers electrically connected to the capacitors are arranged on both sides of the capacitors, and the second insulating layer exposes the second metal layer away from the surface of the second substrate.
[0015] Optionally, when the first wafer is bonded to the second wafer, the first metal layer on the surface of the first insulating layer is bonded to the second metal layer on the surface of the second insulating layer.
[0016] Optionally, a first bonding mark is formed in the first insulating layer, and a second bonding mark is formed in the second insulating layer, and the first wafer and the second wafer are bonded via the first bonding mark and the second bonding mark.
[0017] Optionally, after bonding the first wafer to the second wafer, the manufacturing method further includes:
[0018] removing the second substrate;
[0019] Thinning the second insulating layer until the second metal layer is exposed;
[0020] A third metal layer, a metal pad and a third insulating layer surrounding the third metal layer and the metal pad are formed on the second insulating layer, the metal pad, the third metal layer and the second metal layer are electrically connected in sequence, and the third insulating layer is away from the surface of the second insulating layer to expose the metal pad.
[0021] In order to solve the above technical problem, according to a second aspect of the present invention, a memory is provided, which is manufactured by the manufacturing method of the memory as described above.
[0022] In summary, in the memory and the manufacturing method thereof provided by the present invention, a first wafer formed with a metal silicide and a second wafer formed with a ferroelectric layer or a magnetic layer are provided, and then the first wafer and the second wafer are bonded. Since the ferroelectric layer or the magnetic layer is formed in the second wafer and the metal silicide is formed in the first wafer, the high temperature environment when the ferroelectric layer or the magnetic layer is formed will not affect the metal silicide and the active area, so that the advantages of the metal silicide are guaranteed while the defects of the metal silicide are not caused, thereby improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0024] Figure 1 It is a flowchart of a method for manufacturing a memory provided by an embodiment of the present invention.
[0025] Figures 2 to 6 It is a schematic structural diagram of each step of a method for manufacturing a memory provided by an embodiment of the present invention.
[0026] In the attached figure:
[0027] 10-first wafer; 11-first substrate; 12-gate; 13-source; 14-drain; 15-sidewall; 16-first insulating layer; 17-metal plug; 18-first metal layer; 20-second wafer; 21-second substrate; 22-second insulating layer; 23-second metal layer; 24-capacitor; 31-third insulating layer; 32-third metal layer; 33-metal pad. DETAILED DESCRIPTION
[0028] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0029] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.
[0030] The core idea of the present invention is to provide a memory and a method for manufacturing the same, forming a metal silicide in a first wafer and a ferroelectric layer or a magnetic layer in a second wafer, thereby avoiding the high temperature environment when forming the ferroelectric layer or the magnetic layer from affecting the metal silicide and avoiding defects caused by the metal silicide.
[0031] The method for manufacturing the memory includes: providing a first wafer, forming a transistor in the first wafer, and the transistor includes a metal silicide; providing a second wafer, forming a capacitor in the second wafer, and the capacitor includes a ferroelectric layer or a magnetic layer; and bonding the first wafer to the second wafer.
[0032] The memory is manufactured by using the manufacturing method of the memory as described above.
[0033] The present invention forms a capacitor including a ferroelectric layer or a magnetic layer in a second wafer and forms a transistor including a metal silicide in a first wafer. The high temperature environment when forming the ferroelectric layer or the magnetic layer will not affect the metal silicide, thereby ensuring the advantages of the metal silicide without causing defects to the metal silicide, thereby improving the performance of the memory.
[0034] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a memory provided by an embodiment of the present invention. Figure 1 As shown, the manufacturing method of the memory provided in this embodiment includes the following steps:
[0035] S1: providing a first wafer, wherein the first wafer has transistors, and the transistors include metal silicide;
[0036] S2: providing a second wafer, wherein a capacitor is formed in the second wafer, and the capacitor includes a ferroelectric layer or a magnetic layer; and
[0037] S3: Bonding the first wafer and the second wafer.
[0038] It should be understood that although Figure 1 The steps in the flowchart shown are displayed in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; moreover, these steps are not necessarily executed in sequence, and the present application does not exclude the situation where at least two steps are executed at the same time or are executed alternately, for example, step S2 can be executed synchronously with step S1. The execution order between the steps should still be determined according to the specific logical relationship.
[0039] Figures 2 to 6 FIG. 1 is a schematic diagram of the structure of each step of the method for manufacturing a memory provided by an embodiment of the present invention. Figure 1 and Figures 2 to 6 The method for manufacturing the memory provided by the embodiment of the present invention is described in detail.
[0040] In step S1, refer to Figure 2 As shown, a first wafer 10 is provided, in which transistors are formed, and the transistors include metal silicide.
[0041] In this embodiment, the first wafer 10 includes a first substrate 11 and a first insulating layer 16 located on the first substrate 11. The material of the first substrate 11 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., or it can be silicon on insulator, germanium on insulator; or it can also be other materials, such as III-V compounds such as gallium arsenide. The present invention is not limited to this. The first insulating layer 16 is used to isolate the devices and metal layers in the first wafer 10, and its material includes but is not limited to silicon oxide, such as silicon dioxide.
[0042] A transistor is formed on the first substrate 11, and the transistor includes metal silicide. Exemplarily, the transistor includes a gate 12 located on the first substrate 11 and a source 13 and a drain 14 located in the first substrate 11 on both sides of the gate 12. Sidewalls 15 are also formed on both sides of the gate 12, and a gate oxide layer (not shown) is also formed between the gate 12 and the first substrate 11. The first insulating layer 16 covers the gate 12, the sidewalls 15 and the first substrate 11.
[0043] The metal silicide (not shown) is formed on the surface of the gate 12, the source 13 and the drain 14. The metal silicide includes but is not limited to at least one of nickel silicide, nickel platinum silicide, titanium silicide, titanium platinum silicide, cobalt silicide and cobalt platinum silicide, and may also include other metal silicides known to those skilled in the art that have poor thermal stability in a high temperature environment, and of course may also include any other metal silicides known to those skilled in the art.
[0044] A metal plug 17 electrically connected to the gate 12 , the source 13 , and the drain 14 , respectively, and a first metal layer 18 electrically connected to the metal plug 17 are formed in the first insulating layer 16 . The first insulating layer 16 is away from the surface of the first substrate 11 , exposing the first metal layer 18 .
[0045] A plurality of first metal layers 18 are formed in the first insulating layer 16, and each of the first metal layers 18 may be a multi-layer metal layer. Figure 2 Only two layers are shown in the figure, and two adjacent metal layers are electrically connected through metal plugs. Figure 2 The metal plugs between metal layers are not distinguished in the present invention, and are uniformly identified as first metal layers 18. Figure 2 Different adjacent first metal layers 18 in the horizontal direction are isolated by the first insulating layer 16. The first metal layer 18 is electrically connected to the metal plug 17, and the metal plug 17 is electrically connected to the gate 12, the source 13 and the drain 14 respectively.
[0046] A first bonding mark 19 is also formed in the first insulating layer 16 , and the first bonding mark 19 is exposed on the surface of the first insulating layer 16 away from the first substrate 11 , that is, the upper surface of the first bonding mark 19 is flush with the upper surface of the first insulating layer 16 , for subsequent bonding with the second wafer.
[0047] Exemplarily, first, a gate 12 is formed on the first substrate 11, then, a sidewall 15 is formed on the first substrate 11 on both sides of the gate 12, and then, a source 13 and a drain 14 are formed in the first substrate 11 on both sides of the gate 12. Afterwards, a metal material layer may be formed on the first substrate 11, the metal material layer covering the gate 12, the sidewall 15, and the first substrate 11. Then, a rapid thermal treatment is performed so that the metal material layer reacts with silicon in the gate 12, the source 13, and the drain 14 to form a metal silicide, and then the remaining metal material layer is removed.
[0048] Next, a first insulating layer 16 of a partial thickness is formed on the first substrate 11, the first insulating layer 16 is etched to form a through hole, and a metal is filled in the through hole to form a metal plug 17. Then, the first insulating layer 16 of a partial thickness is further formed, the first insulating layer 16 is etched to form a groove, and a metal is filled in the groove to form a first metal layer 18. The above steps can be repeated until multiple layers of first metal layers 18 are formed, and the multiple layers of first metal layers 18 are electrically connected through metal plugs, and finally a structure as shown in FIG. Figure 2 The structure shown can form the first bonding mark 19 while forming the last first metal layer 18. Of course, the manufacturing steps of the first wafer 10 are not limited thereto, and can also be formed by other methods known to those skilled in the art, which is not limited by the present invention.
[0049] In step S2, please refer to Figure 3 As shown, a second wafer 20 is provided, in which a capacitor 24 is formed. The capacitor 24 includes a ferroelectric layer or a magnetic layer.
[0050] A capacitor 24 is formed in the second wafer 20, and the capacitor 24 includes a dielectric layer, i.e., a capacitor dielectric layer, and the dielectric layer is a ferroelectric layer or a magnetic layer. Specifically, the capacitor 24 includes a first electrode, a dielectric layer, and a second electrode stacked in sequence, and the dielectric layer is a ferroelectric layer or a magnetic layer. Of course, the dielectric layer does not only include one ferroelectric layer or a magnetic layer, but may include multiple layers, which is not limited in the present invention.
[0051] The second wafer 20 includes a second substrate 21 and a second insulating layer 22 located on the second substrate 21. The second substrate 21 will be subsequently peeled off from the second insulating layer 22, and the second substrate 21 may be a glass substrate, a sapphire substrate, a silicon substrate, or other substrates known to those skilled in the art. The second insulating layer 22 is used to isolate the metal layer in the second wafer 20, and its material includes but is not limited to silicon oxide, such as silicon dioxide.
[0052] A plurality of capacitors 24 are formed in the second insulating layer 22 , and the capacitors 24 correspond to the gate 12 , the source 13 or the drain 14 in the first wafer 10 , that is, after subsequent bonding, the capacitors 24 electrically connected thereto are formed on the gate 12 , the source 13 or the drain 14 .
[0053] A plurality of second metal layers 23 are also formed in the second insulating layer 22, and the plurality of second metal layers 23 are isolated by the second insulating layer 22, and each second metal layer 23 may include multiple metal layers. The second metal layer 23 may correspond to the gate 12, the source 13, and the drain 14 in the first wafer 10. The capacitor 24 is located in the second metal layer 23, that is, the second metal layer 23 is formed on both sides of the capacitor 24 and is electrically connected to the capacitor 24. In this embodiment, the capacitor 24 is located in the second metal layer 23 corresponding to the gate 12, but is not limited thereto.
[0054] The second metal layer 23 is exposed on the surface of the second insulating layer 22 away from the second substrate 21, that is, the upper surface of the second metal layer 23 is flush with the upper surface of the second substrate 21. The lower surface of the second metal layer 23 and the lower surface of the second substrate 21 may have a gap therebetween.
[0055] A second bonding mark 25 is also formed in the second insulating layer 22 , and the second bonding mark 25 is exposed on the surface of the second insulating layer 22 away from the second substrate 21 , that is, the upper surface of the second bonding mark 25 is flush with the upper surface of the second insulating layer 22 , for subsequent bonding with the first wafer 10 .
[0056] Exemplarily, a second insulating layer 22 of partial thickness is formed on the second substrate 21, the second insulating layer 22 is etched to form a plurality of grooves, and a metal layer is filled in the grooves to form a second metal layer 23. Then, the second insulating layer 22 of partial thickness is further formed, the second insulating layer 22 is etched to form a through hole exposing the second metal layer 23, and a metal is filled in the through hole to form a metal plug electrically connected to the second metal layer 23. Then, the above steps are repeated to form multiple layers of second metal layers 23 connected to each other through metal plugs. Figure 3 In the figure, the second metal layer and the metal plug are not distinguished and are uniformly identified as the second metal layer 23 .
[0057] When forming one of the second metal layers 23, the capacitor 24 can be formed in part of the groove. The temperature used when forming the capacitor 24 is higher than the thermal stability temperature of the metal silicide. The thermal stability temperature means that at this temperature, the performance of the metal silicide will change, such as deactivation, phase change, resistance increase, morphology change, accelerated diffusion, etc. When forming the ferroelectric layer or magnetic layer in the capacitor 24, it is formed under a high temperature environment. However, since the ferroelectric layer or magnetic layer and the metal silicide are formed on different wafers, even if the temperature used when forming the capacitor 24 is higher than the thermal stability temperature of the metal silicide, the high temperature environment when forming the capacitor 24 before bonding will not affect the performance of the metal silicide. When forming the last second metal layer 23, the second bonding mark 25 can be formed at the same time. Of course, the manufacturing steps of the second wafer 20 are not limited to this, and can also be formed by other methods known to those skilled in the art, and the present invention is not limited to this.
[0058] In step S3, please refer to Figure 4 As shown, the first wafer 10 and the second wafer 20 are bonded.
[0059] The first insulating layer 16 is bonded to the second insulating layer 22, and the first metal layer 18 formed in the first insulating layer 16 is bonded to the second metal layer 23 formed in the second insulating layer 22. The second metal layer 23 is electrically connected to the first metal layer 18 and to the gate 12, the source 13 or the drain 14. In this embodiment, a capacitor 24 is formed between the metal layers electrically connected to the gate 12, but is not limited thereto.
[0060] In the present application, a metal silicide is formed on the first substrate 11, and a ferroelectric layer or a magnetic layer is formed on the second substrate 21. The high temperature environment when forming the ferroelectric layer or the magnetic layer will not affect the metal silicide and the active area, thereby ensuring the advantages of the metal silicide without causing defects to the metal silicide, thereby improving the performance of the memory.
[0061] Please refer to Figure 5 As shown, after bonding the first wafer 10 and the second wafer 20, the second substrate 21 is removed, and then the second insulating layer 22 is thinned to expose the second metal layer 23. The second insulating layer 22 can be thinned by rough grinding and fine grinding.
[0062] Please refer to Figure 6As shown, a third metal layer 32, a metal pad 33, and a third insulating layer 31 surrounding the third metal layer 32 and the metal pad 33 are formed on the second insulating layer 22. Exemplarily, a third insulating layer 31 of a partial thickness is formed on the second insulating layer 22, the third insulating layer 31 is etched to form a through hole or a groove exposing the second metal layer 23, and metal is filled in the through hole or the groove to form the third metal layer 32. Of course, the third metal layer 32 can be a metal layer or a metal plug. Then, the third insulating layer 31 of a partial thickness is formed, the third insulating layer 31 is etched to form a groove exposing the third metal layer 32, and metal is filled in the groove to form a metal pad 33. In this embodiment, only the metal pad 33 electrically connected to the source 13 is shown, but it is not limited to this.
[0063] Correspondingly, the present invention also provides a memory, which is manufactured using the manufacturing method of the memory as described above. Figure 6 As shown, the memory includes:
[0064] A first wafer, wherein a transistor is formed in the first wafer, and the transistor includes a metal silicide;
[0065] The second wafer is located on the first wafer. A capacitor 24 is formed in the second wafer. The capacitor 24 includes a ferroelectric layer or a magnetic layer.
[0066] Further, the first wafer includes a first substrate 11 and a first insulating layer 16 located on the first substrate 11. A transistor is formed in the first wafer, and the transistor includes a gate 12 located on the first substrate 11, and a source 13 and a drain 14 located in the first substrate 11 on both sides of the gate 12. Sidewalls 15 are also formed on both sides of the gate 12, and a gate oxide layer (not shown) is also formed between the gate 12 and the first substrate 11. The metal silicide is formed on the gate 12, the source 13, and the drain 14;
[0067] Also formed are: a plurality of metal plugs 17 and a plurality of first metal layers 18 located in the first insulating layer 16 . The metal plugs 17 are electrically connected to the gate 12 , the source 13 or the drain 14 . The first metal layer 18 is electrically connected to the metal plugs 17 .
[0068] The first metal layer 18 is exposed on the upper surface of the first insulating layer 16 , that is, the upper surface of the first insulating layer 16 is flush with the upper surface of the first metal layer 18 .
[0069] Furthermore, the second wafer comprises a second insulating layer 22. The second wafer is formed with:
[0070] A plurality of capacitors 24 are connected to a plurality of second metal layers 23, and each of the second metal layers 23 is electrically connected to each of the first metal layers 18. The capacitors 24 are formed between the second metal layers 23 electrically connected to the gate electrode 12.
[0071] The second metal layer 23 is exposed on a surface of the second insulating layer 22 away from the first insulating layer 16 .
[0072] The memory further includes a third insulating layer 31, and a third metal layer 32 and a metal pad 33 formed in the third insulating layer 31. The third metal layer 32 is electrically connected to the second metal layer 23, and the metal pad 33 is electrically connected to the third metal layer 32. The metal pad 33 is exposed on a surface of the third insulating layer 31 away from the second insulating layer 22.
[0073] In summary, in the memory device and the manufacturing method thereof provided by the present invention, a first wafer formed with a metal silicide and a second wafer formed with a ferroelectric layer or a magnetic layer are provided, and then the first wafer and the second wafer are bonded. Since a ferroelectric layer or a magnetic layer is formed in the second wafer and a metal silicide is formed in the first wafer, the high temperature environment when the ferroelectric layer or the magnetic layer is formed will not affect the metal silicide and the active area, thereby ensuring the advantages of the metal silicide without causing defects to the metal silicide, thereby improving the performance of the memory device.
[0074] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a memory, characterized in that: The following steps are involved: Providing a first wafer, wherein a transistor is formed in the first wafer, and the transistor includes a metal silicide; Providing a second wafer, wherein a capacitor is formed in the second wafer, and the capacitor includes a ferroelectric layer or a magnetic layer; as well as The first wafer is bonded to the second wafer.
2. The method for manufacturing a memory according to claim 1, characterized in that: The temperature used when forming the capacitor in the second wafer is higher than the thermal stability temperature of the metal silicide.
3. The method for manufacturing a memory according to claim 1, characterized in that: The first wafer includes a first substrate and a first insulating layer located on the first substrate, the transistor includes a gate located on the first substrate and a source and a drain located in the first substrate on both sides of the gate, the first insulating layer covers the gate, and the metal silicide is formed on the gate, the source and the drain.
4. The method for manufacturing a memory according to any one of claims 1 to 3, characterized in that: The metal silicide includes at least one of nickel silicide, nickel platinum silicide, titanium silicide, titanium platinum silicide, cobalt silicide, and cobalt platinum silicide.
5. The method for manufacturing a memory according to claim 3, characterized in that: Metal plugs electrically connected to the gate, the source and the drain respectively and a first metal layer electrically connected to the metal plugs are formed in the first insulating layer, and the first insulating layer is away from a surface of the first substrate to expose the first metal layer.
6. The method for manufacturing a memory according to claim 5, characterized in that: The second wafer includes a second substrate and a second insulating layer located on the second substrate, a plurality of capacitors and a plurality of second metal layers are formed in the second insulating layer, the second metal layers electrically connected to the capacitors are arranged on both sides of the capacitors, and the second insulating layer exposes the second metal layer away from the surface of the second substrate.
7. The method for manufacturing a memory according to claim 6, characterized in that: When the first wafer is bonded to the second wafer, the first metal layer on the surface of the first insulating layer is bonded to the second metal layer on the surface of the second insulating layer.
8. The method for manufacturing a memory according to claim 6 or 7, characterized in that: A first bonding mark is formed in the first insulating layer, and a second bonding mark is formed in the second insulating layer. The first wafer and the second wafer are bonded via the first bonding mark and the second bonding mark.
9. The method for manufacturing a memory according to claim 6 or 7, characterized in that: After bonding the first wafer to the second wafer, the manufacturing method further includes: removing the second substrate; Thinning the second insulating layer until the second metal layer is exposed; A third metal layer, a metal pad and a third insulating layer surrounding the third metal layer and the metal pad are formed on the second insulating layer, the metal pad, the third metal layer and the second metal layer are electrically connected in sequence, and the third insulating layer is away from the surface of the second insulating layer to expose the metal pad.
10. A memory, characterized in that: The memory is manufactured by the manufacturing method of any one of claims 1 to 9.