Semiconductor rectification device and manufacturing method thereof

Abstract

The invention relates to a semiconductor rectification device and a manufacturing method thereof. The semiconductor rectification device includes: an epitaxial layer having a top surface and a bottom surface opposite to each other; the first doped region is located in the epitaxial layer, and the first doped region has a first conductive type; the first groove structure is located in the first doped region and extends from the top surface to the bottom surface; the second groove structure is located in the first doped region, extends from the top surface to the bottom surface and is adjacent to the first groove structure; the second doped region is located in the epitaxial layer between the first groove structure and the second groove structure and extends from the top surface to the bottom surface, the second doped region is of a second conductivity type, and the depth of the second doped region is smaller than that of the first groove structure; and the metal layer is located on the top surface of the epitaxial layer and covers the first groove structure, the second groove structure and the second doped region, and the metal layer is in contact with the top surface of the epitaxial layer to form a Schottky junction.

Description

Technical Field

[0001] The present invention relates to a structure of a semiconductor rectifier device and a manufacturing method thereof, and more specifically, to a structure of a Schottky barrier rectifier device and a manufacturing method thereof. Background Art

[0002] As we all know, power circuits require power rectifiers. With the advancement of the times and technology, power rectifiers need to have good power switching performance and low power consumption. Schottky rectifiers have a lower forward voltage, which is beneficial to forward power loss. However, Schottky rectifiers also have higher reverse leakage, resulting in higher reverse power loss. The Schottky barrier height affects the forward voltage (VF) and reverse current (IR). For example, reducing the Schottky barrier height can reduce VF but will cause IR to rise, resulting in increased reverse power loss. How to reduce VF while reducing IR while maintaining the breakdown voltage (BV) has become a technical bottleneck in this field. Summary of the invention

[0003] The embodiment of the present disclosure relates to a semiconductor rectifier device. The semiconductor rectifier device includes: an epitaxial layer having a top surface and a bottom surface opposite to each other; a first doped region located in the epitaxial layer, wherein the first doped region has a first conductivity type; a first trench structure located in the first doped region, extending from the top surface to the bottom surface; a second trench structure located in the first doped region, extending from the top surface to the bottom surface and adjacent to the first trench structure; a second doped region located in the epitaxial layer between the first trench structure and the second trench structure, extending from the top surface to the bottom surface, wherein the second doped region has a second conductivity type, and the depth of the second doped region is less than the depth of the first trench structure; and a metal layer located on the top surface of the epitaxial layer, covering the first trench structure, the second trench structure and the second doped region, wherein the metal layer contacts the top surface of the epitaxial layer to form a Schottky junction.

[0004] The embodiments of the present disclosure relate to a method for manufacturing a semiconductor rectifier device. The method comprises: forming an epitaxial layer with a first conductivity type on a substrate; forming a first trench structure and a second trench structure adjacent to the first trench in the epitaxial layer; forming a doped region with a second conductivity type in the epitaxial layer between the first trench structure and the second trench structure; and forming a metal layer on the epitaxial layer, wherein the metal layer covers the first trench structure, the second trench structure and the doped region. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of several embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0006] Figure 1 , 2 , 3, 4, 5, 6, 7, 8, 9, 10, and 11 show one or more stages in a method for manufacturing a semiconductor rectifier device according to certain embodiments of the present case.

[0007] The same or similar components are marked with the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0009] The following is a detailed discussion of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0010] The present disclosure provides a structure of a semiconductor rectifier device and a manufacturing method thereof. Compared with a general manufacturing method of a semiconductor rectifier device, the semiconductor rectifier device of the present disclosure has a Schottky barrier structure, and further, the Schottky barrier junction rectifier of the present disclosure has a lower electric field strength at the interface between the metal and the semiconductor, so that it can achieve the effect of maintaining a low VF while also reducing IR, and has the effect of improving reverse leakage. Therefore, the structure of the present disclosure can achieve the effect of reducing IR without increasing VF, and provide a rectifier device with improved reverse leakage.

[0011] Figures 1 to 10 Shown are one or more stages in a method of manufacturing a semiconductor rectifier device 1 according to some embodiments of the present invention. At least some of these drawings have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0012] Reference Figure 1 , the manufacturing method of the semiconductor rectifier device 1 includes performing epitaxial growth on the surface 11A of the substrate 11 to form an epitaxial layer 12, and forming a doped region 25 in the epitaxial layer 12. The substrate 11 has a relative surface 11A and a surface 11B. In some embodiments, the surface 11A and the surface 11B can be horizontal planes. For convenience of explanation, the direction orthogonal to the surface 11A and the surface 11B is defined as a vertical direction, and the direction orthogonal to the vertical direction is defined as a horizontal direction. In some embodiments, the surface 11A is the top surface of the substrate 11, and the surface 11B is the bottom surface of the substrate 11. In some embodiments, the surface 11A is the top surface of the silicon wafer. Figure 1 The substrate 11 shown may be only a portion of the silicon wafer close to the top surface. The material of the substrate 11 may be polycrystalline silicon or single crystal silicon. The substrate 11 may include a doped region 24. For example, the substrate 11 includes a p-type doped region and an n-type doped region that can be configured for an n-type transistor, and can be configured as a p-type transistor. The N-type doped region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The P-type doped region is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The N-type or P-type doped region may be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping processes. The doped region 24 of the substrate 11 extends from the surface 11A to the surface 11B. In some embodiments, the doped region 24 of the substrate 11 covers the entire surface 11A. In some embodiments, the doped region 24 of the substrate 11 has a first conductivity type. For the convenience of explanation, the first type is described below with N type and the second type is described with P type as an example, but the present disclosure is not limited thereto, and the N type (first type) or P type (second type) substrate 11 can be adjusted according to the conductivity type of the semiconductor rectifier device 1. It should be noted that Figure 1 The substrate 11 shown may be only a portion of the silicon wafer close to the top surface, or in other words, Figure 1 Only part of the doping region 24 of the substrate 11 is shown. In some embodiments, the doping region 24 of the substrate 11 is used as a cathode doping region of the semiconductor rectifier device 1. In some embodiments, the doping region 24 of the substrate 11 is used in a concentration range of 1*10 19 To 7*10 19 Per cubic centimeter (cm -3 )between.

[0013] The epitaxial layer 12 has the same conductivity type as the substrate 11, that is, the first type doping. The material of the epitaxial layer 11 can be polycrystalline silicon, single crystal silicon, silicon carbide, silicon germanium or other suitable semiconductor materials. In some embodiments, ions with N-type electrical properties are introduced into the epitaxial growth to form an N-type epitaxial layer 12 without additional ion implantation. Therefore, the ions with N-type electrical properties can be distributed throughout the epitaxial layer 12 to form a doped region 25 located throughout the epitaxial layer 12. The epitaxial layer 12 may have a surface 12A and a surface 12B opposite to the surface 12A. In some embodiments, the surface 12A and the surface 12B may be horizontal planes. In some embodiments, the surface 12A is the top surface of the epitaxial layer 12, and the surface 12B is the bottom surface of the epitaxial layer 12. In some embodiments, the surface 12B of the epitaxial layer 12 contacts the surface 11A of the substrate 11.

[0014] The thickness and doping concentration of the epitaxial layer 12 can be adjusted according to the voltage requirements of the device. In some embodiments, the thickness of the epitaxial layer 12 ranges from 6 to 12 micrometers (μm). In some embodiments, the thickness of the epitaxial layer 12 ranges from 8 to 10 μm. In some embodiments, the epitaxial layer 12 can have a uniform doping concentration, for example, a doping concentration of 5*10 14 To 1*10 16 cm -3 In some embodiments, ions with N-type electrical properties are uniformly introduced during the epitaxial growth process to form an epitaxial layer 12 with uniform doping concentration, wherein the ion concentration introduced during the epitaxial growth process does not change over time. In some embodiments, the epitaxial layer 12 may have a doping concentration gradient that increases from the surface 12A to the surface 12B, for example, the doping concentration of the epitaxial layer 12 adjacent to the surface 12A is between 4*10 15 To 7*10 15 cm -3 The doping concentration of the adjacent surface 12B is between 1*10 16 To 4*10 16 cm -3 In some embodiments, ions with N-type electrical properties are introduced during the epitaxial growth process, wherein the concentration of the introduced ions decreases with the time of the epitaxial growth to form an epitaxial layer 12 with a decreasing doping concentration.

[0015] In the above embodiment where the epitaxial layer 12 has a doping concentration gradient, the doping concentration of the surface 12A of the epitaxial layer 12 is reduced. Although the reduction in the doping concentration of the surface 12A increases the resistivity of the surface 12A, the increase in the doping concentration inside the epitaxial layer 12 reduces the internal resistivity, so that VF can be further reduced while maintaining BV. In some embodiments, the doping concentration of the portion of the epitaxial layer 12 adjacent to the surface 12A is lower than the doping concentration of the portion adjacent to the surface 12B by approximately one power, that is, the concentration difference between the two is approximately 1*10cm -3 .

[0016] Reference Figure 2 , the manufacturing method of the semiconductor rectifier device 1 includes forming a patterned layer 51 on the surface 12A of the epitaxial layer 12, exposing a portion of the epitaxial layer 12. The patterned layer 51 is used to define the position of the groove to be formed later. In some embodiments, the patterned layer 51 has an opening 511 and an opening 512 that exposes a portion of the epitaxial layer 12. The patterned layer 51 can be a material layer suitable for a mask for a subsequent etching process, such as a photomask, a hardening layer, a dielectric layer (such as an oxide layer or a nitride layer). In some embodiments, the patterned layer 51 includes an oxide (such as silicon oxide). In some embodiments, an oxide layer is formed to cover the surface 12A of the epitaxial layer 12, a patterned photomask is formed on the oxide layer, and a portion of the oxide layer is removed using the patterned photomask, and then the patterned photomask is removed to form a patterned layer 51 that exposes a portion of the silicon carbide layer 12.

[0017] Reference Figure 3 The manufacturing method of the semiconductor rectifier device 1 includes etching the epitaxial layer 12 with the patterned layer 51 as a mask to form a plurality of grooves (such as Figure 3The plurality of grooves are adjacent to each other and extend from the surface 12A to the surface 12B of the epitaxial layer 12. Since they are formed by the same etching step, the plurality of grooves have approximately the same depth. In some embodiments, the groove 41 and the groove 42 have approximately the same depth D40. In some embodiments, the depth D40 of the groove 41 or the groove 42 is between 5-30 μm. In some embodiments, the depth D40 of the groove 41 or the groove 42 is between 8-10 μm. The width of the grooves 41 and 42 can be determined by the openings 511 and 512. In some embodiments, the groove 41 and the groove 42 have approximately the same width W40. In some embodiments, the width W40 of the groove 41 or the groove 42 is between 0.5-3 μm. In some embodiments, the width W40 of the groove 41 or the groove 42 is between 1.3-1.7 μm. The width and depth of the trenches 41 and 42 can be set and adjusted according to the voltage required by the device. Within the scope of the embodiments disclosed above, the greater the value of the depth D40 of the trenches 41 and 42, the lower the resistivity of the epitaxial layer 12 can be.

[0018] Reference Figure 4 , the manufacturing method of the semiconductor rectifier device 1 includes forming a trench 41 and a trench 42 filled with a dielectric layer 13. In some embodiments, the dielectric layer 13 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD) or other deposition processes. In some embodiments, the dielectric layer 13 can be formed by thermal oxidation technology. In some embodiments, the dielectric layer 13 is substrated in the trench 41 and the trench 42. In some embodiments, the dielectric layer 13 can be conformally or conformally deposited on the inner surface of the trenches 41 and 42 (including the opposite sidewalls and the bottom extending between the sidewalls) and the surface 12A of the epitaxial layer 12. In some embodiments, the dielectric layer 13 can be filled in the trenches 41 and 42 by a deposition process, and then a lithography and etching process is performed to partially remove the dielectric layer 13, and at least one groove is formed in the dielectric layer 13. The thickness of the dielectric layer 13 can be set and adjusted according to the voltage required by the device. In some embodiments, the thickness of the dielectric layer 13 is between 0.1-2μm. In some embodiments, the thickness of the dielectric layer 13 is between 0.2 μm and 1.2 μm. In some embodiments, the thickness of the dielectric layer 13 is between 0.5 μm and 0.8 μm.

[0019] The voltage of the semiconductor rectifier device 1 is generally determined by the doping concentration of the epitaxial layer 12 and the thickness of the dielectric layer 13. Figure 1 , 4 The steps shown determine the voltage of the semiconductor rectifier device 1.

[0020] Reference Figure 5 The manufacturing method of the semiconductor rectifier device 1 includes forming a semiconductor material layer 14 in the groove 41 and the groove 42. In some embodiments, the semiconductor material layer 14 can be formed by physical vapor deposition (PVD), CVD or other deposition processes. In some embodiments, the semiconductor material layer 14 fills the grooves 41 and 42 and covers the surface 12A of the epitaxial layer 12. In some embodiments, the semiconductor material layer 14 includes polysilicon.

[0021] Reference Figure 6 , the manufacturing method of the semiconductor rectifier device 1 includes removing a portion of the semiconductor material layer 14 and the dielectric layer 13 outside the grooves 41 and 42. In some embodiments, the semiconductor material layer 14 outside the grooves 41 and 42 is removed to form a first electrode layer 141 and a second electrode layer 142 in the grooves 41 and 42, respectively. In some embodiments, the semiconductor material layer 14 is subjected to a grinding process, such as a chemical mechanical polishing (CMP) process, to remove the semiconductor material layer 14 outside the grooves 41 and 42. In other embodiments, the method of removing a portion of the semiconductor material layer 14 outside the grooves 41 and 42 may also include an etching process, such as a wet etching process or a dry etching process. In some embodiments, after removing the semiconductor material layer 14 on the surface 12A of the epitaxial layer 12, a similar process is performed on the dielectric layer 13 to form a first dielectric layer 131 and a second dielectric layer 132 in the grooves 41 and 42, respectively. In some embodiments, the first dielectric layer 131 surrounds the first electrode layer 141, and the second dielectric layer 132 surrounds the second electrode layer 142. For the sake of convenience, the first electrode layer 141 and the first dielectric layer 131 are collectively referred to as the first trench structure 151, and similarly, the second electrode layer 142 and the second dielectric layer 132 are collectively referred to as the second trench structure 152. In some embodiments, the upper surfaces of the first electrode layer 141 and the second electrode layer 142 are flush with the surface 12A. In some embodiments, the upper surfaces of the first dielectric layer 131 and the second dielectric layer 132 are flush with the surface 12A.

[0022] Reference Figure 7, the manufacturing method of the semiconductor rectifier device 1 includes forming a patterned layer 52 on the surface 12A of the epitaxial layer 12. The patterned layer 52 covers the first and second trench structures 151 and 152, and exposes the portion of the epitaxial layer 12 located between the first trench structure 151 and the second trench structure 152. In some embodiments, the patterned layer 52 has an opening 521, exposing the portion of the epitaxial layer 12 located between the first trench structure 151 and the second trench structure 152. The patterned layer 51 can be a photomask, a hardening layer, a dielectric layer (such as an oxide layer or a nitride layer), or other material layer suitable for being used as a mask for a subsequent etching process. In some embodiments, the patterned layer 51 includes an oxide (such as silicon oxide). In some embodiments, an oxide layer is formed to cover the entire surface 12A of the epitaxial layer 12, a patterned photomask is formed on the oxide layer, and the patterned photomask is used to remove a portion of the oxide layer, and then the patterned photomask is removed to form Figure 7 The patterned layer 52. The opening 521 is located approximately in the middle of the first trench structure 151 and the second trench structure 152. In some embodiments, the distance L1 from the opening 521 to the first trench structure 151 is approximately equal to the distance L2 from the opening 521 to the second trench structure 152. In some embodiments, the distance L3 from the center of the opening 521 (indicated by the dotted line C1) to the first trench structure 151 is approximately equal to the distance L4 from the center of the opening 521 to the second trench structure 152. In some embodiments, the width W521 of the opening 521 is between 0.3 μm and 0.6 μm.

[0023] Reference Figure 8 , the manufacturing method of the semiconductor rectifier device 1 includes using the patterned layer 51 as a mask to perform ion implantation on the surface 12A of the epitaxial layer 12 to form a doped region 21 with a second type of doping. The depth D21 of the doped region 21 is less than the depth of the first trench structure 151 or the second trench structure 152. Since the doped region 21 is defined by the opening 521 of the patterned layer 52, the width W21 of the doped region 21 on the surface 12A of the epitaxial layer 12 is approximately the same as the width W521 of the opening 521. In some embodiments, the width W21 of the doped region 21 is between 0.3-0.6 μm. In some embodiments, the depth D21 of the doped region 21 is between 0.2-0.8 μm. In some embodiments, the doping concentration of the second conductive type doping ions in the doped region 21 is between 1*10 16 To 1*10 18 cm -3 After the ion implantation process, a thermal annealing process is performed to activate the doping ions in the doping region 21 .

[0024] Since a Schottky metal will be formed on the surface 12A of the epitaxial layer 12 later, the junction between the epitaxial layer 12 and the Schottky metal will form a Schottky junction, and the electric field generated by the semiconductor rectifier device 1 during operation will be concentrated between the first trench structure 151 and the second trench structure 152, and is easily concentrated in the position of the surface 12A of the epitaxial layer 12 between the first trench structure 151 and the second trench structure 152, and this electric field concentration area is likely to cause leakage. The formation of a doped region 21 in the epitaxial layer 12 adjacent to the surface 12A between the first trench structure 151 and the second trench structure 152 can effectively block the electric field and avoid the problem of leakage current of the semiconductor rectifier device 1. According to the size and distribution range of the electric field generated by different devices, the width W21 of the doped region 21 (or the lateral area located on the surface 12A) can be adjusted to achieve the effect of blocking the electric field adjacent to the surface 12A, but if the lateral area of ​​the doped region 21 located on the surface 12A is too large, it will cause VF to rise.

[0025] Since the electric field will be concentrated from the first trench structure 151 and the second trench structure 152 to the epitaxial layer 12 between the two, the depth D21 of the doped region 21 can determine the range of blocking the electric fields on both sides in the vertical direction. The larger the blocking range, the less likely it is to form a concentrated electric field at the position adjacent to the surface 12A. Some tests show that the depth D21 of the doped region 21 has no obvious effect on VF, but can improve the effect of electric field blocking. Therefore, the depth D21 of the doped region 21 contributes to improving the leakage current problem. However, the leakage current problem is mainly concentrated at the position adjacent to the surface 12A, so when the depth D21 of the doped region 21 reaches a certain value, it will no longer make a significant contribution to the effect of improving the leakage current. The range of the depth D21 of the aforementioned doped region 21 is based on the overall size of the semiconductor rectifier device 1 and the limitations of the existing manufacturing methods and processes, and the preferred numerical range is obtained, and is not used to limit the above-mentioned inventive concept disclosed in the present invention.

[0026] Reference Fig. 9 The manufacturing method of the semiconductor rectifier device 1 includes conformally forming a metal layer 18 on the surface 12A of the epitaxial layer 12. The metal layer 18 is selected from Schottky metals, such as titanium (Ti), nickel (Ni), molybdenum (Mo), platinum (Pt), nickel platinum (NiPt) or a combination thereof. In some embodiments, the metal layer 18 contacts the surface 12A of the epitaxial layer 12, the top surface of the first trench structure 151, and the top surface of the second trench structure 152. In some embodiments, the metal layer 18 is adjacent to the doped region 21.

[0027] General Schottky barrier rectifier devices only use metals with high Schottky barrier height, such as platinum and molybdenum, to achieve the effect of low reverse leakage, and avoid using metals with low Schottky barrier height, such as titanium. The reason is that using metals with low Schottky barrier height will result in low VF. Although the power loss will be relatively small, the device will be easily affected by the electric field strength. When there is a region with a strong electric field strength, the leakage current will rise sharply.

[0028] The present disclosure forms a doped region 21 in the portion of the epitaxial layer 12 where the electric field is concentrated between the trench structures 151 and 152, which can effectively block the electric field. Compared with the Schottky barrier rectifier device without the doped region 21, it not only improves the original leakage current problem, but also greatly increases the selection of Schottky metals that can be used, and will no longer be limited to using metals with high Schottky barrier heights. Even if a metal with a low Schottky barrier height is used, the same or better performance can be achieved compared to the existing Schottky barrier rectifier device.

[0029] Reference Fig.10 , the manufacturing method of the semiconductor rectifier device 1 includes forming an upper electrode layer 16 on a metal layer 18. The upper electrode layer 16, as the anode electrode of the semiconductor rectifier device 1, may include a suitable metal material or alloy, such as titanium tungsten (TiW), aluminum (Al), aluminum silicon alloy (AlSi), aluminum silicon copper alloy (AlSiCu) or a combination thereof, which is not limited here. After forming the upper electrode layer 16, the upper electrode layer 16 and the contact metal 31 may be etched to form a desired pattern. Since the etching step is performed according to the desired circuit design, the etching step is not shown in the figure, and those skilled in the art may adjust the etching step according to the above contents of the present disclosure to form the desired pattern of the upper electrode layer 16 and the pattern of the metal layer 18.

[0030] Reference Fig.11 , the manufacturing method of the semiconductor rectifier device 1 includes forming a lower electrode layer 17 on a substrate 11 below the epitaxial layer 12. The lower electrode layer 17 and the upper electrode layer 16 are located on opposite sides of the epitaxial layer 12. The doped region 24 of the substrate 11 serves as a cathode contact region of the semiconductor rectifier device 1. The material of the lower electrode layer 17 may be the same as or different from that of the upper electrode layer 16. In some embodiments, the material of the lower electrode layer 17 includes a titanium nickel silver alloy (TiNiAg). In some embodiments, the lower electrode layer 17 contacts the doped region 24 of the substrate 11. In some embodiments, before forming the lower electrode layer 17, the substrate 11 is ground or etched to reduce the thickness of the substrate 11 to expose the doped region 24.

[0031] Spatially relative terms such as "under," "below," "lower," "above," "upper," "left," "right," and the like may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0032] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and explain small changes. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurs precisely and an instance where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. The range can be expressed as one endpoint to another endpoint or between two endpoints herein. All ranges disclosed herein include endpoints unless otherwise specified. The term "substantially coplanar" can refer to a position difference of two surfaces positioned along the same plane within a few microns (μm), such as a position difference positioned along the same plane within 10 μm, within 5 μm, within 1 μm or within 0.5 μm. When a numerical value or characteristic is referred to as being "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value.

[0033] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor rectifier device, characterized in that: include: an epitaxial layer having a top surface and a bottom surface opposite to each other; A first doped region, located in the epitaxial layer, wherein the first doped region has a first conductivity type; A first trench structure, located in the first doped region, extending from the top surface to the bottom surface; A second trench structure, located in the first doped region, extending from the top surface to the bottom surface and adjacent to the first trench structure; a second doped region, located in the epitaxial layer between the first trench structure and the second trench structure, extending from the top surface to the bottom surface, wherein the second doped region has a second conductivity type, and a depth of the second doped region is less than a depth of the first trench structure; as well as A metal layer is located on the top surface of the epitaxial layer and covers the first trench structure, the second trench structure and the second doped region, wherein the metal layer contacts the top surface of the epitaxial layer to form a Schottky junction. 2 . The semiconductor rectifier device according to claim 1 , wherein the doping concentration of the first doping region increases from the top surface to the bottom surface.

3. The semiconductor rectifier device according to claim 1, wherein the concentration of the first doped region adjacent to the top surface is between 4*10 15 To 7*10 15 cm -3 and the concentration of the first doping region adjacent to the bottom surface is between 1*10 16 To 4*10 16 cm -3 between. 4 . The semiconductor rectifier device according to claim 1 , wherein a distance from a center of the second doping region to the first trench structure is approximately the same as a distance from the center of the second doping region to the second trench structure. 5 . The semiconductor rectifier device according to claim 1 , wherein a width of the second doped region is between 0.3 μm and 0.6 μm. 6 . The semiconductor rectifier device according to claim 1 , wherein a depth of the second doped region is between 0.2 μm and 0.8 μm.

7. The semiconductor rectifier device according to claim 1, wherein the concentration of the second doping region is between 1*10 16 To 1*10 18 cm -3 between. 8 . The semiconductor rectifier device according to claim 1 , wherein a top surface of the first trench structure or the second trench structure is flush with the top surface of the epitaxial layer. 9 . The semiconductor rectifier device according to claim 1 , wherein the first trench structure comprises a first dielectric layer and a first electrode layer surrounded by the first dielectric layer, and the second trench structure comprises a second dielectric layer and a second electrode layer surrounded by the second dielectric layer.

10. The semiconductor rectifier device according to claim 1, further comprising: an anode electrode, located on the metal layer; a substrate disposed on the bottom surface of the epitaxial layer; as well as A cathode electrode contacts the substrate layer.

11. The semiconductor rectifier device of claim 1, wherein the depth of the first trench structure is between 8 micrometers and 10 micrometers, and the depth of the second trench structure is approximately the same as the depth of the first trench structure.

12. A method for manufacturing a semiconductor rectifier device, characterized in that: include: forming an epitaxial layer having a first conductivity type on a substrate; forming a first trench structure and a second trench structure adjacent to the first trench in the epitaxial layer; forming a doped region having a second conductivity type in the epitaxial layer between the first trench structure and the second trench structure; as well as A metal layer is formed on the epitaxial layer, wherein the metal layer covers the first trench structure, the second trench structure and the doped region.

13. The manufacturing method according to claim 12, wherein the forming of the epitaxial layer having the first conductivity type comprises: Ions of the first conductivity type are introduced into the epitaxial growth, wherein the concentration of the introduced ions decreases with the time of the epitaxial growth, and the concentration of the ions in the epitaxial layer decreases from the top surface of the semiconductor material layer upward.

14. The manufacturing method according to claim 12, wherein forming the first trench structure and the second trench structure comprises: forming a patterned layer on a top surface of the epitaxial layer to define positions of the first trench structure and the second trench structure; Using the patterned layer as a mask to form a first groove and a second groove; forming a dielectric layer conformally covering the epitaxial layer, wherein a first portion of the dielectric layer is disposed in the first trench, and a second portion of the dielectric layer is disposed in the second trench; forming a polysilicon layer on the dielectric layer, wherein a first portion of the polysilicon layer fills up the first trench and a second portion of the polysilicon layer fills up the second trench; as well as The polysilicon layer and the dielectric layer located above the top surface of the epitaxial layer are removed, wherein the top surface of the first trench structure and the top surface of the second trench structure are flush with the top surface of the epitaxial layer.

15. The method of claim 14, wherein removing the polysilicon layer and the dielectric layer above the top surface of the epitaxial layer comprises: Performing a first etching process on the polysilicon layer to remove a portion of the polysilicon layer; as well as A second etching process is performed on the dielectric layer to remove a portion of the dielectric layer. The manufacturing method according to claim 12 , wherein the thickness of the dielectric layer is between 0.2 μm and 2 μm. 17 . The manufacturing method according to claim 12 , wherein a material of the metal layer comprises titanium, molybdenum, nickel, platinum, nickel-platinum, an alloy thereof, or a combination thereof.

18. The manufacturing method according to claim 12, further comprising: forming an anode electrode on the metal layer; reducing the thickness of the semiconductor material layer from below the semiconductor material layer; as well as A cathode electrode is formed below the semiconductor material layer.

19. The manufacturing method according to claim 18, wherein the material of the anode electrode comprises: Aluminum, aluminum silicon alloy, aluminum silicon copper alloy, and the material of the cathode electrode includes: titanium nickel silver alloy.

20. The manufacturing method of claim 18, wherein the anode electrode has a flat bottom surface that abuts a top surface of the epitaxial layer.

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