Integrated circuit with overlapping stressor

Abstract

The invention relates to an integrated circuit with overlapping stressors. An integrated circuit includes a compressive stressor and a tensile stressor each located directly over an active region of a transistor, wherein a portion of the compressive stressor and a portion of the tensile stressor directly overlap each other. In some embodiments, the stress applied to the channel region of the transistor can be adjusted using a compressive stressor and a tensile stressor located directly above the active region and having overlapping portions to compensate for the stress applied by the package structure.

Description

Technical Field

[0001] The present invention generally relates to integrated circuits having overlapping stressors. Background Art

[0002] Integrated circuits utilize stressors to apply stress to the active areas of transistors to improve transistor performance. A stressor is a dielectric structure formed to induce stress (compressive or tensile) on surrounding structures of the integrated circuit. A stressor can be one of two types of stressors. A compressive stressor applies compressive stress to the structure directly below the compressive stressor. A compressive stressor is formed of a dielectric material (e.g., silicon nitride) and is under tensile stress when formed. A tensile stressor applies tensile stress to the structure directly below the tensile stressor. A tensile stressor is formed of a dielectric material (e.g., silicon nitride) and is under compressive stress when formed. Structures formed to apply neither compressive nor tensile stress are characterized as neutral.

[0003] With some integrated circuits including field effect transistors (FETs), applying stress on the channel region can improve carrier mobility. Changing the carrier mobility can affect the drive current of the transistor. For a specific semiconductor substrate with a given crystal orientation, the carrier mobility (e.g., electron mobility) in the channel region of an N-type FET (NFET) can be improved by applying tensile stress in both the longitudinal and lateral directions of the channel region. The longitudinal direction is the direction of carrier flow in the channel region, and the lateral direction is transversely perpendicular to the direction of carrier flow in the channel region. For a specific semiconductor substrate with a given crystal orientation, the carrier mobility (e.g., hole mobility) in the channel region of a P-type FET (PFET) can be improved by applying compressive stress on the channel in the longitudinal direction and applying tensile stress in the lateral direction. However, for other transistors or substrates with different crystal orientations, channel stress may affect transistor performance in different ways. Summary of the invention

[0004] In one embodiment, an integrated circuit includes: a first transistor including an active region; a first stressor of a first stressor type located directly above the active region; and a second stressor of a second stressor type opposite to the first stressor type located directly above the active region, wherein the first stressor and the second stressor each include a portion that directly overlaps each other.

[0005] According to one or more embodiments, the first stressor and the second stressor each include a portion directly overlapping each other directly above the active region.

[0006] According to one or more embodiments, the first stressor and the second stressor each include a portion directly overlapping each other right above a current terminal region of the first transistor.

[0007] According to one or more embodiments, the first stressor and the second stressor each include a portion directly overlapping each other right above a channel region of the first transistor.

[0008] According to one or more embodiments, the integrated circuit further includes a third stressor of the second stressor type located directly above the active area, wherein the first stressor and the third stressor each include a portion directly overlapping each other.

[0009] According to one or more embodiments, the first stressor includes a portion that does not directly overlap with the third stressor.

[0010] According to one or more embodiments,

[0011] The transistor is characterized as a FET;

[0012] The second stressor is located directly above a source region and not directly above a drain region of the first transistor in the active region of the first transistor, and the third stressor is located directly above the drain region of the first transistor and not directly above the source region of the first transistor.

[0013] According to one or more embodiments, the first stressor includes a portion that does not directly overlap a portion of the second stressor.

[0014] According to one or more embodiments, the first stressor is located directly above the entire active area, wherein the second stressor is not located directly above the entire active area.

[0015] According to one or more embodiments, the first stressor is located directly above the second stressor.

[0016] According to one or more embodiments, the second stressor is located directly above the first stressor.

[0017] According to one or more embodiments, the integrated circuit further comprises:

[0018] a second transistor including a second active area, the second transistor having the same conductivity type as the first transistor;

[0019] a third stressor of the first stressor type located directly above the second active area; and a fourth stressor of the second stressor type located directly above the second active area, wherein the third stressor and the fourth stressor each include a portion that directly overlaps each other.

[0020] According to one or more embodiments,

[0021] The active area and the second active area have the same size;

[0022] An overlapping area between the first stressor and the second stressor is greater than an overlapping area between the third stressor and the fourth stressor.

[0023] According to one or more embodiments, the integrated circuit further comprises:

[0024] A die end is located in a first region of the integrated circuit, wherein the second active region is laterally located at a greater lateral distance from the first region than from the active region.

[0025] According to one or more embodiments, a packaged integrated circuit includes the aforementioned integrated circuit.

[0026] According to one or more embodiments, the first stressor and the second stressor each include silicon nitride.

[0027] According to one or more embodiments, the first transistor includes a gate structure, wherein the first stressor is located directly above the gate structure, and the second stressor is not located directly above the gate structure.

[0028] According to one or more embodiments, the first stressor is made of a first material, and the second stressor is made of a second material having an etching selectivity with respect to the first material.

[0029] According to one or more embodiments, the first stressor serves as an etch stop layer for forming an end contact of the first transistor.

[0030] In another embodiment, an integrated circuit includes: a first field effect transistor (FET) including an active region; a first stressor of a first stressor type located directly above the active region; and a second stressor of a second stressor type opposite to the first stressor type located directly above the active region. The first stressor and the second stressor each include a portion directly overlapping each other above the active region of the FET, wherein the first stressor includes a portion that does not directly overlap a portion of the second stressor. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0032] Figure 1 is a partial cross-sectional side view of a prior art integrated circuit.

[0033] Figure 2is a top view of a prior art integrated circuit showing how die end stress affects different areas of the substrate.

[0034] Figure 3 is a partial cross-sectional side view of an integrated circuit in accordance with one embodiment of the present invention.

[0035] Figure 4 is a cross-sectional side view of a packaged integrated circuit in accordance with one embodiment of the present invention.

[0036] Figure 5 is a partial cross-sectional top view of an integrated circuit according to one embodiment of the present invention.

[0037] Figure 6 is a partial cross-sectional top view of an integrated circuit according to one embodiment of the present invention.

[0038] Figure 7 is a flow chart illustrating a method for designing and manufacturing a packaged integrated circuit according to one embodiment of the present invention.

[0039] Unless otherwise indicated, the same reference symbols are used in different drawings to indicate the same items. The figures are not necessarily drawn to scale. DETAILED DESCRIPTION

[0040] The following is a detailed description of at least one mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be construed as limiting.

[0041] As disclosed herein, an integrated circuit includes a compressive stressor and a tensile stressor, each stressor being located directly above an active region of a transistor, wherein a portion of the compressive stressor and a portion of the tensile stressor directly overlap each other. In some embodiments, utilizing a compressive stressor and a tensile stressor located directly above the active region and having overlapping portions may enable the stress applied to a channel region of the transistor to be adjusted to compensate for stress applied by a packaging structure.

[0042] In one embodiment, compensating the stress of a packaging structure on a channel region of a transistor using overlapping stressors of opposite stressor types may provide stress modulation without utilizing additional masks (eg, for selective ion implantation or forming additional structures).

[0043] Figure 1 is a partial cross-sectional side view of a prior art integrated circuit 101 . Figure 1 PFET 103 and NFET 105 are shown, each including an active region located in substrate 107. Figure 1 Not shown in Figure 11. The PFET 103 includes a gate 121 located above an active region positioned between shallow trench isolation (STI) structures 117 and 119, and also includes a P-type source region 128, a P-type drain region 129, and an N-type well (N-well) region 109. When the gate 121 is applied with a voltage lower than the threshold voltage of the PFET 103, a conductive channel region 125 is formed in the well region 109 between the source region 128 and the drain region 129, directly below the gate 121.

[0044] NFET 105 includes a gate 123 located above an active region located between shallow trench isolation structures 119 and 120, the active region including an N-type source region 138, an N-type drain region 139, and a P-type well (P-well) region 111. When gate 121 is applied with a voltage higher than the threshold voltage of NFET 105, a conductive channel region 135 is formed in well region 111 between source region 138 and drain region 139.

[0045] Compressive stressor 131 is located directly above PFET 103 and is made of a patterned layer of silicon nitride under tensile stress. Stressor 131 applies a desired amount of compressive stress on channel region 125 in the direction of carrier flow to increase carrier flow during transistor on-time.

[0046] Tensile stressor 133 is located directly above NFET 105 and is made of a patterned layer of silicon nitride under compressive stress. Stressor 133 applies a desired amount of tensile stress in channel region 135 in the direction of carrier flow to increase carrier flow during transistor on-time.

[0047] The stressors 131 and 133 are configured (e.g., in terms of size, location, thickness, and amount of internal stress) to exert a desired amount of stress on the channel region to improve carrier mobility in the transistor. However, other packaging structures (e.g., packaging structures) of packaged integrated circuits implementing the integrated circuit 101 may also be used. Figure 1 ), such as metal interconnect structures in the die interconnect layer, external die terminals (e.g., bonding pads, pillars, bumps), metal plates, solder, package plates, and package encapsulation (see Figure 4), may also impose stress on the channel region, which may offset or add to the stress provided by stressors 131 and 133, so that the channel region is not provided with a desired amount of stress. In addition, the stress caused by the package structure is not necessarily uniform across the entire integrated circuit, but may depend on the distance of the package structure to the channel region. Because the compressive stressor can be patterned from a single layer, and the tensile stressor can also be patterned from a single layer, it is impossible to change the parameters of the layer to have the desired stress to deal with the changes in the package structure stress caused by the position. Therefore, the transistor mobility can vary based on the transistor position in the integrated circuit. This variation in carrier mobility may cause a change in the drive current based on the transistor position. Such a variation is not desirable for proper integrated circuit operation.

[0048] Figure 2 is a top view of integrated circuit 201 showing areas of stress variation on the channel region caused by external die terminals (eg, bond pads, pillars, studs). Figure 2 The smaller identified areas (e.g., 203) represent the approximate locations of the outer die ends, where the greatest stress affects the channel regions of the transistors in these areas. The areas 205 surrounding the smaller areas represent areas of moderate stress from the outer die ends. Figure 2 As shown, the stress caused by the die end tends to decrease as the distance away from the end increases. The stress of the external die end includes not only the stress applied by the die end structure itself, but also the stress of other packaging structures mechanically coupled to the end. In addition, the amount of stress applied by the die end can depend on the location of the die end. For example, compared with the internal die end, the corner die end can apply greater stress on the substrate.

[0049] The active region of a transistor includes the area in the semiconductor material substrate for the terminals of the transistor (e.g., the current terminal and the control terminal (if present) in the substrate) and the semiconductor path that conducts carriers between the terminals of the transistor. For a FET, the active region will include the source region, the drain region, and the channel region.

[0050] Figure 3 3 is a partial cross-sectional side view of an integrated circuit 301 according to one embodiment of the present invention. Integrated circuit 301 includes PFETs 321 and 323 and NFETs 322 and 324, where each transistor includes an active region located in substrate 303.

[0051] Substrate 303 is made of one or more semiconductor materials, such as single crystal silicon, silicon germanium, gallium nitride, gallium arsenide, or other III-V semiconductor materials. In one embodiment, substrate 303 has a bulk semiconductor configuration. In other embodiments, the substrate may have a semiconductor on insulator (SOI) configuration. In some embodiments, substrate 303 is formed from a single portion of an integrally grown semiconductor material. In other embodiments, portions of substrate 303 may include epitaxially grown semiconductor material. Substrate 303 also includes a dielectric structure (e.g., shallow trench isolation structure (STI) 313). In the illustrated embodiment, transistors 321-324 are planar transistors. However, in other embodiments, transistors 321-324 are characterized as FinFETs, where Figure 3 A cross-sectional view cut longitudinally through a semiconductor fin.

[0052] exist Figure 3 Not shown in Figure 3 An interconnect layer above the structure shown includes conductive interconnects, vias, terminal contacts, and die terminals (e.g., pads, pillars, bumps), and includes intervening dielectric materials that provide electrical isolation of these conductive structures. The conductive structures of the interconnect layer provide conductive paths between terminal regions of transistors and to other devices of the integrated circuit 301 and circuit systems external to the integrated circuit 301.

[0053] Substrate 303 includes regions formed by selective doping of P-type dopants (e.g., boron) and N-type dopants (phosphorus, arsenic), which are located above base substrate layer 305. The "P-type" region has a net P-type doping concentration. The "N-type" region has a net N-type doping concentration.

[0054] PFET 321 includes a gate 327 located above an active region located between shallow trench isolation structures (STI) 313 and 314, the active region including a P-type source region 329, a P-type drain region 330, and an N-type well region 307. When gate 327 is applied with a voltage lower than the threshold voltage of PFET 321, a conductive channel region 326 is formed in well region 307 between source region 329 and drain region 330, directly below gate 327.

[0055] NFET 322 includes a gate 361 located above an active region located between shallow trench isolation structures 314 and 315, the active region including an N-type source region 362, an N-type drain region 363, and a P-type well region 309. When gate 361 is applied with a voltage higher than the threshold voltage of NFET 322, a conductive channel region 364 is formed in well region 309 between source region 362 and drain region 363.

[0056] PFET 323 includes a gate 347 located above an active region located between shallow trench isolation structures 316 and 317, the active region including a P-type source region 349, a P-type drain region 340, and an N-type well region 308. When gate 347 is applied with a voltage lower than the threshold voltage of PFET 323, a conductive channel region 346 is formed in well region 308 between source region 349 and drain region 340, directly below gate 347.

[0057] NFET 324 includes a gate 371 located above an active region located between shallow trench isolation structures 317 and 318, the active region including an N-type source region 372, an N-type drain region 373, and a P-type well region 310. When gate 371 is applied with a voltage higher than the threshold voltage of NFET 324, a conductive channel region 374 is formed in well region 310 between source region 372 and drain region 373. Figure 3 The body contacts of transistors 321-324 are not shown.

[0058] Compressive stressor 328 is located directly above PFET 321 to provide compressive stress to channel region 326 in the longitudinal direction. Compressive stressor 344 is located directly above PFET 323 to provide compressive stress to channel region 346 in the longitudinal direction. Tensile stressor 351 is located directly above NFET 322 to provide tensile stress to channel region 364 in the longitudinal direction. Tensile stressor 354 is located directly above NFET 324 to provide tensile stress to channel region 374 in the longitudinal direction. In one embodiment, stressors 328, 351, 344, and 354 act as an etch stop layer for forming source and drain contacts (not shown).

[0059] PFET 321 and NFET 322 are located in a region 304 of integrated circuit 301 that is subject to tensile stress from packaging structures (e.g., interconnects, die terminations, solder, encapsulation). Therefore, compressive stressors 342 and 343 are located over portions of the active region of NFET 322 (e.g., source region 362 and drain region 363, respectively) to reduce the stress impact of tensile stressor 351 in order to provide a desired amount of tensile stress to channel region 364. Otherwise, the tensile stress applied by the packaging structure would result in a greater than desired amount of tensile stress being applied to channel region 364.

[0060] A stressor of one stressor type (e.g., compressive stressor 342) overlaps a stressor of another stressor type (e.g., tensile stressor 351) to reduce the amount of stress provided by the other stressor. The amount of channel stress reduction of the second stressor depends on the amount of overlap and the location of the overlap relative to the channel. The closer the overlap is to the channel, the greater the stress reduction. Additionally, the greater the overlap, the greater the stress reduction.

[0061] PFET 323 and NFET 324 are located in a region 306 of integrated circuit 301 that is subject to compressive stress from the packaging structure. Therefore, tensile stressors 352 and 353 are located over portions of the active region of PFET 323 (e.g., source region 349 and drain region 340, respectively) to reduce the stress effects of compressive stressor 344 in order to provide a desired amount of compressive stress to channel region 364. Otherwise, the compressive stress applied by the packaging structure would cause a greater amount of compressive stress to be applied to channel region 346 than is desired.

[0062] In the illustrated embodiment, compressive stressors 341, 342, 343, and 344 are formed from a layer of dielectric material, the process, parameters, and materials of which are selected to provide a dielectric layer formed to have a desired tensile stress. In one embodiment, the dielectric layer is a silicon nitride layer formed with a stress of 524 MPa by a plasma enhanced chemical vapor deposition process after annealing. Typical process conditions are gas flow rates of 1960 sccm nitrogen, 40 sccm silane, 55 sccm ammonia, and a power of 55 mW / cm213.56 MHz. Thereafter, the layer is selectively patterned to form compressive stressors 341, 342, 343, and 344. However, in other embodiments, the compressive stressors may be formed by other methods and / or from other materials in other embodiments.

[0063] In the illustrated embodiment, tensile stressors 351, 352, 353, and 354 are formed from a layer of dielectric material, the process, parameters, and materials of which are selected to provide a dielectric layer formed to have compressive stress. In one embodiment, the dielectric layer includes silicon nitride and is formed by a plasma enhanced chemical vapor deposition process at a stress of -506 MPa after annealing. Typical process conditions are gas flow rates of 1500 sccm nitrogen, 100 sccm silane, no ammonia, and a power of 165 mW / cm20.308 MHz. Thereafter, the layer is selectively patterned to form tensile stressors 351, 352, 353, and 354. However, in other embodiments, the tensile stressors may be formed by other methods and / or from other materials in other embodiments.

[0064] In one embodiment, the stressor is used as an etch stop layer for forming contacts (not shown) that contact the source region, drain region, and gate of transistors 321-324. In such embodiments, after forming the stressor, a blanket dielectric layer (e.g., oxide) (not shown) is formed over the wafer and planarized. Then, patterned openings are formed in the oxide layer and in the stressor to contact the silicide (not shown) on the gate, source region, and drain region of the transistor. The openings are filled with one or more conductive contact materials and then planarized to form contacts (not shown).

[0065] In the illustrated embodiment, tensile stressors 351, 352, 353, and 354 are formed before compressive stressors 341, 342, 343, and 344. However, in other embodiments, compressive stressors may be formed before tensile stressors. In the illustrated embodiment, all tensile stressors are formed from a single layer, and all compressive stressors are formed from a single layer. However, in other embodiments, compressive stressors may be formed from different layers, and tensile stressors may be formed from different layers.

[0066] In one embodiment, the compressive stressor and the tensile stressor may be made of different dielectric materials (e.g., silicon nitride and silicon oxynitride) that have etch selectivity relative to each other. Thus, the subsequently formed stressor layer may be etched without etching the first formed stressor. However, in other embodiments, the first formed stressor will include a capping layer (e.g., oxide) having an etch selective material from the subsequently formed stressor layer. Thus, the subsequently formed stressor layer may be etched using an anisotropic etch without etching the previously formed stressor.

[0067] In one embodiment, the layers used to form the compressive stressors are designed to provide a desired amount of compressive stress to the PFET in the areas of the integrated circuit that are under the most tensile stress from the packaging structure. For PFETs located in areas with less tensile packaging stress to areas with more compressive packaging stress, tensile stressors (e.g., 352 and 353) can be added on the active area of ​​the PFET to reduce the amount of compressive stress provided by the compressive stressors (e.g., 344). In this way, the amount of compressive stress provided to the PFET channel can be "tuned" to offset stress variations caused by packaging structures at different locations.

[0068] Likewise, in one embodiment, the layers used to form the tensile stressors are designed to provide a desired amount of tensile stress to the NFET in the regions of the integrated circuit that are under the most compressive stress from the packaging structure. For NFETs located in regions with less compressive packaging stress to regions with more tensile packaging stress, compressive stressors (e.g., 342 and 343) can be added on the active region of the NFET to reduce the amount of tensile stress provided by the tensile stressors (e.g., 351). In this way, the amount of tensile stress provided to the NFET channel can be "tuned" to offset stress variations caused by packaging structures at different locations.

[0069] In some prior art integrated circuits, stressors can be mitigated in certain areas by selectively implanting dopants into these areas to reduce the amount of stress provided by the stressors. However, this stress modulation method requires at least one additional mask and additional implantation steps. With the methods described herein, stressor tuning can be achieved using existing processes (forming tensile stressors and compressive stressors). However, in some embodiments, ion implantation can additionally be used to tune stressors as well as overlapping stressors.

[0070] In other embodiments, the transistors may have other transistor types, have other structures, and / or be formed by other methods. For example, in some embodiments, adjacent transistors may share a current terminal region or gate structure, such as where two transistors are connected in series. Also, a stressor located above one transistor may be connected to a stressor located above another transistor.

[0071] Figure 4 4 is a cross-sectional side view of a packaged integrated circuit 401 according to one embodiment of the present invention. The integrated circuit 402 includes a substrate having a plurality of transistors formed therein. The integrated circuit 402 includes a substrate on one side of the integrated circuit 402 (e.g., Figure 4 406 is electrically attached to a package board pad 407 of a package board 405. The package board 405 includes embedded conductors (not shown) for electrically coupling the board pad 407 to solder balls 409. The integrated circuit 402 is encapsulated in the encapsulation 403. Other integrated circuit packages may have other structures or configurations in other embodiments. For example, in some embodiments, the packaged integrated circuit may be oriented with the die pad 406 facing up and include bonding wires (not shown). In other embodiments, the packaged integrated circuit may include a lead frame (not shown).

[0072] In addition to the stress caused by the die pad 406, the package board 405, the package pad 407 and the solder 408 may also generate stress on the substrate through the die pad 406 and the encapsulant 403. Therefore, using different types of stressors for each transistor can tune the stress generated in the channel region to adjust the stress provided by the package structure, which may depend on the location in the integrated circuit.

[0073] Figure 5 A cut-away top view of an integrated circuit 501 is shown, illustrating how additional stressors of the opposite stressor type may be used to tune the amount of stress provided to the channel region of the transistor to accommodate stress induced by the packaging structure.

[0074] Integrated circuit 501 includes three NFETs 510, 520, and 530 laterally located at different distances from region 502, with a die pad (not shown) located directly above the region. NFET 510 includes a source region 513, a drain region 515, and a gate 511 located above a substrate. A channel region (not shown) is located directly below gate 511 between source region 513 and drain region 515. A tensile stressor 516 is located directly above NFET 510 in the region indicated by the dashed line. NFET 520 includes a source region 523, a drain region 525, and a gate 521 located above a substrate. A channel region (not shown) is located directly below gate 521 between source region 523 and drain region 525. A tensile stressor 526 is located directly above NFET 520 in the region indicated by the dashed line. A compressive stressor 527 is located directly above the stressor 526 and the source region 523, and a compressive stressor 528 is located directly above the stressor 526 and the drain region 525. The NFET 530 includes a source region 533, a drain region 535, and a gate 531 located above the substrate. A channel region (not shown) is located directly below the gate 531 between the source region 533 and the drain region 535. A tensile stressor 536 is located directly above the NFET 530 in the area shown by the dashed line. A compressive stressor 537 is located directly above the stressor 536 and the source region 533, and a compressive stressor 538 is located directly above the stressor 536 and the drain region 535.

[0075] The liner located above region 502 applies a tensile stress in the region of the substrate that laterally surrounds region 502. The magnitude of the tensile stress decreases with increasing lateral distance from region 502. Therefore, the amount of overlap of compressive stressors 537 and 538 with tensile stressor 536 in the active region of NFET 530 is greater than the amount of overlap of compressive stressors 527 and 528 with tensile stressor 526 above the active region of transistor 520 to provide more offsetting compressive stress in the channel region of NFET 530 than in the channel region of NFET 520. Transistor 510 does not include an overlap of compressive stressors with tensile stressor 516 because it is located farthest from region 502 where the stress of the die liner has little effect on the channel region of NFET 510. For PFETs, compressive stress from the packaging structure can be compensated by overlapping stressors in a similar manner.

[0076] Figure 6 A cutaway top view of an integrated circuit 601 is shown, illustrating how different configurations of stressors of an opposing stressor type can be used to regulate stressors of another stressor type. As described below, the opposing stressor type can have various shapes and locations to reduce the stress provided by the primary stressor. Figure 6In the embodiment of FIG. 1 , the tensile stressor is shown as the primary stressor. However, in other embodiments, the compressive stressor is the primary stressor and the tensile stressor is a secondary stressor that is used to reduce the stress of the primary stressor. Figure 6 The contact openings for the source, drain and gate contacts in the stressor are not shown.

[0077] NFET 610 includes a source region 615, a drain region 613, and a gate 611 located above a substrate. A channel region (not shown) is located between the source region 615 and the drain region 613 and directly below the gate 611. A tensile stressor 616 is located directly above NFET 610 in the area indicated by the dashed line. A compressive sensor 617 is located directly above the stressor 616, the gate 611, the source region 615, and the drain region 613 to reduce the tensile stress provided by the tensile stressor 616 in the channel region.

[0078] NFET 620 includes a source region 625, a drain region 623, and a gate 621 located above a substrate. A channel region (not shown) is located directly below gate 621 between source region 625 and drain region 623. A tensile stressor 626 is located directly above NFET 620 in the area indicated by the dashed line. Compressive sensors 627 and 628 are located directly above stressor 626, gate 621, source region 625, and drain region 623 to reduce the tensile stress provided by tensile stressor 626 in the channel region.

[0079] NFET 630 includes a source region 635, a drain region 633, and a gate 631 located above a substrate. A channel region (not shown) is located directly below gate 631 between source region 635 and drain region 633. A tensile stressor 636 is located directly above NFET 630 in the area shown by the dashed line. A compressive stressor 637 is located directly above stressor 636 and source region 635. A compressive stressor 638 is located above stressor 636 and drain region 633.

[0080] although Figure 6 The embodiment of the present invention describes the case where the tensile stressor is formed first, but in other embodiments, the compressive stressor is formed first. In addition, in other embodiments, the stressor may have other configurations and / or be located at different areas of the active area to offset the stress of the main stressor.

[0081] In the illustrated embodiment, one primary stressor covers the entire active area of ​​the transistor, and stressors of the opposite stressor type overlap with the primary stressor to reduce the stress applied by the primary stressor. However, in other embodiments, no single stressor may cover the entire active area. For example, Figure 5NFET 520 may be modified so that the lateral ends of source region 523 and drain region 525 are not covered by stressor 526. However, compressive stressors 527 and 528 still overlap the edges of tensile stressor 526 to ensure that the active area is covered for contact formation.

[0082] In some embodiments, it may be desirable to use overlapping stressors of opposite types to tune a transistor of a symmetric device pair to match the performance device characteristics of the other transistor in the symmetric pair. Such use of overlapping stressors can improve the performance of circuits having symmetric device pairs.

[0083] Figure 7 7 is a flow chart showing a method 701 for designing and manufacturing a packaged integrated circuit according to one embodiment of the present invention. The method 701 begins by generating a desired channel stress profile for transistors of the integrated circuit in operation 703. In one embodiment, for each transistor, the generated desired channel stress profile is based on the conductivity type of the transistor (e.g., N-type or P-type), the size of the transistor, and the desired drive current of the transistor.

[0084] In operation 705 , a distribution of cumulative stress effects of a package structure on a substrate of an integrated circuit is generated. The distribution indicates cumulative package structure stress at each channel position of the integrated circuit. In one embodiment, operation 705 may be performed before operation 703 .

[0085] At operation 707, a placement scheme of compressive stressors and tensile stressors is generated based on the desired stress distribution generated in operation 703 and the package structure stress distribution generated in operation 705. The stressors are placed at various locations to provide the desired stress in the channel of each transistor, thereby compensating for the package stress on the channel at each location. The scheme is implemented in a wafer mask set and a process recipe for manufacturing an integrated circuit wafer. Operations 703, 705, and 707 can be performed using a computer-aided design (CAD) tool for integrated circuit design.

[0086] In operation 709, an integrated circuit is fabricated with the designed stressor locations. In one embodiment, the stressors and transistors are formed on a wafer, and then the wafer is singulated to form multiple integrated circuits. In operation 711, the integrated circuits are packaged to form packaged integrated circuits. In other embodiments, integrated circuits with overlapping stressors can be designed and fabricated by other processes.

[0087] As shown and described herein, providing an integrated circuit with overlapping stressors of different stressor types may enable stress in a channel region of the integrated circuit to be individually adjusted based on cumulative package structure stress at different locations of the integrated circuit.

[0088] Additionally, using overlapping stressors for channel stress tuning allows transistors of different sizes with the same conductivity type that require different channel stress levels to use only one stressor layer for each stressor type. For example, if the channel regions of two different NFETs of different transistor sizes require different tensile stress levels, the same layer can be used as a tensile stressor for both transistors, where the transistor with the channel having the lower desired tensile stress level will include more areas of overlapping stressors. Thus, the number of layer formation and patterning operations can be reduced.

[0089] The source region and the drain region are the current end regions of the FET, and the gate is the control end of the FET.

[0090] As disclosed herein, a first structure is "directly above" a second structure if the first structure is located above the second structure along a line having a direction perpendicular to the generally planar major side of a wafer or substrate. Figure 3 , stressor 351 is directly above P-well 309. Stressor 341 is not directly above P-well 309. As disclosed herein, a first structure is "directly beneath" or "directly under" a second structure if the first structure is located below the second structure along a line having a direction perpendicular to a generally planar major side of a wafer or substrate. For example, in Figure 3 In FIG. 3 , N-well 308 is directly below stressor 344. N-well 308 is not directly below stressor 354. If two structures are located on opposite sides of a structure along a line, then the one structure is "directly in the middle" of the two other structures along the line. For example, in Figure 3 In the example, stress source 342 is Figure 3 327 and 361 in a cross-sectional side view of FIG. 314 is not located along a line directly between gates 327 and 361. A first structure is "directly transverse to" a second structure if the first structure and the second structure are located along a line having a direction parallel to a generally planar major side of the wafer or substrate. For example, gate 327 and gate 361 are directly transverse to each other. A structure is "laterally directly between" two other structures if the two structures are located on opposite sides of the other structure along a line parallel to a generally planar major side of the wafer or substrate. For example, in Figure 3, stressor 342 is located laterally between gates 327 and 361. Two structures are directly overlapping each other if one of the structures is directly above the other of the structures along a line having a direction perpendicular to the generally planar major side of the wafer or substrate. For example, stressor 342 and stressor 351 are directly overlapping. A surface is at a "higher elevation" than another surface if the surface is located closer to the top of the active side of the wafer or integrated circuit along a line having a direction perpendicular to the generally planar major side of the wafer or integrated circuit. Figure 3 In the view of FIG. 3 , the active side of the integrated circuit 301 is Figure 3 For example, gate 361 is at a higher elevation than STI 314.

[0091] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0092] In one embodiment, an integrated circuit includes: a first transistor including an active region; a first stressor of a first stressor type located directly above the active region; and a second stressor of a second stressor type opposite to the first stressor type located directly above the active region, wherein the first stressor and the second stressor each include a portion that directly overlaps each other.

[0093] In another embodiment, an integrated circuit includes: a first field effect transistor (FET) including an active region; a first stressor of a first stressor type located directly above the active region; and a second stressor of a second stressor type opposite to the first stressor type located directly above the active region. The first stressor and the second stressor each include a portion directly overlapping each other above the active region of the FET, wherein the first stressor includes a portion that does not directly overlap a portion of the second stressor.

[0094] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from the present invention and its broader aspects, and therefore, the appended claims are intended to cover within their scope all such changes and modifications that are within the true spirit and scope of the present invention.

Claims

1. An integrated circuit, characterized in that: include: a first transistor comprising an active region; a first stressor of a first stressor type, located directly above the active area; A second stressor of a second stressor type opposite to the first stressor type is located directly above the active area, wherein the first stressor and the second stressor each include a portion that directly overlaps each other.

2. The integrated circuit according to claim 1, characterized in that The first stressor and the second stressor each include a portion directly overlapping each other directly above the active region.

3. The integrated circuit according to claim 1, characterized in that Additionally included is a third stressor of the second stressor type located directly above the active area, wherein the first stressor and the third stressor each include portions that directly overlap each other.

4. The integrated circuit according to claim 3, characterized in that: The transistor is characterized as a FET; The second stressor is located directly above a source region and not directly above a drain region of the first transistor in the active region of the first transistor, and the third stressor is located directly above the drain region of the first transistor and not directly above the source region of the first transistor.

5. The integrated circuit according to claim 1, characterized in that Also includes: a second transistor including a second active area, the second transistor having the same conductivity type as the first transistor; a third stressor of the first stressor type, located directly above the second active area; A fourth stressor of the second stressor type is located directly above the second active area, wherein the third stressor and the fourth stressor each include a portion that directly overlaps each other.

6. The integrated circuit according to claim 5, further characterized in that: The active area and the second active area have the same size; An overlapping area between the first stressor and the second stressor is greater than an overlapping area between the third stressor and the fourth stressor.

7. A packaged integrated circuit, characterized in that: Comprising an integrated circuit according to claim 1.

8. The integrated circuit according to claim 1, characterized in that The first stressor is made of a first material, and the second stressor is made of a second material having an etching selectivity with respect to the first material.

9. The integrated circuit according to claim 1, characterized in that: The first stressor acts as an etch stop layer for forming an end contact of the first transistor.

10. An integrated circuit, characterized in that: include: a first field effect transistor (FET) comprising an active region; a first stressor of a first stressor type, located directly above the active area; a second stressor of a second stressor type opposite to the first stressor type, located directly above the active area, wherein the first stressor and the second stressor each include a portion that directly overlaps each other above the active area of ​​the FET, and wherein the first stressor includes a portion that does not directly overlap a portion of the second stressor.

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