Super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with fast reverse recovery performance

Abstract

The invention discloses a super junction MOSFET device with fast reverse recovery performance, which comprises an N + substrate and an N-type epitaxial layer, a plurality of P-type columns are arranged in the N-type epitaxial layer, and the P-type columns and the N-type epitaxial layer form alternative P-type columns and N-type columns; a plurality of P body regions are arranged on the N-type epitaxial layer; a plurality of N + doped regions are arranged on each P body region; gate oxide layers are respectively arranged on two sides and in the middle of the primitive cell, a gate electrode is arranged on the gate oxide layer in the middle, the upper surface of the gate electrode is sequentially covered with a dielectric oxide layer and a source electrode, and the source electrode is insulated from the gate electrode through the dielectric oxide layer; grid polycrystalline silicon is arranged on the grid oxide layers on the two sides, the grid polycrystalline silicon is sequentially covered with a dielectric oxide layer and a source electrode, and the grid polycrystalline silicon is in contact with the source electrode through a contact hole to form an MOS channel diode. According to the invention, the MOS channel diode is integrated in the device without changing the area of the device, and the reverse recovery performance of the device is optimized.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a super junction MOSFET device with fast reverse recovery performance. Background Art

[0002] Electricity is an indispensable part of people's daily production activities. With the advancement of science and technology and the growing demand for new energy, the importance of electricity has become more and more prominent. Power semiconductor devices are the core devices for power processing. They are used as power conversion and circuit control components in power equipment. They are widely used in the fields of communications, industrial control, consumer electronics, and automotive electronics. They are the bridge between weak current control and strong current operation.

[0003] The body diode formed by the contact between the P-body region and the top of the N-type column of the superjunction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device also has a reverse recovery process like the ordinary PN junction. When it is used in a circuit system, its reverse recovery characteristics will directly affect the efficiency and stability of the circuit. The slow reverse recovery characteristics of the body diode will limit the application of superjunction MOSFET devices in high-speed topologies and will also cause additional switching losses. Therefore, it is very necessary to develop and design superjunction MOSFET devices with fast reverse recovery performance. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a super junction MOSFET device with fast reverse recovery performance. The technical problem to be solved by the present invention is achieved by the following technical solution: The present invention provides a super junction MOSFET device with fast reverse recovery performance, comprising an N+ substrate and an N-type epitaxial layer arranged on the N+ substrate, wherein a plurality of P-type columns are arranged at intervals inside the N-type epitaxial layer, the N-type epitaxial layer between adjacent P-type columns forms an N-type column, the P-type columns and the N-type columns are arranged alternately, and each N-type column and half of the P-type columns adjacent to the left and right sides form a primitive cell; A plurality of P body regions are arranged at intervals on the upper surface of the N-type epitaxial layer, and the P body regions and the P-type columns are spaced apart from each other; A plurality of N+ doped regions are arranged at intervals on the upper surface of each of the P body regions, and the junction depth of the N+ doped regions is smaller than the junction depth of the P body regions; The upper surfaces of the left and right sides and the middle area of ​​the primitive cell are respectively provided with gate oxide layers, and the gate oxide layers on the left and right sides are provided with gate polysilicon; and the gate oxide layer in the middle area is provided with a gate electrode; The upper surfaces of the gate electrode and the gate polysilicon are covered with a dielectric oxide layer, the dielectric oxide layer covers the source electrode, and the source electrode contacts the gate polysilicon through a contact hole to form a MOS channel diode; the source electrode is isolated from the gate electrode by the dielectric oxide layer; A drain electrode is also disposed on the lower surface of the N+ substrate.

[0005] In one embodiment of the present invention, two P body regions are arranged on the upper surface of the N-type epitaxial layer of each unit cell, and the upper surface of each P body region is flush with the upper surface of the N-type epitaxial layer.

[0006] In one embodiment of the present invention, the outer side of each P body region has a predetermined distance from the edge of the primitive cell.

[0007] In one embodiment of the present invention, the doping concentration of the N+ substrate is 10 19 ~10 20 cm -3 ; The doping concentration of the N-type epitaxial layer is 10 14 ~10 16 cm -3 , the doping concentration of the P-type column is 10 14 ~10 16 cm -3 .

[0008] In one embodiment of the present invention, two N+ doped regions are arranged on the upper surface of each of the P body regions at intervals, and the upper surface of the N+ doped region is flush with the upper surface of the P body region.

[0009] In one embodiment of the present invention, the doping concentration of the P body region is 10 16 ~10 18 cm -3 ; The doping concentration of the N+ doped region is 10 18 ~10 20 cm -3 .

[0010] In one embodiment of the present invention, the gate oxide layer located in the middle area of ​​the primitive cell is arranged on the upper surface between adjacent P body regions, and covers at least a portion of the upper surface of the P body region and a portion of the upper surface of the N+ doped region. In one embodiment of the present invention, the gate oxide layers on the left and right sides of the primitive cell cover at least a portion of the upper surface of the P body region and a portion of the upper surface of the N+ doped region.

[0011] In one embodiment of the present invention, the dielectric oxide layer covers the gate polysilicon, and a contact hole is opened in the dielectric oxide layer above the gate polysilicon, and the gate polysilicon is connected to the source electrode through the contact hole to form a MOS channel diode.

[0012] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention proposes a super junction MOSFET device with fast reverse recovery performance, wherein a plurality of P body regions are arranged at intervals on the upper surface of an N-type epitaxial layer, and a plurality of N+ doped regions are arranged at intervals on the upper surface of each P body region; gate oxide layers are arranged on the left and right sides and the middle of the original cell respectively, a gate electrode is arranged on the middle gate oxide layer, the upper surface of the gate electrode is sequentially covered with a dielectric oxide layer and a source electrode, and the source electrode and the gate electrode are insulated by the dielectric oxide layer; gate polysilicon is arranged on the gate oxide layers on the left and right sides, the gate polysilicon is sequentially covered with a dielectric oxide layer and a source electrode, and the gate polysilicon contacts the source electrode through a contact hole to form a MOS channel diode. The present invention integrates a MOS channel diode internally without changing the device area, thereby optimizing the reverse recovery performance of the super junction MOSFET device.

[0013] 2. The reverse recovery time of the superjunction MOSFET device proposed in the present invention is shorter than that of the conventional structure MOSFET, which is more suitable for high-frequency and high-efficiency application scenarios, and the di / dt (rate of change of current over time) during the reverse recovery process is smaller, while improving the electromagnetic interference (EMI) characteristics of the device.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a cross-sectional schematic diagram of a super junction MOSFET device with fast reverse recovery performance provided by an embodiment of the present invention; Figure 2 2 is a schematic diagram comparing reverse recovery characteristics of a super junction MOSFET device provided by an embodiment of the present invention and a common super junction MOSFET device; Figure 3 It is a schematic diagram comparing the reverse recovery characteristics of the super junction MOSFET device provided by the embodiment of the present invention and the common super junction MOSFET device under different carrier lifetimes.

[0016] Description of reference numerals: 1-N+ substrate; 2-N-type epitaxial layer; 3-P-type pillar; 4-P body region; 5-N+ doped region; 6-gate oxide layer; 7-gate polysilicon; 8-gate electrode; 9-dielectric oxide layer; 10-source electrode; 11-drain electrode. DETAILED DESCRIPTION

[0017] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a super junction MOSFET device with fast reverse recovery performance proposed by the present invention is described in detail below in combination with the accompanying drawings and specific implementation methods.

[0018] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0019] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0020] Embodiment 1 See also Figure 1 , Figure 1 It is a cross-sectional schematic diagram of a super junction MOSFET device with fast reverse recovery performance provided by an embodiment of the present invention. The super junction MOSFET device includes an N+ substrate 1 and an N-type epitaxial layer 2 arranged on the N+ substrate 1. A plurality of P-type columns 3 are arranged at intervals inside the N-type epitaxial layer 2, and the plurality of P-type columns 3 and the N-type epitaxial layer 2 between adjacent P-type columns 3 form alternatingly arranged P-type columns and N-type columns, and each N-type column forms a primitive cell with the adjacent half P-type columns 3 on the left and right sides. The super junction MOSFET device of this embodiment is formed by a plurality of primitive cells arranged regularly.

[0021] A plurality of P body regions 4 are arranged at intervals on the upper surface of the N-type epitaxial layer 2, and the P body regions 4 are spaced apart from the P-type columns 3; a plurality of N+ doped regions 5 are arranged at intervals on the upper surface of each P body region 4, and the junction depth of the N+ doped region 5 is smaller than the junction depth of the P body region 4; gate oxide layers 6 are arranged on the upper surfaces of the left and right sides and the middle area of ​​the primitive cell, respectively, and gate polysilicon 7 is arranged on the gate oxide layers 6 on the left and right sides; a gate electrode 8 is arranged on the gate oxide layer 6 in the middle area; the upper surfaces of the gate electrode 8 and the gate polysilicon 7 are covered with a dielectric oxide layer 9, and a source electrode 10 is covered above the dielectric oxide layer 9, and the source electrode 10 is in contact with the gate polysilicon 7 through a contact hole to form a MOS channel diode; the source electrode 10 is isolated from the gate electrode 8 by the dielectric oxide layer 9; a drain electrode 11 is also arranged on the lower surface of the N+ substrate 1.

[0022] Further, two P-body regions 4 are arranged at intervals on the upper surface of the N-type epitaxial layer 2 in each primitive cell region, and the upper surface of each P-body region 4 is flush with the upper surface of the N-type epitaxial layer 2. The outer side of each P-body region 4 has a predetermined distance from the edge of the primitive cell, and preferably, the predetermined distance can be 0~10μm. In other words, the outer edge of each P-body region 4 retains a certain width of the material of the N-type epitaxial layer 2, or the outer edge of each P-body region 4 can be flush with the edge of the primitive cell. Further, the doping concentration of the N+ substrate 1 is greater than the doping concentration of the N-type epitaxial layer 2, and the doping concentration of the P-type column 3 can be equal to the doping concentration of the N-type epitaxial layer 2. Preferably, the doping concentration of the N+ substrate 1 is 10 19 ~10 20 cm -3 ; The doping concentration of the N-type epitaxial layer 2 is 10 14 ~10 16 cm -3 , the doping concentration of P-type column 3 is 10 14 ~10 16 cm -3 .

[0023] In a specific embodiment of the present invention, two N+ doping regions 5 are arranged on the upper surface of each P body region 4, and the upper surface of the N+ doping region 5 is flush with the upper surface of the P body region 4. The doping concentration of the N+ doping region 5 is greater than the doping concentration of the P body region 4. Preferably, the doping concentration of the P body region 4 is 10 16 ~10 18 cm -3 ; The doping concentration of N+ doping region 5 is 10 18 ~10 20 cm -3 .

[0024] Furthermore, the gate oxide layer 6 located in the middle area of ​​the primitive cell is arranged on the upper surface between adjacent P body regions 4, and covers at least a portion of the upper surface of the P body region 4 and a portion of the upper surface of the N+ doped region 5. The gate oxide layers 6 on the left and right sides of the primitive cell cover at least a portion of the upper surface of the P body region 4 and a portion of the upper surface of the N+ doped region 5. The dielectric oxide layer 9 covers the gate polysilicon 7, and the dielectric oxide layer 9 above the gate polysilicon 7 is provided with a contact hole, and the gate polysilicon 7 is connected to the source electrode 10 through the contact hole to form a MOS channel diode. The material of the gate electrode 8 is polysilicon, and in this embodiment, it is formed simultaneously with the gate polysilicon 7 on both sides.

[0025] See also Figure 2 and Figure 3 , Figure 2 3 is a schematic diagram comparing reverse recovery characteristics of a super junction MOSFET device provided by an embodiment of the present invention and a common super junction MOSFET device, wherein the abscissa represents time and the ordinate represents drain current; Figure 3 : is a schematic diagram comparing the reverse recovery characteristics of the super junction MOSFET device provided by the embodiment of the present invention and the common super junction MOSFET device under different carrier lifetimes, wherein the carrier lifetimes are 1e-5 (1×10 -5 ) seconds, 1e-6(1×10 -6 ) seconds, 1e-7(1×10 -7 )Second.

[0026] from Figure 2 and Figure 3 It can be seen that, whether it is an ordinary super junction MOSFET or a super junction MOSFET with minority carrier lifetime control, the reverse recovery time of the super junction MOSFET device proposed in the present invention is shorter than that of the conventional structure MOSFET, and the di / dt (rate of change of current with time) is smaller, thereby improving the EMI characteristics of the device.

[0027] In addition, it should be noted that the structure of the present invention is also applicable to a P-channel superjunction MOSFET device, specifically, the superjunction MOSFET device includes a P+ substrate and a P-type epitaxial layer arranged on the P+ substrate. A plurality of N-type columns are arranged at intervals inside the P-type epitaxial layer, and the plurality of N-type columns and the P-type epitaxial layer between adjacent N-type columns form alternatingly arranged P-type columns and N-type columns.

[0028] The present invention proposes a super junction MOSFET device with fast reverse recovery performance, wherein a plurality of P body regions are arranged at intervals on the upper surface of an N-type epitaxial layer, and a plurality of N+ doped regions are arranged at intervals on the upper surface of each P body region; gate oxide layers are arranged on the upper surfaces of the left and right sides of the original cell respectively, and gate polysilicon is arranged on the gate oxide layers; a gate electrode is arranged in the middle area of ​​the original cell, and the upper surfaces of the gate electrode and the gate polysilicon are covered with a source electrode, and the source electrode is in contact with the gate polysilicon to form a MOS channel diode. The present invention integrates a MOS channel diode inside the device without changing the device area, thereby optimizing the reverse recovery performance of the traditional super junction MOSFET device structure.

[0029] The reverse recovery time of the super junction MOSFET device proposed in the present invention is shorter than that of the conventional structure MOSFET, which is more suitable for high-frequency and high-efficiency application scenarios, and the di / dt during the reverse recovery process is smaller, while improving the electromagnetic interference (EMI) characteristics of the device.

[0030] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0031] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0032] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A super junction MOSFET device with fast reverse recovery performance, characterized in that: The invention comprises an N+ substrate (1) and an N-type epitaxial layer (2) arranged on the N+ substrate (1), wherein a plurality of P-type columns (3) are arranged at intervals inside the N-type epitaxial layer (2), the N-type epitaxial layer (2) between adjacent P-type columns (3) forms an N-type column, the P-type columns (3) and the N-type columns are arranged alternately, and each N-type column and half of the P-type columns (3) adjacent to the left and right sides form a primitive cell; A plurality of P body regions (4) are arranged at intervals on the upper surface of the N-type epitaxial layer (2), and the P body regions (4) and the P-type columns (3) are spaced apart from each other; A plurality of N+ doping regions (5) are arranged at intervals on the upper surface of each of the P body regions (4), and the junction depth of the N+ doping regions (5) is smaller than the junction depth of the P body region (4); The upper surfaces of the left and right sides and the middle region of the primitive cell are respectively provided with gate oxide layers (6), and the gate oxide layers (6) on the left and right sides are provided with gate polysilicon (7); and the gate oxide layer (6) in the middle region is provided with a gate electrode (8); The upper surfaces of the gate electrode (8) and the gate polysilicon (7) are covered with a dielectric oxide layer (9), the upper surface of the dielectric oxide layer (9) is covered with a source electrode (10), and the source electrode (10) and the gate polysilicon (7) are in contact through a contact hole to form a MOS channel diode; the source electrode (10) is isolated from the gate electrode (8) by the dielectric oxide layer (9); A drain electrode (11) is also provided on the lower surface of the N+ substrate (1).

2. The super junction MOSFET device with fast reverse recovery performance according to claim 1, characterized in that: Two P body regions (4) are arranged at intervals on the upper surface of the N-type epitaxial layer (2) of each unit cell, and the upper surface of each P body region (4) is flush with the upper surface of the N-type epitaxial layer (2).

3. The super junction MOSFET device with fast reverse recovery performance according to claim 2, characterized in that: The outer side of each P body region (4) has a predetermined distance from the edge of the primitive cell.

4. The super junction MOSFET device with fast reverse recovery performance according to claim 1, characterized in that: The doping concentration of the N+ substrate (1) is 10 19 ~10 20 cm -3 The doping concentration of the N-type epitaxial layer (2) is 10 14 ~10 16 cm -3 The doping concentration of the P-type column (3) is 10 14 ~10 16 cm -3 .

5. The super junction MOSFET device with fast reverse recovery performance according to claim 1, characterized in that: Two N+ doping regions (5) are arranged at intervals on the upper surface of each P body region (4), and the upper surface of the N+ doping region (5) is flush with the upper surface of the P body region (4).

6. The super junction MOSFET device with fast reverse recovery performance according to claim 5, characterized in that: The doping concentration of the P body region (4) is 10 16 ~10 18 cm -3 The doping concentration of the N+ doping region (5) is 10 18 ~10 20 cm -3 .

7. The super junction MOSFET device with fast reverse recovery performance according to claim 2, characterized in that: The gate oxide layer (6) located in the middle region of the primitive cell is arranged on the upper surface between adjacent P body regions (4) and covers at least part of the upper surface of the P body region (4) and part of the upper surface of the N+ doped region (5).

8. The super junction MOSFET device with fast reverse recovery performance according to claim 2, characterized in that: The gate oxide layers (6) on the left and right sides of the primitive cell cover at least a portion of the upper surface of the P body region (4) and a portion of the upper surface of the N+ doped region (5).

9. The super junction MOSFET device with fast reverse recovery performance according to any one of claims 1 to 8, characterized in that: The dielectric oxide layer (9) covers the gate polysilicon (7), and a contact hole is opened in the dielectric oxide layer (9) above the gate polysilicon (7), and the gate polysilicon (7) is connected to the source electrode (10) through the contact hole to form a MOS channel diode.

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