Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate, a dielectric wall and a transistor group. The dielectric wall and the transistor group are both located on the substrate. The transistor group comprises two transistors which are respectively arranged on two opposite sides of the dielectric wall. Each transistor comprises a channel, a first electrode, a second electrode, a gate dielectric layer and a gate electrode. The channel is attached to the dielectric wall. The first pole is located between the substrate and the channel. The second pole is located on the channel. The gate dielectric layer is at least located on the side, away from the dielectric wall, of the channel. The gate is located at one side of the gate dielectric layer away from the channel. The channel is a vertical channel, the thickness and the width of the channel can be freely adjusted, the limitation of the structure of the transistor in the semiconductor structure on the performance of the device can be improved, and the requirements of different circuits and chips on the performance of the transistor device can be met. The dielectric wall is beneficial for further improving the integration density of the transistor.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same, and an electronic device. Background Art

[0002] As Moore's Law continues to advance, the feature size of complementary metal-oxide-semiconductor field-effect transistors (CMOSFET) in chips continues to shrink and has reached its physical limit. In order to improve the PPAC (performance, power, area, cost) of chips, CMOSFET has gradually evolved from a two-dimensional (2D) planar structure to a three-dimensional (3D) fin field-effect transistor (FinFET) structure, and further evolved to a gate-all-around (GAA) structure. In order to improve the performance and power consumption of CMOSFET, its structure is moving towards Figure 1 The evolution of the ring-gate nanosheet structure is shown.

[0003] However, based on Figure 1 Due to the structural limitations of the ring-gate nanosheet structure, the device performance of CMOSFET is relatively single, and it is difficult to simultaneously meet the requirements of different CMOSFETs in the chip for device performance and power consumption. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for preparing the same, as well as an electronic device, for achieving further miniaturization of the transistor unit area and improving the limitations of the transistor's own structure on its device performance in the semiconductor structure, thereby meeting the requirements of different transistors for device performance and power consumption.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] In a first aspect, a semiconductor structure is provided, which includes: a substrate, a dielectric wall and a transistor group. The dielectric wall and the transistor group are both located on the substrate. The transistor group includes two transistors, and the two transistors are respectively arranged on opposite sides of the dielectric wall. Wherein, each transistor includes: a channel, a first pole, a second pole, a gate dielectric layer and a gate. The channel is attached to the dielectric wall. The first pole is located between the substrate and the channel. The second pole is located on the channel. The channel extends in a direction from the first pole to the second pole. The gate dielectric layer is at least located on a side of the channel away from the dielectric wall. The gate is located on a side of the gate dielectric layer away from the channel. The direction from the first pole to the second pole is perpendicular to a surface of the substrate close to the dielectric wall. Accordingly, the channel is a vertical channel.

[0007] The semiconductor structure provided by some embodiments of the present application, by setting the channel in the transistor as a vertical channel and attaching it to the dielectric wall, can use the dielectric wall to achieve isolation between the two transistors, effectively reduce the distance between the two transistors, reduce the area of ​​the circuit standard unit including the transistor group, and improve the integration density of the semiconductor structure.

[0008] Moreover, since the above-mentioned channel is arranged vertically, the embodiment of the present application can freely adjust the thickness, width and other parameters of the channel, so that the thickness of the channels of different transistors in the semiconductor structure can be the same or different, and the width of the channels of different transistors in the semiconductor structure can be the same or different. This means that the embodiment of the present application can adjust the thickness, width and other parameters of the channel of the corresponding transistor according to the requirements of different chips and circuits for different device performance and power consumption of transistors, thereby optimizing the performance of the corresponding transistor, while meeting the requirements of different chips and circuit functions for the device performance and power consumption of different transistors, optimizing the performance of the semiconductor structure, and thus being conducive to application in different application scenarios and in different types of chips.

[0009] In addition, compared to planar transistors, the transistors used in this embodiment are vertical channel transistors, which can reduce the area of ​​the transistors, reduce the area of ​​the circuit standard units including the transistor group, and improve the integration density of the semiconductor structure; moreover, this decouples the miniaturization of the feature size and the gate length, so that the gate length of the transistor is no longer limited by the technology of traditional lithography machines, alleviates the device performance, reliability, parasitic capacitance, parasitic resistance and other problems caused by further miniaturization of the feature size, and can achieve stronger dynamic power consumption and improve the PPAC of the semiconductor structure.

[0010] In a possible implementation of the first aspect, the channel has a first side, a second side, and a third side connected in sequence, the second side is opposite to the dielectric wall, and the first side and the third side are both connected to the second side and the dielectric wall. The gate dielectric layer is located on the first side, the second side, and the third side. The gate is located on the side of the gate dielectric layer away from the first side, the second side, and the third side. In this case, the transistor can also be called a vertical tri-gate transistor. This is conducive to increasing the control capability of the gate and improving the device performance of the transistor.

[0011] In a possible implementation of the first aspect, the dielectric wall includes a first sub-portion and a second sub-portion connected to each other. The first sub-portion is located between the first electrodes of the two transistors, and the second sub-portion is located between the channels of the two transistors. Along a direction parallel to a side surface of the substrate close to the dielectric wall and perpendicular to the arrangement direction of the dielectric wall and the channel, both opposite ends of the first sub-portion protrude from the second sub-portion. Along a direction parallel to a side surface of the substrate close to the dielectric wall and parallel to the arrangement direction of the dielectric wall and the channel, the orthographic projection of the channel coincides with the orthographic projection of the second sub-portion.

[0012] In a possible implementation manner of the first aspect, the orthographic projection of the gate on the substrate is located within the orthographic projection range of the first electrode on the substrate, which facilitates the extraction of the first electrode.

[0013] In a possible implementation of the first aspect, the gate has a top surface away from the substrate. Relative to the substrate, the top surface is flush with the surface of the gate dielectric layer away from the substrate. The transistor also includes: a first isolation layer located on the top surface; the first isolation layer is in contact with the channel and the gate dielectric layer. The first isolation layer covers a portion of the top surface. In this way, electrical insulation between the gate and the second electrode can be achieved, and the gate can be easily led out.

[0014] In a possible implementation of the first aspect, the top surface includes a first step surface and a second step surface connected to each other, and the second step surface is located on a side of the first step surface away from the channel. Relative to the substrate, the first step surface is higher than the second step surface. The first isolation layer is located on the first step surface and covers the first step surface. In this way, the gate can be led out through the second step surface.

[0015] In a possible implementation of the first aspect, the transistor further includes: a second isolation layer. The second isolation layer is located between the first electrode and the gate. The gate dielectric layer is also located between the second isolation layer and the gate. In this way, electrical insulation between the first electrode and the gate can be achieved.

[0016] In a possible implementation manner of the first aspect, the two transistors are respectively a first transistor and a second transistor, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.

[0017] In a possible implementation of the first aspect, the gate dielectric layer of the first transistor is connected to the gate dielectric layer of the second transistor, surrounding a portion of the dielectric wall; the gate of the first transistor is connected to the gate of the second transistor, surrounding a portion of the gate dielectric layer. The semiconductor structure further includes: a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern is located on the gate of the first transistor and / or the gate of the second transistor. The first conductive pattern is used to transmit an input signal to the gate of the first transistor and the gate of the second transistor. The second conductive pattern is located on the first electrode of the first transistor. The second conductive pattern is used to transmit a ground signal to the first electrode of the first transistor. The third conductive pattern is located on the first electrode of the second transistor. The third conductive pattern is used to transmit a voltage signal to the first electrode of the second transistor. The fourth conductive pattern is located on the second electrode of the first transistor and the second electrode of the second transistor. The fourth conductive pattern is used to transmit a ground signal from the first transistor, or to transmit a voltage signal from the second transistor. At this time, the transistor group constitutes an inverter.

[0018] In a possible implementation of the first aspect, the channel is a nanosheet channel, which can improve the device performance of the transistor.

[0019] In a second aspect, a method for preparing a semiconductor structure is provided, the method comprising: providing a substrate; forming an initial first pole on the substrate; forming a channel layer on the initial first pole; forming a dielectric wall, the dielectric wall penetrating the channel layer and the initial first pole to form a first pole located on opposite sides of the dielectric wall; etching the channel layer to form a channel attached to opposite sides of the dielectric wall; forming a gate dielectric layer and a gate on a side of the channel away from the dielectric wall; and forming a second pole on the channel.

[0020] In a possible implementation of the second aspect, a gate dielectric layer and a gate electrode are formed on a side of the channel away from the dielectric wall, including: forming a gate dielectric film and a gate film in sequence on the channel and the dielectric wall; etching the gate dielectric film and the gate film to expose the top of the channel and the dielectric wall to form a gate dielectric layer and a gate electrode.

[0021] In a possible implementation of the second aspect, before forming the second electrode on the channel, the preparation method further includes: forming a first isolation layer on the gate and the gate dielectric layer; relative to the substrate, a surface of the first isolation layer on a side away from the substrate is lower than a surface of the channel on a side away from the substrate. The above-mentioned forming the second electrode on the channel includes: performing a doping process on a portion of the channel protruding from the first isolation layer to form the second electrode.

[0022] In a possible implementation manner of the second aspect, forming an initial first pole on a substrate includes: performing a doping treatment on a preset area of ​​the substrate to obtain the initial first pole.

[0023] In a third aspect, an electronic device is provided, the electronic device comprising: a circuit board, and a semiconductor structure electrically connected to the circuit board. The semiconductor structure is the semiconductor structure as described in any embodiment of the first aspect.

[0024] The technical effects brought about by the second and third aspects can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A structural diagram of a transistor provided in an embodiment of the present application;

[0026] Figure 2 A structural diagram of an electronic device provided in an embodiment of the present application;

[0027] Figure 3 A structural diagram of a circuit board and a semiconductor structure provided in an embodiment of the present application;

[0028] Figure 4 A structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0029] Figure 5 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0030] Figure 6 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0031] Figure 7 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0032] Figure 8 for Figure 7 A top view of the semiconductor structure shown;

[0033] Fig. 9 for Figure 7 A cross-sectional structural diagram of the semiconductor structure shown along the AA direction;

[0034] Fig.10 for Figure 7 A cross-sectional structural diagram of the semiconductor structure shown along the BB direction;

[0035] Fig.11 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0036] Fig.12 for Fig.11 A cross-sectional structural diagram of the semiconductor structure shown along the CC direction;

[0037] Fig.13A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0038] Fig.14 for Fig.13 A cross-sectional structural diagram of the semiconductor structure shown along the DD direction;

[0039] Fig.15 A structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0040] Fig.16 for Fig.15 A cross-sectional structural diagram of the semiconductor structure shown along the EE direction;

[0041] Fig.17 An equivalent circuit diagram of a semiconductor structure provided in an embodiment of the present application;

[0042] Fig.18 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0043] Figure 19a to Figure 19j A structural diagram corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0045] In the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one item" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one item of a, b, and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0046] "And / or" describes the relationship between the associated objects, indicating that there can be three relationships. For example, a and / or b can mean: a exists alone, a and b exist at the same time, and b exists alone, where a and b can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0047] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0048] When describing some embodiments, the expression "connected" and its derivatives are used. The term "connected" should be understood in a broad sense. For example, "connected" can be fixedly connected, detachably connected, or integrated; it can be directly connected or indirectly connected through an intermediate medium. In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more of the conditions or values ​​can be based on additional conditions or values ​​beyond the described values ​​in practice.

[0049] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0050] In the embodiments of the present application, "up", "down", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the areas shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device, and are not intended to limit the scope of the exemplary embodiments.

[0051] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0052] The embodiment of the present application provides an electronic device. The electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device and / or a smart city device, etc. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.

[0053] Figure 2 The following is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. Figure 2 As shown, the electronic device 1000 includes: a memory 100, a processor 200, an input device 300, an output device 400 and other components. Those skilled in the art can understand that Figure 2The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device 1000. The electronic device 1000 may include, for example Figure 2 More or fewer components may be shown, or they may be combined as shown. Figure 2 Some of the components shown may be combined with Figure 2 The components shown are arranged differently.

[0054] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110 includes, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 120 includes, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a read-only memory, etc.

[0055] The processor 200 is the control center of the electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000. By running or executing software programs and / or modules stored in the memory 100, and calling data stored in the memory 100, it performs various functions of the electronic device 1000 and processes data, thereby monitoring the electronic device 1000 as a whole. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, and may also be other specific integrated circuits (application specific integrated circuits, ASICs), etc. Figure 2In the example, the processor 200 is a CPU, and the CPU may include an operator 210 and a controller 220. The operator 210 obtains data stored in the internal memory 120, processes the data stored in the internal memory 120, and generally sends the processed result back to the internal memory 120. The controller 220 may control the operator 210 to process the data, and the controller 220 may also control the external memory 110 and the internal memory 120 to store data or read data. The memory 100 may store data generated by the processor 200.

[0056] The input device 300 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device 1000. Exemplarily, the input device 300 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, a stylus, etc.), and drive the corresponding connection device according to a pre-set program. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the touch point coordinates, and then sends it to the processor 200, and can receive and execute the command sent by the processor 200. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic waves. Other input devices may include but are not limited to one or more of a physical keyboard, function keys (such as a volume control key, a power switch key, etc.), a trackball, a mouse, a joystick, etc. The controller 220 in the processor 200 can also control the input device 300 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 300, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 120.

[0057] The output device 400 is used to output a signal corresponding to the data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the processor 200 can also control the output device 400 to output a signal or not output a signal.

[0058] It should be noted that Figure 2The thick arrows in the figure are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 indicates that the data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the operator 210 and the internal memory 120 indicates that the data stored in the internal memory 120 can be transmitted to the operator 210, and the data processed by the operator 210 can be transmitted to the internal memory 120. Figure 2 The thin arrows in the figure represent components that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, and the like.

[0059] Alternatively, if Figure 2 The electronic device 1000 shown may also include various sensors, such as a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which are not described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which are not described in detail here.

[0060] Figure 3 FIG. 1 schematically shows a partial structure of the electronic device 1000. Figure 3 As shown, the electronic device 1000 may further include a circuit board 500 and a semiconductor structure 600 . The semiconductor structure 600 is disposed on the circuit board 500 and is electrically connected to the circuit board 500 .

[0061] like Figure 3 As shown, the electronic device 1000 further includes a connector disposed between the circuit board 500 and the semiconductor structure 600, and the semiconductor structure 600 is electrically connected to the circuit board 500 via the connector. The connector includes but is not limited to a ball grid array (BGA).

[0062] Optionally, other structures, such as a packaging substrate, may be provided between the connector and the circuit board 500. That is, the semiconductor structure 600 may be packaged on the packaging substrate and then connected to the circuit board 500 via the packaging substrate.

[0063] The number of the semiconductor structure 600 may be one or more. When the number of the semiconductor structure 600 is more than one, the semiconductor structures 600 may be arranged flat or stacked.

[0064] The semiconductor structure 600 may be a wafer or a chip. When the semiconductor structure 600 is a chip, the chip may be a bare chip (also referred to as a grain or particle) obtained by cutting the wafer, or a packaged chip obtained by packaging the bare chip. The semiconductor structure 600 may be applied to logic devices (such as the arithmetic unit 210, the controller 220, the sensor, etc.), or to storage devices (such as the external memory 110, the internal memory 120, etc.), which is not limited in the embodiments of the present application.

[0065] Figures 4 to 6 The semiconductor structure includes a substrate 1 and a plurality of transistors 2, wherein the plurality of transistors 2 are located on the substrate 1. Figure 4 The transistor 2 shown in FIG. 1 is a transistor with a ring-gate nanosheet structure. Figure 5 The transistor 2 shown in FIG. 1 is another transistor with a ring-gate nanosheet structure. Figure 6 The transistor 2 shown in FIG. 1 is another transistor with a gate-all-around nanosheet structure.

[0066] For example, Figures 4 to 6 Two transistors 2 are schematically shown in each figure, wherein the two transistors 2 shown in each figure are of different types, wherein one transistor 2 is a PMOS transistor (PFET) and the other transistor 2 is an NMOS transistor (NFET).

[0067] It is understandable that the manufacturing process of transistors is becoming more and more complicated, and the design-technology co-optimization (DTCO) technology based on materials, processes, structures, circuit designs, etc. plays an increasingly important role in the structural evolution of transistors. As the miniaturization of the characteristic size of transistors slows down, how to reduce the area of ​​the circuit standard cell including PMOS transistors and NMOS transistors is also a technical problem that needs to be solved.

[0068] exist Figure 4 In the structure shown in , the planar device nanosheet structure limits the distance between the PMOS transistor and the NMOS transistor (i.e., the two transistors 2 mentioned above). If the distance between the PMOS transistor and the NMOS transistor is simply reduced, it is easy to cause problems with reliability, parasitic resistance and capacitance, and process cost. In other words, Figure 4 In the structure shown in , it is difficult to reduce the area of ​​the circuit standard cell.

[0069] exist Figure 5In the structure shown, a shallow trench isolation (STI) structure is provided between the PMOS transistor and the NMOS transistor (ie, the two transistors 2 mentioned above) to separate the PMOS transistor from the NMOS transistor.

[0070] Due to the limitation of the STI structure, the distance between the PMOS transistor and the NMOS transistor is relatively large, which makes it difficult to reduce the area of ​​the circuit standard unit.

[0071] Figure 6 The structure shown can also be called a forksheet structure. Figure 6 In the structure shown, a dielectric wall 3 is provided. The PMOS transistor and the NMOS transistor are respectively provided on both sides of the dielectric wall 3, and the dielectric wall 3 can be used to separate the PMOS transistor and the NMOS transistor. Figure 4 The structure shown, Figure 6 The fork-piece structure shown can greatly reduce the spacing between PMOS transistors and NMOS transistors without sacrificing device performance and reliability, thereby realizing a compact CMOS circuit standard unit.

[0072] However, in Figure 6 In the embodiment, the size and quantity of nanosheets in different transistors 2 are basically the same, which makes the device performance of different transistors 2 relatively simple, and it is difficult to simultaneously meet the requirements of different chip application scenarios for different CMOSFET device performance, thereby limiting the performance of semiconductor structure 600. Its planar conductive channel structure also limits the further miniaturization of transistor size.

[0073] Based on this, the embodiment of the present application further provides a semiconductor structure, Figure 7 and Fig.11 The structure of a semiconductor structure is schematically shown respectively. Figure 8 Indicated Figure 7 A top-down view of the semiconductor structure shown, Fig. 9 Indicated Figure 7 The semiconductor structure shown is a cross-sectional structure along the AA direction. Fig.10 Indicated Figure 7 The semiconductor structure shown is a cross-sectional structure along the BB direction. Fig.12 Indicated Fig.11 The semiconductor structure shown is a cross-sectional structure along the CC direction.

[0074] Combination Figure 7 to Figure 12The semiconductor structure 600 includes a dielectric wall 3 and a transistor group 4. The dielectric wall 3 and the transistor group 4 are both located on a substrate 1. There are multiple dielectric walls 3 and multiple transistor groups 4, and the multiple dielectric walls 3 and the multiple transistor groups 4 are arranged in a one-to-one correspondence, for example.

[0075] In the following, in conjunction with the accompanying drawings, taking a corresponding dielectric wall 3 and a transistor group 4 as an example, the arrangement between the dielectric wall 3 and the transistor group 4 is schematically described.

[0076] Combination Figure 7 and Figure 8 , the size of the dielectric wall 3 in the first direction X is smaller than the size of the dielectric wall 3 in the second direction Y. Moreover, the size of the dielectric wall 3 in the first direction X is smaller than the size of the dielectric wall 3 in the third direction Z. For example, the first direction X and the second direction Y are both parallel to a side surface of the substrate 1 close to the dielectric wall 3, the third direction Z is perpendicular to a side surface of the substrate 1 close to the dielectric wall 3, and the first direction X and the second direction Y are perpendicular to each other.

[0077] The dielectric wall 3 has two opposite surfaces (i.e., a first surface A1 and a second surface A2) along the first direction X. The first surface A1 and the second surface A2 are both perpendicular to a surface of the substrate 1 close to the dielectric wall 3. Accordingly, the dielectric wall 3 is vertically disposed on the substrate 1.

[0078] Exemplarily, the material of the dielectric wall 3 includes but is not limited to silicon oxide, silicon nitride, etc.

[0079] Combination Figure 7 and Fig. 9 ,and Fig.11 and Fig.12 The transistor group 4 includes two transistors 41 (i.e., a first transistor 41a and a second transistor 41b), which are respectively arranged on opposite sides of the dielectric wall 3. For example, the first transistor 41a is arranged on the side where the first surface A1 is located, and the second transistor 41b is arranged on the side where the second surface A2 is located. The dielectric wall 3 separates the two transistors 41.

[0080] One of the two transistors 41 is an N-type transistor (ie, an NMOS transistor), and the other is a P-type transistor (ie, a PMOS transistor).

[0081] The embodiment of the present application uses a dielectric wall 3 to separate the two transistors 41 in the transistor group 4, and uses the dielectric wall 3 to achieve isolation between the N-type transistor and the P-type transistor, which can effectively reduce the distance between the above-mentioned two transistors 41 and reduce the area occupied by the isolation between the two transistors 41, which is conducive to realizing a more compact circuit standard unit.

[0082] In the embodiment of the present application, the structures of the two transistors 41 included in the transistor group 4 may be the same or different. The embodiment of the present application is described by taking the case where the structures of the two transistors 41 included in the transistor group 4 are the same as an example.

[0083] Combination Figure 7 and Fig. 9 ,and Fig.11 and Fig.12 Each transistor 41 includes a channel 411, a first electrode 412, a second electrode 413, a gate dielectric layer 414 and a gate 415. One of the first electrode 412 and the second electrode 413 is a drain, and the other is a source, which may be determined according to the type of the transistor 41.

[0084] like Fig. 9 and Fig.12 As shown, the channel 411 is in sheet form and is attached to one side of the dielectric wall 3. The channel 411 is, for example, a nanosheet channel. It is understandable that, from a physical point of view, the use of a nanosheet channel can effectively improve the device performance of the transistor 41.

[0085] Optionally, the channel 411 of the first transistor 41a is attached to the first surface A1 of the dielectric wall 3, and the channel 411 of the second transistor 41b is attached to the second surface A2 of the dielectric wall 3. The channel 411 of the first transistor 41a and the channel 411 of the second transistor 41b are separated by the dielectric wall 3 located therebetween and are not in direct contact, thereby achieving isolation between the first transistor 41a and the second transistor 41b.

[0086] In addition, the dielectric wall 3 can also serve as a supporting structure to provide support for the channel 411 , so as to improve the structural stability of the channel 411 , and further improve the structural stability of the transistor 41 .

[0087] like Fig. 9 and Fig.12 As shown, in the third direction Z, there is a gap between the channel 411 and the substrate 1, and the channel 411 and the substrate 1 are not in direct contact. The above-mentioned first pole 412 is located in the gap between the substrate 1 and the channel 411. The first pole 412 is in contact with the channel 411 and the dielectric wall 3. The second pole 413 is located on the channel 411. The second pole 413 is in contact with the channel 411 and the dielectric wall 3. Optionally, the first pole 412 and the channel 411 may be in direct contact or indirect contact through other structures. The second pole 413 and the channel 411 may be in direct contact or indirect contact through other structures.

[0088] For example, the first electrode 412 and the substrate 1 are in an integral structure.

[0089] For example, the orthographic projection of the second pole 413 on the side surface of the substrate 1 close to the dielectric wall 3 coincides with the orthographic projection of the channel 411 on the side surface of the substrate 1 close to the dielectric wall 3. And / or, the second pole 413 and the channel 411 are in an integral structure. The channel 411 extends in the direction from the first pole 412 to the second pole 413. The direction from the first pole 412 to the second pole 413 is the third direction Z, which is perpendicular to the side surface of the substrate 1 close to the dielectric wall 3. Accordingly, the channel 411 is a vertical channel.

[0090] like Fig. 9 and Fig.12 As shown, the gate dielectric layer 414 is at least located on the side of the channel 411 away from the dielectric wall 3. The portion of the gate dielectric layer 414 located on the side of the channel 411 away from the dielectric wall 3 is, for example, in direct contact with the channel 411. The gate 415 is located on the side of the gate dielectric layer 414 away from the channel 411. The gate 415 is, for example, in direct contact with the gate dielectric layer 414. The gate dielectric layer 414 is used to separate the gate 415 from the channel 411 to achieve electrical insulation between the gate 415 and the channel 411; the gate 415 is used to control the conduction state of the transistor 41.

[0091] Exemplarily, the material of the channel 411 includes, but is not limited to, silicon-based semiconductor materials such as silicon, silicon germanium, polysilicon, amorphous silicon, or oxide semiconductor materials such as indium gallium zinc oxide, or Group III-V compound semiconductor materials.

[0092] Exemplarily, the material of the first electrode 412 includes a doped semiconductor material, such as an N-type doped semiconductor material or a P-type doped semiconductor material. The material of the second electrode 413 includes a doped semiconductor material, such as an N-type doped semiconductor material or a P-type doped semiconductor material.

[0093] Exemplarily, the material of the gate dielectric layer 414 is a dielectric material. Optionally, the material of the gate dielectric layer 414 can be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof. In addition, the gate dielectric layer 414 can be a single-layer structure or a multi-layer stacked structure. The material of the single-layer structure and the material of each layer in the multi-layer stacked structure can be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof.

[0094] Exemplarily, the material of the gate 415 is a conductive material, such as a metal material. Optionally, the material of the gate 415 can be titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof.

[0095] from Fig. 9 and Fig.12It can be seen that along the third direction Z, the first pole 412, the channel 411 and the second pole 413 are arranged in sequence and attached to the side of the dielectric wall 3 in sequence. When the gate 415 controls the transistor 41 to be turned on, the current between the first pole 412 and the second pole 413 flows along the third direction Z. Accordingly, the channel 411 can be called a vertical channel. The transistor 41 in the embodiment of the present application is a vertical transport field-effect transistor (VTFET).

[0096] It is understandable that, unlike a planar channel transistor, the transistor 41 in the embodiment of the present application decouples the miniaturization of the characteristic size and the length of the gate 415 (that is, the size of the gate 415 in the third direction Z), so that the length of the gate 415 of the transistor 41 is no longer limited by the technology of the traditional photolithography machine, alleviating the device performance, reliability and other problems caused by the further miniaturization of the characteristic size. Moreover, the transistor 41 in the embodiment of the present application has relatively low parasitic capacitance and parasitic resistance, and can also achieve stronger dynamic power consumption, thereby improving the PPAC of the semiconductor structure 600. In addition, the transistor 41 provided in the embodiment of the present application has a smaller positive projection area on the surface of one side of the substrate 1 close to the dielectric wall 3, which can form a tighter arrangement, thereby realizing a more compact circuit standard unit, effectively improving the integration density of the semiconductor structure 600, and is conducive to the continuation of Moore's Law.

[0097] Furthermore, since the above-mentioned channel 411 is arranged perpendicular to the substrate 1, the thickness of the channel 411 (that is, the size of the channel 411 in the first direction X) and the width of the channel 411 (that is, the size of the channel 411 in the second direction Y) are easier to adjust. In the process of preparing different transistors 41, multiple channels 411 with different thicknesses and / or different widths can be simultaneously prepared in a single patterning process. Among them, the device performance and power consumption of the transistor 41 are mainly determined by the thickness, width and other parameters of the channel 411. This means that the semiconductor structure 600 in the embodiment of the present application can adjust the thickness, width and other parameters of the channel 411 of the corresponding transistor 41 according to the requirements of different chip application scenarios for the device performance and power consumption of the transistor 41, that is, optimize the performance of the corresponding transistor 41, and at the same time meet the requirements of different application scenarios in the chip for the device performance and power consumption of different transistors 41, optimize the performance of the semiconductor structure 600, and then facilitate application in different application scenarios and in chips of different types (including but not limited to logic, radio frequency, power, storage, etc.).

[0098] In the two transistors 41 included in the transistor group 4, the gate dielectric layer 414 and the gate 415 may be arranged in a variety of ways, which may be selected according to actual needs. In addition, the arrangement of the first pole 412 and the dielectric wall 3 is related to the arrangement of the gate dielectric layer 414 and the gate 415. In the following, in conjunction with the accompanying drawings, the arrangement of the gate dielectric layer 414 and the gate 415 is described respectively, and the arrangement of the first pole 412 and the dielectric wall 3 is described under different arrangements of the gate dielectric layer 414 and the gate 415.

[0099] like Fig.10 As shown, the shape of the channel 411 is, for example, a rectangular parallelepiped. The channel 411 has a first side surface B1, a second side surface B2, and a third side surface B3 connected in sequence. The second side surface B2 is opposite to the dielectric wall 3, and the first side surface B1 and the third side surface B3 are both connected to the second side surface B2 and the dielectric wall 3.

[0100] For example, the first side surface B1, the second side surface B2, and the third side surface B3 are all perpendicular to the side surface of the substrate 1 close to the dielectric wall 3. Any one of the first side surface B1 and the third side surface B3 is perpendicular to the first surface A1. The second side surface B2 is not in direct contact with the channel 411. It can be understood that, based on the limitation of the etching process, any one of the first side surface B1, the second side surface B2, and the third side surface B3 may not be completely perpendicular to the side surface of the substrate 1 close to the dielectric wall 3.

[0101] In a possible example, the gate dielectric layer 414 is located on the second side surface B2 , but not on the first side surface B1 and the third side surface B3 . The gate 415 is located on a side of the gate dielectric layer 414 away from the second side surface B2 .

[0102] In this case, the gate 415 covers a portion of the second side B2 of the channel 411 in the first direction X. There is no overlap between the gate 415 and the first side B1 or the third side B3 of the channel 411 in the second direction Y. For example, the size of the gate 415 is equal to the size of the channel 411.

[0103] Furthermore, the dielectric wall 3 is shaped like a cuboid, and the first surface A1 and the second surface A2 of the dielectric wall 3 are shaped like a rectangle or a square. In the second direction Y, the size of the dielectric wall 3, the size of the channel 411, and the size of the first pole 412 are, for example, equal.

[0104] Optionally, in the first direction X, the size of the first pole 412 is larger than the size of the gate 415. Accordingly, the orthographic projection of the gate 415 on the surface of the side of the substrate 1 close to the dielectric wall 3 is located within the orthographic projection range of the first pole 412 on the surface of the side of the substrate 1 close to the dielectric wall 3. In the third direction Z, the gate 415 does not completely cover the first pole 412. This facilitates the subsequent extraction of the first pole 412 through the portion of the first pole 412 exposed by the gate 415.

[0105] In another possible example, Fig.10 As shown, the gate dielectric layer 414 is located on the first side B1, the second side B2 and the third side B3. The gate dielectric layer 414, for example, completely covers the first side B1, the second side B2 and the third side B3. The gate 415 is located on a side of the gate dielectric layer 414 away from the first side B1, the second side B2 and the third side B3.

[0106] In this case, in the first direction X, the gate 415 covers a portion of the second side B2 of the channel 411. In the second direction Y, the gate 415 covers a portion of the first side B1 of the channel 411 and covers a portion of the third side B3 of the channel 411. That is, the gate dielectric layer 414 and the gate 415 both wrap the three sides of the channel 411. At this time, the transistor 41 can also be called a vertical tri-gate transistor. This is conducive to increasing the control capability of the gate 415 and improving the device performance of the transistor 41.

[0107] Furthermore, if Fig.11 and Fig.12 As shown, the dielectric wall 3 includes a first sub-portion 31 and a second sub-portion 32 connected to each other, and the first sub-portion 31 is located between the substrate 1 and the second sub-portion 32. In the direction parallel to the side surface of the substrate 1 close to the dielectric wall 3 and perpendicular to the arrangement direction of the dielectric wall 3 and the channel 411, that is, in the second direction Y, the opposite ends of the first sub-portion 31 are protruding from the second sub-portion 32. At this time, in the second direction Y, the size of the first sub-portion 31 is larger than the size of the second sub-portion 32, and the overall shape of the dielectric wall 3 is, for example, an inverted "T" shape, and the shapes of the first surface A1 and the second surface A2 of the dielectric wall 3 are, for example, an inverted "T" shape.

[0108] For example, Fig.12 As shown, the first sub-portion 31 is located between the first electrodes 412 of two transistors 41 in the transistor group 4. In the second direction Y, the orthographic projection of the first electrode 412 of each transistor 41, for example, coincides with the orthographic projection of the first sub-portion 31. At this time, in the second direction Y, the size of the first electrode 412 of each transistor 41, for example, is equal to the size of the first sub-portion 31; and in the third direction Z, the size of the first electrode 412 of each transistor 41, for example, is equal to the size of the first sub-portion 31.

[0109] For example, Fig.12 As shown, the second sub-portion 32 is located between the channels 411 of the two transistors 41 in the transistor group 4. Along the direction parallel to the side surface of the substrate 1 close to the dielectric wall 3 and parallel to the arrangement direction of the dielectric wall 3 and the channel 411, that is, along the first direction X, the orthographic projection of the channels 411 of the two transistors 41 in the transistor group 4 coincides with the orthographic projection of the second sub-portion 32. At this time, in the second direction Y, the size of the channel 411 of each transistor 41 is, for example, equal to the size of the second sub-portion 32; and in the third direction Z, the size of the channel 411 of each transistor 41 is, for example, equal to the size of the second sub-portion 32. Further, since the size of the second sub-portion 32 in the second direction Y is smaller than the size of the first sub-portion 31 in the second direction Y, the size of the channel 411 of each transistor 41 in the second direction Y is smaller than the size of the first electrode 412 of each transistor 41 in the second direction Y.

[0110] Optionally, in the first direction X, the size of the first pole 412 is larger than the size of the gate 415. And, in the second direction Y, the size of the first pole 412 is equal to the size of the gate 415. Accordingly, the orthographic projection of the gate 415 on the surface of the side of the substrate 1 close to the dielectric wall 3 is located within the orthographic projection range of the first pole 412 on the surface of the side of the substrate 1 close to the dielectric wall 3. In the third direction Z, the gate 415 does not completely cover the first pole 412. This facilitates the subsequent extraction of the first pole 412 through the portion of the first pole 412 exposed by the gate 415.

[0111] It is understandable that the gate 415 of the transistor 41 is insulated from the first electrode 412. There are many ways to set the insulation between the gate 415 of the transistor 41 and the first electrode 412, which can be selected according to actual needs.

[0112] like Fig. 9 and Fig.12 As shown, there is a gap between the gate electrode 415 and the first electrode 412 .

[0113] In a possible example, the gate dielectric layer 414 is also located in a gap between the gate 415 and the first electrode 412 to separate the gate 415 from the first electrode 412 and achieve electrical insulation between the gate 415 and the first electrode 412 .

[0114] In another possible example, Fig. 9 and Fig.12 As shown, the transistor 41 further includes a second isolation layer 416. The second isolation layer 416 is located in the gap between the gate 415 and the first electrode 412. The second isolation layer 416 is also in contact with the channel layer 411, for example.

[0115] For example, the material of the second isolation layer 416 is a dielectric material. Optionally, the material of the second isolation layer 416 can be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof. The material of the second isolation layer 416 and the material of the gate dielectric layer 414 can be the same or different.

[0116] The second isolation layer 416 is used to isolate the gate 415 from the first electrode 412 to achieve electrical insulation between the gate 415 and the first electrode 412 .

[0117] In another possible example, Fig. 9 and Fig.12 As shown, the gate dielectric layer 414 and the second isolation layer 416 are disposed between the gate 415 and the first electrode 412. The second isolation layer 416 is located between the gate 415 and the first electrode 412, and the second isolation layer 416 is in contact with the first electrode 412, and there is a gap between the second isolation layer 416 and the gate 415. The gate dielectric layer 414 is also located in the gap between the second isolation layer 416 and the gate 415.

[0118] For example, the thickness of the second isolation layer 416 is greater than the thickness of the gate dielectric layer 414 .

[0119] At this time, the gate 415 and the first electrode 412 are separated by the second isolation layer 416 and the gate dielectric layer 414 to achieve electrical insulation between the gate 415 and the first electrode 412. This is conducive to improving the reliability of electrical insulation between the gate 415 and the first electrode 412 and improving the device performance of the transistor 41.

[0120] It can be understood that the gate electrode 415 and the second electrode 413 of the transistor 41 are insulated from each other.

[0121] In some embodiments, Figure 7 , Fig. 9 , Fig.11 and Fig.12 As shown, the gate 415 has a top surface C1 away from the substrate 1. Relative to the substrate 1, the top surface C1 is flush with the surface of the gate dielectric layer 414 away from the substrate 1. This means that the gate dielectric layer 414 does not cover the top surface C1 of the gate 415.

[0122] At this time, if Figure 7 , Fig. 9 , Fig.11 and Fig.12As shown, the transistor 41 further includes a first isolation layer 417. The first isolation layer 417 is located on the top surface C1 of the gate 415 and contacts the channel 411 and the gate dielectric layer 414. The first isolation layer 417 is used to isolate the gate 415 from the second electrode 413 to achieve electrical insulation between the gate 415 and the second electrode 413.

[0123] The first isolation layer 417 covers a portion of the top surface C1 of the gate 415 and exposes a portion of the top surface C1 of the gate 415. For example, in the first direction X, the size of the first isolation layer is smaller than the size of the gate 415; and in the second direction Y, the size of the first isolation layer is smaller than the size of the gate 415. This facilitates the subsequent extraction of the gate 415 through the portion of the gate 415 exposed by the first isolation layer 417.

[0124] For example, the material of the first isolation layer 417 is a dielectric material. Optionally, the material of the first isolation layer 417 can be silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof. The material of the first isolation layer 417 and the material of the second isolation layer 416 can be the same or different. The thickness of the first isolation layer 417 and the thickness of the second isolation layer 416 can be equal or equal. It can be understood that the first isolation layer 417 is located above the second isolation layer 416, and accordingly, the first isolation layer 417 can also be called a top insulating layer (topspacer), and the second isolation layer 416 can also be called a bottom insulating layer (bottom spacer).

[0125] In some examples, relative to the substrate 1, the surface of the first isolation layer 417 on one side away from the substrate 1 is flush with the surface of the channel 411 on one side away from the substrate 1. Accordingly, the first isolation layer 417 and the first pole 412 are staggered, and in the first direction X, the first isolation layer 417 and the first pole 412 do not overlap.

[0126] The top surface C1 of the gate 415 can be arranged in a variety of ways, and can be selected according to actual needs.

[0127] In some examples, such as Figure 7 and Fig. 9 As shown, the top surface C1 of the gate 415 is planar.

[0128] In other examples, such as Fig.11 and Fig.12 As shown, the top surface C1 of the gate 415 is stepped. The top surface C1 includes a first step surface C11 and a second step surface C12 connected to each other. Relative to the substrate 1, there is a height difference between the first step surface C11 and the second step surface C12. For example, relative to the substrate 1, the first step surface C11 is higher than the second step surface C12.

[0129] The second step surface C12 is located on the side of the first step surface C11 away from the channel 411. For example, the second step surface C12, the first step surface C11 and the channel 411 are arranged in sequence along the first direction X. Fig.11 In the structure shown, in the orthographic projection of the surface on one side of the substrate 1 close to the dielectric wall 3, the first step surface C11 is in a "U" shape or a "C" shape, and the first step surface C11 is arranged around the channel 411; the second step surface C12 is in a "U" shape or a "C" shape, and is arranged around the first step surface C11, and the opening direction of the first step surface C11 is the same as the opening direction of the second step surface C12.

[0130] The first isolation layer 417 is located on the first step surface C11 and covers the first step surface C11. For example, the orthographic projection of the first isolation layer 417 on the surface of the substrate 1 close to the dielectric wall 3 coincides with the orthographic projection of the first step surface C11 on the surface of the substrate 1 close to the dielectric wall 3. The first isolation layer 417 and the first step surface C11 can be formed by etching in the same etching process, for example, to simplify the manufacturing process of the transistor 41.

[0131] The second step surface C12 is exposed by the first isolation layer 417. In this way, the gate 415 can be led out through the second step surface C12 later.

[0132] Figure 13 to Figure 16 A schematic diagram shows an electrical connection method of two transistors in a transistor group 4, Fig.17 The equivalent circuit of a transistor group 4 is shown. It is understandable that in the semiconductor structure 600 provided in the embodiment of the present application, different transistors 41 can be electrically connected in a variety of ways, but are not limited to Figure 13 to Figure 17 The electrical connections are shown in the figure. Figure 13 to Figure 17 In the embodiment, it is taken as an example that the first transistor 41a is an N-type transistor and the second transistor 41b is a P-type transistor.

[0133] like Fig.13 and Fig.15As shown, the gate dielectric layer 414 of the first transistor 41a and the gate dielectric layer 414 of the second transistor 41b are connected and form an integral structure. That is, the gate dielectric layer 414 of the first transistor 41a and the gate dielectric layer 414 of the second transistor 41b are continuous and unbroken. In the orthographic projection of the surface of the side close to the dielectric wall 3 of the substrate 1, the gate dielectric layer 414 of the first transistor 41a and the gate dielectric layer 414 of the second transistor 41b are ring-shaped and surround a part of the dielectric wall 3. For example, in the case where the dielectric wall 3 includes the first sub-portion 31 and the second sub-portion 32, in the orthographic projection of the surface of the side close to the dielectric wall 3 of the substrate 1, the gate dielectric layer 414 of the first transistor 41a and the gate dielectric layer 414 of the second transistor 41b surround the second sub-portion 32 and overlap with the first sub-portion 31.

[0134] The gate 415 of the first transistor 41a and the gate 415 of the second transistor 41b are connected and form an integral structure. That is, the gate 415 of the first transistor 41a and the gate 415 of the second transistor 41b are continuous and unbroken. In the orthographic projection of the surface of the side close to the dielectric wall 3 of the substrate 1, the gate 415 of the first transistor 41a and the gate 415 of the second transistor 41b are ring-shaped and surround a portion of the gate dielectric layer 414. At this time, the first transistor 41a and the second transistor 41b are set with a common gate.

[0135] like Figure 13 to Figure 16 As shown, the semiconductor structure 600 further includes: a first conductive pattern 5 , a second conductive pattern 6 , a third conductive pattern 7 , and a fourth conductive pattern 8 .

[0136] The first conductive pattern 5 is located on the gate 415 of the first transistor 41a and / or the gate 415 of the second transistor 41b. Figure 14 to Figure 17 , the first conductive pattern 5 is located on the gate 415 of the first transistor 41a and is electrically connected to the gate 415 of the first transistor 41a to lead out the gate 415 of the first transistor 41a. The first conductive pattern 5 is used to transmit the input signal Vin to the gate 415 of the first transistor 41a and the gate 415 of the second transistor 41b. Since the first transistor 41a and the second transistor 41b are of opposite types, the first transistor 41a and the second transistor 41b can be turned on and the other turned off under the control of the input signal Vin.

[0137] The second conductive pattern 6 is located on the first electrode 412 of the first transistor 41a and is electrically connected to the first electrode 412 of the first transistor 41a to lead out the first electrode 412 of the first transistor 41a. The second conductive pattern 6 is used to transmit the ground signal GND to the first electrode 412 of the first transistor 41a. When the first transistor 41a is turned on, the first electrode 412 of the first transistor 41a can receive the ground signal GND from the second conductive pattern 6 and transmit the ground signal GND to the second electrode 413 of the first transistor 41a.

[0138] The third conductive pattern 7 is located on the first electrode 412 of the second transistor 41b and is electrically connected to the first electrode 412 of the second transistor 41b to lead out the first electrode 412 of the second transistor 41b. The third conductive pattern 7 is used to transmit the voltage signal VDD to the first electrode 412 of the second transistor 41b. When the second transistor 41b is turned on, the first electrode 412 of the second transistor 41b can receive the voltage signal VDD from the third conductive pattern 7 and transmit the voltage signal VDD to the second electrode 413 of the second transistor 41b.

[0139] The fourth conductive pattern 8 is located on the second electrode 413 of the first transistor 41a and the second electrode 413 of the second transistor 41b, and is electrically connected to the second electrode 413 of the first transistor 41a and the second electrode 413 of the second transistor 41b, so as to lead out the second electrode 413 of the first transistor 41a and the second electrode 413 of the second transistor 41b. The fourth conductive pattern 8 is used to transmit an output signal Vout, which is a ground signal GND from the first transistor 41a or a voltage signal VDD from the second transistor 41b.

[0140] The structure of the fourth conductive pattern 8 includes various types. For example, Fig.15 and Fig.16 As shown, the fourth conductive pattern 8 is in a block shape, covering the second electrode 413 of the first transistor 41a, the second electrode 413 of the second transistor 41b and a portion of the dielectric wall 3. Fig.14 and Fig.15 As shown, the fourth conductive pattern 8 includes a first conductive block 81 and a second conductive block 82 connected to each other. The first conductive block 81 is block-shaped and covers the second electrode 413 of the first transistor 41a, the second electrode 413 of the second transistor 41b and a portion of the dielectric wall 3. The second conductive block 82 is located on a side of the first conductive block 81 away from the substrate 1. The material of the first conductive block 81 includes but is not limited to metal silicide, and the material of the second conductive block 82 includes but is not limited to metal material.

[0141] The working process of the two transistors 41 in the transistor group 4 is schematically described below. The input signal Vin is, for example, a clock signal, the ground signal GND is, for example, a DC low-level signal (whose voltage value is, for example, 0V), and the voltage signal VDD is, for example, a DC high-level signal. In this example, the "DC high-level signal" is relative, and does not limit the magnitude relationship between it and the voltage value of 0V.

[0142] When the level of the input signal Vin is low, there is basically no voltage difference or a small voltage difference between the gate 415 and the second electrode 413 of the first transistor 41a, and the first transistor 41a is turned off under the control of the input signal Vin. There is a large voltage difference between the gate 415 and the second electrode 413 of the second transistor 41b, and the second transistor 41b is turned on under the control of the input signal Vin. The voltage signal VDD from the third conductive pattern 7 is sequentially transmitted to the fourth conductive pattern 8 through the first electrode 412 and the second electrode 413 of the second transistor 41b, and is output from the fourth conductive pattern 8 as the output signal Vout.

[0143] When the level of the input signal Vin is high, similarly, the first transistor 41a is turned on under the control of the input signal Vin, and the second transistor 41b is turned off under the control of the input signal Vin. The ground signal GND from the second conductive pattern 6 is sequentially transmitted to the fourth conductive pattern 8 via the first electrode 412 and the second electrode 413 of the first transistor 41a, and is output from the fourth conductive pattern 8 as the output signal Vout.

[0144] It can be seen from the working process of transistor group 4 that when the level of input signal Vin is low, the level of output signal Vout is high; when the level of input signal Vin is high, the level of output signal Vout is low. That is, the voltage polarity of input signal Vin is opposite to the voltage polarity of output signal Vout. Transistor group 4 realizes the function of inverter.

[0145] It is understandable that the CMOS inverter formed by the transistor group 4 is a basic semiconductor circuit structure. The semiconductor circuit structure can be used as a circuit standard unit in a logic circuit, and can also be used to form a more complex circuit structure (including but not limited to a multiplier, NAND flash memory, NOR flash memory, etc.), and applied to different circuit designs. For example, the transistor group 4 can be applied to related circuits in the fields of power, radio frequency, storage, sensor devices, etc.

[0146] Moreover, since the channel 411 in the above-mentioned transistor 41 is a vertical channel, the freedom in the vertical direction (ie, the third direction Z) can be utilized to provide more space for planning and arranging the circuit structure composed of different transistors 41, thereby facilitating the realization of different wiring arrangements.

[0147] Some embodiments of the present application also provide a method for preparing a semiconductor structure, which is used, for example, to prepare the semiconductor structure 600 described in any of the above examples. Fig.18 As shown, the method for preparing a semiconductor structure includes: S100-S700.

[0148] S100, such as Fig.19a As shown, a substrate 1 is provided.

[0149] The material of the substrate 1 is the same as that of the substrate 1 in some of the above examples, and will not be described again here.

[0150] S200, such as Fig.19b As shown, an initial first electrode 412 a is formed on the substrate 1 .

[0151] Exemplarily, the substrate 1 has a plurality of preset regions arranged at intervals. Each preset region includes, for example, an N-type doping region and a P-type doping region, and the boundary of the N-type doping region partially overlaps with the boundary of the P-type doping region.

[0152] Exemplarily, the embodiment of the present application may use an ion implantation process to perform heavy doping treatment on the portion of the substrate 1 located in each preset area to form a plurality of initial first electrodes 412a. The depth of the ion implantation is less than the thickness of the substrate 1. Among them, the embodiment of the present application may use N-type ions to perform heavy doping treatment on the N-type doping area to form the initial first electrode corresponding to the N-type transistor; the embodiment of the present application may use P-type ions to perform heavy doping treatment on the P-type doping area to form the initial first electrode corresponding to the P-type transistor.

[0153] The above method for forming the first electrode 412 a is relatively simple and has low cost.

[0154] Of course, the embodiment of the present application may also adopt a deposition process, an etching process, etc. to form the initial first pole 412 a.

[0155] S300, such as Fig.19c As shown, a channel layer 411 a is formed on the initial first electrode 412 a .

[0156] For example, in the embodiment of the present application, an epitaxial growth process may be used to form a channel layer 411 a on the initial first electrode 412 a. The channel layer 411 a covers the aforementioned multiple initial first electrodes 412 a.

[0157] The channel layer 411a is not doped. Of course, the embodiment of the present application can also perform light doping on the channel layer 411a.

[0158] In the third direction Z, the size of the channel layer 411 a can be determined according to actual needs, and accordingly, the length of the channel 411 can be defined in S300 .

[0159] S400, such as Fig.19d As shown, a dielectric wall 3 is formed. The dielectric wall 3 penetrates the channel layer 411 a and the initial first electrode 412 a to form the first electrode 412 located on the opposite sides of the dielectric wall 3 .

[0160] Exemplarily, in the embodiment of the present application, an etching process (including but not limited to a photolithography process) may be used to etch the channel layer 411a to form a groove, which penetrates the channel layer 411a and the initial first pole 412a; and then a deposition process is used to deposit a dielectric material in the groove to form a dielectric wall 3. The above-mentioned groove penetrates the overlapping part of the boundary between the N-type doped region and the P-type doped region, and the initial first pole 412a is divided into two parts arranged at intervals, corresponding to the first pole 412 of the N-type transistor and the first pole 412 of the P-type transistor. Accordingly, the dielectric wall 3 can separate the N-type doped region from the P-type doped region, and further separate the first pole 412 of the N-type transistor from the first pole 412 of the corresponding P-type transistor.

[0161] The dielectric wall 3 is perpendicular to a surface of the substrate 1 close to the dielectric wall 3 .

[0162] S500, such as Fig.19e As shown, the channel layer 411 a is etched to form channels 411 that are attached to opposite sides of the dielectric wall 3 .

[0163] For example, in the embodiment of the present application, an etching process (including but not limited to a photolithography process) can be used to etch the channel layer 411a, and portions of the channel layer 411a that are attached to opposite sides of the dielectric wall 3 are retained to obtain the channel 411. The channel 411a is, for example, a nanosheet channel. The dielectric walls 3 and channels 411 corresponding to different transistor groups 4 are independently arranged.

[0164] Here, while etching the channel layer 411a, for example, the dielectric wall 3 may also be etched. The structure of the dielectric wall 3 obtained by etching is the same as the structure of the dielectric wall 3 in some of the above examples, and will not be described in detail here.

[0165] It is understandable that, in the process of etching the channel layer 411a, the sizes of different openings in the mask (corresponding to the removed portions of the channel layer 411a) can be adjusted as needed, thereby adjusting the area of ​​the removed portions of the channel layer 411a, and then freely adjusting the thickness and width of the retained channel 411. Among them, the thicknesses of different channels 411 can be the same or different; the widths of different channels 411 can be the same or different. That is to say, in the above S500, the embodiment of the present application can, as needed, simultaneously prepare and form multiple channels 411 with different thicknesses and / or different widths, so that different transistors 41 can have different device performances.

[0166] Moreover, the dielectric wall 3 separates the two channels 411, and accordingly, the dielectric wall 3 can separate the two transistors 41 in the transistor group 4 formed subsequently. This is conducive to reducing the distance between the two transistors 41 in the transistor group 4, realizing a more compact circuit standard unit, effectively improving the integration density of the semiconductor structure 600, and is conducive to continuing Moore's Law.

[0167] S600, such as Figure 19h As shown, a gate dielectric layer 414 and a gate 415 are formed on a side of the channel 411 away from the dielectric wall 3 .

[0168] For example, the embodiment of the present application may form the gate dielectric layer 414 and the gate 415 by deposition process, etching process, etc. The structures of the gate dielectric layer 414 and the gate 415 are the same as those of the gate dielectric layer 414 and the gate 415 in some of the above examples, and will not be repeated here.

[0169] S700, such as Fig.19j As shown, a second electrode 413 is formed on the channel 411 .

[0170] Illustratively, the embodiment of the present application may adopt an ion implantation process or an epitaxial growth process to form the second electrode 413 .

[0171] Illustratively, the structure of the second pole 413 is the same as the structure of the second pole 413 in some of the above examples, and will not be described again here.

[0172] Depend on Fig.19jIt can be seen that the first pole 412, the channel 411 and the second pole 413 are located in different layers, and the current between the first pole 412 and the second pole 413 flows along the third direction Z. Accordingly, the channel 411 can be called a vertical channel. Compared with the planar channel, the embodiment of the present application can reduce the area of ​​the transistor 41 formed by the preparation, reduce the area of ​​the circuit standard unit including the transistor group 4, and improve the integration density of the semiconductor structure 600; moreover, the miniaturization of the characteristic size and the gate length is decoupled, so that the gate length of the transistor 41 is no longer limited by the technology of the traditional lithography machine, and the device performance, reliability, parasitic capacitance, parasitic resistance and other problems caused by the further miniaturization of the characteristic size are alleviated, and stronger dynamic power consumption can be achieved, and the PPAC of the semiconductor structure is improved.

[0173] Moreover, by preparing the above-mentioned channel 411 as a vertical channel and attaching it to the dielectric wall 3, the dielectric wall 3 can be used to achieve isolation between the two transistors 41, effectively reducing the distance between the two transistors 41, reducing the area of ​​the circuit standard unit including the transistor group 4, and improving the integration density of the semiconductor structure 600.

[0174] In some embodiments, the gate dielectric layer 414 is also located between the first electrode 412 and the gate 415. In the above S600, the gate dielectric layer 414 and the gate 415 are formed on the side of the channel 411 away from the dielectric wall 3, including: S610-S620.

[0175] S610, such as Figure 19g As shown, a gate dielectric film 414a and a gate film 415a are sequentially formed on the channel 411 and the dielectric wall 3.

[0176] Exemplarily, the embodiment of the present application may adopt a deposition process to sequentially form a gate dielectric film 414a and a gate film 415a. The gate dielectric film 414a and the gate film 415a are, for example, both whole film layers, the gate dielectric film 414a covers the channel 411, the dielectric wall 3 and the first pole 412, and the gate film 415a covers the gate dielectric film 414a. The orthographic projection of the gate film 415a on the surface of the side of the substrate 1 close to the dielectric wall 3, for example, coincides with the orthographic projection of the gate dielectric film 414a on the surface of the side of the substrate 1 close to the dielectric wall 3.

[0177] S620, such as Figure 19h As shown, the gate dielectric film 414 a and the gate film 415 a are etched to expose the channel 411 and the top of the dielectric wall 3 , thereby forming a gate dielectric layer 414 and a gate 415 .

[0178] For example, in the embodiment of the present application, a photolithography process or a selective etching process may be used to simultaneously etch the gate film 415a and the gate dielectric film 414a, remove the portion of the gate film 415a and the gate dielectric film 414a covering the top of the channel 411 and the dielectric wall 3, expose the top of the channel 411 and the dielectric wall 3, and form the gate dielectric layer 414 and the gate 415. Of course, in the process of removing the portion of the gate film 415a and the gate dielectric film 414a covering the top of the channel 411 and the dielectric wall 3, the portion of the gate film 415a and the gate dielectric film 414a located between two adjacent preset regions may also be removed, so that the gate dielectric layer 414 and the gate 415 in different transistor groups 4 are independent of each other.

[0179] This is helpful to simplify the manufacturing process of the gate dielectric layer 414 and the gate 415 , and to simplify the manufacturing process of the semiconductor structure 600 .

[0180] Optionally, in the case where the transistor 41 further includes a second isolation layer 416, as shown in FIG. Fig.19f As shown, before the above S610 , the preparation method also includes: using a deposition process, an etching process, etc. to form a second isolation layer 416 on the first pole 412 , the second isolation layer 416 contacts the channel 411 and covers the portion of the second isolation layer 416 not covered by the channel 411 .

[0181] In some embodiments, Fig.19i As shown, before the above S700, that is, before forming the second electrode 413 on the channel 411, the preparation method further includes: forming a first isolation layer 417 on the gate 415 and the gate dielectric layer 414. Relative to the substrate 1, the first isolation layer 417 is located on a side surface away from the substrate 1 and is lower than the side surface of the channel 411 away from the substrate 1.

[0182] For example, the embodiment of the present application can use a deposition process, an etching process, etc. to form the first isolation layer 417. The first isolation layer 417 contacts the channel 411, covers the surface of the gate dielectric layer 414 away from the substrate 1, and covers a portion of the surface of the gate 415 away from the substrate 1.

[0183] Illustratively, the structure of the first isolation layer 417 is the same as the structure of the first isolation layer 417 in some of the above examples, and will not be repeated here.

[0184] Based on this, Fig.19j As shown, in the above S700 , forming the second electrode 413 on the channel 411 includes: performing doping treatment on a portion of the channel 411 protruding from the first isolation layer 417 to form the second electrode 413 .

[0185] Exemplarily, the embodiment of the present application may use an ion implantation process to heavily dope the portion of the channel 411 protruding from the first isolation layer 417 to form a second pole 413. The second pole 413 is close to the surface of one side of the substrate 1 and is flush with the surface of the first isolation layer 417 away from the substrate 1. In particular, the embodiment of the present application may use N-type ions to heavily dope the channel 411 on one side of the dielectric wall 3 to form a second pole corresponding to an N-type transistor; the embodiment of the present application may use P-type ions to heavily dope the channel 411 on the other side of the dielectric wall 3 to form a second pole corresponding to a P-type transistor.

[0186] The above method for forming the second electrode 413 is relatively simple and has low cost.

[0187] Exemplarily, the second pole 413 and the channel 411 are in an integral structure.

[0188] It is understandable that the method for preparing the semiconductor structure provided in the embodiment of the present application is not limited thereto, and each step can be adjusted or modified accordingly according to actual needs, so long as the desired structure can be prepared. Fig.19c , Fig.19d , Fig.19e , Figure 19h , Fig.19i and Fig.19j In the drawings, (a) in each drawing shows a three-dimensional structure prepared in a corresponding step, and (b) in each drawing shows a cross-sectional structure along a first direction X and along a third direction Z.

[0189] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; a dielectric wall located on the substrate; A transistor group is located on the substrate; the transistor group includes two transistors, and the two transistors are respectively arranged on opposite sides of the dielectric wall; Wherein, the transistor comprises: A channel is attached to the dielectric wall; A first electrode, located between the substrate and the channel; A second pole is located on the channel; the channel extends in a direction from the first pole to the second pole; A gate dielectric layer, at least located on a side of the channel away from the dielectric wall; The gate is located on a side of the gate dielectric layer away from the channel.

2. The semiconductor structure according to claim 1, characterized in that: The channel has a first side surface, a second side surface and a third side surface connected in sequence, the second side surface is opposite to the dielectric wall, and the first side surface and the third side surface are both connected to the second side surface and the dielectric wall; The gate dielectric layer is located on the first side surface, the second side surface and the third side surface; The gate is located on a side of the gate dielectric layer away from the first side surface, the second side surface and the third side surface.

3. The semiconductor structure according to claim 2, characterized in that: The dielectric wall comprises a first sub-portion and a second sub-portion connected to each other, wherein the first sub-portion is located between the first electrodes of the two transistors, and the second sub-portion is located between the channels of the two transistors; Along a direction parallel to a surface of the substrate close to the dielectric wall and perpendicular to an arrangement direction of the dielectric wall and the channel, opposite ends of the first sub-portion both protrude from the second sub-portion; Along a direction parallel to a surface of the substrate close to the dielectric wall and parallel to an arrangement direction of the dielectric wall and the channel, an orthographic projection of the channel and an orthographic projection of the second sub-portion overlap.

4. The semiconductor structure according to claim 1, characterized in that The orthographic projection of the gate on the substrate is located within the orthographic projection range of the first electrode on the substrate.

5. The semiconductor structure according to claim 1, characterized in that The gate has a top surface away from the substrate; Relative to the substrate, the top surface is flush with a surface of the gate dielectric layer on a side away from the substrate; The transistor further comprises: a first isolation layer located on the top surface; the first isolation layer is in contact with the channel and the gate dielectric layer; The first isolation layer covers a portion of the top surface.

6. The semiconductor structure according to claim 5, characterized in that: The top surface comprises a first step surface and a second step surface connected to each other, wherein the second step surface is located on a side of the first step surface away from the channel; With respect to the substrate, the first step surface is higher than the second step surface; The first isolation layer is located on the first step surface and covers the first step surface.

7. The semiconductor structure according to claim 1, characterized in that: The transistor further includes: a second isolation layer; The second isolation layer is located between the first electrode and the gate; Wherein, the gate dielectric layer is also located between the second isolation layer and the gate.

8. The semiconductor structure according to claim 1, characterized in that: The two transistors are respectively a first transistor and a second transistor, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.

9. The semiconductor structure according to claim 8, characterized in that: The gate dielectric layer of the first transistor is connected to the gate dielectric layer of the second transistor, surrounding a portion of the dielectric wall; the gate of the first transistor is connected to the gate of the second transistor, surrounding a portion of the gate dielectric layer; The semiconductor structure further comprises: a first conductive pattern, located on the gate of the first transistor and / or the gate of the second transistor; the first conductive pattern is used to transmit an input signal to the gate of the first transistor and the gate of the second transistor; a second conductive pattern, located on the first electrode of the first transistor; the second conductive pattern is used to transmit a ground signal to the first electrode of the first transistor; a third conductive pattern, located on the first electrode of the second transistor; the third conductive pattern is used to transmit a voltage signal to the first electrode of the second transistor; A fourth conductive pattern is located on the second electrode of the first transistor and the second electrode of the second transistor; the fourth conductive pattern is used to transmit a ground signal from the first transistor, or transmit a voltage signal from the second transistor.

10. The semiconductor structure according to claim 1, characterized in that The channel is a nanosheet channel.

11. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: providing a substrate; forming an initial first pole on the substrate; forming a channel layer on the initial first electrode; forming a dielectric wall, wherein the dielectric wall penetrates the channel layer and the initial first electrode, and forms first electrodes located on opposite sides of the dielectric wall; Etching the channel layer to form channels attached to opposite sides of the dielectric wall; Forming a gate dielectric layer and a gate on a side of the channel away from the dielectric wall; A second electrode is formed on the channel.

12. The preparation method according to claim 11, characterized in that: The step of forming a gate dielectric layer and a gate on a side of the channel away from the dielectric wall comprises: Sequentially forming a gate dielectric film and a gate film on the channel and the dielectric wall; The gate dielectric film and the gate film are etched to expose the channel and the top of the dielectric wall, thereby forming the gate dielectric layer and the gate.

13. The preparation method according to claim 11, characterized in that: Before forming the second pole on the channel, the preparation method further comprises: A first isolation layer is formed on the gate and the gate dielectric layer; relative to the substrate, a surface of the first isolation layer on one side away from the substrate is lower than a surface of the channel on one side away from the substrate; The forming of a second pole on the channel comprises: The portion of the channel protruding from the first isolation layer is doped to form the second electrode.

14. The preparation method according to claim 11, characterized in that: The forming of an initial first pole on the substrate comprises: Doping is performed on a preset area of ​​the substrate to obtain the initial first pole.

15. An electronic device, characterized in that: The electronic device comprises: a circuit board, and a semiconductor structure according to any one of claims 1 to 10, wherein the circuit board is electrically connected to the semiconductor structure.

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