Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The laminated structure is located on the substrate and comprises a channel layer and a first conducting layer which are stacked, the channel layer comprises a channel region in the first direction, the first conducting layer is located in the channel region and extends in the second direction to be located on the substrate, the laminated structure further comprises a dielectric layer located between the first conducting layer and the channel layer, and the second direction is perpendicular to the first direction; the second conductive layers are respectively positioned on the substrate at two sides of the channel region along the first direction and are respectively contacted with the channel layer; the first through hole interconnection structure penetrates through the first conductive layer at the side part of the channel layer and is electrically connected with the first conductive layer; and the second through hole interconnection structure penetrates through the second conductive layer at the side part of the channel layer and is electrically connected with the second conductive layer. The performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] At present, the world has entered the era of "information revolution". Display technology, namely display devices, has played a very important role in the development of information technology. Portable devices such as televisions, computers, mobile phones, and display screens on various instruments and meters provide a large amount of information for daily life and work. With the breakthrough of technology and the rapid growth of market demand, flat panel display technology represented by liquid crystal display (LCD) has risen rapidly, which has promoted the development of thin film transistor (TFT).

[0003] Typically, a thin film transistor has at least a gate, a source, a drain, and a channel layer. The conductive properties of the channel layer can be changed by controlling the voltage of the gate to form a conductive (on) or insulating (off) state between the source and the drain. Depending on the channel layer material, thin film transistors can be divided into organic thin film transistors and inorganic thin film transistors. Inorganic thin film transistors based on silicon-based materials are mainly divided into amorphous silicon, polycrystalline silicon or nano-silicon thin film transistors.

[0004] However, the electrical performance of thin film transistors formed by the prior art needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a stacked structure located on the substrate, the stacked structure including a stacked channel layer and a first conductive layer, the channel layer including a channel region along a first direction, the first conductive layer being located in the channel region and extending along a second direction and located on the substrate, the stacked structure also including a dielectric layer located between the first conductive layer and the channel layer, the second direction being perpendicular to the first direction; a second conductive layer being located on the substrate at both sides of the channel region along the first direction and respectively contacting the channel layer; a first through-hole interconnection structure penetrating the first conductive layer on the side of the channel layer and being electrically connected to the first conductive layer; a second through-hole interconnection structure penetrating the second conductive layer on the side of the channel layer and being electrically connected to the second conductive layer.

[0007] Optionally, the first conductive layer includes a first sub-conductive layer located between the channel layer and the substrate in the channel region, and a second sub-conductive layer located on the channel layer in the channel region; the dielectric layer includes a first sub-dielectric layer located between the first sub-conductive layer and the channel layer, and a second sub-dielectric layer located between the second sub-conductive layer and the channel layer.

[0008] Optionally, the first sub-dielectric layer covers the surface of the first sub-conductive layer and extends to cover the substrate surface on the side of the first sub-conductive layer; the second sub-dielectric layer covers the channel layer below the second sub-conductive layer and extends to cover the surface of the second conductive layer.

[0009] Optionally, the semiconductor structure further includes: a dummy conductive layer located on the top of the second conductive layer at the side of the channel layer; and the second through-hole interconnection structure also penetrates the dummy conductive layer.

[0010] Optionally, the dummy conductive layer and the second sub-conductive layer are in the same layer structure.

[0011] Optionally, the second conductive layers on the substrate respectively located on both sides of the channel region are of the same layer structure.

[0012] Optionally, the semiconductor structure further includes: an upper metal layer located on top of the first through-hole interconnect structure and electrically connected to the first through-hole interconnect structure, and located on top of the second through-hole interconnect structure and electrically connected to the second through-hole interconnect structure.

[0013] Optionally, the semiconductor structure further includes: a lower metal layer located in the substrate at the bottom of the first through-hole interconnect structure and electrically connected to the first through-hole interconnect structure, and located in the substrate at the bottom of the second through-hole interconnect structure and electrically connected to the second through-hole interconnect structure.

[0014] Optionally, the material of the first conductive layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second conductive layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the dielectric layer includes one or more of La2O3, HfO2, ZrO2 and Al2O3.

[0015] Optionally, the material of the channel layer includes polysilicon or indium gallium zinc oxide.

[0016] Optionally, the thickness of the second conductive layer is to

[0017] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a stacked channel layer and a first conductive layer, the channel layer comprising a channel region along a first direction, the first conductive layer being located in the channel region and extending along a second direction on the substrate, the stacked structure also comprising a dielectric layer between the first conductive layer and the channel layer, the second direction being perpendicular to the first direction; forming a second conductive layer on the substrate, the second conductive layer being located on the substrate at both sides of the channel region along the first direction and respectively contacting the channel layer; forming a first through-hole interconnection structure of the first conductive layer penetrating a side portion of the channel layer, the first through-hole interconnection structure being electrically connected to the first conductive layer; forming a second through-hole interconnection structure of the second conductive layer penetrating a side portion of the channel layer, the second through-hole interconnection structure being electrically connected to the second conductive layer.

[0018] Optionally, in the step of forming a stacked structure on the substrate, the first conductive layer includes a first sub-conductive layer located between the channel layer in the channel region and the substrate, and a second sub-conductive layer located on the channel layer in the channel region; in the step of forming a dielectric layer between the first conductive layer and the channel layer, the dielectric layer includes a first sub-dielectric layer located between the first sub-conductive layer and the channel layer, and a second sub-dielectric layer located between the second sub-conductive layer and the channel layer.

[0019] Optionally, the step of forming a first sub-conductive layer includes: forming a first conductive material layer covering the substrate; patterning the first conductive material layer to form a first sub-conductive layer; the step of forming a second sub-conductive layer includes: forming a channel layer covering the first sub-conductive layer, and after forming a second conductive layer on the substrate, forming a second conductive material layer covering the channel layer and the second conductive layer; patterning the second conductive material layer, retaining the second conductive material layer located on the channel layer as the second sub-conductive layer.

[0020] Optionally, before forming the channel layer covering the first sub-conductive layer, a first sub-dielectric layer is formed, and in the step of forming the first sub-dielectric layer, the first sub-dielectric layer covers the surface of the first sub-conductive layer and extends to cover the substrate surface on the side of the first sub-conductive layer; before forming the second sub-conductive layer, a second sub-dielectric layer is formed, and in the step of forming the second sub-dielectric layer, the second sub-dielectric layer covers the channel layer and extends to cover the surface of the second conductive layer.

[0021] Optionally, the forming method further includes: forming a dummy conductive layer on top of the second conductive layer at the side of the channel layer; in the step of forming the second through-hole interconnection structure, the second through-hole interconnection structure also penetrates the dummy conductive layer.

[0022] Optionally, the dummy conductive layer and the second sub-conductive layer are formed in the same step.

[0023] Optionally, the step of forming the second conductive layer includes: forming a third conductive material layer covering the channel layer and the substrate; patterning the third conductive material layer, retaining the third conductive material layers located on the substrate on both sides of the channel region along the first direction and in contact with the channel layer as the second conductive layer.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0025] In the semiconductor structure provided by the embodiment of the present invention, the stacked structure is located on the substrate, the stacked structure includes a stacked channel layer and a first conductive layer, the channel layer includes a channel region along a first direction, the first conductive layer is located in the channel region and extends along a second direction on the substrate, the stacked structure also includes a dielectric layer located between the first conductive layer and the channel layer, the second direction is perpendicular to the first direction, the first through-hole interconnection structure penetrates the first conductive layer on the side of the channel layer and is electrically connected to the first conductive layer, the second through-hole interconnection structure penetrates the second conductive layer on the side of the channel layer and is electrically connected to the second conductive layer; in the embodiment of the present invention, the channel layer, the first conductive layer and the second conductive layer constitute a thin film transistor (Thin Film Transistor). Transistor (TFT), an electrical signal is loaded to the first conductive layer through a first through-hole interconnection structure, and an electrical signal is loaded to the second conductive layer through a second through-hole interconnection structure, the first through-hole interconnection structure penetrates the first conductive layer on the side of the channel layer, and the second through-hole interconnection structure penetrates the second conductive layer on the side of the channel layer, which is beneficial to make the electrical connection between the first through-hole interconnection structure and the first conductive layer more sufficient, and the electrical connection between the second through-hole interconnection structure and the second conductive layer more sufficient, so that the electrical signal loading for the transistor is more accurate, which is beneficial to improve the performance of the semiconductor structure.

[0026] In the method for forming a semiconductor structure provided in an embodiment of the present invention, a stacked structure is formed on a substrate, the stacked structure comprising a stacked channel layer and a first conductive layer, the channel layer comprising a channel region along a first direction, the first conductive layer being located in the channel region and extending along a second direction on the substrate, the stacked structure further comprising a dielectric layer located between the first conductive layer and the channel layer, the second direction being perpendicular to the first direction, forming a first through-hole interconnection structure of the first conductive layer penetrating a side portion of the channel layer, the first through-hole interconnection structure being electrically connected to the first conductive layer, forming a second through-hole interconnection structure of the second conductive layer penetrating a side portion of the channel layer, the second through-hole interconnection structure being electrically connected to the second conductive layer; in the embodiment of the present invention, the channel layer, the first conductive layer and the second conductive layer constitute a thin film transistor (Thin Film Transistor). Transistor (TFT), an electrical signal is loaded to the first conductive layer through a first through-hole interconnection structure, and an electrical signal is loaded to the second conductive layer through a second through-hole interconnection structure, the first through-hole interconnection structure penetrates the first conductive layer on the side of the channel layer, and the second through-hole interconnection structure penetrates the second conductive layer on the side of the channel layer, which is beneficial to make the electrical connection between the first through-hole interconnection structure and the first conductive layer more sufficient, and the electrical connection between the second through-hole interconnection structure and the second conductive layer more sufficient, so that the electrical signal loading for the transistor is more accurate, which is beneficial to improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a semiconductor structure;

[0028] Figures 2 to 4 A schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0029] Figures 5 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0030] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a semiconductor structure.

[0031] Figure 1 It is a structural diagram of a semiconductor structure.

[0032] refer to Figure 1The semiconductor structure includes: a substrate 10; a first gate layer 21 located on the substrate 10; a first dielectric layer covering the first gate layer 21; a channel layer 20 on the first dielectric layer; a second dielectric layer located on the channel layer 20; a second gate layer 22 located on the second dielectric layer; a third dielectric layer covering the first dielectric layer, the channel layer 20, the second gate layer 22 and the second dielectric layer; a first through-hole interconnection structure 31, penetrating the first dielectric layer and the third dielectric layer on the first gate layer 21, being located on the first gate layer 21 and being electrically connected to the first gate layer 21; a second through-hole interconnection structure 32, penetrating the third dielectric layer on the channel layer 20, being located on the channel layer 20 and being electrically connected to the channel layer 20; a third through-hole interconnection structure 30, penetrating the third dielectric layer on the second gate layer 22, being located on the second gate layer 22 and being electrically connected to the second gate layer 22.

[0033] The first through-hole interconnect structure 31 is located on the upper surface of the first gate layer 21, the second through-hole interconnect structure 32 is located on the upper surface of the channel layer 20, and the third through-hole interconnect structure 30 is located on the upper surface of the second gate layer 22, which may easily lead to insufficient electrical connection between the first through-hole interconnect structure 31 and the first gate layer 21, the second through-hole interconnect structure 32 and the channel layer 20, and the third through-hole interconnect structure 30 and the second gate layer 22, making it difficult to load the electrical signal of the transistor more accurately, thereby affecting the performance of the semiconductor structure. Moreover, due to the limitation that the film layers are at different heights in the semiconductor structure, it is difficult to unify the heights of the first through-hole interconnect structure 31, the second through-hole interconnect structure 32 and the third through-hole interconnect structure 30, which may easily lead to leakage, thereby affecting the performance of the semiconductor structure.

[0034] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a stacked structure located on the substrate, the stacked structure including a stacked channel layer and a first conductive layer, the channel layer including a channel region along a first direction, the first conductive layer being located in the channel region and extending along a second direction on the substrate, the stacked structure also including a dielectric layer between the first conductive layer and the channel layer, the second direction being perpendicular to the first direction; a second conductive layer being located on the substrate at both sides of the channel region along the first direction and respectively contacting the channel layer; a first through-hole interconnection structure penetrating the first conductive layer on the side of the channel layer and electrically connected to the first conductive layer; a second through-hole interconnection structure penetrating the second conductive layer on the side of the channel layer and electrically connected to the second conductive layer.

[0035] In an embodiment of the present invention, the channel layer, the first conductive layer and the second conductive layer constitute a thin film transistor (TFT), and an electrical signal is loaded to the first conductive layer through a first through-hole interconnection structure, and an electrical signal is loaded to the second conductive layer through a second through-hole interconnection structure. The first through-hole interconnection structure penetrates the first conductive layer on the side of the channel layer, and the second through-hole interconnection structure penetrates the second conductive layer on the side of the channel layer, which is beneficial for making the electrical connection between the first through-hole interconnection structure and the first conductive layer more sufficient, and making the electrical connection between the second through-hole interconnection structure and the second conductive layer more sufficient, so that the electrical signal loading for the transistor is more accurate, which is beneficial to improving the performance of the semiconductor structure.

[0036] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 2 to 4 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0037] Combined with reference Figures 2 to 4 , Figure 2 is a cross-sectional view of the semiconductor structure along the X direction, Figure 3 is a cross-sectional view of the semiconductor structure along the Y direction, Figure 3 1 is a top view of a semiconductor structure, the semiconductor structure comprising: a substrate 100; a stacked structure 400, located on the substrate 100, the stacked structure 400 comprising a stacked channel layer 200 and a first conductive layer 210, the channel layer 200 along a first direction (eg Figure 2 The first conductive layer 210 is located in the channel region 200c and extends along the second direction (as shown in the X direction). Figure 2 The stacked structure 400 further includes a dielectric layer 230 located between the first conductive layer 210 and the channel layer 200, and the second direction is perpendicular to the first direction; the second conductive layer 220 is located on the substrate 100 at both sides of the channel region 200c along the first direction, and is in contact with the channel layer 200 respectively; the first through-hole interconnection structure 320 penetrates the first conductive layer 210 at the side of the channel layer 200 and is electrically connected to the first conductive layer 210; the second through-hole interconnection structure 310 penetrates the second conductive layer 220 at the side of the channel layer 200 and is electrically connected to the second conductive layer 220.

[0038] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0039] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0040] The stacked structure 400 is used to form a transistor structure. Specifically, this embodiment is used to form a thin film transistor (TFT).

[0041] Specifically, in this embodiment, the channel layer 200 is used to provide a channel. Specifically, the channel layer 200 in the channel region 200c serves as a channel, the first conductive layer 210 serves as a gate structure for controlling the opening and closing of the channel, and the dielectric layer 230 serves as a gate dielectric layer between the gate structure and the channel.

[0042] Among them, the stacked structure 400 includes a stacked channel layer 200 and a first conductive layer 210, and the stacked structure 400 also includes a dielectric layer 230 located between the first conductive layer 210 and the channel layer 200, which means that in the stacked structure 400, the first conductive layer 210 can be located below the channel layer 200, or above the channel layer 200, or the first conductive layer 210 can be formed both above and below the channel layer 200. Regardless of the formation position of the first conductive layer 210, a dielectric layer 230 is always formed between the first conductive layer 210 and the channel layer 200.

[0043] In this embodiment, the first conductive layer 210 is located in the channel region 200c and extends along the second direction on the substrate 100. The portion of the first conductive layer 210 extending out of the channel region 200c along the second direction is used to load an electrical signal for the first conductive layer 210, so that the extending portion of the first conductive layer 210 along the second direction can be penetrated by the first through-hole interconnection structure 320, thereby forming an electrical connection structure penetrating the first conductive layer 210.

[0044] Accordingly, in this embodiment, the first conductive layer 210 is made of metal material, and the channel layer 200 is made of semiconductor material, so that the first conductive layer 210 , the dielectric layer 230 and the channel layer 200 can form a transistor structure.

[0045] Specifically, in this embodiment, the material of the first conductive layer 210 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the dielectric layer 230 includes one or more of La2O3, HfO2, ZrO2 and Al2O3; the material of the channel layer 200 includes polycrystalline silicon or indium gallium zinc oxide.

[0046] As an example, in this embodiment, the material of the channel layer 200 is indium gallium zinc oxide (IGZO). The IGZO material is easy to form a thinner film layer, which is conducive to forming a thinner channel layer 200 .

[0047] In this embodiment, in the stacked structure 400 , the first conductive layer 210 includes a first sub-conductive layer 211 located between the channel layer 200 and the substrate 100 in the channel region 200 c , and a second sub-conductive layer 212 located on the channel layer 200 in the channel region 200 c .

[0048] The first sub-conductive layer 211 and the second sub-conductive layer 212 are respectively used as a bottom gate structure (Bottom Gate, BG) and a top gate structure (Top Gate, TG) of a TFT transistor to form a dual-gate transistor.

[0049] The use of the first sub-conductive layer 211 and the second sub-conductive layer 212 to form a dual-gate transistor is beneficial to enhancing the control ability of the gate structure over the channel, and has the advantages of higher mobility, larger on-state current, smaller subthreshold swing, better threshold voltage (Vth) stability and uniformity, and better gate bias stability.

[0050] Accordingly, in this embodiment, the dielectric layer 230 includes a first sub-dielectric layer 231 located between the first sub-conductive layer 211 and the channel layer 200 , and a second sub-dielectric layer 232 located between the second sub-conductive layer 212 and the channel layer 200 .

[0051] In other embodiments, the first conductive layer may be formed only below the channel layer, or only above the channel layer, to form a single-gate transistor.

[0052] In the present embodiment, after the first sub-conductive layer 211 is formed, a first sub-dielectric layer 231 of the substrate covering the first sub-conductive layer 211 and the side of the first sub-conductive layer 211 is formed, so that the first sub-dielectric layer 231 has better coverage of the first sub-conductive layer 211, and the channel layer 200 and the first sub-conductive layer 211 are better isolated. Therefore, in the present embodiment, the first sub-dielectric layer 231 covers the surface of the first sub-conductive layer 211 and extends to cover the surface of the substrate 100 on the side of the first sub-conductive layer 211.

[0053] In the present embodiment, after the channel layer 200 is formed, a second conductive layer 220 in contact with the channel layer 200 is formed on both sides of the channel region 200c. In order to simplify the formation steps of the second sub-dielectric layer 232, the second sub-dielectric layer 232 is directly deposited on the substrate 100. Therefore, in the present embodiment, the second sub-dielectric layer 232 covers the channel layer 200 below the second sub-conductive layer 212 and extends to cover the surface of the second conductive layer 220.

[0054] The second conductive layer 220 is used to form a source and drain layer of the transistor structure.

[0055] Specifically, in this embodiment, electrical signals are respectively loaded on the second conductive layer 220 , so that the second conductive layer 220 located on both sides of the channel layer 200 and in contact with the channel layer 200 is regarded as a source-drain layer of the transistor structure.

[0056] In this embodiment, the second conductive layers 220 on the substrate 100 respectively located on both sides of the channel region 200 c are of the same layer structure.

[0057] The second conductive layer 220 on the substrate 100 respectively located on both sides of the channel region 200c is a same-layer structure, which means that in the semiconductor process, the second conductive layer 220 on the substrate 100 respectively located on both sides of the channel region 200c is obtained by patterning the same conductive material layer, which is beneficial to simplifying the formation process of the semiconductor structure and improving the process efficiency.

[0058] It should be noted that, in this embodiment, the thickness of the second conductive layer 220 should not be too large or too small. If the thickness of the second conductive layer 220 is too large, it is easy to cause excessive space occupation, resulting in unnecessary waste; if the thickness of the second conductive layer 220 is too small, it is easy to cause the resistance of the second conductive layer 220 to be too large, affecting the performance of the transistor structure, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the second conductive layer 220 is to

[0059] In this embodiment, the material of the second conductive layer 220 is a metal material, so that the electrical connection performance of the second conductive layer 220 can be achieved.

[0060] Specifically, in the present embodiment, the material of the second conductive layer 220 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0061] In this embodiment, the semiconductor structure further includes: a dummy conductive layer 240 located on the top of the second conductive layer 220 at the side of the channel layer 200 .

[0062] In the present embodiment, in the stacked structure 400, the first conductive layer 210 includes a first sub-conductive layer 211 located between the channel layer 200 and the substrate 100 in the channel region 200c, and a second sub-conductive layer 212 located on the channel layer 200 in the channel region 200c, that is, the first through-hole interconnect structure 320 penetrates the two first conductive layers 210, and the dummy conductive layer 240 is used to increase the thickness of the metal film layer at the position where the second through-hole interconnect structure 310 is formed, so that the thickness of the metal film layer etched when forming the first through-hole interconnect structure 320 is consistent with the thickness of the metal film layer etched when forming the second through-hole interconnect structure 310, so that the etching process when forming the first through-hole interconnect structure 320 and the etching process when forming the second through-hole interconnect structure 310 can be performed with the same etching process parameters, that is, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 can be formed in the same step, thereby improving the process efficiency.

[0063] In this embodiment, the dummy conductive layer 240 and the second sub-conductive layer 212 are in the same layer structure.

[0064] In the step of forming the semiconductor structure, the pseudo conductive layer 240 and the second sub-conductive layer 212 are obtained by patterning the same conductive material layer, so the pseudo conductive layer 240 and the second sub-conductive layer 212 are the same layer structure, which is beneficial to simplify the process flow and improve the process efficiency. Moreover, the thickness of the pseudo conductive layer 240 and the first conductive layer 210 penetrated by the first through-hole interconnection structure 320 are equal, and the thickness of the metal film layer etched when forming the first through-hole interconnection structure 320 is further made consistent with the thickness of the metal film layer etched when forming the second through-hole interconnection structure 310, which is further beneficial to form the first through-hole interconnection structure 320 and the second through-hole interconnection structure 310 in the same step.

[0065] In this embodiment, the material of the dummy conductive layer 240 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0066] In this embodiment, the first conductive layer 210 and the second conductive layer 220 of the channel layer 200 constitute a thin film transistor (TFT), and an electrical signal is loaded to the first conductive layer 210 through the first through-hole interconnection structure 320, and an electrical signal is loaded to the second conductive layer 220 through the second through-hole interconnection structure 310. The first through-hole interconnection structure 320 penetrates the first conductive layer 210 on the side of the channel layer 200, and the second through-hole interconnection structure 310 penetrates the second conductive layer 220 on the side of the channel layer 200, which is conducive to making the electrical connection between the first through-hole interconnection structure 320 and the first conductive layer 210 more sufficient, and making the electrical connection between the second through-hole interconnection structure 310 and the second conductive layer 220 more sufficient, so that the electrical signal loading for the transistor is more accurate, which is conducive to improving the performance of the semiconductor structure.

[0067] Specifically, in the present embodiment, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 330 also penetrate into the substrate 100, so that the height of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 330 can be flexibly adjusted, which is beneficial for making the height consistency of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 330 better, thereby helping to reduce the leakage probability during the operation of the transistor, and further helping to improve the performance of the semiconductor structure.

[0068] The first through-hole interconnect structure 320 is used to electrically connect to the first conductive layer 210 .

[0069] In this embodiment, the material of the first through-hole interconnect structure 320 is a conductive material. As an example, the material of the first through-hole interconnect structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0070] The second through-hole interconnect structure 310 is used to electrically connect to the second conductive layer 220 .

[0071] In this embodiment, the material of the second through-hole interconnect structure 310 is a conductive material. As an example, the material of the second through-hole interconnect structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0072] Accordingly, in the present embodiment, the second through-hole interconnect structure 310 also penetrates the pseudo conductive layer 240, so that the thickness of the metal film layer etched when forming the first through-hole interconnect structure 320 is consistent with the thickness of the metal film layer etched when forming the second through-hole interconnect structure 310, so that the etching process when forming the first through-hole interconnect structure 320 and the etching process when forming the second through-hole interconnect structure 310 can be performed with the same etching process parameters, that is, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 can be formed in the same step, thereby improving the process efficiency.

[0073] In this embodiment, the semiconductor structure also includes: a lower metal layer 110, located in the substrate 100 at the bottom of the first through-hole interconnection structure 320 and electrically connected to the first through-hole interconnection structure 320, and located in the substrate 100 at the bottom of the second through-hole interconnection structure 310 and electrically connected to the second through-hole interconnection structure 310.

[0074] The lower metal layer 110 is used to realize electrical connection between the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 and the outside, and is also used to provide positioning for the formation of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 .

[0075] In this embodiment, the material of the lower metal layer 110 is a conductive material. As an example, the material of the lower metal layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0076] In this embodiment, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 are electrically connected to the lower metal layer 110 of the same layer, which is conducive to obtaining the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 with good consistency, thereby ensuring that the probability of leakage during the operation of the transistor is reduced, and further conducive to improving the performance of the semiconductor structure.

[0077] In this embodiment, the semiconductor structure further includes: an etch stop layer 500 located on the lower metal layer 110 , and both the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 penetrate the etch stop layer 500 .

[0078] The etch stop layer 500 is used as an etch stop position for forming the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310, which is beneficial to further obtain the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 with good high consistency, thereby further ensuring that the probability of leakage during the operation of the transistor is reduced, and further helping to further improve the performance of the semiconductor structure.

[0079] In this embodiment, the semiconductor structure further includes: an upper metal layer 120 located on top of the first via interconnect structure 320 and electrically connected to the first via interconnect structure 320 , and located on top of the second via interconnect structure 310 and electrically connected to the second via interconnect structure 310 .

[0080] The upper metal layer 120 is used to realize electrical connection between the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 and the outside.

[0081] In this embodiment, the material of the upper metal layer 120 is a conductive material. As an example, the material of the upper metal layer 120 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0082] It should be noted that, in the present embodiment, according to actual process requirements, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 can realize electrical connection with the outside from the upper metal layer 120 or from the lower metal layer 110, so that the electrical connection route of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 is more flexible, which is conducive to improving the flexible application of the semiconductor structure.

[0083] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0084] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0085] refer to Figure 5 , providing a substrate 100.

[0086] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0087] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0088] In this embodiment, in the step of providing the substrate 100 , a lower metal layer 110 is formed in the substrate 100 .

[0089] The lower metal layer 110 is used to subsequently realize electrical connection between the first through-hole interconnect structure and the second through-hole interconnect structure and the outside, and is also used to provide positioning for the subsequent formation of the first through-hole interconnect structure and the second through-hole interconnect structure.

[0090] In this embodiment, the material of the lower metal layer 110 is a conductive material. As an example, the material of the lower metal layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0091] In this embodiment, in the step of providing the substrate 100 , an etching stop layer 500 is further formed in the substrate 100 and is located on the lower metal layer 110 .

[0092] The etch stop layer 500 is used as an etch stop position for subsequently forming the first through-hole interconnect structure and the second through-hole interconnect structure, which is beneficial to obtaining the first through-hole interconnect structure and the second through-hole interconnect structure with good high consistency, thereby ensuring that the probability of leakage during the operation of the transistor is reduced, and further beneficial to improving the performance of the semiconductor structure.

[0093] Combined with reference Figures 5 to 11 A stacked structure 400 is formed on a substrate 100. The stacked structure 400 includes a stacked channel layer 200 and a first conductive layer 210. The channel layer 200 is disposed along a first direction (eg Fig.10 The first conductive layer 210 is located in the channel region 200c and extends along the second direction (as shown in the X direction). Fig.11 The second direction is perpendicular to the first direction. A second conductive layer 220 is formed on the substrate 100. The second conductive layer 220 is respectively located on the substrate 100 on both sides of the channel region 200c along the first direction and are in contact with the channel layer 200 respectively.

[0094] The stacked structure 400 is used to form a transistor structure. Specifically, this embodiment is used to form a thin film transistor (TFT).

[0095] Specifically, in this embodiment, the channel layer 200 is used to provide a channel. Specifically, the channel layer 200 in the channel region 200c serves as a channel, the first conductive layer 210 serves as a gate structure for controlling the opening and closing of the channel, and the dielectric layer 230 serves as a gate dielectric layer between the gate structure and the channel.

[0096] Among them, the stacked structure 400 includes a stacked channel layer 200 and a first conductive layer 210, and the stacked structure 400 also includes a dielectric layer 230 located between the first conductive layer 210 and the channel layer 200, which means that in the stacked structure 400, the first conductive layer 210 can be located below the channel layer 200, or above the channel layer 200, or the first conductive layer 210 can be formed both above and below the channel layer 200. Regardless of the formation position of the first conductive layer 210, a dielectric layer 230 is always formed between the first conductive layer 210 and the channel layer 200.

[0097] In this embodiment, the first conductive layer 210 is located in the channel region 200c and extends along the second direction on the substrate 100. The portion of the first conductive layer 210 extending out of the channel region 200c along the second direction is used to load an electrical signal for the first conductive layer 210, so that the extending portion of the first conductive layer 210 along the second direction can be penetrated by the first through-hole interconnection structure to form an electrical connection structure penetrating the first conductive layer 210.

[0098] Accordingly, in this embodiment, the first conductive layer 210 is made of metal material, and the channel layer 200 is made of semiconductor material, so that the first conductive layer 210 , the dielectric layer 230 and the channel layer 200 can form a transistor structure.

[0099] Specifically, in this embodiment, in the step of forming the stacked structure 400, the material of the first conductive layer 210 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the dielectric layer 230 includes one or more of La2O3, HfO2, ZrO2 and Al2O3; the material of the channel layer 200 includes polycrystalline silicon or indium gallium zinc oxide.

[0100] As an example, in this embodiment, the material of the channel layer 200 is indium gallium zinc oxide (IGZO). The IGZO material is easy to form a thinner film layer, which is conducive to forming a thinner channel layer 200 .

[0101] In this embodiment, in the step of forming the stacked structure 400 on the substrate 100, the first conductive layer 210 includes a first sub-conductive layer 211 located between the channel layer 200 and the substrate 100 in the channel region 200c, and a second sub-conductive layer 212 located on the channel layer 200 in the channel region 200c.

[0102] The first sub-conductive layer 211 and the second sub-conductive layer 212 are respectively used as a bottom gate structure (Bottom Gate, BG) and a top gate structure (Top Gate, TG) of a TFT transistor to form a dual-gate transistor.

[0103] The use of the first sub-conductive layer 211 and the second sub-conductive layer 212 to form a dual-gate transistor is beneficial to enhancing the control ability of the gate structure over the channel, and has the advantages of higher mobility, larger on-state current, smaller subthreshold swing, better threshold voltage (Vth) stability and uniformity, and better gate bias stability.

[0104] Accordingly, in this embodiment, in the step of forming the dielectric layer 230 between the first conductive layer 210 and the channel layer 200 , the dielectric layer 230 includes a first sub-dielectric layer 231 located between the first sub-conductive layer 211 and the channel layer 200 , and a second sub-dielectric layer 232 located between the second sub-conductive layer 212 and the channel layer 200 .

[0105] In other embodiments, in the step of forming a stacked structure on the substrate, the first conductive layer may be formed only below the channel layer, or only above the channel layer, to form a single-gate transistor.

[0106] The second conductive layer 220 is used to form a source and drain layer of the transistor structure.

[0107] Specifically, in this embodiment, electrical signals are respectively loaded on the second conductive layer 220 , so that the second conductive layer 220 located on both sides of the channel layer 200 and in contact with the channel layer 200 is regarded as a source-drain layer of the transistor structure.

[0108] It should be noted that, in this embodiment, the thickness of the second conductive layer 220 should not be too large or too small. If the thickness of the second conductive layer 220 is too large, it is easy to cause excessive space occupation, resulting in unnecessary waste; if the thickness of the second conductive layer 220 is too small, it is easy to cause the resistance of the second conductive layer 220 to be too large, affecting the performance of the transistor structure, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the second conductive layer 220 is to

[0109] In this embodiment, the material of the second conductive layer 220 is a metal material, so that the electrical connection performance of the second conductive layer 220 can be achieved.

[0110] Specifically, in the present embodiment, the material of the second conductive layer 220 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0111] Specifically, in conjunction with reference Figure 6 and Figure 7 , Figure 6 is a cross-sectional view of the semiconductor structure along the X direction, Figure 7It is a cross-sectional view of the semiconductor structure along the Y direction. The step of forming the first sub-conductive layer 211 includes: forming a first conductive material layer (not shown) covering the substrate 100 ; and patterning the first conductive material layer to form the first sub-conductive layer 211 .

[0112] Continue to combine references Figure 6 and Figure 7 Before forming the channel layer 200 covering the first sub-conductive layer 211 , a first sub-dielectric layer 231 is formed. In the step of forming the first sub-dielectric layer 231 , the first sub-dielectric layer 231 covers the surface of the first sub-conductive layer 211 and extends to cover the surface of the substrate 100 on the side of the first sub-conductive layer 211 .

[0113] After forming the first sub-conductive layer 211, a first sub-dielectric layer 231 is formed as a substrate covering the first sub-conductive layer 211 and the side of the first sub-conductive layer 211, so that the first sub-dielectric layer 231 has better coverage of the first sub-conductive layer 211 and the channel layer 200 has better isolation from the first sub-conductive layer 211.

[0114] Continue to combine references Figure 6 and Figure 7 , forming a channel layer 200 of the first sub-dielectric layer 231 covering the top and sidewalls of the first sub-conductive layer 211 .

[0115] In this embodiment, the channel layer 200 is made of IGZO material, which is easy to form a thinner film layer, and is conducive to forming a thin film channel layer 200 covering the top and sidewalls of the first sub-conductive layer 211 .

[0116] Combined with reference Figure 8 and Fig. 9 , Figure 8 is a cross-sectional view of the semiconductor structure along the X direction, Fig. 9 It is a cross-sectional view of the semiconductor structure along the Y direction, and the steps of forming the second conductive layer 220 include: forming a third conductive material layer (not shown) covering the channel layer 200 and the substrate 100; patterning the third conductive material layer, and retaining the third conductive material layers located on the substrate 100 on both sides of the channel region 200c along the first direction and in contact with the channel layer 200 as the second conductive layer 220.

[0117] In the semiconductor manufacturing process, the second conductive layer 220 on the substrate 100 respectively located on both sides of the channel region 200c is obtained by patterning the same third conductive material layer, so that the second conductive layer 220 on the substrate 100 respectively located on both sides of the channel region 200c is a same-layer structure, which is beneficial to simplifying the formation process of the semiconductor structure and improving the process efficiency.

[0118] Continue to refer Figure 8 and Fig. 9Before forming the second sub-conductive layer 212 , a second sub-dielectric layer 232 is formed. In the step of forming the second sub-dielectric layer 232 , the second sub-dielectric layer 232 covers the channel layer 200 and extends to cover the surface of the second conductive layer 220 .

[0119] In the present embodiment, after the channel layer 200 is formed, a second conductive layer 220 in contact with the channel layer 200 is formed on both sides of the channel region 200c. In order to simplify the formation steps of the second sub-dielectric layer 232, the second sub-dielectric layer 232 is directly deposited on the substrate 100. Therefore, in the present embodiment, the second sub-dielectric layer 232 covers the channel layer 200 below the second sub-conductive layer 212 and extends to cover the surface of the second conductive layer 220.

[0120] Combined with reference Fig.10 and Fig.11 , Fig.10 is a cross-sectional view of the semiconductor structure along the X direction, Fig.11 It is a cross-sectional view of the semiconductor structure along the Y direction, and the steps of forming the second sub-conductive layer 212 include: forming a channel layer 200 covering the first sub-conductive layer 211, and after forming the second conductive layer 220 on the substrate 100, forming a second conductive material layer (not shown) covering the channel layer 200 and the second conductive layer 220; patterning the second conductive material layer, retaining the second conductive material layer located on the channel layer 200 as the second sub-conductive layer 212.

[0121] Continue to refer Fig.10 and Fig.11 The forming method further includes: forming a dummy conductive layer 240 on the top of the second conductive layer 220 at the side of the channel layer 200 .

[0122] In the present embodiment, in the stacked structure 400, the first conductive layer 210 includes a first sub-conductive layer 211 located between the channel layer 200 and the substrate 100 in the channel region 200c, and a second sub-conductive layer 212 located on the channel layer 200 in the channel region 200c, that is, the first through-hole interconnect structure formed subsequently penetrates the two first conductive layers 210, and the dummy conductive layer 240 is used to increase the thickness of the metal film layer at the position where the second through-hole interconnect structure is formed subsequently, so that the thickness of the metal film layer etched when forming the first through-hole interconnect structure is consistent with the thickness of the metal film layer etched when forming the second through-hole interconnect structure, so that the etching process when forming the first through-hole interconnect structure and the etching process when forming the second through-hole interconnect structure can be performed with the same etching process parameters, that is, the first through-hole interconnect structure and the second through-hole interconnect structure can be formed in the same step subsequently, thereby improving the process efficiency.

[0123] In this embodiment, the dummy conductive layer 240 and the second sub-conductive layer 212 are formed in the same step.

[0124] Specifically, in the step of forming the semiconductor structure, the pseudo conductive layer 240 and the second sub-conductive layer 212 are obtained by patterning the same second conductive material layer, so the pseudo conductive layer 240 and the second sub-conductive layer 212 are the same layer structure, which is beneficial to simplify the process flow and improve the process efficiency. Moreover, the thickness of the pseudo conductive layer 240 is equal to the thickness of the first conductive layer 210 penetrated by the first through-hole interconnection structure formed subsequently, and further makes the thickness of the metal film layer etched when the first through-hole interconnection structure is subsequently formed and the thickness of the metal film layer etched when the second through-hole interconnection structure is formed tend to be consistent, which is further beneficial to the subsequent formation of the first through-hole interconnection structure and the second through-hole interconnection structure in the same step.

[0125] In the present embodiment, in the step of forming the dummy conductive layer 240 , the material of the dummy conductive layer 240 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0126] Combined with reference Figure 12 to Figure 14 , Fig.12 is a cross-sectional view of the semiconductor structure along the X direction, Fig.13 is a cross-sectional view of the semiconductor structure along the Y direction, Fig.14 It is a top view of the semiconductor structure, forming a first through-hole interconnect structure 320 penetrating the first conductive layer 210 at the side of the channel layer 200, and the first through-hole interconnect structure 320 is electrically connected to the first conductive layer 210; forming a second through-hole interconnect structure 310 penetrating the second conductive layer 220 at the side of the channel layer 200, and the second through-hole interconnect structure 310 is electrically connected to the second conductive layer 220.

[0127] In this embodiment, the first conductive layer 210 and the second conductive layer 220 of the channel layer 200 constitute a thin film transistor (TFT), and an electrical signal is loaded to the first conductive layer 210 through the first through-hole interconnection structure 320, and an electrical signal is loaded to the second conductive layer 220 through the second through-hole interconnection structure 310. The first through-hole interconnection structure 320 penetrates the first conductive layer 210 on the side of the channel layer 200, and the second through-hole interconnection structure 310 penetrates the second conductive layer 220 on the side of the channel layer 200, which is conducive to making the electrical connection between the first through-hole interconnection structure 320 and the first conductive layer 210 more sufficient, and making the electrical connection between the second through-hole interconnection structure 310 and the second conductive layer 220 more sufficient, so that the electrical signal loading for the transistor is more accurate, which is conducive to improving the performance of the semiconductor structure.

[0128] Specifically, in the present embodiment, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 330 also penetrate into the substrate 100, so that the height of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 330 can be flexibly adjusted, which is beneficial for making the height consistency of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 330 better, thereby helping to reduce the leakage probability during the operation of the transistor, and further helping to improve the performance of the semiconductor structure.

[0129] The first through-hole interconnect structure 320 is used to electrically connect to the first conductive layer 210 .

[0130] In the present embodiment, in the step of forming the first through-hole interconnect structure 320 penetrating the first conductive layer 210 at the side of the channel layer 200, the material of the first through-hole interconnect structure 320 is a conductive material. As an example, the material of the first through-hole interconnect structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0131] The second through-hole interconnect structure 310 is used to electrically connect to the second conductive layer 220 .

[0132] In the present embodiment, in the step of forming the second through-hole interconnect structure 310 penetrating the second conductive layer 220 at the side of the channel layer 200, the material of the second through-hole interconnect structure 310 is a conductive material. As an example, the material of the second through-hole interconnect structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0133] Accordingly, in the present embodiment, in the step of forming the second through-hole interconnect structure 310 penetrating the second conductive layer 220 on the side of the channel layer 200, the second through-hole interconnect structure 310 also penetrates the pseudo conductive layer 240, so that the thickness of the metal film layer etched when forming the first through-hole interconnect structure 320 is consistent with the thickness of the metal film layer etched when forming the second through-hole interconnect structure 310, so that the etching process when forming the first through-hole interconnect structure 320 and the etching process when forming the second through-hole interconnect structure 310 can be performed with the same etching process parameters, that is, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 can be formed in the same step, thereby improving the process efficiency.

[0134] Accordingly, in this embodiment, the first through-hole interconnection structure 320 and the second through-hole interconnection structure 310 are formed in the same step.

[0135] In the present embodiment, in the step of forming the first through-hole interconnection structure 320 and the second through-hole interconnection structure 310 , the first through-hole interconnection structure 320 and the second through-hole interconnection structure 310 are electrically connected to the lower metal layer 110 at the bottom thereof, respectively.

[0136] In this embodiment, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 are electrically connected to the lower metal layer 110 of the same layer, which is conducive to obtaining the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 with good consistency, thereby ensuring that the probability of leakage during the operation of the transistor is reduced, and further conducive to improving the performance of the semiconductor structure.

[0137] In this embodiment, in the step of forming the first through-hole interconnection structure 320 and the second through-hole interconnection structure 310 , the first through-hole interconnection structure 320 and the second through-hole interconnection structure 310 also penetrate the etch stop layer 500 .

[0138] The etch stop layer 500 is used as an etch stop position for forming the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310, which is beneficial to further obtain the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 with good high consistency, thereby further ensuring that the probability of leakage during the operation of the transistor is reduced, and further helping to further improve the performance of the semiconductor structure.

[0139] In this embodiment, the forming method further includes: forming an upper metal layer 120 located on top of the first via interconnect structure 320 and electrically connected to the first via interconnect structure 320 , and located on top of the second via interconnect structure 310 and electrically connected to the second via interconnect structure 310 .

[0140] The upper metal layer 120 is used to realize electrical connection between the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 and the outside.

[0141] In this embodiment, the material of the upper metal layer 120 is a conductive material. As an example, the material of the upper metal layer 120 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0142] It should be noted that, in the present embodiment, according to actual process requirements, the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 can realize electrical connection with the outside from the upper metal layer 120 or from the lower metal layer 110, so that the electrical connection route of the first through-hole interconnect structure 320 and the second through-hole interconnect structure 310 is more flexible, which is conducive to improving the flexible application of the semiconductor structure.

[0143] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A stacked structure, located on the substrate, the stacked structure includes a stacked channel layer and a first conductive layer, the channel layer includes a channel region along a first direction, the first conductive layer is located in the channel region and extends along a second direction on the substrate, the stacked structure also includes a dielectric layer between the first conductive layer and the channel layer, the second direction is perpendicular to the first direction; A second conductive layer is located on the substrate at two sides of the channel region along the first direction and is in contact with the channel layer respectively; A first through-hole interconnect structure passes through the first conductive layer at the side of the channel layer and is electrically connected to the first conductive layer; The second through hole interconnection structure penetrates the second conductive layer at the side of the channel layer, and the second conductive layer is electrically connected.

2. The semiconductor structure according to claim 1, wherein: In the stacked structure, the first conductive layer includes a first sub-conductive layer located between the channel layer in the channel region and the substrate, and a second sub-conductive layer located on the channel layer in the channel region; The dielectric layer includes a first sub-dielectric layer located between the first sub-conductive layer and the channel layer, and a second sub-dielectric layer located between the second sub-conductive layer and the channel layer.

3. The semiconductor structure according to claim 2, wherein: The first sub-dielectric layer covers the surface of the first sub-conductive layer and extends to cover the substrate surface at the side of the first sub-conductive layer; The second sub-dielectric layer covers the channel layer below the second sub-conductive layer and extends to cover the surface of the second conductive layer.

4. The semiconductor structure according to claim 2, characterized in that The semiconductor structure further includes: a dummy conductive layer located on top of the second conductive layer at the side of the channel layer; The second through-hole interconnection structure also penetrates the dummy conductive layer.

5. The semiconductor structure according to claim 4, characterized in that The dummy conductive layer and the second sub-conductive layer are in the same layer structure.

6. The semiconductor structure according to claim 1, wherein: The second conductive layers on the substrate respectively located on both sides of the channel region are of the same layer structure.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes an upper metal layer located on top of the first through-hole interconnect structure and electrically connected to the first through-hole interconnect structure, and located on top of the second through-hole interconnect structure and electrically connected to the second through-hole interconnect structure.

8. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a lower metal layer located in the substrate at the bottom of the first through-via interconnect structure and electrically connected to the first through-via interconnect structure, and located in the substrate at the bottom of the second through-via interconnect structure and electrically connected to the second through-via interconnect structure.

9. The semiconductor structure according to claim 1, wherein: The material of the first conductive layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; The material of the second conductive layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; The material of the dielectric layer includes one or more of La2O3, HfO2, ZrO2 and Al2O3.

10. The semiconductor structure according to claim 1, wherein: The material of the channel layer includes polysilicon or indium gallium zinc oxide.

11. The semiconductor structure according to claim 1, wherein: The thickness of the second conductive layer is to 12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A stacked structure is formed on the substrate, the stacked structure comprising a stacked channel layer and a first conductive layer, the channel layer comprising a channel region along a first direction, the first conductive layer being located in the channel region and extending along a second direction on the substrate, the stacked structure further comprising a dielectric layer between the first conductive layer and the channel layer, the second direction being perpendicular to the first direction; forming a second conductive layer on the substrate, wherein the second conductive layers are respectively located on the substrate at two sides of the channel region along the first direction and are respectively in contact with the channel layer; forming a first through-hole interconnect structure penetrating the first conductive layer at the side of the channel layer, wherein the first through-hole interconnect structure is electrically connected to the first conductive layer; A second through-hole interconnection structure penetrating the second conductive layer at the side of the channel layer is formed, wherein the second through-hole interconnection structure is electrically connected to the second conductive layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: In the step of forming the stacked structure on the substrate, the first conductive layer includes a first sub-conductive layer located between the channel layer in the channel region and the substrate, and a second sub-conductive layer located on the channel layer in the channel region; In the step of forming a dielectric layer between the first conductive layer and the channel layer, the dielectric layer includes a first sub-dielectric layer located between the first sub-conductive layer and the channel layer, and a second sub-dielectric layer located between the second sub-conductive layer and the channel layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The step of forming the first sub-conductive layer includes: forming a first conductive material layer covering the substrate; patterning the first conductive material layer to form the first sub-conductive layer; The step of forming the second sub-conductive layer includes: forming a channel layer covering the first sub-conductive layer, and after forming the second conductive layer on the substrate, forming a second conductive material layer covering the channel layer and the second conductive layer; patterning the second conductive material layer, retaining the second conductive material layer located on the channel layer as the second sub-conductive layer.

15. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the channel layer covering the first sub-conductive layer, forming a first sub-dielectric layer, in the step of forming the first sub-dielectric layer, the first sub-dielectric layer covers the surface of the first sub-conductive layer and extends to cover the substrate surface at the side of the first sub-conductive layer; Before forming the second sub-conductive layer, a second sub-dielectric layer is formed. In the step of forming the second sub-dielectric layer, the second sub-dielectric layer covers the channel layer and extends to cover the surface of the second conductive layer.

16. The method for forming a semiconductor structure according to claim 13, wherein: The forming method further comprises: forming a dummy conductive layer on top of the second conductive layer at the side of the channel layer; In the step of forming the second through-hole interconnection structure, the second through-hole interconnection structure also penetrates the dummy conductive layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The dummy conductive layer and the second sub-conductive layer are formed in the same step.

18. The method for forming a semiconductor structure according to claim 12, wherein: The step of forming the second conductive layer includes: forming a third conductive material layer covering the channel layer and the substrate; The third conductive material layer is patterned, and the third conductive material layers respectively located on the substrate at both sides of the channel region along the first direction and in contact with the channel layer are retained as the second conductive layers.

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