Three-dimensional integrated chip structure, arrangement method thereof and chip
By embedding through silicon through-holes in the array of nano-gate transistors in a three-dimensional integrated chip structure, the problems of thermal stress influence and nano-gate field-effect transistor integration in 3D-IC technology are solved, and higher performance and stability are achieved.
Patent Information
- Application Number
- CN202411704337.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-02-25
AI Technical Summary
In 3D-IC technology, thermal stress caused by the difference in thermal expansion coefficients between metal materials and silicon in TSV affects the electrical characteristics of adjacent devices, and how to integrate nanosheet ring-gate field effect transistors into three-dimensional integrated circuits to improve performance is a challenge.
Design a three-dimensional integrated chip structure, including a silicon substrate, a silicon via array and a number of nanogate transistors. The through-silicon array is composed of a plurality of array units, each array unit including four through-silicon holes arranged in a rectangular or diamond shape. The nano-gate transistor is arranged in the first and second regions of the array unit, the first region is located in the center of the array unit, and the second region is connected to the first region, close to the through-silicon hole and avoids the stress concentration area.
By embedding through silicon holes in the array of nanogate transistors, metal wiring is shortened, heat output is improved, chip performance is enhanced, and the areas of nanogate transistors are reasonably arranged to avoid stress concentration areas under thermal loads to ensure stable electrical characteristics.
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Figure CN119521782A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional integrated chip structure and an arrangement method thereof, and a chip. Background Art
[0002] 3D-IC (three-dimensional integrated circuit) technology is a semiconductor manufacturing technology that uses TSV (through silicon via), micro bumps, hybrid bonding, etc. to vertically stack multiple chips or wafer layers to achieve higher functional density, lower power consumption and faster data transmission speed. In 3D-IC technology, TSV plays an important role in connecting different chip layers. However, the thermal stress generated by the different thermal expansion coefficients (CTE) between the metal material filled in TSV and silicon will affect the electrical characteristics of adjacent devices.
[0003] Nanosheet gate-all-around field-effect transistors (NSFETs) have become mainstream devices at advanced technology nodes due to their stronger gate control capabilities and larger effective conductive channel widths. However, the key is how to integrate nanosheet gate-all-around field-effect transistors into three-dimensional integrated circuits and maximize the performance of three-dimensional integrated circuits. Summary of the invention
[0004] The object of the present invention is to provide a three-dimensional integrated chip structure and its arrangement method and chip, so as to improve the performance of the three-dimensional integrated circuit.
[0005] In order to solve the above technical problems, the present invention provides a three-dimensional integrated chip structure, comprising:
[0006] Silicon substrate;
[0007] A through silicon via array provided in the silicon substrate, the through silicon via array having at least one array unit, the array unit including four through silicon vias arranged in a rectangular or diamond shape;
[0008] A plurality of nano-ring gate transistors are provided in the silicon substrate, and the plurality of nano-ring gate transistors are arranged in a first area and a second area of the array unit, wherein the first area is located in a central area of the array unit, the second area is connected to the first area, the second area is close to the through silicon via and avoids a stress concentration area of an adjacent through silicon via under a preset thermal load, and electrical characteristic fluctuations of the nano-ring gate transistors in the first area and the second area are less than or equal to a preset range.
[0009] Optionally, the nano-ring gate transistor includes an N-type nano-ring gate transistor and a P-type nano-ring gate transistor with the same orientation, and the N-type nano-ring gate transistor and the P-type nano-ring gate transistor are arranged in the first region and / or the second region.
[0010] Optionally, the P-type nano-ring gate transistor is arranged in the first region, and the N-type nano-ring gate transistor is arranged in the second region and the remaining area of the first region.
[0011] Optionally, the array units are arranged in a square shape, the first area is a square area located at the center of the array units, and the second area is a round-shaped area surrounding the first area.
[0012] Optionally, the array units are arranged in a diamond shape, the first region is a diamond region located at the center of the array unit, the second region extends from each side of the first region to between adjacent through silicon vias, and the first region and the second region form an X shape.
[0013] According to another aspect of the present invention, a method for arranging a three-dimensional integrated chip structure is also provided, comprising:
[0014] Providing a silicon substrate having a through silicon via array, wherein the through silicon via array has at least one array unit, and the array unit includes four through silicon vias arranged in a rectangular or diamond shape;
[0015] Setting a thermal load parameter to obtain a stress distribution in a region around each through silicon via on the silicon substrate under the thermal load, wherein the stress distribution includes stress components arranged along an orthogonal first direction and a second direction;
[0016] Disposing a plurality of nano-ring-gate transistors in the area surrounding each of the through silicon vias to obtain stress components of the nano-ring-gate transistors at various positions under the stress distribution;
[0017] Obtaining electrical characteristic fluctuations of each of the nano-ring-gate transistors relative to a nano-ring-gate transistor to which no stress is applied, according to each of the stress components of each of the nano-ring-gate transistors;
[0018] A preset range is set, and an area where the electrical characteristic fluctuation of the nano-ring gate transistor is less than or equal to the preset range is set as an arrangement area of the nano-ring gate transistor in the silicon substrate, wherein the arrangement area includes a first area and a second area, wherein the first area is located in a central area of the array unit, the second area is connected to the first area, and the second area is close to the through silicon via.
[0019] Optionally, the nano-ring gate transistor includes an N-type nano-ring gate transistor and a P-type nano-ring gate transistor, and a first layout area of the N-type nano-ring gate transistor and a second layout area of the P-type nano-ring gate transistor are obtained, and an overlapping area of the first layout area and the second layout area is used as the layout area.
[0020] Optionally, after obtaining the stress distribution of the area around each silicon via under the thermal load, the mobility distribution of N-type carriers and P-type carriers of the silicon substrate is obtained according to the stress distribution, and the nano-ring gate transistor is set in the area around each silicon via according to the mobility distribution.
[0021] Optionally, the ratio of the sum of the areas of the first region and the second region to the area covered by the array unit is calculated, and the size of the array unit is optimized to obtain the largest possible ratio while satisfying other conditions.
[0022] According to another aspect of the present invention, a chip is also provided, comprising the three-dimensional integrated chip structure as described above.
[0023] In summary, the present invention provides a three-dimensional integrated chip structure and its arrangement method, chip, and electronic device. The chip structure includes a silicon substrate; a through silicon via array provided in the silicon substrate, the through silicon via array has at least one array unit, and the array unit includes four through silicon vias arranged in a rectangle or a diamond shape; a plurality of nano-ring gate transistors provided in the silicon substrate, the plurality of nano-ring gate transistors are arranged in a first area and a second area of the array unit, the first area is located in the central area of the array unit, the second area is connected to the first area, the second area is close to the through silicon via and avoids the stress concentration area of the adjacent through silicon via under a preset thermal load, and the electrical characteristic fluctuations of the nano-ring gate transistors in the first area and the second area are less than or equal to a preset range. Compared with the related art in which TSVs are arranged at the periphery of the array of nano-ring-gate transistors, in the present invention, a TSV array including a plurality of array units is arranged in a silicon substrate, and the nano-ring-gate transistors are arranged between the TSVs of the array units. In other words, the TSVs are embedded in the arrangement method of the array of nano-ring-gate transistors, which can shorten the metal wiring (interconnection lines) and is also beneficial for extracting heat from the inside of the array of nano-ring-gate transistors, thereby improving the performance of the chip. By reasonably arranging the arrangement area of the nano-ring-gate transistors in the array units to avoid the stress concentration area of the TSVs under a preset thermal load, the nano-ring-gate transistors in the arrangement area are made less than or equal to a preset range, thereby ensuring the stable performance of the nano-ring-gate transistors in the three-dimensional integrated chip structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0025] Figure 1 is a flow chart of a method for arranging a three-dimensional integrated chip structure provided in an embodiment of the present application;
[0026] Figure 2a to Figure 2e This is a schematic diagram corresponding to the corresponding steps of the method for arranging a three-dimensional integrated chip structure provided in this embodiment.
[0027] In the attached figure:
[0028] 10-silicon substrate; 11-through silicon via; 12-nano-ring gate transistor; 13-layout area; 13a-first area; 13b-second area; Z-first direction; Y-second direction. DETAILED DESCRIPTION
[0029] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0030] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0031] An embodiment of the present application provides a method for arranging a three-dimensional integrated chip structure.
[0032] Figure 1 It is a flow chart of a method for arranging a three-dimensional integrated chip structure provided in an embodiment of the present application.
[0033] like Figure 1 As shown, the arrangement method of the three-dimensional integrated chip structure provided in this embodiment includes:
[0034] S01: providing a silicon substrate having a through silicon via array, wherein the through silicon via array has at least one array unit, and the array unit includes four through silicon vias arranged in a rectangular or diamond shape;
[0035] S02: Setting a thermal load parameter, obtaining a stress distribution in a region around each through silicon via on the silicon substrate under the thermal load, and stress components of the stress distribution set along an orthogonal first direction and a second direction;
[0036] S03: disposing a plurality of nano-ring-gate transistors in the area around each of the through silicon vias, and obtaining stress components of the nano-ring-gate transistors at various positions under the stress distribution;
[0037] S04: obtaining electrical characteristic fluctuations of each of the nano-ring-gate transistors relative to a nano-ring-gate transistor to which no stress is applied, according to each stress component of each of the nano-ring-gate transistors;
[0038] S05: Setting a preset range, and setting a region where the electrical characteristic fluctuation of the nano-ring gate transistor is less than or equal to the preset range as a layout region of the nano-ring gate transistor in the silicon substrate, wherein the layout region includes a first region and a second region, wherein the first region is located in a central region of the array unit, the second region is connected to the first region, and the second region is close to the through silicon via.
[0039] Figure 2a to Figure 2e The schematic diagram corresponding to the corresponding steps of the arrangement method of the three-dimensional integrated chip structure provided in this embodiment is shown in FIG. Figure 2a to Figure 2e The arrangement method of the three-dimensional integrated chip structure is described in detail.
[0040] First, please refer to Figure 2a , performing step S01, providing a silicon substrate 10 having an array of through silicon vias 11, the array of through silicon vias 11 having at least one array unit, and the array unit includes four through silicon vias 11 arranged in a rectangular or diamond shape.
[0041] The material of the silicon substrate 10 may be any suitable single crystal silicon, and the structure of the silicon through via 11 in the silicon substrate 10 may include a silicon oxide layer, a metal barrier layer and a metal filling layer arranged in sequence. In the present embodiment, the conductive material of the silicon through via 11 is copper, that is, the material of the metal filling layer includes copper, and the material of the metal barrier layer may be tantalum nitride. Among them, the silicon through via 11 array may be composed of a plurality of array units, and the nano-ring gate transistor 12 is arranged in the silicon through via 11 array (arranged between the silicon through vias 11 of the array unit). In other words, a plurality of silicon through vias 11 are embedded in the array of the nano-ring gate transistor 12. Compared with the arrangement method of arranging the silicon through via 11 at the periphery of the array of the nano-ring gate transistor 12 in the related art, the arrangement method of arranging the silicon through via 11 in the array of the nano-ring gate transistor 12 in the present embodiment can not only shorten the metal wiring (interconnection line), but also facilitate the heat extraction from the inside of the array of the nano-ring gate transistor 12.
[0042] During specific implementation, simulation software (emulation software) can be used to model and simulate the arrangement method in this embodiment to obtain the corresponding arrangement area 13, and then the above-mentioned arrangement area 13 can be verified in the actual silicon substrate 10. Among them, the relevant parameters of the silicon substrate 10 and the array unit in the software can be referred to the actual needs. In this embodiment, the thickness of the silicon substrate 10 (the height of the silicon via 11) can be 30 microns, the radius of the silicon via 11 is 2.5 microns, the thickness of the silicon oxide layer in the silicon via 11 is 125 nanometers, the thickness of the tantalum nitride layer is 50 nanometers, the spacing between adjacent silicon vias 11 is 15 microns, and the four silicon vias 11 in the array unit are arranged in a rhombus with an angle of 90° (the connecting line of the silicon via 11 is 45° with the first direction Z or the second direction Y, and the first direction Z is orthogonal to the second direction Y). Of course, under the premise of meeting the setting density of the silicon via 11, it is also feasible to arrange the four silicon vias 11 in the array unit in other structures (such as square).
[0043] Next, please refer to Figure 2b , execute step S02, set the thermal load parameters, obtain the stress distribution of the area around each silicon through via 11 on the silicon substrate 10 under the thermal load, and the stress components of the stress distribution set along the orthogonal first direction Z and second direction Y.
[0044] The heat load parameters (e.g., 250°C) can be set according to actual needs, and the heat load parameters, various parameters of the silicon substrate 10 and the silicon through via 11 are input into the simulation software for simulation, so as to obtain the stress distribution of the area around each silicon through via 11 on the silicon substrate 10 under the heat load. The silicon substrate 10 area around each silicon through via 11 has a similar stress distribution. Since the silicon substrate 10 is a single crystal structure (cubic structure), the silicon substrate 10 area around the silicon through via 11 has different stress performances in two orthogonal directions (first direction Z and second direction Y). Figure 2b The partial stress distribution diagram shown in the dotted box shows that the stress along the first direction Z is greater than 0, and the stress along the second direction Y is less than 0, wherein, in terms of the distance relative to the center of the through silicon via 11, the absolute value of the stress of the silicon substrate 10 region closer to the through silicon via 11 is greater, and thus, in terms of the circumference of the through silicon via 11, the closer to the first direction Z or the second direction Y (the smaller the angle with the first direction Z or the second direction Y), the greater the absolute value of the stress of the silicon substrate 10 region.
[0045] Next, please refer to Figure 2c , executing step S03, setting a plurality of nano-ring gate transistors 12 in the area around each through silicon via 11, and obtaining various stress components of the nano-ring gate transistors 12 at various positions under stress distribution.
[0046] According to the design requirements, a nano-ring gate transistor 12 model can be established to obtain the size of the nano-ring gate transistor 12, and then the average stress of the area occupied by the nano-ring gate transistor 12 in the stress distribution at different positions is obtained as the stress of the nano-ring gate transistor 12 at the position. Among them, the stress of the nano-ring gate transistor 12 in multiple directions can be decomposed (simplified) into a first component along the first direction Z and a second component along the second direction Y for easy calculation. Moreover, all the above nano-ring gate transistors 12 can have the same orientation, that is, the channels of the nano-ring gate transistors 12 are arranged along the same direction (for example, 110 crystal direction).
[0047] In such Figure 2c In the example of the embodiment, the nano-ring gate transistors 12 are arranged in an array (e.g., a square array, with an interval of, for example, 100 nanometers to 500 nanometers) from the center of the array unit to the area around the through silicon via 11, and the nano-ring gate transistors 12 that are too close to the through silicon via 11 are excluded. In other examples of this embodiment, the nano-ring gate transistors 12 in the area around the through silicon via 11 have different intervals, for example, the nano-ring gate transistors 12 near the through silicon via 11 have a first interval, and the nano-ring gate transistors 12 far from the through silicon via 11 have a second interval, and the second interval is greater than the first interval. By arranging nano-ring gate transistors 12 with different intervals in different areas, both the accuracy and the amount of calculation of the test can be taken into account. In a preferred example, after obtaining the stress distribution of the area around each silicon via 11 under thermal load and before setting a plurality of nano-ring gate transistors 12 in the area around the silicon via 11, the mobility distribution of N-type carriers (electrons) and P-type carriers (holes) of the silicon substrate 10 can be obtained according to the stress distribution, and a plurality of nano-ring gate transistors 12 can be set in the area around each silicon via 11 according to the mobility distribution.
[0048] Next, step S04 is performed to obtain the electrical characteristic fluctuation of each nano-ring gate transistor relative to a nano-ring gate transistor to which no stress is applied, according to each stress component of each nano-ring gate transistor.
[0049] The stress components (first component and second component) at different positions are applied to the channel of the nano-ring-gate transistor model, and combined with carrier models such as drift-diffusion transport, mobility, Fermi statistics, and embedded stress models of stress and channel interaction, and the factor model is used to integrate (integrate) the above-mentioned influencing factors, so as to obtain the electrical characteristics of the nano-ring-gate transistor at each position, including Ioff (off-state current), Idsat (saturated drain current) and Vth (threshold voltage), etc. The electrical characteristics of the nano-ring-gate transistor at different positions are combined with the standard electrical characteristics of the nano-ring-gate transistor under an ideal state (stress is 0) to obtain the electrical characteristic fluctuations of each nano-ring-gate transistor, that is, the difference (absolute value) between the electrical characteristics of the nano-ring-gate transistor at different positions and the corresponding standard electrical characteristics divided by the standard electrical characteristics is used as the electrical characteristic fluctuations. In addition, since the stress in the centermost area of the array unit is relatively low (close to 0), the difference (absolute value) between the electrical characteristics of the nano-ring gate transistors at different positions and the electrical characteristics of the nano-ring gate transistor at the centermost position divided by the electrical characteristics of the nano-ring gate transistor at the centermost position can also be used as the electrical characteristics fluctuation.
[0050] Since carriers of different electrical properties behave differently in the silicon substrate, the electrical characteristic fluctuations at different locations can be calculated using N-type carriers and P-type carriers respectively. In other words, models of N-type nano-ring gate transistors and P-type nano-ring gate transistors can be established respectively to obtain the electrical characteristic fluctuations of transistors of the two conductive types at different locations.
[0051] Next, step S05 is executed to set a preset range, and the area where the electrical characteristic fluctuation of the nano-ring gate transistor 12 is less than or equal to the preset range is set as the layout area 13 of the nano-ring gate transistor 12 in the silicon substrate 10, and the layout area 13 includes a first area 13a and a second area 13b, the first area 13a is located in the central area of the array unit, the second area 13b is connected to the first area 13a, and the second area 13b is close to the silicon through hole 11.
[0052] A preset range can be set according to design requirements, and the area in the array unit where the electrical characteristic fluctuation of the nano-ring gate transistor 12 is less than or equal to the preset range is set as the arrangement area 13 for arranging the nano-ring gate transistor 12. In other words, the silicon substrate 10 area outside the arrangement area 13 is the stress concentration area. Figure 2dAs shown, the TSVs 11 in the array unit may be arranged in a rhombus with an angle of 90°. According to the distance relative to the TSVs 11, the arrangement area 13 may be divided into a first area 13a and a second area 13b. The first area 13a is an area in the arrangement area 13 located near the center of the array unit, and the second area 13b is an area in the arrangement area 13 close to the TSVs 11 (far away from the center of the array unit). The first area 13a may be a rhombus area (second rhombus) located at the center of the array unit, and the second area 13b is composed of four rectangular areas extending from the sides of the first area 13a to adjacent TSVs 11, and the first area 13a and the second area 13b form an X-shape. Of course, the arrangement area 13 divided by the fluctuation of electrical characteristics is only roughly X-shaped, not a standard (absolute) X-shape, and the range covered by its edge is larger (slightly larger) than the first area 13a and the second area 13b. In other examples of this embodiment, according to the corresponding parameters of the silicon through via 11, the silicon substrate 10, the preset heat load, the preset range, etc., the shape and size of the first area 13a and the second area 13b also change accordingly. For example, the side length of the first area 13a is greater than or less than the side corresponding to the above-mentioned side length in the second area 13b.
[0053] In addition, in other examples of this embodiment, Figure 2e As shown, the TSVs 11 in the array unit may be arranged in a square shape (first square shape), and the arrangement area 13 may be divided into a first area 13a and a second area 13b according to the distance relative to the TSVs 11. The first area 13a may be a square area (second square shape) located at the center of the array unit, and the second area 13b may be a third area with the round-shaped area surrounding the first area 13a, the first area 13a and the second area 13b. Of course, the arrangement area 13 divided by the fluctuation of electrical characteristics is only roughly square, not a standard (absolute) X-shape, and the range covered by its edge is larger (slightly larger) than the first area 13a and the second area 13b.
[0054] It should be noted that the ratio of the sum of the areas of the first region and the second region to the area covered by the array unit (the area of the figure formed by the center lines of the silicon vias) can also be calculated, and the size and shape of the array unit can be optimized to make the above ratio as large as possible while meeting other conditions, so as to improve area utilization.
[0055] The embodiment of the present application also provides a three-dimensional integrated chip structure.
[0056] Figure 2d This is a schematic diagram of the structure of a three-dimensional integrated chip provided in this embodiment.
[0057] like Figure 2dAs shown, the three-dimensional integrated chip structure provided in this embodiment includes a silicon substrate, a through silicon via array and a nano-ring gate transistor. The through silicon via array is arranged in the silicon substrate, and the through silicon via array has at least one array unit, and the array unit includes four through silicon vias arranged in a rectangular or diamond shape. A plurality of nano-ring gate transistors are arranged in the silicon substrate, and the plurality of nano-ring gate transistors are arranged in the first area and the second area of the array unit, the first area is located in the central area of the array unit, the second area is connected to the first area, the second area is close to the through silicon via and avoids the stress concentration area of the adjacent through silicon via under thermal load, and the electrical characteristic fluctuation of the nano-ring gate transistor in the first area and the second area is less than or equal to the preset range.
[0058] The material of the silicon substrate may be any suitable single crystal silicon, and the structure of the silicon via in the silicon substrate may include a silicon oxide layer, a metal barrier layer and a metal filling layer arranged in sequence. In the present embodiment, the conductive material of the silicon via is copper, that is, the material of the metal filling layer includes copper, and the material of the metal barrier layer may be tantalum nitride. Among them, the silicon via array may be composed of a plurality of array units, and the nano-ring gate transistor is arranged in the silicon via array (arranged between the silicon vias of the array unit). In other words, a plurality of silicon vias are embedded in the array of nano-ring gate transistors. Compared with the arrangement method of arranging the silicon vias at the periphery of the array of nano-ring gate transistors in the related art, the arrangement method of arranging the silicon vias at the array of nano-ring gate transistors in the present embodiment can not only shorten the metal wiring (interconnection line), but also facilitate the heat extraction from the inside of the array of nano-ring gate transistors.
[0059] A plurality of the above chip structures are stacked vertically and packaged into a chip, and the device units (including nano-ring gate transistors) in the upper and lower chip structures are electrically connected by silicon vias. The size of the silicon vias can be set according to the electrical requirements and heat dissipation requirements during vertical stacking, and on the premise of meeting the above requirements, the size of the silicon vias can be minimized to reduce stress (i.e., avoid stress concentration areas of adjacent silicon vias under thermal load) and improve area utilization. The density requirement for silicon vias during chip stacking will determine the size of the array unit. On the premise that the arrangement density of the silicon vias is determined, this embodiment can maximize the area of the arrangement area of the nano-ring gate transistor by arranging the four silicon vias in the array unit in a rectangular or diamond shape. Under a preset thermal load, the electrical characteristic fluctuation of the nano-ring gate transistor in the above-mentioned arrangement area is less than or equal to a preset range. The above-mentioned electrical characteristic fluctuation may be the difference between the maximum value and the minimum value of the electrical characteristic of the nano-ring gate transistor in the arrangement area. Since the stress in the centralmost area of the array unit is relatively low (close to 0), the above-mentioned electrical characteristic fluctuation may also be regarded as the difference in electrical characteristics of nano-ring gate transistors at different positions (different stresses) relative to an ideal nano-ring gate transistor (the stress of the substrate is 0).
[0060] In one example, if Figure 2dAs shown, the height of the through silicon via 11 (the thickness of the silicon substrate 10) can be 30 microns, the radius of the through silicon via 11 is 2.5 microns, the thickness of the silicon oxide layer in the through silicon via 11 is 125 nanometers, the thickness of the tantalum nitride layer is 50 nanometers, the array unit can be arranged in a first rhombus with an angle of 90°, the spacing between adjacent through silicon vias 11 is 15 microns, and under the conditions of a heat load of 250°C and a preset range of 10% (i.e., the fluctuation of the electrical characteristics is less than or equal to 10%), the first area 13a is located in the central area of the array unit and is in a second rhombus parallel to the corresponding sides of the array unit, the second area 13b extends from the sides of the first area 13a to between the adjacent through silicon vias 11, and the first area 13a and the second area 13b form an X-shape.
[0061] In another example, if Figure 2e As shown, the various configurations of the through silicon via 11 are similar to Figure 2a Similar to the above, the array unit may be arranged in a first square, the spacing between adjacent through silicon vias 11 is 15 microns, and under the conditions of a heat load of 250°C and a preset range of 10% (i.e., the electrical characteristic fluctuation is less than or equal to 10%), the first area 13a is located in the central area of the array unit and is in a second square parallel to each corresponding side of the array unit, the second area 13b is a round-shaped area surrounding the first area 13a, and the first area 13a and the second area 13b constitute a third square.
[0062] It should be noted that, in this embodiment, the nano-ring gate transistor may include an N-type nano-ring gate transistor and a P-type nano-ring gate transistor, and the above-mentioned N-type nano-ring gate transistor and the P-type nano-ring gate transistor have the same orientation, that is, the channel extension direction of the two is the same on the silicon substrate, and the two can be arranged in the above-mentioned first area and / or the second area. In a preferred example, since the P-type nano-ring gate transistor is more sensitive to stress than the N-type nano-ring gate transistor, the P-type nano-ring gate transistor can be arranged in the first area (far away from the silicon through hole), and the N-type nano-ring gate transistor is arranged in the second area and the remaining areas in the first area. On the other hand, the nano-ring gate transistor may include a first nano-ring gate transistor and a second nano-ring gate transistor, and the electrical characteristic requirement (fluctuation limit) of the first nano-ring gate transistor is higher than the electrical characteristic requirement (fluctuation limit) of the second nano-ring gate transistor. The first nano-ring gate transistor may be preferentially arranged in the first area, and the second nano-ring gate transistor may be arranged in the remaining areas in the first area and the second area. In one example, the electrical characteristic requirement of the first nano-ring gate transistor includes leakage current.
[0063] The present application also provides a chip, which includes the above-mentioned three-dimensional integrated chip structure, that is, the chip includes at least two layers of the above-mentioned three-dimensional integrated chip structure stacked vertically.
[0064] In summary, the present invention provides a three-dimensional integrated chip structure and its arrangement method, chip, and electronic device. The chip structure includes a silicon substrate; a through silicon via array provided in the silicon substrate, the through silicon via array has at least one array unit, and the array unit includes four through silicon vias arranged in a rectangle or a diamond shape; a plurality of nano-ring gate transistors provided in the silicon substrate, the plurality of nano-ring gate transistors are arranged in a first area and a second area of the array unit, the first area is located in the central area of the array unit, the second area is connected to the first area, the second area is close to the through silicon via and avoids the stress concentration area of the adjacent through silicon via under a preset thermal load, and the electrical characteristic fluctuations of the nano-ring gate transistors in the first area and the second area are less than or equal to a preset range. Compared with the related art in which TSVs are arranged at the periphery of the array of nano-ring-gate transistors, in the present invention, a TSV array including a plurality of array units is arranged in a silicon substrate, and the nano-ring-gate transistors are arranged between the TSVs of the array units. In other words, the TSVs are embedded in the arrangement method of the array of nano-ring-gate transistors, which can shorten the metal wiring (interconnection lines) and is also beneficial for extracting heat from the inside of the array of nano-ring-gate transistors, thereby improving the performance of the chip. By reasonably arranging the arrangement area of the nano-ring-gate transistors in the array units to avoid the stress concentration area of the TSVs under a preset thermal load, the nano-ring-gate transistors in the arrangement area are made less than or equal to a preset range, thereby ensuring the stable performance of the nano-ring-gate transistors in the three-dimensional integrated chip structure.
[0065] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A three-dimensional integrated chip structure, characterized in that: include: Silicon substrate; A through silicon via array provided in the silicon substrate, the through silicon via array having at least one array unit, the array unit including four through silicon vias arranged in a rectangular or diamond shape; A plurality of nano-ring gate transistors are provided in the silicon substrate, and the plurality of nano-ring gate transistors are arranged in a first area and a second area of the array unit, wherein the first area is located in a central area of the array unit, the second area is connected to the first area, the second area is close to the through silicon via and avoids a stress concentration area of an adjacent through silicon via under a preset thermal load, and electrical characteristic fluctuations of the nano-ring gate transistors in the first area and the second area are less than or equal to a preset range.
2. The three-dimensional integrated chip structure according to claim 1, characterized in that: The nano-ring gate transistor comprises an N-type nano-ring gate transistor and a P-type nano-ring gate transistor in the same orientation, and the N-type nano-ring gate transistor and the P-type nano-ring gate transistor are arranged in the first region and / or the second region.
3. The three-dimensional integrated chip structure according to claim 2, characterized in that: The P-type nano-ring gate transistor is disposed in the first region, and the N-type nano-ring gate transistor is disposed in the second region and the remaining area of the first region.
4. The three-dimensional integrated chip structure according to claim 1, characterized in that: The array units are arranged in a square shape, the first area is a square area located at the center of the array units, and the second area is a round-shaped area surrounding the first area.
5. The three-dimensional integrated chip structure according to claim 1, characterized in that: The array units are arranged in a diamond shape, the first area is a diamond area located at the center of the array unit, the second area extends from each side of the first area to between adjacent silicon through vias, and the first area and the second area form an X shape.
6. A method for arranging a three-dimensional integrated chip structure, characterized in that: include: Providing a silicon substrate having a through silicon via array, wherein the through silicon via array has at least one array unit, and the array unit includes four through silicon vias arranged in a rectangular or diamond shape; Setting a thermal load parameter to obtain a stress distribution in a region around each through silicon via on the silicon substrate under the thermal load, wherein the stress distribution includes stress components arranged along an orthogonal first direction and a second direction; Disposing a plurality of nano-ring-gate transistors in the area surrounding each of the through silicon vias to obtain stress components of the nano-ring-gate transistors at various positions under the stress distribution; Obtaining electrical characteristic fluctuations of each of the nano-ring-gate transistors relative to a nano-ring-gate transistor to which no stress is applied, according to each of the stress components of each of the nano-ring-gate transistors; A preset range is set, and an area where the electrical characteristic fluctuation of the nano-ring gate transistor is less than or equal to the preset range is set as an arrangement area of the nano-ring gate transistor in the silicon substrate, wherein the arrangement area includes a first area and a second area, wherein the first area is located in a central area of the array unit, the second area is connected to the first area, and the second area is close to the through silicon via.
7. The method for arranging a three-dimensional integrated chip structure according to claim 6, characterized in that: The nano-ring gate transistor includes an N-type nano-ring gate transistor and a P-type nano-ring gate transistor, a first arrangement area of the N-type nano-ring gate transistor and a second arrangement area of the P-type nano-ring gate transistor are obtained, and an overlapping area of the first arrangement area and the second arrangement area is used as the arrangement area.
8. The method for arranging a three-dimensional integrated chip structure according to claim 6, characterized in that: After obtaining the stress distribution of the area around each silicon via under the thermal load, the mobility distribution of N-type carriers and P-type carriers of the silicon substrate is obtained according to the stress distribution, and the nano-ring gate transistor is set in the area around each silicon via according to the mobility distribution.
9. The method for arranging a three-dimensional integrated chip structure according to claim 6, characterized in that: The ratio of the sum of the areas of the first region and the second region to the area covered by the array unit is calculated, and the size of the array unit is optimized to obtain the largest possible ratio while satisfying other conditions.
10. A chip, characterized in that: Comprising the three-dimensional integrated chip structure as claimed in any one of claims 1 to 5.