Image sensor

Abstract

The invention discloses an image sensor. The present disclosure relates to an image sensor comprising a plurality of pixels (100), each pixel comprising an unpinned photodiode (101) connected by a metal connection element (103) to a pinned region (105) formed in a first semiconductor substrate.

Description

Technical Field

[0001] The present specification relates generally to the field of electronic devices, and more particularly to image sensors and image sensor pixels. Background Art

[0002] Among the pixels used in existing image sensors, pixels have been proposed that include a non-pinned photodiode, combined with a so-called "3T" readout circuit including three MOS (Metal Oxide Semiconductor) transistors. These circuits typically include a MOS transistor for resetting the photosensitive node, a MOS follower transistor, and a MOS transistor for selecting the pixel. The photosensitive node of the pixel (which corresponds to the cathode of the photodiode) is connected to the conduction electrode of the reset MOS transistor and the gate of the follower MOS transistor, while the conduction electrode of the selection MOS transistor is connected to the conduction electrode of the follower MOS transistor and the column conductive track of the image sensor, respectively. The voltage of the photosensitive node is first initialized in the reset phase. During the subsequent exposure phase, the photosensitive node undergoes a voltage drift caused by the current generated by the photodiode, which is proportional to the incident luminous flux. At the end of the exposure phase, the voltage present at the photosensitive node (from which the reset voltage is subtracted and therefore substantially corresponds to the light signal integrated by the pixel) is copied back to the image sensor column (within the gate-source voltage) for subsequent reading and processing at the column foot. One disadvantage of this type of pixel is that the value of the reset voltage is parasitized by sampling noise or kTC noise. Since the parasitic voltage is not correlated with the voltage present at the photosensitive node at the end of the exposure phase, the value of the signal read by the readout circuit is contaminated by kTC noise. This has an adverse effect on the quality of the image acquired by the sensor.

[0003] Furthermore, pixels of depth image sensors comprising non-pinned photodiodes combined with 3T-type readout circuits have been proposed for indirect Time-of-Flight (iToF) distance measurements. These depth pixels implement a sampling function that allows the distance between the sensor and the object to be imaged in the scene to be determined. The use of non-pinned photodiodes in this type of application means sampling the current generated by the photodiode. This has many disadvantages, such as parasitic coupling, loss of the operating point of the structure (e.g., loss of photodiode bias voltage, loss of signal, etc.), degraded frequency response, noisy sampled values, etc. This distorts the depth measurement of the image sensor and leads to results that are difficult to use.

[0004] In an attempt to overcome these various disadvantages, image sensor pixels have been proposed that include a pinned photodiode (PPD) in combination with a so-called 4T readout circuit that includes four MOS transistors. The pinned photodiode of these pixels typically includes an N-type doped semiconductor region formed in a P-type doped semiconductor substrate and is connected to the P-type semiconductor substrate by a thin, highly doped P-type semiconductor layer (P + Layer) is separated from the top surface of the substrate. In addition, in these pixels, in addition to the MOS transistors described above for the 3T readout circuit, the readout circuit includes an additional MOS charge transfer transistor. In this case, the readout circuit of the pixel includes an intermediate storage node or sensing node, which is inserted between the photosensitive node and the gate of the follower MOS transistor. The photosensitive node is thus separated from the sensing node so that the sensing node can be used as a charge storage node. At the end of the exposure phase, during which the photosensitive node integrates and converts the incident luminous flux into a charge packet, the sensing node is first reset to a reset voltage, which is read and stored at the column foot. The subsequent transfer phase then allows the charge packet from the photosensitive node to be transferred to the sensing node. The resulting signal voltage is then read in sequence and stored at the column foot. The reset voltage and the signal voltage are therefore related. By subtracting the reset voltage from the signal voltage, the kTC noise is eliminated, resulting in a noise-free image.

[0005] However, implementing a pinned photodiode associated with a 4T readout circuit may prove difficult or even impossible, for example due to constraints associated with the materials or fabrication methods used to form the photodiode. Summary of the invention

[0006] There is a need to overcome some or all of the disadvantages of existing image sensor pixels or pictures. In particular, there is a need to overcome the disadvantages associated with using image sensor pixels that include non-pinned photodiodes or photodiodes.

[0007] To this end, one embodiment provides an image sensor including a plurality of pixels, each pixel including a non-pinned photodiode connected to a pinning region formed in a first semiconductor substrate through a metal connection element.

[0008] According to one embodiment, a non-pinned photodiode includes a P-type doped anode semiconductor region and an N-type doped cathode semiconductor region.

[0009] According to one embodiment, the anode semiconductor region and the cathode semiconductor region of the non-pinned photodiode are bonded.

[0010] According to one embodiment, the non-pinned photodiode is formed on a second semiconductor substrate different from the first substrate.

[0011] According to one embodiment, a non-pinned photodiode is hybridized to a first substrate, the first substrate being made of silicon.

[0012] According to one embodiment, the metal connection elements include conductive tracks, conductive vias and / or contact pickup elements formed in first and second interconnect stacks located on the first and second substrates, respectively.

[0013] According to one embodiment, the pinning region includes a first N-type doped semiconductor region formed in a first substrate, the first substrate being P-type doped.

[0014] According to one embodiment, the second P-type doped semiconductor region formed in the first substrate is interposed between the top surface of the first substrate and the first semiconductor region.

[0015] According to one embodiment, the second semiconductor region has a higher doping level than the first substrate.

[0016] According to one embodiment, the metal connection element is in contact with a third N-type doped semiconductor region extending vertically from a top surface of the first substrate through the thickness of the first substrate.

[0017] According to one embodiment, the first semiconductor region penetrates into the third semiconductor region.

[0018] According to one embodiment, each pixel further comprises a transistor connected between the metal connection element and the pinned region.

[0019] According to one embodiment, the pixel further comprises:

[0020] - at least one first photosensitive region formed in a first substrate and adapted to collect light in a first wavelength range;

[0021] - a fourth semiconductor region formed in the first substrate aligned with the at least one photosensitive region, wherein a pinning region is formed;

[0022] - at least one charge collection region arranged on a side of the second substrate opposite to the at least one first photosensitive region;

[0023] - at least one transfer region extending from at least one first photosensitive region to at least one charge collection region; and

[0024] - at least one transfer gate extending vertically between the at least one transfer region and the fourth semiconductor region and laterally adjoining the at least one transfer region.

[0025] According to one embodiment, the non-pinned photodiode is adapted to capture light in a second wavelength range different from the first wavelength range.

[0026] According to one embodiment, the pixel further comprises at least one further transfer gate and at least one further charge collecting region, the at least one further transfer gate extending laterally on the side of the first substrate opposite to the at least one first photosensitive region.

[0027] According to one embodiment, the pinned region is not intended to be subjected to incident light radiation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0029] Figure 1 An example pixel of an image sensor according to one embodiment is schematically and partially shown;

[0030] Figure 2 According to an embodiment Figure 1 A partial schematic side view and cross-sectional view of an example of a pinning region of the illustrated pixel;

[0031] Figure 3 is a schematic, partial side view and cross-sectional view of an example image sensor according to one embodiment;

[0032] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a diagram showing a method according to an embodiment Figure 1 A diagram of the operation steps of the pixel shown;

[0033] Figure 5 It is shown Figure 1 A diagram of alternative operations for the illustrated pixels;

[0034] Fig. 6A and Figure 6B Schematic partial top view and along the image sensor pixel according to one embodiment Fig. 6A A cross-sectional view of the plane BB shown;

[0035] Figure 7 An example image sensor pixel is schematically and partially illustrated according to one embodiment;

[0036] Figure 8 According to an embodiment Figure 7 A partial schematic side view and cross-sectional view of an example pinning region of the illustrated pixel; and

[0037] Fig. 9 is a diagram showing a method according to an embodiment Figure 7 Diagram of the operation steps for the pixel shown. DETAILED DESCRIPTION

[0038] In the various drawings, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0039] For the sake of clarity, only the operations and elements that are helpful for understanding the embodiments described herein are illustrated and described in detail. In particular, readout circuits, or column decoders, control circuits, or row decoders, and applications in which image sensors may be provided are not described in detail, because the described embodiments and variants are compatible with readout circuits and control circuits of conventional image sensors and conventional applications involving image sensors.

[0040] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0041] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or to qualifiers to orientation, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figure.

[0042] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0043] In the following description, "visible light" refers to electromagnetic radiation with a wavelength between 380nm and 780nm, and "infrared radiation" refers to electromagnetic radiation with a wavelength between 780nm and 15μm. In addition, "near infrared radiation" more specifically refers to electromagnetic radiation with a wavelength between 780nm and 1.7μm.

[0044] Figure 1 An example pixel 100 of an image sensor according to one embodiment is shown schematically and partially.

[0045] In the example shown, the pixel 100 includes a photosensitive diode or photodiode 101. The photodiode 101 of the pixel 100 is non-pinned and includes, for example, a P-type doped anode semiconductor region connected to an anode and an N-type doped cathode semiconductor region connected to a cathode. By way of example, the anode semiconductor region and the cathode semiconductor region of the photodiode 101 are joined, wherein the anode region contacts the cathode region and forms a PN junction. Alternatively, the anode semiconductor region and the cathode semiconductor region of the photodiode 101 can be separated from each other, and the photodiode 101 then includes at least one intermediate layer inserted between the anode region and the cathode region, such as an intermediate layer in which a plurality of quantum dots are formed.

[0046] According to one embodiment, non-pinned photodiode 101 of pixel 100 is connected to pinned region 105 via metal connection element 103. More specifically, in the example shown, node 104 corresponding to, for example, the cathode of photodiode 101 is connected to pinned region 105 via metal connection element 103. Pinned region 105 is, for example, offset.

[0047] In the example shown, the pinning region 105 is further connected to a readout circuit 107. In the example shown, the readout circuit 107 is of the "4T" type and comprises four MOS transistors:

[0048] a charge transfer MOS transistor 109, one of whose conduction terminals (e.g., source) is connected to the pinning region 105, another of whose conduction terminals (e.g., drain) is connected to the sensing node 110, and a control terminal or gate of which is connected to a node for applying a control voltage TG;

[0049] a reset MOS transistor 111 having one conduction terminal (e.g., source) connected to the sensing node 110, another terminal (e.g., drain) connected to a node for applying a reset voltage VRTRST, and a control terminal or gate connected to a node for applying a control voltage RST;

[0050] a follower MOS transistor 113 having one conduction terminal (e.g., source) connected to an internal node 115 of the readout circuit 107, another conduction terminal (e.g., drain) connected to a node for applying a voltage VRSTF, and a control terminal or gate connected to the sensing node 110; and

[0051] - A selection MOS transistor 117, one conduction terminal of which (eg source) is connected to the column conductive track Vx of the image sensor, another conduction terminal of which (eg drain) is connected to the internal node 115 and a control terminal or gate of which is connected to a node for applying a control voltage RD.

[0052] Optionally, the pixel 100 may further include a circuit 119 including a reset MOS transistor 121 connected to the metal connection element 103, between the photodiode 101 and the pinning region 105. In this case, the MOS transistor 121 includes a conduction terminal (e.g., a source) connected to the metal connection element 103, another conduction terminal (e.g., a drain) connected to a node for applying a reset voltage VRSTPH, and a control terminal or gate connected to a node for applying a control voltage RSTPH.

[0053] The voltages TG, VRTRST, RST, VRSTF, RD, VRSTPH, and RSTPH are, for example, based on a reference potential ( Figure 1 ) as a reference, such as the ground.

[0054] By way of example, the photodiode 101 of the pixel 100 is intended to capture visible light. Alternatively, the photodiode 101 may be intended to capture infrared radiation, such as near infrared radiation. In this case, the pixel 100 may be a depth photosite or a pixel whose photodiode 101 is connected to one or more readout circuits of the type of circuit 107 previously described.

[0055] The operation of pixel 100, and in particular the operation of readout circuitry 107, will be explained in more detail below.

[0056] Figure 2 According to an embodiment Figure 1 Schematic, partial side and cross-sectional views of an example pinning region 105 of a pixel 100 are shown.

[0057] In the example shown, the pinning region 105 is formed in a semiconductor substrate 201, such as a wafer or a wafer made of a semiconductor material such as silicon. In this example, the semiconductor substrate 201 is P-type doped. The semiconductor substrate 201 includes an N-type doped semiconductor region 203. Figure 2 In the orientation shown, region 203 extends laterally below the top surface of substrate 201. By way of example, region 203 has a width between 1.10 10 to 1.10 18 at. / cm 3 between the doping levels.

[0058] In the example shown, a P-type doped semiconductor region 205 is inserted between region 203 and the top surface of substrate 201. Region 205 allows, for example, the surface of substrate 201 to be passivated. For example, region 205 has a higher doping level than substrate 201.

[0059] Furthermore, in the example shown, the metal connection element 103 is connected to a highly N-type doped (N + In the example shown, region 203 penetrates into region 207. Region 207 has, for example, a higher doping level than region 203. For example, the doping level of region 207 is selected so as to enable an optimal electrical connection with metal connection element 103. By way of example, region 207 has a doping level between 1.10 17 to 5.10 20 at. / cm 3 between the doping levels.

[0060] In the example shown, the MOS transfer transistor 109 includes a gate region including an electrically insulating layer 209 interposed between, for example, a conductive layer 211 serving as a gate of the MOS transistor 109 and a top surface of the substrate 201. In the example shown, the gate region extends laterally over regions 203 and 205, wherein the region 203 forms, for example, a source region of the MOS transistor 109, and over another, highly N-type doped semiconductor region 213 forming, for example, a drain region of the MOS transistor 109. The region 213 has, for example, a doping level substantially equal to the doping level of the region 207. The region 213 is laterally separated from the regions 203 and 205 by a portion of the substrate 201.

[0061] In the example shown, a peripheral isolation trench 215, such as a Capacitive Deep Trench Isolation (CDTI) trench, is formed in the semiconductor substrate 201. The peripheral isolation trench has, for example, a ring shape surrounding the regions 203, 205, 207 and 213 when viewed from above.

[0062] exist Figure 2 In the example shown, the pinning region 105 corresponds, for example, to an N-type doped region 203 vertically interposed between a highly P-type doped region 205 and a P-type doped substrate 201. The pinning region 105 has a pinch-off voltage Vp that depends in particular on the doping level, geometry and environment of the semiconductor region 203.

[0063] Pinning region 105 is, for example, formed in a portion of the image sensor that is not exposed to incident radiation intended to be picked up by photodiode 101 of pixel 100. For example, substrate 201 lacks a photosensitive region and pinning region 105 is not intended to experience incident light radiation.

[0064] Figure 3 is a schematic, partial side view and cross-sectional view of an example image sensor 300 according to one embodiment.

[0065] In the example shown, the image sensor 300 includes a plurality of pixels 100. The photodiode 101 of the pixel 100 is, for example, formed on a substrate 301, such as a wafer or a wafer made of, for example, a semiconductor material other than silicon. In the example shown, the photodiode 101 includes two photosensitive layers 303 and 305, for example, which are bonded together to form a PN junction. By way of example, the layers 303 and 305 are made of a material that is sensitive to near-infrared radiation. The layers 303 and 305 are, for example, hybridized to the substrate 201. The layers 303 and 305 correspond, for example, to the anode semiconductor region and the cathode semiconductor region of the photodiode 101, respectively.

[0066] by Figure 3 In the orientation shown, the substrate 301 comprises, on its back side, an interconnect stack 307 consisting of alternating dielectric and conductive layers. Conductive tracks are formed in the conductive layers or in metallization levels, for example, whereby conductive tracks belonging to different layers can be connected to each other by conductive vias.

[0067] In the example shown, substrate 201 (in which pinning region 105 of pixel 100 is formed) is covered by interconnect stack 309, which is similar to interconnect stack 307, for example. Figure 3 In the orientation shown, interconnect stack 309 is in contact with the bottom surface of interconnect stack 307 via its bottom surface. By way of example, interconnect stacks 307 and 309 are in contact with each other and mechanically attached by molecular bonding (e.g., by hybrid molecular bonding). In this case, the contact pickup element flush with the top surface of interconnect stack 309 is, for example, connected to the top surface of interconnect stack 309. Figure 3 The orientation shown places the contact pickup element contacts flush with the bottom surface of the interconnect stack 307 .

[0068] exist Figure 3 In the example shown, the metal connection elements 103 of each pixel 100 include metal conductive tracks, conductive vias and / or contact pickup elements formed, for example, in the interconnect stacks 307 and 309. Figure 3 The metal connection elements 103 are not described in detail in order not to overload the drawing, but their implementation is within the capabilities of a person skilled in the art based on the teachings of this specification.

[0069] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a diagram showing a method according to an embodiment Figure 1 FIG. 1 is a diagram of the operation steps of the pixel 100. More specifically, FIG. 4A to FIG. 4D The variation of the voltage V at different points on the pixel 100 is shown. In particular, Figures 4A to 4D Shown are changes in:

[0070] - a control voltage VPH applied to the node 104;

[0071] - voltage TG applied to the gate of the charge transfer MOS transistor 109;

[0072] - a voltage SN applied to the sensing node 110; and

[0073] - A control voltage RST applied to the gate of the reset MOS transistor 111.

[0074] More specifically, Figure 4A A preliminary step is shown, in which photogenerated charges 401 (here electrons) are accumulated at the node 104 under the effect of the current IPH generated by the photodiode 101, until the voltage VPH present at the node 104 becomes substantially equal to the pinch-off voltage Vp of the pinning region 105. During this step, the charges accumulated at the node 104 fill the potential well formed by the metal connection element 103. However, the charges accumulated at the node 104 during this step are not transferred to the sensing node 110 during subsequent steps.

[0075] To speed up this process, an optional reset MOS transistor 121 can be used to initialize the voltage present at the node 104 to a value close to the value of the pinch-off voltage Vp. The reset voltage VRSTPH can, for example, be slightly higher than the pinch-off voltage Vp. Alternatively, the reset voltage VRSTPH can be lower than the pinch-off voltage Vp, wherein the excess charge accumulated at the node 104 is then discharged in a subsequent reset step.

[0076] Once the potential well formed by the metal connection element 103 is filled, ie once the voltage present at the node 104 is substantially equal to the pinch-off voltage Vp, the photogenerated charges start to accumulate in the pinning region 105 .

[0077] More specifically, Figure 4B A subsequent step is shown for resetting the pinning region 105 and the sensing node 110. During this step, the charge transfer MOS transistor 109 and the reset MOS transistor 111 are controlled to an on state to transfer the photogenerated charges previously accumulated in the pinning region 105 during the previous step to the sensing node 110.

[0078] More specifically, Figure 4C The subsequent exposure step, or exposure phase, is shown. During this step, the charge transfer MOS transistor 109 and the reset MOS transistor 111 are controlled to the off state. The pinned region 105 then acts as a collection area for the charges photogenerated by the photodiode 101 during the exposure step. Since the potential well formed by the metal connection element 103 has previously been Figure 4AIn the step described, charge generated during the exposure step and routed by the current IPH of the photodiode 101 accumulates in the pinning region 105 and causes its voltage to drop from the voltage Vp.

[0079] The amount of charge accumulated in the pinned region 105 is proportional to the photon current IPH generated during the exposure step by the non-pinned photodiode 101. The amount of charge accumulated during this step is therefore proportional to the incident luminescence current to which the photodiode 101 is exposed.

[0080] More specifically, Figure 4D A subsequent charge transfer step is shown. During this step, the charge transfer MOS transistor 109 is controlled in an on state and the charges accumulated in the pinning region 105 during the exposure step are then transferred to the sensing node 110.

[0081] Before the charge transfer is implemented by turning on the charge transfer MOS transistor 109, the sensing node 110 is first initialized to the reset voltage VRTRST and the value of the voltage present at the sensing node 110 is read on the column conductive track Vx and stored at the column foot. The voltage present at the sensing node 110 is then read a second time after the transfer and this value is stored at the column foot. These two consecutive readings of the voltage present at the sensing node 110 enable Correlated Double Sampling (CDS) to be performed, thus allowing the kTC noise and any voltage offset and / or fixed noise in the readout circuit to be eliminated.

[0082] Depending on the incident luminous flux, the voltage read at the sensing node 110 of the pixel 100 has:

[0083] a plateau corresponding to conditions of low illumination (or too short an exposure time) for which the potential well formed by the metal connection element 103 cannot be filled during the preliminary step;

[0084] a linear region, corresponding to the case where during the preliminary step the incident luminous flux is sufficient to completely fill the potential well, then during the exposure step the photogenerated charges can be stored in the pinning region 105 and the conversion of the current IPH into a charge quantity can take place; and

[0085] - Saturation region, corresponding to the situation where the incident luminous current is too large (or the exposure time is too long), the pinning region 105 is then completely filled with charges until it is saturated, or even overflows onto adjacent nodes.

[0086] Figure 5 It is shown Figure 1 FIG. 1 is a diagram of an alternative operation of the pixel 100 shown. More specifically, Figure 5The operation of the pixel 100 in "cascode" mode is shown. Figure 5 The illustrated operation mode corresponds to, for example, a case where the pixel 100 lacks the charge transfer MOS transistor 109 , or a case where the MOS transistor 109 is kept in an on state.

[0087] In this mode of operation, once the potential well formed by the metal connection element 103 has been filled, the charge photogenerated by the photodiode 101 is continuously discharged to the sensing node 110 via the pinned region 105, which in this case acts as a potential barrier. The voltage present across the metal connection element 103 then has a value Vpol that is substantially constant and approximately equal to Vp. The current leaving the pinned region 105 is then substantially equal to the current IPH photogenerated by the photodiode 101. The pinned region 105 thus performs a cascode function, allowing the non-pinned photodiode 101 to be biased by a voltage while transmitting the photon current IPH generated by it to the sensing node 110.

[0088] Fig. 6A is a schematic, partial top view of a pixel 600 of an image sensor according to one embodiment. Figure 6B yes Fig. 6A The pixel 600 is shown along Fig. 6A A cross-sectional view of plane BB is shown.

[0089] In the example shown, the pixel 600 is formed in and on a semiconductor substrate 601, such as a silicon wafer or wafer, in which a photosensitive region 603 is formed. Each photosensitive region 603 extends vertically from a bottom surface 601B of the substrate 601 through the thickness of the semiconductor substrate 601 to a depth less than the thickness of the substrate 601. In the example shown, the pixel 600 includes four photosensitive regions 603. When viewed from above, each photosensitive region 603 has a substantially square periphery. In the example shown, the photosensitive regions 603 are coplanar and are arranged to be substantially square in shape when viewed from above. The photosensitive regions 603 are, for example, formed in a region of the substrate 601 doped with a first type of conductivity (e.g., N-type).

[0090] In the example shown, the pixel 600 also includes a region 605 formed in the semiconductor substrate 601. The region 605 is located in a straight line with the photosensitive region 603 (with a Figure 6BThe orientation shown is above the photosensitive region 603). Region 605 extends vertically through the thickness of semiconductor substrate 601 from top surface 601T of substrate 601 (opposite to bottom surface 601B). When viewed from above, region 605 has a substantially square periphery. In this example, region 605 has a lateral dimension substantially equal to the lateral dimension of the square formed by four photosensitive regions 603. For example, region 105 is formed in a portion of substrate 601 doped with a second conductivity type (in this example, P-type) opposite to the first conductivity type. By way of example, region 605 has a lateral dimension of 1x10 10 Up to 1x10 17 at. / cm 3 In this example, the bottom surface of region 105 is in contact with the top surface of the underlying photosensitive region 603 .

[0091] Each photosensitive region 603 is designed, for example, to collect photons during an illumination phase of the image sensor (of which the pixel 600 is part) and to convert these photons into electron-hole pairs. The photosensitive region 103 is adapted to capture light in a first wavelength range. In the example shown, the region 605 of the pixel 600 is connected to the first region 605 via the metal connection element 103 in a manner similar to that previously described. Figure 1 The pixel 100 described is connected in a similar manner to a photodiode 101. The photodiode 101 is adapted to capture, for example, light in a second wavelength range, which is different from the first wavelength range. The photosensitive area 603 is, for example, intended to capture a 2D image, while the photodiode 101 is, for example, intended to capture a depth image. By way of example, the photosensitive area 603 of the pixel 600 is adapted to capture visible light, such as blue light, and the photodiode 101 of the pixel 600 is adapted to capture infrared radiation, such as near infrared radiation.

[0092] In the example shown, the pixel 600 further comprises a peripheral isolation trench 607, for example a capacitive isolation trench, which laterally delimits the region 605 and the arrangement formed by the photosensitive area 603. More specifically, in this example, the peripheral isolation trench 607 completely surrounds the region 605 and has a substantially square outline when viewed from above.

[0093] Peripheral isolation trench 607 electrically allows photosensitive region 603 and region 605 of pixel 600 to be electrically isolated from each other. Fig. 6A and Figure 6B The adjacent pixels not shown in the figure are isolated. A peripheral isolation trench 607 is formed in the substrate 601. Figure 6B In the orientation shown, the peripheral isolation trench 607 extends vertically through the thickness of the substrate 601 from the top surface 601T of the substrate 601 to the bottom surface 601B of the substrate 601 .

[0094] Despite Fig. 6A and Figure 6BDetailed description is not given in the specification, the peripheral isolation trench 607 includes, for example, a conductive region whose sidewalls are coated with an electrically insulating layer. The electrically insulating layer electrically isolates the conductive region of the trench 607 from the substrate 601. By way of example, the conductive region of the trench 607 is made of polysilicon, a metal (such as copper) or a metal alloy, and the electrically insulating layer of the trench 607 is made of a dielectric material (such as silicon oxide). By way of example, the peripheral isolation trench 607 is a capacitive deep trench isolation (CDTI) trench.

[0095] In the example shown, the photosensitive areas 603 of the pixel 600 are separated from each other by isolation trenches 609, for example capacitive isolation trenches, for example of the CDTI type. In this example, the pixel 600 more precisely comprises an isolation trench 609 which, when viewed from above, has a generally cross-shaped form substantially centered relative to the pixel 600. Figure 6B As shown, the isolation trench 609 extends vertically from the bottom surface 601B of the substrate 601 through the thickness of the semiconductor substrate 601 to the region 605, but does not open on one side of the top surface 601T of the substrate 601. Figure 6B As shown, the isolation trench 609 has a height substantially equal to the thickness of the photosensitive area 603. In the example shown, each photosensitive area 603 is therefore adjoined laterally by a peripheral isolation trench 607 and by an isolation trench 609. By way of example, the trench 609 has a structure similar to the trench 607. More specifically, the trench 609 can, for example, have a conductive area (for example a metal area), or a charged area (for example made of charged polysilicon), the sides of which are coated with an electrically insulating layer. Alternatively, the trench 609 is a charged isolation trench, for example of the DTI (Deep Trench Isolatio) type. In this case, the trench 609 has no conductive area.

[0096] exist Fig. 6A and Figure 6B In the example shown, the pixel 600 further includes four vertical transfer gates 610, each including an isolation trench 611, such as a capacitive isolation trench. In this example, each isolation trench 611 is generally L-shaped when viewed from above. Figure 6B As shown, each isolation trench 611 extends vertically from the top surface 601T of the substrate 601 through the thickness of the semiconductor substrate 601 to one of the photosensitive regions 603, and partially penetrates into the photosensitive region 603 to a depth that is less than the depth of the peripheral isolation trench 607. In other words, each isolation trench 611 is interrupted in the thickness of the substrate 601 and does not open outward on one side of the bottom surface 601B of the substrate 601. By way of example, each isolation trench 611 has a depth between 3 μm and 18 μm.

[0097] In this example, the isolation trenches 611 are located at the four corners of a square formed by the peripheral isolation trenches 607 when viewed from above. More precisely, the isolation trenches 611 are arranged so as to define an area of ​​the substrate 601 that is substantially square when viewed from above. Fig. 6A In the example shown, a portion of the substrate 601 is interposed between the end of the L formed by each isolation trench 611 and the facing walls of the peripheral isolation trench 607 .

[0098] Each isolation trench 611 has, for example, a structure similar to that of the peripheral isolation trench 607 .

[0099] The conductive region of each isolation trench 611 is, for example, electrically isolated from the conductive region of the peripheral isolation trench 607. This allows, for example, the conductive region of each isolation trench 611 to be biased independently of the conductive region of the peripheral isolation trench 607.

[0100] In the example shown, the pixel 600 also includes a charge collection region 613 arranged on the side of the substrate opposite to the photosensitive region 603, i.e., on the side of the surface 601T of the substrate. The charge collection region 613 extends vertically from the top surface 601T of the substrate 601 through the thickness of the substrate 601 to a depth less than the depth of the isolation trench 611. In this example, each load collection region 613 is surrounded by one of the isolation trenches 611 and by a peripheral isolation trench 607. By way of example, each load collection region 613 is substantially square in shape when viewed from above. Each charge collection region 613 is, for example, more heavily doped with a first conductivity type, in this example N-type (N-type), than the photosensitive region 603. + ). By way of example, the substrate 601 has a thickness between 1.10 16 to 5.10 20 at. / cm 3 between the doping levels.

[0101] In the example shown, each photosensitive region 603 includes a doped region 615 of the second conductivity type, which is P-type in this example. The region 615 is, for example, heavily doped P-type (P + ). In this example, region 615 extends vertically from one side of the photosensitive region 603 on one side of region 605 through the thickness of substrate 601 to a depth less than the thickness of the photosensitive region 603. Within each photosensitive region 603, region 615 forms a photodiode with a portion of substrate 601 doped with a first conductivity type (in this example, N-type). Region 615 further allows blocking the transfer of charges from the photosensitive region 603 to region 605 of pixel 601. Alternatively, region 615 can be omitted, for example in the case where vertical transfer gate 610 is close to isolation trench 609.

[0102] In the example shown, region 605 includes a doped region 617 of a first conductivity type (in this example, N-type) covered by a heavily doped region 618 of a second conductivity type (in this example, P-type). In this example, region 618 extends vertically from a top surface 601T of substrate 601 through the thickness of substrate 601 to a depth less than the thickness of region 605. Fig. 6A In the example shown, region 618 is substantially square in shape and is approximately centered relative to the peripheral isolation trench 607 of pixel 600. Furthermore, in this example, region 617 extends vertically from region 618 through the thickness of substrate 601 to a depth that is less than the thickness of region 605. Region 617, for example, has a larger lateral dimension than region 618, wherein metal connection element 103 contacts a portion of region 617 that is not positioned to align with region 618. Regions 617 and 618, for example, are similar to those previously described with respect to Figure 2 Described regions 203 and 205 , region 617 of pixel 600 in FIG. 6 , for example, corresponds to a pinning region formed in substrate 601 .

[0103] In the example shown, the pixel 600 also includes a charge collection region 619 disposed on one side of the top surface 601T of the substrate 601. The charge collection region 619 extends vertically from the top surface 601T of the substrate 601 through the thickness of the substrate 601 to a depth that is less than the thickness of the region 617. More specifically, in this example, the pixel 600 has three charge collection regions 619, each located between one side of the region 617 and one side of the peripheral isolation trench 607.

[0104] In the example shown, the pixel 600 also includes a transfer gate 621, such as a planar transfer gate, which is located on and in contact with the top surface 601T of the substrate 601. Each transfer gate 621 is, for example, positioned to align with a portion of the substrate 601 between the region 617 and one of the charge collection regions 619. Alternatively, the pixel 600 can include a different number of transfer gates 621 and charge collection regions 619 than those shown, such as four charge collection regions 619 associated with four transfer gates 621, respectively.

[0105] In this example, the photosensitive region 603 and the photodiode 101 (at Fig. 6A and Figure 6B (not described in detail) is intended to be illuminated from the bottom surface 601B of the substrate 601. Figure 6BAs shown, the pixel 600 may further include a color filter 623 located on and in contact with the bottom surface 601B of the substrate 601. In the example shown, each color filter 623 is positioned to coincide with one of the photosensitive regions 603. Some color filters 623 are, for example, transparent to only a portion of the visible spectrum (e.g., blue light) and transparent to at least a portion of the infrared spectrum (e.g., near infrared radiation), while other color filters 623 are, for example, transparent to another portion of the visible spectrum (e.g., green light or red light) and opaque to infrared radiation. To this end, a layer of resin ( Fig. 6A and Figure 6B ), for example, it is aligned with a color filter 623 that is transparent to green or red light. Fig. 6A and Figure 6B Not shown in the figure, the pixel 600 may further include one or more passivation layers, for example interposed between the bottom surface 601B of the substrate 601 and the color filter 623, and other optical elements such as one or more micro lenses.

[0106] During the exposure phase of the pixel 600, electron-hole pairs are created, for example, within each photosensitive region 603. During this phase, the conductive region of each isolation trench 611 is brought to a fixed potential, for example a negative potential, for example equal to about -1.5 V, by a control circuit (not shown). Applying this potential to the conductive region of each trench 611 during the sensor exposure phase enables the formation of a potential barrier between the photosensitive region 603 and the collection region 613 in the transfer region located inside each vertical transfer gate 610. In the example shown, the transfer region is adjoined by the inner sidewalls of the peripheral isolation trench 607 and the isolation trench 611 and extends vertically through the thickness of the substrate 601 below the collection region 613.

[0107] The presence of a potential barrier in the transfer region allows blocking the transfer of photogenerated electrons from the photosensitive region 603 to the collection region 613 during the exposure phase. In this example, this potential barrier is created by the presence of an inversion layer along the sidewalls of the isolation trenches 607 and 611 that attracts holes.

[0108] During a reading phase following the exposure phase, the conductive area of ​​each isolation trench 611 is initialized, for example in the case of a sampling channel, or maintained by a control circuit (not shown) at a potential higher than the potential applied during the exposure phase, for example a positive potential, for example equal to about 0.5 V, in the case of a photodiode reset channel. Applying this potential to the conductive area of ​​each trench 611 reduces or even eliminates the potential barrier in the transfer region between the photosensitive region 603 and the charge collection region 613. The disappearance of the potential barrier enables the photogenerated electrons to be transferred 625 from the photosensitive region 603 to the collection region 613 during the reading phase. By way of example, the charge collection region 613 is brought to a fixed potential, for example a positive potential, for example equal to about 2.5 V, during both the exposure and reading phases. This allows the photogenerated electrons to be attracted towards the region 613 during the reading phase.

[0109] Furthermore, during the phase of exposing the pixel 600, the charge is, for example, as previously described with respect to FIG. 4A to FIG. 4B The charge in the region 605 is accumulated inside the region 605 as explained for the pinning region 105 of the pixel 100. For example, during this phase, the charge in the region 605 is sequentially transferred to the individual charge collection regions 619 of the pixel 600. To this end, one of the planar transfer gates 621 is, for example, brought to a first potential to transfer the charge from the region 605 to one of the regions 619, while the other gate 621 is brought to a second potential to block the transfer of electrons to the other regions 619. Then, the other gate 621 is brought to a first potential, the other gates are then brought to a second potential, and so on, until all the gates 621 are successively brought to the first potential. During the same exposure phase, the gates 621 of the pixel 600 are therefore sequentially opened, for example by applying control signals that are out of phase with each other to these gates, so as to enable the transfer of charge from the region 605 to a single collection region 619 at a time. For example, this sequence of opening the transfer gates 621 is repeated multiple times during the exposure phase. This enables the pixel 600 to implement time-of-flight distance measurement, for example, indirect time-of-flight (iToF) measurement. By way of example, the opening frequency of each transfer gate 621 is between 10 MHz and 300 MHz, and each exposure phase includes a number of opening time periods of the transfer gate 621 between ten thousand and one million.

[0110] During the exposure phase, the gate 621 brings the potential barrier in the transfer region between the region 617 of the region 605 and the collection regions 619 associated with these gates to a second potential. In this example, this potential barrier is caused by the presence of a hole-attracting inversion layer under the planar transfer gate 621 at the second potential. Conversely, the gate 621 brought to the first potential reduces or even eliminates the potential barrier in the transfer region between the region 617 and the charge collection region 619 associated with this gate. By way of example, the first potential is positive, for example equal to about 0.5 V, and the second potential is lower than the first potential, for example negative, for example equal to about -2 V.

[0111] By way of example, prior to an exposure phase, the charge collection regions 619 are each brought to a fixed starting potential, such as a positive potential, for example equal to about 2.5 V. This allows the photogenerated charges to be attracted toward the regions 619 during the exposure phase. During the exposure phase, the potential of each region 619 decreases according to the number of electrons transferred from region 605 to that region 619. At the end of the exposure phase, the potentials of the regions 619 are measured, for example, in order to determine the total amount of charge integrated by each region 619 during the exposure phase. Once the measurements are completed, the charge collection regions are brought back to their initial potentials, for example, prior to the next exposure phase.

[0112] In the example shown, in which the pixel 600 includes three planar transfer gates 621 respectively associated with the three charge collection regions 619, one of the planar transfer gates 621 implements a reset function, for example by keeping this transfer gate 621 in an on state during the phase when the pixel 600 is not collecting samples, and the pinning area is permanently cleared or reset.

[0113] Figure 7 An example of an image sensor pixel 700 according to one embodiment is schematically and partially shown. Figure 7 The pixel 700 shown includes Figure 1 The common elements of the pixel 100 are shown. These common elements will not be described again below.

[0114] Figure 7 The pixel 700 shown is Figure 1The pixel 100 shown differs in that the pixel 700 additionally comprises another transistor 701, for example a MOS transistor, which is connected between the metal connection element 103 and the pinning region 105. In the example shown, the transistor 701 comprises a conduction terminal (for example a source) connected to the metal connection element 103, another conduction terminal (for example a drain) connected to the pinning region 105, and a control terminal or gate connected to a node for applying a control voltage PC. In the case where the pixel 700 comprises an optional circuit 119, the optional circuit 119 comprises a reset MOS transistor 121, the source of the transistor 121 being connected to the source of the transistor 701, for example.

[0115] The transistor 701 is designed, for example, to compensate for the fact that the height of the electric field lines between the metal connection element 103 and the pinning region 105 depends on the geometry and doping level of the structure of the pixel 700. The transistor 701 is, for example, controlled to be in an on-state to ensure the transfer of the photogenerated charges 401 from the metal connection element 103 to the pinning region 105. By way of example, the channel voltage level of the transistor 701 is regulated by its gate voltage PC. This advantageously allows providing an external control of the slope of the potential level between the metal connection element 103 and the pinning region 105. In particular, this allows achieving the steepest possible slope in the case of small structures with low charge collection areas.

[0116] Figure 8 According to an embodiment Figure 7 Schematic, partial side and cross-sectional views of examples of pinning regions 105 of pixel 700 are shown.

[0117] Figure 8 The pinning region 105 of the pixel 700 is shown with Figure 2 The pinning region 105 of the illustrated pixel 100 differs in that the pinning region 105 of the pixel 700 comprises a transistor 701 comprising a gate region comprising an electrically insulating layer 709 interposed between a conductive layer 711 (e.g., serving as a gate of the MOS transistor 701) and a top surface of the substrate 201. The layers 709 and 711 of the transistor 701 are, for example, similar or identical to the layers 209 and 211, respectively, of the transistor 109. In the illustrated example, the gate region extends laterally over regions 203 and 205, the region 203 forming, for example, a drain region of the MOS transistor 701, and over region 207 forming, for example, a source region of the MOS transistor 701. In the illustrated example, the region 203 is laterally separated from the region 207 by a portion of the substrate 201.

[0118] Fig. 9 is a diagram showing a method according to an embodiment Figure 7 A diagram of the operating steps of pixel 700 is shown.

[0119] The operation steps of pixel 700 are similar to the operation steps of pixel 100 and can be understood by a person skilled in the art from the above, especially with respect to FIG. 4A to FIG. 4D Specifically, Fig. 9 The steps illustrated in the figure are similar to those previously described with respect to Figure 4A The operation steps of the pixel 100 are described.

[0120] More precisely, Fig. 9 A preliminary step is shown, in which photogenerated charges 401 (here electrons) are accumulated at the node 104 under the effect of the current IPH generated by the photodiode 101, until the voltage VPH present at the node 104 becomes substantially equal to the pinch-off voltage Vp of the pinning region 105. During this step, the MOS transistor 701 is kept in the on state, in the example shown, the control voltage PC applied to its gate being greater than the pinch-off voltage Vp.

[0121] One advantage of pixels 100, 600, and 700 is that they enable the use of non-pinned photodiodes associated with 4T-type readout circuits. This allows, for example, image sensors to be implemented with photodiodes that cannot be implemented with pinned structures (such as silicon hybrid photodiodes) while maintaining a charge integration mode of operation. This allows for reduced kTC noise compared to image sensors that include non-pinned pixels or photodiodes associated with 3T-type circuits.

[0122] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined and that those skilled in the art will readily conceive of other variations. In particular, those skilled in the art will be able to convert the read circuit 107 from the instructions of this specification to the Figure 1 The pixel 100 shown is adapted to Fig. 6A and Figure 6B Pixel 600 is shown. Furthermore, a person skilled in the art will be able to combine the design of pixel 700 with the design of pixel 600, ie in order to provide in pixel 600 a transistor connected between metal connection element 103 and pinning region 617.

[0123] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of a person skilled in the art based on the functional description provided herein. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this specification.

Claims

1. An image sensor (300) comprising a plurality of pixels (100; 600; 700), each pixel comprising a non-pinned photodiode (101), wherein the non-pinned photodiode (101) is connected to a pinning region (105) formed in a first semiconductor substrate (201; 601) via a metal connection element (103).

2. The sensor according to claim 1, wherein: The non-pinned photodiode (101) includes a P-type doped anode semiconductor region (303) and an N-type doped cathode semiconductor region (305).

3. The sensor according to claim 2, wherein: The anode semiconductor region (303) and the cathode semiconductor region (305) of the non-pinned photodiode (101) are bonded.

4. The sensor according to any one of claims 1 to 3, wherein: The non-pinned photodiode (101) is formed on a second semiconductor substrate (301) different from the first substrate (201; 601).

5. The sensor according to claim 4, wherein: The non-pinned photodiode (101) is hybridized to the first substrate (201), which is made of silicon.

6. The sensor according to claim 4 or 5, wherein: The metal connection elements (103) include conductive tracks, conductive vias and / or contact pickup elements formed in a first interconnect stack (309) and a second interconnect stack (307) located on the first substrate (201; 601) and the second substrate (301), respectively.

7. The sensor according to any one of claims 1 to 6, wherein: The pinning region (105) includes a first N-type doped semiconductor region (203; 617) formed in the first substrate (201; 601), the first substrate being P-type doped.

8. The sensor according to claim 7, wherein: A second P-type doped semiconductor region (205; 618) formed in the first substrate (201; 601) is interposed between the top surface of the first substrate and the first semiconductor region (203; 617).

9. The sensor according to claim 8, wherein: The second semiconductor region (205; 618) has a higher doping level than the first substrate (201; 601).

10. The sensor according to claim 7, 8 or 9, wherein: The metal connection element (103) contacts a third N-type doped semiconductor region (207) extending vertically from the top surface of the first substrate (201) through the thickness of the first substrate (201).

11. The sensor according to claim 10, wherein: The first semiconductor region (203) penetrates into the third semiconductor region (207).

12. The sensor according to any one of claims 1 to 10, wherein: Each pixel (700) also includes a transistor (701) connected between the metal connection element (103) and the pinning region (105).

13. The sensor according to any one of claims 1 to 12, wherein: The pixel (600) further comprises: - at least one first photosensitive region (603) formed in said first substrate (601) and adapted to collect light in a first wavelength range; - a fourth semiconductor region (605) formed in the first substrate aligned with the at least one photosensitive region, wherein the pinning region (105) is formed; - at least one charge collection region (613) arranged on a side (601T) of the second substrate opposite to the at least one first photosensitive region; - at least one transfer region extending from said at least one first photosensitive region to said at least one charge collecting region; and - at least one transfer gate (610) extending vertically between the at least one transfer region and the fourth semiconductor region and laterally adjoining the at least one transfer region.

14. The sensor according to claim 13, wherein: The non-pinned photodiode (101) is adapted to capture light in a second wavelength range different from the first wavelength range.

15. The sensor according to claim 13 or 14, wherein: The pixel (600) further comprises at least one further transfer gate (621) and at least one further charge collection region (619), wherein the at least one further transfer gate (621) extends laterally on the side (601T) of the first substrate (601) opposite to the at least one first photosensitive region (603).

16. The sensor according to any one of claims 1 to 15, wherein: The pinning region (105) is not intended to be subjected to incident light radiation.

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