Planar detector, photosensitive chip thereof and preparation method of photosensitive chip
By generating epitaxial materials on the substrate and etching treatment, combining the structure of the tunneling layer and the field passivation layer, the complex and unsafe PN junction preparation process of the planar detector is solved, and high-performance photosensitive chip preparation is achieved.
Patent Information
- Application Number
- CN202310956778.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-31
- Publication Date
- 2025-02-25
AI Technical Summary
In the prior art, the PN junction preparation technology of planar detectors mainly adopts diffusion method, which is complex in the process and is not conducive to safe production.
By generating epitaxial materials on the substrate and etching the epitaxial materials, a photosensitive chip is formed, and a combination structure of a tunneling layer and a field passivation layer is adopted, the use of traditional diffusion methods is avoided.
It realizes a photosensitive chip that obtains a planar detector with excellent performance without diffusion process, improves the stability and reliability of the device, and is conducive to safe production.
Smart Images
Figure CN119521820A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor optoelectronic devices, and in particular to a photosensitive chip of a planar detector and a method for manufacturing the same. Background Art
[0002] The structure of an InGaAs photodetector (photosensitive chip) can be divided into two types: mesa type and planar type. Among them, the manufacturing process of the mesa type detector is simple, but due to the exposure of the PN junction (space charge region), the dark current is large and the performance is poor; while for the planar type detector, since the PN junction is buried in the cap layer / absorption layer, the dark current is small and the device performance is good. Currently, for planar InGaAs (indium gallium arsenide) detectors, the PN junction preparation technology of lattice-matched In 0.53 Ga 0.47 As / InP (indium phosphide) and extended wavelength In x Ga 1-x As / InP (0.53 < x ≤ 0.83) detectors all adopt the diffusion method. The diffusion method for preparing planar junctions has become the mainstream technology in the InGaAs detector industry due to its excellent equipment and good device performance. The diffusion method can be divided into the closed-tube diffusion method and the MOCVD (new gas-phase epitaxial growth technology) diffusion method. The former has a complex process, and the latter requires the use of highly toxic gases such as PH 3 (phosphorus cyanide), which is not conducive to safe production. Summary of the Invention
[0003] The technical problem to be solved by the present disclosure is to overcome the defect that the PN junction preparation technology of planar detectors in the prior art all adopts the diffusion method, which has a complex process and is not conducive to safe production, and to provide a planar detector, its photosensitive chip and a method for manufacturing the photosensitive chip, which neither require a diffusion process nor can obtain a planar junction detector with good performance, and is of great significance to the industrialization of InGaAs detectors.
[0004] The present disclosure solves the above technical problems through the following technical solutions:
[0005] In a first aspect, a method for manufacturing a photosensitive chip of a planar detector is provided, and the manufacturing method includes:
[0006] Generating an epitaxial material on a substrate;
[0007] Etching the epitaxial material to form the photosensitive chip;
[0008] Wherein, the epitaxial material includes a buffer layer, an absorption layer, a tunneling layer, and a field passivation layer sequentially stacked on the substrate;
[0009] The tunneling layer is used to allow holes in the absorption layer to tunnel based on the tunneling effect and to block electrons in the absorption layer from passing through; the field passivation layer is used to provide a low-energy position for the holes after tunneling through the tunneling layer.
[0010] Preferably, the step of etching the epitaxial material to form the photosensitive chip includes:
[0011] Etching the epitaxial material to expose a portion of the buffer layer, and using the portion of the buffer layer as a common N (N is the prefix of Negative, which is named because electrons carry negative charges) region;
[0012] The field passivation layer is etched to obtain a plurality of array-type P (P is the prefix of Positive, so named because holes are positively charged) regions to form a detector wafer;
[0013] The photosensitive chip is obtained based on the detector wafer.
[0014] Preferably, the step of obtaining the photosensitive chip based on the detector wafer comprises:
[0015] Depositing a dielectric protection layer on the detector wafer, and etching the deposited dielectric protection layer to obtain a plurality of metal contact holes;
[0016] A metal electrode is generated on each of the metal contact holes to form the photosensitive chip.
[0017] Preferably, the substrate is a semi-insulating InP material;
[0018] And / or, the buffer layer is an N-type material;
[0019] And / or, the absorption layer is I (undoped with impurities) type material;
[0020] And / or, the tunneling layer is a type I material;
[0021] And / or, the field passivation layer is a P-type material.
[0022] Preferably, the absorption layer is made of InGaAs.
[0023] Preferably, the tunnel layer is made of InAlAs (indium aluminum arsenic);
[0024] And / or, the tunneling layer and the absorption layer have the same lattice constant;
[0025] And / or, the thickness of the tunneling layer meets a first preset thickness value.
[0026] Preferably, the field passivation layer and the absorption layer have the same component.
[0027] Preferably, the field passivation layer is a P-type InGaAs component, and the absorption layer is an I-type InGaAs component;
[0028] And / or, the carrier concentration of the field passivation layer meets the preset carrier concentration, and the thickness meets the second preset thickness value.
[0029] In a second aspect, a photosensitive chip of a planar detector is also provided, and the photosensitive chip is prepared by using the above-mentioned method for preparing the photosensitive chip of the planar detector.
[0030] In a third aspect, a planar detector is also provided, wherein the planar detector comprises the above-mentioned photosensitive chip.
[0031] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0032] The positive and progressive effects of this disclosure are:
[0033] The planar detector and its photosensitive chip and the method for preparing the photosensitive chip disclosed in the present invention generate epitaxial material on a substrate, and etch the epitaxial material to form a photosensitive chip. The photosensitive chip of the planar detector with excellent performance can be obtained without the existing ion implantation or impurity diffusion method, which is conducive to safe production. A tunneling layer and a field passivation layer are grown on the absorption layer by epitaxial growth. The tunneling layer allows holes in the absorption layer to tunnel based on the tunneling effect, and blocks electrons in the absorption layer from passing through, thereby preventing the recombination of electrons and holes. The field passivation layer provides a low-energy position for holes after tunneling through the tunneling layer, and the tunneling layer and the field passivation layer together form a passivation structure, which provides good interface passivation for the photosensitive chip and improves the stability and reliability of the photosensitive chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 A schematic diagram of a first process of a method for preparing a photosensitive chip of a planar detector provided in Example 1 of the present disclosure;
[0035] Figure 2 A second schematic diagram of the method for preparing the photosensitive chip of the planar detector provided in Example 1 of the present disclosure;
[0036] Figure 3 A third schematic flow chart of the method for preparing the photosensitive chip of the planar detector provided in Example 1 of the present disclosure;
[0037] Figure 4 The structural intention of the epitaxial material in the method for preparing the photosensitive chip of the planar detector provided in Example 1 of the present disclosure;
[0038] Figure 5The structural intention of the photosensitive chip of the planar detector provided in Example 2 of the present disclosure;
[0039] Figure 6 This is the structural intention of the planar detector provided in Example 3 of the present disclosure. DETAILED DESCRIPTION
[0040] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0041] Example 1
[0042] This embodiment provides a method for preparing a photosensitive chip of a planar detector, such as Figure 1 As shown, the preparation method comprises:
[0043] S101, generating epitaxial material on a substrate.
[0044] S102, etching the epitaxial material to form a photosensitive chip.
[0045] Among them, the epitaxial material includes a buffer layer, an absorption layer, a tunneling layer and a field passivation layer stacked in sequence on the substrate; the tunneling layer is used to allow holes in the absorption layer to tunnel based on the tunneling effect and block the passage of electrons in the absorption layer; the field passivation layer is used to provide a low-energy position for the holes after tunneling through the tunneling layer.
[0046] Epitaxial materials can be grown epitaxially by MBE (Molecular Beam Epitaxy) or MOCVD.
[0047] The epitaxial material of traditional photosensitive chips does not have a tunneling layer and a field passivation layer. Therefore, a different doping process is required. Through the diffusion method, P-type semiconductors and N-type semiconductors are made on the same semiconductor (usually silicon or germanium) substrate, and a space charge region, namely a PN junction, is formed at their interface. The PN junction has unidirectional conductivity, which makes the traditional photosensitive chip have excellent conductive properties.
[0048] Since the movement of electrons will form electron current and the movement of holes will form hole current, by setting up a tunneling layer, conditions are provided for the holes in the absorption layer to tunnel to the field passivation layer based on the tunneling effect, thereby preventing the recombination of electrons and holes. The field passivation layer provides a low-energy position for the holes after tunneling through the tunneling layer, thereby ensuring the good conductive performance of the photosensitive chip. There is no need to use the traditional diffusion method to prepare the PN junction, and the etching method can be used to obtain a photosensitive chip with excellent conductive performance.
[0049] The photosensitive chip is made of semiconductor material and is extremely sensitive to the external environment atmosphere, which has a decisive influence on the performance of the detector. In order to ensure the performance of the device and improve reliability and stability, it is necessary to take effective protection measures for the surface, namely the so-called surface passivation technology, to passivate (reduce) the sensitivity to the external environment.
[0050] The method for preparing the photosensitive chip of the planar detector of the present embodiment can obtain a photosensitive chip of the planar detector with excellent performance without the need for existing ion implantation or impurity diffusion methods, which is beneficial to safe production. The tunneling layer and the field passivation layer together form a passivation structure, which provides good interface passivation for the photosensitive chip and improves the stability and reliability of the photosensitive chip.
[0051] In an optional embodiment, if Figure 2 As shown, the above step S102 includes:
[0052] S1021, etching the epitaxial material to expose part of the buffer layer, and using part of the buffer layer as a common N region.
[0053] S1022, etching the field passivation layer to obtain a plurality of array-type P regions to form a detector wafer.
[0054] S1023. Obtain a photosensitive chip based on the detector wafer.
[0055] The etching process includes but is not limited to photolithography, dry etching and wet etching. A portion of the buffer layer can be exposed as a common N region by photolithography, dry etching or wet etching, and the field passivation layer can be photolithographically or wet-etched to obtain a patterned field passivation layer. The field passivation layer in an isolated state corresponds to the P region of a single photosensitive element, that is, a plurality of array-type P regions are obtained.
[0056] The method for preparing the photosensitive chip of the planar detector of this embodiment uses etching treatment on the epitaxial material, and can obtain a photosensitive chip of the planar detector with excellent performance without the need for existing ion implantation or impurity diffusion methods, which is conducive to safe production and improves the stability and reliability of the photosensitive chip.
[0057] In an optional embodiment, if Figure 3 As shown, the above step S1023 includes:
[0058] S10231. Deposit a dielectric protection layer on the detector wafer, and etch the deposited dielectric protection layer to obtain a plurality of metal contact holes.
[0059] S10232. Generate a metal electrode on each metal contact hole to form a photosensitive chip.
[0060] The dielectric protection layer can also be referred to as a dielectric film, which covers the epitaxial material and plays a protective role for the epitaxial material. Specifically, the dielectric protection layer can be prepared at a temperature below 300 °C.
[0061] SiN can be deposited on the entire area of the detector wafer a (a silicon nitride) or SiO 2 (silicon dioxide), and several metal contact holes are obtained through photolithography and wet etching; on each metal contact hole, several metal electrodes (which can also be referred to as contact electrodes / extension electrodes) can be obtained through photolithography, metal deposition, or stripping, and finally the preparation of the photosensitive chip is completed.
[0062] The photosensitive chip includes a substrate, a buffer layer, an absorption layer, a tunneling layer, a field passivation layer, a dielectric protection layer, and metal electrodes. The metal electrodes are a metal combination that can form good ohmic contacts with both the N-type buffer layer and the P-type field passivation layer without an annealing process. The low-temperature process helps to prevent the analysis of surface elements of the epitaxial material and protect the quality of the epitaxial layer interface.
[0063] In an alternative embodiment, as Figure 4 shown, the substrate is a semi-insulating InP material, the buffer layer is an N-type material, the absorption layer is an I-type material, the tunneling layer is an I-type material, and the field passivation layer is a P-type material.
[0064] For example, N-type In x Al 1-x As buffer layer is a Si (silicon)-doped In x Al 1-x As material with a linearly graded composition or a Si-doped In x Al 1-x As material with a fixed composition that is lattice-matched (same lattice constant) to the absorption layer, where the range of x is 0.52 < x ≤ 1 and the carrier concentration is ≥ 2 * 10 18 cm -3 .
[0065] In an alternative embodiment, the composition of the absorption layer is InGaAs.
[0066] Specifically, the absorption layer is an I-type In y Ga 1-y As composition, where the range of y is 0.53 < y ≤ 1.
[0067] In an alternative embodiment, the composition of the tunneling layer is InAlAs;
[0068] Specifically, the tunneling layer is an I-type In z Al 1-z As composition.
[0069] In an optional implementation, the tunneling layer and the absorption layer have the same lattice constant, and the thickness of the tunneling layer meets a first preset thickness value.
[0070] Specifically, the absorber layer is type I In y Ga 1-y As component, the tunneling layer is I-type In z Al 1-z As component, the lattice constant of the tunneling layer is the same as that of the absorption layer. Since the tunneling layer has a larger bandgap width than the absorption layer, a better chemical passivation effect can be achieved to obtain a high-quality interface; at the same time, the thickness of the tunneling layer meets the first preset thickness value, providing the necessary conditions for the tunneling effect of holes.
[0071] For example, the first preset thickness value is 1-5 nm.
[0072] In an alternative embodiment, the field passivation layer has the same composition as the absorption layer.
[0073] Specifically, the absorption layer is In y Ga 1-y As component, the field passivation layer is In y Ga 1-y As component, the field passivation layer and the absorption layer are epitaxial materials of the same component.
[0074] In an optional embodiment, the field passivation layer is composed of P-type InGaAs, and the absorption layer is composed of I-type InGaAs.
[0075] Specifically, the absorber layer is type I In y Ga 1-y As component, the field passivation layer is P-type In y Ga 1-y As component, the field passivation layer and the absorption layer are epitaxial materials of the same component, the difference is that the field passivation layer is P type.
[0076] In an optional implementation, the carrier concentration of the field passivation layer meets the preset carrier concentration, and the thickness meets the second preset thickness value.
[0077] The carrier concentration of the field passivation layer meets the preset carrier concentration, and the thickness meets the second preset thickness value to meet the field passivation and contact requirements.
[0078] For example, the carrier concentration is set to be no less than 2×10 18 cm -3 , the second preset thickness value is not less than 20nm.
[0079] In a specific example, the photosensitive chip of the planar detector is an In nanostructured laser with a cutoff wavelength of 2.6 μm. 0.83 Ga 0.17As, the epitaxial material of the photosensitive chip is grown by MBE method, including a semi-insulating InP substrate, 1 μm thick, and a carrier concentration of 2×10 18 cm -3 N-type linear gradient component In x Al 1-x As and In with a fixed composition lattice-matched to the absorber layer 0.82 Al 0.18 As buffer layer, 1.5 μm thick I-type In 0.83 Ga 0.17 As absorption layer S13, 2nm thick I-type In 0.82 Al 0.18 As tunneling layer, 500nm thick, carrier concentration 2×10 18 cm -3 P-type In 0.83 Ga 0.17 As field passivation layer, and dielectric protection layer SiN a , metal electrodes Ti (titanium) / Pt (platinum) / Au (gold), where the tunneling layer needs to have the same lattice constant as the intrinsic absorption layer to ensure a good interface between the two, and a larger bandgap to reduce surface leakage current. Materials that meet the conditions include In 0.82 Al 0.18 As、InAs 0.6 P 0.4 , due to In 0.82 Al 0.18 As has a larger bandgap, so In is selected 0.82 Al 0.18 As is used as a tunneling layer with a thickness of 2nm, which provides the necessary conditions for the tunneling effect of holes. The ultra-thin tunneling layer allows holes to tunnel while blocking electrons from passing through, thus preventing the recombination of electrons and holes.
[0080] Example 2
[0081] This embodiment provides a photosensitive chip, which is prepared by the method for preparing the photosensitive chip of the planar detector in Embodiment 1.
[0082] like Figure 5 As shown, the photosensitive chip includes a substrate A1, a buffer layer A2, an absorption layer A3, a tunneling layer A4 and a field passivation layer A5, a dielectric protection layer A6, and a metal electrode A7. The metal electrode does not require an annealing process to form a metal combination with good ohmic contact with the N-type buffer layer and the P-type field passivation layer at the same time. The low temperature process helps to prevent the analysis of elements on the surface of the epitaxial material and protect the quality of the epitaxial layer interface.
[0083] The photosensitive chip of this embodiment is prepared by the preparation method of the photosensitive chip of the planar detector in Example 1. A photosensitive chip of a planar detector with excellent performance can be obtained without the existing ion implantation or impurity diffusion method, which is beneficial to safe production. The tunneling layer and the field passivation layer together form a passivation structure, which provides good interface passivation for the photosensitive chip and improves the stability and reliability of the photosensitive chip.
[0084] Example 3
[0085] This embodiment provides a planar detector, such as Figure 6 As shown, the planar detector includes the photosensitive chip of Example 3.
[0086] The planar detector may also include other components, such as readout circuitry.
[0087] The planar detector of this embodiment includes the photosensitive chip in Example 2. The photosensitive chip is prepared by the preparation method of the photosensitive chip of the planar detector in Example 1. The photosensitive chip of the planar detector with excellent performance can be obtained without the existing ion implantation or impurity diffusion method, which is beneficial to safe production. The tunneling layer and the field passivation layer together form a passivation structure, which provides good interface passivation for the photosensitive chip, improves the stability and reliability of the photosensitive chip, and ensures the stability of the performance of the planar detector.
[0088] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A method for preparing a photosensitive chip of a planar detector, characterized in that: The preparation method comprises: growing epitaxial material on a substrate; Etching the epitaxial material to form the photosensitive chip; Wherein, the epitaxial material comprises a buffer layer, an absorption layer, a tunneling layer and a field passivation layer which are sequentially stacked on the substrate; The tunneling layer is used to allow holes in the absorption layer to tunnel based on the tunneling effect and to block electrons in the absorption layer from passing through; the field passivation layer is used to provide a low-energy position for the holes after tunneling through the tunneling layer.
2. The preparation method according to claim 1, characterized in that The step of etching the epitaxial material to form the photosensitive chip includes: Etching the epitaxial material to expose a portion of the buffer layer, and using the portion of the buffer layer as a common N region; Etching the field passivation layer to obtain a plurality of array-type P regions to form a detector wafer; The photosensitive chip is obtained based on the detector wafer.
3. The preparation method according to claim 2, characterized in that: The step of obtaining the photosensitive chip based on the detector wafer comprises: Depositing a dielectric protection layer on the detector wafer, and etching the deposited dielectric protection layer to obtain a plurality of metal contact holes; A metal electrode is generated on each of the metal contact holes to form the photosensitive chip.
4. The preparation method according to any one of claims 1 to 3, characterized in that The substrate is a semi-insulating InP material; And / or, the buffer layer is an N-type material; And / or, the absorption layer is type I material; And / or, the tunneling layer is a type I material; And / or, the field passivation layer is a P-type material.
5. The preparation method according to claim 4, characterized in that: The absorption layer is composed of InGaAs.
6. The preparation method according to claim 5, characterized in that: The component of the tunneling layer is InAlAs; And / or, the tunneling layer and the absorption layer have the same lattice constant; And / or, the thickness of the tunneling layer meets a first preset thickness value.
7. The preparation method according to claim 4, characterized in that: The field passivation layer has the same composition as that of the absorption layer.
8. The preparation method according to claim 7, characterized in that: The field passivation layer is a P-type InGaAs component, and the absorption layer is an I-type InGaAs component; And / or, the carrier concentration of the field passivation layer meets the preset carrier concentration, and the thickness meets the second preset thickness value.
9. A photosensitive chip for a planar detector, characterized in that: The photosensitive chip is prepared by the method for preparing a photosensitive chip of a planar detector as described in any one of claims 1 to 8.
10. A planar detector, characterized in that: The planar detector comprises the photosensitive chip as claimed in claim 9.