A tbc cell structure and method of making the same

Abstract

The application relates to a TBC battery structure and a preparation method thereof, and belongs to the technical field of photovoltaic modules. The TBC battery structure comprises a first region and a second region which are alternately and intervally arranged on the back surface of a silicon wafer. The first region comprises a first passivation contact area, a first passivation non-contact area and a first electrode. The second region comprises a second passivation contact area, a second passivation non-contact area and a second electrode. The first region and the second region are opposite in polarity. The cross-sectional area of the first passivation contact area and the second passivation contact area is smaller than that of the first passivation non-contact area and the second passivation non-contact area. The application has the effects of optimizing the preparation process of the TBC battery structure, reducing the parasitic absorption of a Poly layer and improving the conversion efficiency of the battery.

Description

Technical Field

[0001] This invention belongs to the technical field of photovoltaic modules, specifically relating to a TBC cell structure and its preparation method. Background Technology

[0002] TBC (Tunneling Oxide Passivated Contact Back Contact Battery) is a battery that combines the structural features of both Tunneling Oxide Passivated Contact (TOPCon) and Back Contact (IBC) batteries to achieve the advantages of unobstructed front side, high open-circuit voltage, and large short-circuit current.

[0003] As attached Figure 1 As shown, the structure of the TBC battery in the related technology includes a first region 2 and a second region 3 deposited on a silicon wafer 1. The first region 2 includes a first tunneling layer 221, a first polycrystalline silicon layer 222 and a first electrode 4 sequentially disposed from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. The first region 2 also includes a third tunneling layer 321, a third polycrystalline silicon layer 322 and a second electrode 5 sequentially disposed from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. The preparation method includes polishing, PPoly, boron diffusion, primary patterning, etching, N Poly, phosphorus diffusion, secondary patterning, texturing and passivation to form the battery structure. The thickness of the Poly layer in contact with the electrode in the first region 2 of the battery structure is 300 nm, and the thickness of the Poly layer in contact with the electrode in the second region 3 is 200 nm.

[0004] The TBC battery structure fabrication process in related technologies is complex. The first and second regions need to be fabricated separately, requiring at least two high-temperature doping processes and two patterning processes to complete the battery fabrication. In addition, the poly layer in the PN region on the back of the battery is relatively thick, resulting in severe parasitic absorption of the poly layer, which limits the improvement of battery conversion efficiency. Summary of the Invention

[0005] In order to optimize the fabrication process of TBC battery structure and reduce parasitic absorption of Poly layer, thereby improving battery conversion efficiency, this application provides a TBC battery structure and its fabrication method.

[0006] In a first aspect, this application provides a TBC battery structure, which adopts the following technical solution:

[0007] A TBC battery structure includes a first region and a second region alternately disposed on the back side of a silicon wafer. The first region includes a first passivated contact region, a first passivated non-contact region and a first electrode. The second region includes a second passivated contact region, a second passivated non-contact region and a second electrode. The first region and the second region have opposite polarities.

[0008] The first passivation non-contact region includes a first tunneling layer and a first polysilicon layer sequentially disposed from the side closest to the silicon wafer to the side furthest from the silicon wafer. The first passivation contact region includes a second tunneling layer and a second polysilicon layer sequentially disposed from the side closest to the first polysilicon layer to the side furthest from the first polysilicon layer. The first electrode forms an ohmic contact with the second polysilicon layer.

[0009] The second passivation non-contact region includes a third tunneling layer and a third polysilicon layer sequentially disposed from the side closest to the silicon wafer to the side furthest from the silicon wafer. The second passivation contact region includes a fourth tunneling layer and a fourth polysilicon layer sequentially disposed from the side closest to the third polysilicon layer to the side furthest from the third polysilicon layer. The second electrode forms an ohmic contact with the fourth polysilicon layer.

[0010] The cross-sectional area of ​​the first passivated contact area and the second passivated contact area is smaller than the cross-sectional area of ​​the first passivated non-contact area and the second passivated non-contact area.

[0011] By adopting the above technical solution, since the cross-sectional area of ​​the first passivation contact area and the second passivation contact area is smaller than that of the first passivation non-contact area and the second passivation non-contact area, the battery structure of this application has a thinner polycrystalline silicon layer that does not contact the electrode. Furthermore, the passivation contact areas on the back of the silicon wafer all adopt a complete SiOx / Poly structure, and the passivation non-contact areas adopt a thin-layer SiOx / Poly passivation structure. This not only ensures passivation and contact performance but also reduces the thickness of the Poly layer, thereby reducing its parasitic absorption and improving battery efficiency.

[0012] Both the first and second passivation contact regions are areas in contact with the electrode. The second and fourth tunneling layers in the first and second passivation contact regions can block some of the diffusion of dopant sources, resulting in a stepped distribution of concentration within the Poly layer, with a low concentration on the side closer to the silicon wafer and a high concentration on the side farther from the silicon wafer, thus improving the cell conversion efficiency.

[0013] Preferably, the thickness of the first tunneling layer in the first passivation non-contact region and the third tunneling layer in the second passivation non-contact region is the same, both being 1.5~2.5nm.

[0014] More preferably, the first tunneling layer of the first passivation non-contact region and the third tunneling layer of the second passivation non-contact region have the same thickness, both being 1.5~2nm.

[0015] Preferably, the second tunneling layer of the first passivation contact region and the fourth tunneling layer of the second passivation contact region have the same thickness, both being 0.5~1.5nm.

[0016] More preferably, the second tunneling layer of the first passivation contact region and the fourth tunneling layer of the second passivation contact region have the same thickness, both being 0.5~1 nm.

[0017] Preferably, the first polysilicon layer in the first passivation contact region and the third polysilicon layer in the second passivation contact region have the same thickness, both being 30~100nm.

[0018] More preferably, the first polysilicon layer in the first passivation contact region and the third polysilicon layer in the second passivation contact region have the same thickness, both being 30~50nm.

[0019] Preferably, the second polysilicon layer in the first passivation contact region and the fourth polysilicon layer in the second passivation contact region have the same thickness, both being 100~200nm.

[0020] More preferably, the second polysilicon layer in the first passivation contact region and the fourth polysilicon layer in the second passivation contact region have the same thickness, both being 100~150nm.

[0021] Secondly, this application provides a method for preparing a TBC battery structure, comprising the following steps:

[0022] S1. Polishing: The silicon wafer is polished using an alkaline solution to remove the damaged layer and form a flat planar structure.

[0023] S2, Polysilicon stack deposition: A stack is deposited on the back side of the polished silicon wafer. First, the first tunneling layer and the third tunneling layer are deposited simultaneously. Then, the first polysilicon layer and the third polysilicon layer, the second tunneling layer and the fourth tunneling layer, and the second polysilicon layer and the fourth polysilicon layer are deposited simultaneously in sequence.

[0024] S3, PN doped source fabrication: P-type and N-type doped sources are directionally implanted using a printing method to achieve specific patterns;

[0025] S4. Annealing: The printed silicon wafer is annealed at high temperature to achieve PN region doping. The annealing temperature is 850-950℃ and the annealing time is 10-40 minutes.

[0026] S5. Laser patterning: After annealing, the wafer is patterned to remove the phosphorus silicate glass and borosilicate glass that are not in contact with the electrodes, as well as the stacked tunneling oxide layer and polysilicon layer in the undoped area.

[0027] S6. Texturing: Texturing is performed on the front side of the patterned silicon wafer, while the second and fourth polysilicon layers in the back PN region that are not in contact with the electrodes are thinned and undoped to form a GAP (height difference).

[0028] S7. Passivation: Passivation film is deposited on the front and back sides of the texturized silicon wafer, with a film thickness of 3-8nm.

[0029] S8. Metallization: P-type and N-type silver pastes are printed on the back of the passivated silicon wafer, and then sintered to complete the electrode preparation.

[0030] By adopting the above technical solution, the P / N Poly layer of this application is completed in one step, with the same stacked structure, and two different polarities of doping are achieved at the same annealing temperature. When the annealing temperature is between 850-950℃, the battery structure produced has good performance. When the temperature is below this range, the activation amount of the doping source will be insufficient, resulting in poor performance. When the temperature is above this range, the doping source will be over-activated, thereby destroying the oxide layer to form passivation, resulting in poor battery performance.

[0031] Preferably, in step 3, the doping concentration of the first polysilicon layer is 1×10⁻⁶. 19 atom / cm 3 ~5×10 19 atom / cm 3 The doping concentration of the second polysilicon layer is 5×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the third polysilicon layer is 5×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 The fourth polysilicon layer has a doping concentration of 1×10⁻⁶. 20 atom / cm 3 ~1×10 21 atom / cm 3 .

[0032] Preferably, in step 7, the raw material of the passivation film is two or more of aluminum oxide, silicon nitride, silicon oxynitride, or silicon oxide.

[0033] Preferably, in step 1, the grain size of the planar structure is 25-30 μm.

[0034] By adopting the above technical solution, the grain size on the surface of the silicon wafer after polishing will affect the battery performance. When the grain size is too small, it is easy to fail to etch the damaged layer, while when the grain size is too large, it will be detrimental to the production of the battery structure. When the grain size is 25-30um, the battery performance is better.

[0035] In summary, this application has the following beneficial effects:

[0036] 1. The battery structure of this application has a thin polycrystalline silicon layer that does not contact the electrode, and the passivation contact area on the back of the silicon wafer adopts a complete SiOx / Poly structure, while the passivation non-contact area adopts a thin SiOx / Poly passivation structure. This not only ensures passivation and contact performance, but also reduces the thickness of the Poly layer, reduces its parasitic absorption, and is conducive to improving battery efficiency.

[0037] Both the first and second passivation contact regions are areas in contact with the electrode. The second and fourth tunneling layers in the first and second passivation contact regions can block some of the diffusion of dopant sources, resulting in a stepped distribution of concentration within the Poly layer, with a low concentration on the side closer to the silicon wafer and a high concentration on the side farther from the silicon wafer, thus improving the cell conversion efficiency.

[0038] 2. The battery structure of this application, by setting a second polycrystalline silicon layer and a fourth polycrystalline silicon layer of the same thickness, can block the penetration of some doping sources, thereby making the concentration in the poly layer distributed in a stepped manner, improving the battery efficiency, and at the same time blocking the printing silver paste from etching the non-contact area, protecting the structural integrity of the non-contact area.

[0039] 3. The preparation method of this application completes the P / N Poly layer in one step, has the same stacked structure, and achieves two different polarities of doping at the same annealing temperature. When the annealing temperature is 850-950℃, the prepared battery structure has good performance. Attached Figure Description

[0040] Figure 1 This refers to the back structure of a TBC battery in the prior art.

[0041] Figure 2 This is the back structure of the TBC battery in this application.

[0042] Figure 3 The diagram shows the TBC battery structure forming process of Example 2 and Comparative Example 3.

[0043] Explanation of reference numerals in the attached figures: 1. Silicon wafer; 2. First region; 21. First passivation contact region; 211. Second tunneling layer; 212. Second polysilicon layer; 22. First passivation non-contact region; 221. First tunneling layer; 222. First polysilicon layer; 3. Second region; 31. Second passivation contact region; 311. Fourth tunneling layer; 312. Fourth polysilicon layer; 32. Second passivation non-contact region; 321. Third tunneling layer; 322. Third polysilicon layer; 4. First electrode; 5. Second electrode. Detailed Implementation

[0044] Unless otherwise specified, the experimental methods described in the following embodiments of the present invention are generally performed under conventional conditions or as recommended by the manufacturer. All commonly used chemical reagents used in the embodiments are commercially available products.

[0045] The following description is based on specific embodiments.

[0046] Example 1

[0047] like Figure 2 As shown, a TBC battery structure includes a first region 2 and a second region 3 deposited alternately on the back side of a silicon wafer 1. The first region 2 includes a first passivated contact region 21, a first passivated non-contact region 22 and a first electrode 4. The second region 3 includes a second passivated contact region 31, a second passivated non-contact region 32 and a second electrode 5. The first region 2 and the second region 3 have opposite polarities.

[0048] The first passivation non-contact region 22 includes a first tunneling layer 221 and a first polysilicon layer 222 sequentially disposed from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. The first passivation contact region 21 includes a second tunneling layer 211 and a second polysilicon layer 212 sequentially disposed from the side close to the first polysilicon layer 222 to the side away from the first polysilicon layer 222. The first electrode 4 forms an ohmic contact with the second polysilicon layer 212.

[0049] The second passivation non-contact region 32 includes a third tunneling layer 321 and a third polysilicon layer 322 sequentially disposed from the side near the silicon wafer 1 to the side away from the silicon wafer 1. The second passivation contact region 31 includes a fourth tunneling layer 311 and a fourth polysilicon layer 312 sequentially disposed from the side near the third polysilicon layer 322 to the side away from the third polysilicon layer 322. The second electrode 5 forms an ohmic contact with the fourth polysilicon layer 312.

[0050] The cross-sectional area of ​​the first passivation contact region 21 and the second passivation contact region 31 is smaller than the cross-sectional area of ​​the first passivation non-contact region 22 and the second passivation non-contact region 32.

[0051] A method for preparing a TBC battery structure includes the following steps:

[0052] S1. Polishing: Silicon wafer 1 is polished using an alkaline solution. Polishing is performed by adding a polishing additive with a volume fraction of 2% to an 8% NaOH alkaline solution to remove the damaged layer and form a flat planar structure with a grain size of 25µm.

[0053] S2, Polysilicon stack deposition: A stack of tunneling oxide (SiO2) and polysilicon (Poly) layers is deposited on the back side of the polished silicon wafer 1; the first tunneling layer 221 of the first passivation non-contact region 21 and the third tunneling layer 321 of the second passivation non-contact region 31 have the same thickness, both being 1.5~2.5nm.

[0054] The second tunneling layer 211 of the first passivation contact region 21 and the fourth tunneling layer 311 of the second passivation contact region 31 have the same thickness, both being 0.5~1.5nm.

[0055] The first polysilicon layer 222 of the first passivation non-contact region 22 and the third polysilicon layer 322 of the second passivation non-contact region 32 have the same thickness, both being 30~100nm.

[0056] The second polysilicon layer 212 of the first passivation contact region 21 and the fourth polysilicon layer 312 of the second passivation contact region 31 have the same thickness, both being 100~300nm.

[0057] S3, PN doped source fabrication: P-type and N-type doped sources are directionally implanted using a printing method to achieve specific patterns;

[0058] The doping concentration of the first polysilicon layer is 1×10⁻⁶. 19 atom / cm 3 ~5×10 19 atom / cm 3 The doping concentration of the second polysilicon layer is 5×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the third polysilicon layer is 5×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the fourth polysilicon layer is 1×10⁻⁶. 20 atom / cm 3 ~1×10 21 atom / cm 3 ;

[0059] S4. Annealing: The printed silicon wafer 1 is subjected to high-temperature annealing to achieve PN region doping. The annealing time is 25 minutes and the annealing temperature is 850℃.

[0060] S5. Laser patterning: After annealing, the wafer is patterned to remove the phosphorus silicate glass and borosilicate glass that are not in contact with the electrodes, as well as the stacked tunneling oxide layer and polysilicon layer in the undoped area.

[0061] S6. Texturing: Texturing is performed on the front side of the patterned silicon wafer 1, and the second polysilicon layer 212 and the fourth polysilicon layer 312 that are not in contact with the electrodes in the PN region on the back side are removed, as well as the undoped GAP (height difference) is formed.

[0062] S7. Passivation: Passivation films are deposited on the front and back sides of the texturized silicon wafer 1. Al2O3 is deposited using an ALD device with trimethylaluminum (TMA) and water (H2O) as reaction sources. A passivation antireflection film is deposited using a PECVD device with silane (SiH4), ammonia (NH3), and nitrous oxide (N2O) as reaction gases. The film layer is silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx) in a weight ratio of 1:1:1, and the film thickness is 3nm.

[0063] S8. Metallization: P-type and N-type silver pastes are printed on the back side of the passivated silicon wafer 1, and then sintered to complete the electrode preparation.

[0064] Example 2-3

[0065] A TBC battery structure differs from Example 1 in that the process parameters of the preparation method are different.

[0066] The fabrication process parameters of the TBC battery structures in Examples 1-3 are shown in Table 1.

[0067] Table 1. Fabrication process parameters of TBC battery structures in Examples 1-3

[0068]

[0069] Comparative Example

[0070] Comparative Examples 1-2

[0071] One TBC battery structure differs from Example 2 in that the annealing temperature in S4 is different.

[0072] The annealing temperature in S4 of Comparative Example 1 is 820℃.

[0073] The annealing temperature in S4 of Comparative Example 2 is 980℃.

[0074] Comparative Example 3

[0075] like Figure 1As shown, a TBC battery structure differs from Embodiment 2 in that it includes a first region 2 and a second region 3 deposited on a silicon wafer 1. The first region 2 includes a first tunneling layer 221 and a first polycrystalline silicon layer 222 sequentially disposed from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. A first electrode 4 is provided on the side of the first polycrystalline silicon layer 222 away from the first tunneling layer 221. The first region 2 also includes a third tunneling layer 321 and a third polycrystalline silicon layer 322 sequentially disposed from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. A second electrode 5 is provided on the side of the third polycrystalline silicon layer 322 away from the third tunneling layer 321. The fabrication method includes polishing, P Poly, boron diffusion, primary patterning, etching, N Poly, phosphorus diffusion, secondary patterning, texturing, and passivation steps to form the back structure of the battery. The phosphorus diffusion temperature is 900°C and the diffusion time is 100 min. The boron diffusion temperature is 830°C and the boron diffusion time is 15 min.

[0076] The changes in the back structure of the battery during the preparation process of Comparative Example 3 and Example 2 are shown in the figure. Figure 3 As shown.

[0077] Comparative Example 4

[0078] A TBC battery structure differs from Example 2 in that, in step 5, the phosphorus silicate glass and borosilicate glass in contact with the electrodes, as well as the stacked tunneling oxide layer and polycrystalline silicon layer in the undoped region, are not removed; and in step 6, the second and fourth polycrystalline silicon layers in the back PN region that are not in contact with the electrodes and the undoped GAP layer are not removed simultaneously.

[0079] Performance testing

[0080] The battery structures of Examples 1-3 and Comparative Examples 1-2 were tested using a Sinton WCT120 device, and the test results are shown in Table 2.

[0081] Table 2 Test results of Examples 1-3 and Comparative Examples 1-2

[0082]

[0083] As can be seen from the test results in Table 2, Examples 1-3 are superior to Comparative Examples 1-2. This is because the P / N Poly layer is completed in one step in the preparation method of this application, resulting in the same stacked structure. Furthermore, two different polarities of doping are achieved at the same annealing temperature. When the annealing temperature is between 850-950℃, the prepared battery structure exhibits good performance. When the temperature is below this range (i.e., Comparative Example 1), the activation amount of the dopant source is insufficient, leading to a deterioration in performance. When the temperature is above this range (i.e., Comparative Example 2), the dopant source is over-activated, thereby damaging the oxide layer and forming a passivation effect, resulting in a deterioration in battery performance.

[0084] The battery structures of Example 2 and Comparative Example 3 were tested, and the test results are shown in Table 3.

[0085] Table 3 Test results of Example 2 and Comparative Example 3

[0086]

[0087] Combining Example 2 and Comparative Example 3 with the test results in Table 3, it can be seen that the test results of the TBC battery structure of this application, such as short-circuit current density, open-circuit voltage, fill factor, and photoelectric conversion efficiency, are basically at or better than those of Comparative Example 3. It is speculated that this may be because the battery structure of Example 2 of this application, by setting a second polycrystalline silicon layer and a fourth polycrystalline silicon layer of the same thickness, can, on the one hand, block the penetration of some doping sources, thereby making the concentration in the poly layer present in a stepped distribution and improving the battery efficiency; on the other hand, it can prevent the printed silver paste from etching the non-contact area and protect the structural integrity of the non-contact area.

[0088] In addition, combined with the appendix Figure 3 It can also be seen that, in terms of the preparation process, the preparation process of Comparative Example 3 requires high-temperature diffusion of two different electrodes at two different temperatures. For different electrodes, different optimal temperatures are required to improve the battery performance. Therefore, for the technical solution of Comparative Example 3, the improvement of battery efficiency depends on using different optimal temperatures for different electrodes to improve battery performance. However, in Example 2 of this application, the same annealing temperature is used for two different electrodes to control the temperature balance point when the two electrodes activate the ion source. Although some battery performance will be sacrificed, by adjusting the process, the doping of the ion source is carried out in a directional doping manner, and during the texturing process, some of the second and fourth polycrystalline silicon layers that are not in contact with the electrodes are removed. While retaining their contact performance, parasitic absorption is reduced and passivation performance is satisfied, thereby improving battery efficiency.

[0089] Example 2 and Comparative Example 4 were tested, and the test results are shown in Table 4.

[0090] Table 4 Test results of Example 2 and Comparative Example 4

[0091]

[0092] Based on the experimental data test results in Example 2 and Comparative Example 4, it can be seen that when the second and fourth polycrystalline silicon layers that are not in contact with the electrode are not removed (Comparative Example 4), the electrode structure will have large parasitic absorption, resulting in a decrease in battery efficiency.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A TBC battery structure, comprising a first region (2) and a second region (3) alternately spaced and deposited on the back side of a silicon wafer (1), characterized in that, The first region (2) includes a first passivated contact region (21), a first passivated non-contact region (22) and a first electrode (4), and the second region (3) includes a second passivated contact region (31), a second passivated non-contact region (32) and a second electrode (5). The first region (2) and the second region (3) have opposite polarities. The first passivation non-contact region (22) includes a first tunneling layer (221) and a first polysilicon layer (222) sequentially disposed from the side close to the silicon wafer (1) to the side away from the silicon wafer (1). The first passivation contact region (21) includes a second tunneling layer (211) and a second polysilicon layer (212) sequentially disposed from the side close to the first polysilicon layer (222) to the side away from the first polysilicon layer (222). The first electrode (4) forms an ohmic contact with the second polysilicon layer (212). The second passivation non-contact region (32) includes a third tunneling layer (321) and a third polysilicon layer (322) sequentially disposed from the side near the silicon wafer (1) to the side away from the silicon wafer (1). The second passivation contact region (31) includes a fourth tunneling layer (311) and a fourth polysilicon layer (312) sequentially disposed from the side near the third polysilicon layer (322) to the side away from the third polysilicon layer (322). The second electrode (5) forms an ohmic contact with the fourth polysilicon layer (312). The cross-sectional areas of the first passivation contact area (21) and the second passivation contact area (31) are both smaller than the cross-sectional areas of the first passivation non-contact area (22) and the second passivation non-contact area (32); The first polysilicon layer (222) of the first passivation non-contact region (22) and the third polysilicon layer (322) of the second passivation non-contact region (32) have the same thickness, both being 30~100nm; The second polysilicon layer (212) of the first passivation contact region (21) and the fourth polysilicon layer (312) of the second passivation contact region (31) have the same thickness, both being 100~200nm.

2. The TBC battery structure according to claim 1, characterized in that: The first tunneling layer (221) of the first passivation non-contact region (22) and the third tunneling layer (321) of the second passivation non-contact region (32) have the same thickness, both being 1.5~2.5nm.

3. The TBC battery structure according to claim 1, characterized in that: The second tunneling layer (211) of the first passivation contact region (21) and the fourth tunneling layer (311) of the second passivation contact region (31) have the same thickness, both being 0.5~1.5nm.

4. A method for preparing a TBC battery structure according to any one of claims 1-3, characterized in that: Includes the following steps: S1. Polishing: The silicon wafer (1) is polished with alkaline solution to remove the damaged layer and form a flat planar structure. S2, Polysilicon stack deposition: A stack is deposited on the back side of the polished silicon wafer (1). First, the first tunneling layer (221) and the third tunneling layer (321) are deposited simultaneously. Then, the first polysilicon layer (222) and the third polysilicon layer (322), the second tunneling layer (211) and the fourth tunneling layer (311), the second polysilicon layer (212) and the fourth polysilicon layer (312) are deposited simultaneously in sequence. S3, PN doped source fabrication: P-type and N-type doped sources are directionally implanted using a printing method to achieve specific patterns; S4, Annealing: The printed silicon wafer (1) is annealed at high temperature to achieve PN region doping. The annealing temperature is 850-950℃ and the annealing time is 10-40 minutes. S5, Laser Patterning: The annealed silicon wafer (1) is patterned to remove the phosphorus silicate glass and borosilicate glass that are not in contact with the electrodes, as well as the stacked tunneling oxide layer and polycrystalline silicon layer in the undoped area. S6. Texturing: Texturing is performed on the front side of the patterned silicon wafer (1), while the second polysilicon layer (212) and the fourth polysilicon layer (312) that are not in contact with the electrodes in the back PN region are thinned and undoped to form GAP. S7, passivation: Passivation film is deposited on the front and back sides of the textured silicon wafer (1) respectively, with a film thickness of 3-8nm; S8. Metallization: P-type and N-type silver pastes are printed on the back side of the passivated silicon wafer (1) respectively, and the electrode is prepared by sintering.

5. The method for preparing a TBC battery structure according to claim 4, characterized in that: In step 3, the doping concentration of the first polysilicon layer is 1×10⁻⁶. 19 atom / cm 3 ~5×10 19 atom / cm 3 The doping concentration of the second polysilicon layer is 5×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the third polysilicon layer is 5×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 The fourth polysilicon layer has a doping concentration of 1×10⁻⁶. 20 atom / cm 3 ~1×10 21 atom / cm 3 .

6. The method for preparing a TBC battery structure according to claim 4, characterized in that: In step 7, the raw material of the passivation film is two or more of aluminum oxide, silicon nitride, silicon oxynitride, or silicon oxide.

7. The method for preparing a TBC battery structure according to claim 4, characterized in that: In step 1, the grain size of the planar structure is 25-30 μm.

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