Light emitting diode, display device, and deposition apparatus

Abstract

A light emitting diode, a display device, and a deposition apparatus are provided. The light emitting diode includes: a pixel electrode; a first functional layer on the pixel electrode; an emission layer on the first functional layer; a second functional layer on the emission layer; and an opposing electrode on the second functional layer, where the second functional layer comprises: an auxiliary electron transport layer on the emission layer and comprising a first deposition material; a mixed layer on the auxiliary electron transport layer and including the first deposition material, the second deposition material, and the third deposition material; and an electron transport layer on the mixed layer and including the second deposited material and the third deposited material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0112288 filed in the Korean Intellectual Property Office on August 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments of the present disclosure relate to a light emitting diode, a display device including the light emitting diode, and a deposition device for forming the light emitting diode. For example, one or more embodiments relate to a light emitting diode including an electron transport layer, an auxiliary electron transport layer, and a mixed layer, a display device including the light emitting diode, and a deposition device for forming the light emitting diode. Background Art

[0004] Typically, a display device may include a light emitting diode including a pixel electrode, an emission layer, and a relative (e.g., a pair) electrode. The light emitting diode receives holes and electrons injected from the pixel electrode and the relative electrode, respectively, to form excitons, and emits light as the excitons transition (e.g., relax) to a ground state. A deposition device may be used to form an organic thin film, a metal thin film, and the like on a substrate of a display device. The deposition device may include a deposition source containing a deposition material and an ejection port for ejecting the deposition material. When the deposition source is heated to a set or predetermined temperature, the deposition material in the deposition source is evaporated, and the evaporated deposition material is ejected through the ejection port. If (e.g., when) the deposition material ejected from the ejection port is formed or deposited on a substrate, a thin film may be formed.

[0005] The above information disclosed in this Background section is provided for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute related (or prior) art. Summary of the invention

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to one or more embodiments of the present disclosure, a light-emitting diode includes: a pixel electrode; a first functional layer on the pixel electrode; an emission layer on the first functional layer; a second functional layer on the emission layer; and a relative (e.g., counter) electrode on the second functional layer, wherein the second functional layer includes: an auxiliary electron transport layer on the emission layer and comprising a first deposition material; a mixing layer on the auxiliary electron transport layer and comprising the first deposition material, the second deposition material, and the third deposition material; and an electron transport layer on the mixing layer and comprising the second deposition material and the third deposition material.

[0008] In one or more embodiments, a lowest unoccupied molecular orbital (LUMO) energy level of the mixed layer may be lower than the LUMO energy level of the auxiliary electron transport layer and higher than the LUMO energy level of the electron transport layer.

[0009] In one or more embodiments, the LUMO energy level of the auxiliary electron transport layer may be lower than the LUMO energy level of the emission layer.

[0010] In one or more embodiments, a highest occupied molecular orbital (HOMO) energy level of the mixed layer may be lower than the HOMO energy level of the emission layer and the HOMO energy level of the electron transport layer.

[0011] In one or more embodiments, the thickness of the mixed layer may be smaller than the thickness of the electron transport layer.

[0012] In one or more embodiments, the thickness of the mixed layer may be about 20 angstroms. to about

[0013] In one or more embodiments, the thickness of the mixed layer may be equal to or greater than the thickness of the auxiliary electron transport layer.

[0014] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a thin film transistor on the substrate; a pixel electrode electrically connected to the thin film transistor; a first functional layer on the pixel electrode; an emission layer on the first functional layer; a second functional layer on the emission layer; and a relative electrode on the second functional layer, wherein the second functional layer includes: an auxiliary electron transport layer on the emission layer and comprising a first deposition material; a mixed layer on the auxiliary electron transport layer and comprising the first deposition material, the second deposition material and the third deposition material; and an electron transport layer on the mixed layer and comprising the second deposition material and the third deposition material.

[0015] In one or more embodiments, the LUMO energy level of the mixed layer may be lower than the LUMO energy level of the auxiliary electron transport layer and higher than the LUMO energy level of the electron transport layer.

[0016] In one or more embodiments, the LUMO energy level of the auxiliary electron transport layer may be lower than the LUMO energy level of the emission layer.

[0017] In one or more embodiments, the HOMO energy level of the mixed layer may be lower than the HOMO energy level of the emission layer and the HOMO energy level of the electron transport layer.

[0018] In one or more embodiments, the thickness of the mixed layer may be smaller than the thickness of the electron transport layer.

[0019] In one or more embodiments, the thickness of the mixed layer may be about to about

[0020] According to one or more embodiments of the present disclosure, a deposition device for forming a functional layer including an electron transport layer on a deposition substrate includes: a first deposition source, a second deposition source and a third deposition source, arranged in a first direction; a first injection port, configured to inject a first deposition material from the first deposition source to a first area of ​​the deposition substrate; a second injection port, configured to inject a second deposition material from the second deposition source to a second area of ​​the deposition substrate; a third injection port, configured to inject a third deposition material from the third deposition source to a third area of ​​the deposition substrate; a first angle limiting plate, located outside the first injection port; a second angle limiting plate, between the first injection port and the second injection port; a third angle limiting plate, between the second injection port and the third injection port; and a fourth angle limiting plate, located outside the third injection port, wherein a portion of the first area overlaps with the second area and the third area.

[0021] In one or more embodiments, the second area may completely overlap with the third area.

[0022] In one or more embodiments, the first injection port may be limited (e.g., controlled) by the first angle limiting plate to inject the first deposition material onto the deposition substrate at a first incident angle, the first injection port may be limited by the second angle limiting plate to inject the first deposition material onto the deposition substrate at a second incident angle, and the first incident angle may be greater than the second incident angle.

[0023] In one or more embodiments, the second injection port is limited by the second angle limiting plate to inject the second deposition material onto the deposition substrate at a third incident angle, and the second incident angle may be smaller than the third incident angle.

[0024] In one or more embodiments, the second incident angle may be about 55° to about 65°.

[0025] In one or more embodiments, the third incident angle may be about 70° to about 80°.

[0026] In one or more embodiments, the second injection port is limited by the third angle limiting plate to inject the second deposition material onto the deposition substrate at a fourth incident angle, and the third injection port is limited by the third angle limiting plate to inject the third deposition material onto the deposition substrate at a fifth incident angle, and the fourth incident angle may be smaller than the third incident angle, the fourth incident angle may be smaller than the fifth incident angle, and the fifth incident angle may be smaller than the third incident angle. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and / or principles of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a schematic cross-sectional view illustrating a deposition apparatus for depositing an auxiliary electron transport layer, a mixed layer, and an electron transport layer according to one or more embodiments of the present disclosure;

[0029] Figure 2 is an example of a method according to one or more embodiments of the present disclosure. Figure 1 A schematic cross-sectional view of an auxiliary electron transport layer, a mixed layer, and an electron transport layer formed or deposited on an emission layer by a deposition device;

[0030] Figure 3 is a diagram illustrating energy bands of an emission layer, an auxiliary electron transport layer, a mixed layer, and an electron transport layer according to one or more embodiments of the present disclosure;

[0031] Figure 4 is a graph showing a ratio of a first deposition material to a third deposition material according to a thickness of a film formed or deposited by a deposition apparatus according to one or more embodiments of the present disclosure;

[0032] Figure 5 is a table showing driving voltage and luminance according to comparative examples and embodiments of the present disclosure;

[0033] Figure 6 It is shown Figure 5 A graph of current density versus voltage for comparative examples and embodiments of the present invention; and

[0034] Figure 7 is a schematic cross-sectional view illustrating a display device including a light emitting diode formed by a deposition apparatus according to one or more embodiments of the present disclosure. Specific embodiments

[0035] The present disclosure can be modified in many alternative forms, and therefore specific embodiments will be illustrated in the drawings and described in more detail. However, it should be understood that this is not intended to limit the present disclosure to the specific form disclosed, but is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present disclosure.

[0036] Now will refer to embodiment in more detail, the example of embodiment is illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements, and its repeated description may not be provided. In this regard, the present embodiment may have different forms, and should not be construed as being limited to the description set forth herein. Accordingly, the embodiment is described below only by reference to the accompanying drawings to explain the aspects of this specification. Embodiments are provided as examples so that the present disclosure will be detailed and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Accordingly, it may not be described that a person of ordinary skill in the art is in order to fully understand the aspects and features of the present disclosure rather than necessary processes, elements and techniques.

[0037] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b or c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof. Unless otherwise apparent from the present disclosure, expressions such as "at least one of...", "a plurality of", "one of..." and other prepositional phrases, when before / after a list of elements, should be understood to include separation if written as a connected list, and vice versa. For example, the expression "at least one of a, b or c", "at least one of a, b and / or c", "one selected from the group consisting of a, b and c", "selected from at least one of a, b and c", "at least one of a, b and c", "one of a, b and c", "at least one of a to c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0038] Since the present disclosure allows various changes and many embodiments, specific embodiments will be illustrated in the drawings and described in more detail in the written description. The effects and features of the present disclosure and the manner in which they are achieved will become apparent by reference to the embodiments that will be described in more detail later with reference to the drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms.

[0039] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same reference numerals refer to the same elements, and redundant descriptions thereof will not be provided.

[0040] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or section described below may be referred to as a second element, component, region, layer or section.

[0041] For ease of explanation, spatial relative terms such as "below", "down", "above", "upper", etc. may be used herein to describe the relationship between an element or feature and another element or feature as illustrated in the figure. It will be understood that, in addition to the orientation depicted in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as "below" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can cover both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0042] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0043] It will be further understood that the terms “include” and “comprising” when used in this specification explicitly indicate the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0044] It will be understood that when an element, such as a zone, region, or layer, is referred to as being "on," "connected to," or "over" another element, it can be directly on, connected to, or coupled to the other element, or there can be one or more intervening elements. For example, herein, when an element (e.g., a zone, region, or layer) is described as being electrically connected, it means both when the element is directly electrically connected and / or when the element is indirectly electrically connected with other elements therebetween. Additionally, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there can also be one or more intervening elements.

[0045] Herein, “A and / or B” may mean only A, only B, or both A and B. Also, “at least one of A and B” may mean only A, only B, or both A and B.

[0046] In this article, the x-axis, y-axis and z-axis are not limited to the three axes on the rectangular coordinate system, but can be interpreted as including these axes. For example, the x-axis, y-axis and z-axis can be at right angles, or can also represent different directions from each other, which are not at right angles.

[0047] In the drawings, the size of the elements may be exaggerated or reduced for convenience of explanation. For example, since the size and thickness of the elements in the drawings are illustrated (eg, arbitrarily illustrated) for convenience of explanation, the following embodiments are not limited thereto.

[0048] Figure 1 is a schematic cross-sectional view illustrating a deposition apparatus 1 for depositing an auxiliary electron transport layer a-ETL, a mixed layer ETL′, and an electron transport layer ETL according to one or more embodiments of the present disclosure. Figure 2 is an example of a method according to one or more embodiments of the present disclosure. Figure 1 Schematic cross-sectional view of an auxiliary electron transport layer a-ETL, a mixed layer ETL′, and an electron transport layer ETL formed or deposited on an emission layer EML by a deposition apparatus 1 . Figure 3 is a diagram illustrating energy bands of an emission layer EML, an auxiliary electron transport layer a-ETL, a mixed layer ETL′, and an electron transport layer ETL according to one or more embodiments of the present disclosure.

[0049] refer to Figure 1 and Figure 2 , the deposition apparatus 1 may include a first deposition source 21, a second deposition source 22, and a third deposition source 23. The deposition apparatus 1 may include a first angle limiting plate 40a, a second angle limiting plate 45, a third angle limiting plate 46, and a fourth angle limiting plate 40b.

[0050] The first deposition source 21, the second deposition source 22, and the third deposition source 23 may be arranged along the first direction DR1. The second deposition source 22 may be located between the first deposition source 21 and the third deposition source 23. In one or more embodiments, the first to third deposition sources 21, 22, and 23 may be located at (eg, in) a single susceptor 10.

[0051] The deposition apparatus 1 may reciprocate in a first horizontal direction (eg, DR1 direction) and a second horizontal direction (eg, −DR1 direction) opposite to the first horizontal direction (eg, DR1 direction).

[0052] The first to third deposition sources 21, 22, and 23 may evaporate or sublimate deposition materials. The first deposition source 21, the second deposition source 22, and the third deposition source 23 may evaporate or sublimate the first deposition material 11, the second deposition material 12, and the third deposition material 13, respectively. As the first to third deposition sources 21, 22, and 23 evaporate or sublimate the first to third deposition materials 11, 12, and 13 stored therein, respectively, the first to third injection ports 31, 32, and 33 may respectively spray the first to third deposition materials 11, 12, and 13 in the direction where the deposition substrate 100 is located (e.g., in the DR2 direction). In one or more embodiments, the first to third deposition sources 21, 22, and 23 include a crucible filled with deposition materials and a heater for heating the crucible to evaporate or sublimate the deposition material filled inside the crucible.

[0053] The deposition apparatus 1 may further include a first injection port 31 formed or disposed on the first deposition source 21, a second injection port 32 formed or disposed on the second deposition source 22, and a third injection port 33 formed or disposed on the third deposition source 23. The first injection port 31 may inject the first deposition material 11 evaporated or sublimated in the first deposition source 21 to a first region of the deposition substrate 100 in a direction (e.g., DR2 direction) where the deposition substrate 100 is located. The second injection port 32 may inject the second deposition material 12 evaporated or sublimated in the second deposition source 22 to a second region of the deposition substrate 100 in a direction (e.g., DR2 direction) where the deposition substrate 100 is located. The third injection port 33 may inject the third deposition material 13 evaporated or sublimated in the third deposition source 23 to a third region of the deposition substrate 100 in a direction (e.g., DR2 direction) where the deposition substrate 100 is located.

[0054] The deposition apparatus 1 may include first to fourth angle limiting plates 40 a , 45 , 46 , and 40 b to limit incident angles of the first to third deposition materials 11 , 12 , and 13 incident on the deposition substrate 100 .

[0055] The first angle limiting plate 40a may be located outside the first injection port 31 (e.g., adjacent to the outside of the first injection port 31). The fourth angle limiting plate 40b may be located outside the third injection port 33 (e.g., adjacent to the outside of the third injection port 33). Each of the second angle limiting plate 45 and the third angle limiting plate 46 may be located between the first angle limiting plate 40a and the fourth angle limiting plate 40b. The second angle limiting plate 45 may be located between the first injection port 31 and the second injection port 32. The third angle limiting plate 46 may be located between the second injection port 32 and the third injection port 33.

[0056] In one or more embodiments of the present disclosure, the incident angle of the first deposition material 11 ejected from the first ejection port 31 limited by the first angle limiting plate 40a with respect to the deposition substrate 100 may be defined as a first incident angle θ1 (for example, the first ejection port 31 may be limited by the first angle limiting plate 40a so that the first deposition material 11 is ejected to the deposition substrate 100 at the first incident angle θ1). The incident angle of the first deposition material 11 ejected from the first ejection port 31 limited by the second angle limiting plate 45 with respect to the deposition substrate 100 may be defined as a second incident angle θ2 (for example, the first ejection port 31 may be limited by the second angle limiting plate 45 so that the first deposition material 11 is ejected to the deposition substrate 100 at the second incident angle θ2). The incident angle of the second deposition material 12 ejected from the second ejection port 32 limited by the second angle limiting plate 45 with respect to the deposition substrate 100 may be defined as a third incident angle θ3 (for example, the second ejection port 32 may be limited by the second angle limiting plate 45 so that the second deposition material 12 is ejected to the deposition substrate 100 at the third incident angle θ3). The incident angle of the second deposition material 12 ejected from the second ejection port 32 limited by the third angle limiting plate 46 with respect to the deposition substrate 100 may be defined as a fourth incident angle θ4 (for example, the second ejection port 32 may be limited by the third angle limiting plate 46 so that the second deposition material 12 is ejected to the deposition substrate 100 at the fourth incident angle θ4). The incident angle of the third deposition material 13 ejected from the third ejection port 33 limited by the third angle limiting plate 46 with respect to the deposition substrate 100 may be defined as a fifth incident angle θ5 (for example, the third ejection port 33 may be limited by the third angle limiting plate 46 so that the third deposition material 13 is ejected to the deposition substrate 100 at the fifth incident angle θ5). The incident angle of the third deposition material 13 ejected from the third ejection port 33 limited by the fourth angle limiting plate 40b with respect to the deposition substrate 100 may be defined as a sixth incident angle θ6 (for example, the third ejection port 33 may be limited by the fourth angle limiting plate 40b so that the third deposition material 13 is ejected to the deposition substrate 100 at the sixth incident angle θ6).

[0057] The first to fourth angle limiting plates 40a, 45, 46, and 40b may limit the incident angles of the first to third deposition materials 11, 12, and 13 so that a portion of the first region where the first deposition material 11 is formed or deposited overlaps with a second region where the second deposition material 12 is formed or deposited and a third region where the third deposition material 13 is formed or deposited. For example, the first to fourth angle limiting plates 40a, 45, 46, and 40b may limit the incident angles of the first to third deposition materials 11, 12, and 13 so that the second deposition material 12 and the third deposition material 13 are formed or deposited together with the first deposition material 11 in a portion of the first region where the first deposition material 11 is formed or deposited, and only the first deposition material 11 is formed or deposited in the remaining region of the first region. The second to fourth angle limiting plates 45, 46, and 40b may limit the incident angles of the second deposition material 12 and the third deposition material 13 so that the entire second region where the second deposition material 12 is formed or deposited overlaps (e.g., completely overlaps) with the third region where the third deposition material 13 is formed or deposited. Accordingly, the deposition apparatus 1 may form an auxiliary electron transport layer a-ETL including the first deposition material 11 , a mixed layer ETL′ including the first deposition material 11 , the second deposition material 12 , and the third deposition material 13 , and an electron transport layer ETL including the second deposition material 12 and the third deposition material 13 .

[0058] The first incident angle θ1 may be greater than the second incident angle θ2. For example, the first incident angle θ1 may be about 75° to about 85°. For example, the second incident angle θ2 may be about 55° to about 65°. The second incident angle θ2 may be less than the third incident angle θ3. The third incident angle θ3 may be less than the first incident angle θ1. For example, the third incident angle θ3 may be about 70° to about 80°. The fourth incident angle θ4 may be less than the second incident angle θ2. The fourth incident angle θ4 may be less than the third incident angle θ3. For example, the fourth incident angle θ4 may be about 35° to about 45°. The fifth incident angle θ5 may be less than the third incident angle θ3. The fifth incident angle θ5 may be greater than the fourth incident angle θ4. For example, the fifth incident angle θ5 may be about 45° to about 55°. The sixth incident angle θ6 may be greater than the fourth incident angle θ4. The sixth incident angle θ6 may be greater than the fifth incident angle θ5. For example, the sixth incident angle θ6 may be about 50° to about 60°.

[0059] In one or more embodiments of the present disclosure, the second incident angle θ2 is limited to be smaller than the third incident angle θ3, and the fifth incident angle θ5 is limited to be smaller than the third incident angle θ3 by the second angle limiting plate 45 and the third angle limiting plate 46, and therefore, the first deposition material 11, the second deposition material 12, and the third deposition material 13 may be formed or deposited together to form the mixed layer ETL'. For example, since the second incident angle θ2 is limited to about 55° to about 65°, the third incident angle θ3 is limited to about 70° to about 80°, and the fifth incident angle θ5 is limited to about 45° to about 55°, the first deposition material 11, the second deposition material 12, and the third deposition material 13 may be formed or deposited together to form the mixed layer ETL'.

[0060] In one or more embodiments of the present disclosure, the fifth incident angle θ5 is limited to be smaller than the third incident angle θ3, and the fourth incident angle θ4 is limited to be smaller than the sixth angle limiting plate θ6 by the second to fourth angle limiting plates 45, 46, 40b, and therefore, the second deposition material 12 and the third deposition material 13 may be formed or deposited together to form the electron transport layer ETL. For example, since the third incident angle θ3 is limited to about 70° to about 80°, the fourth incident angle θ4 is limited to about 35° to about 45°, and the fifth incident angle θ5 is limited to about 45° to about 55°, and the sixth incident angle θ6 is limited to about 50° to about 60°, the second deposition material 12 and the third deposition material 13 may be formed or deposited together to form the electron transport layer ETL.

[0061] The deposition apparatus 1 may further include a slide shutter 50. The slide shutter 50 is located above the first spray port 31, and may control deposition of the first deposition material 11 by reciprocating in a first horizontal direction (eg, DR1 direction).

[0062] For example, when the deposition apparatus 1 has closed the slide shutter 50, the slide shutter 50 may move in a second horizontal direction (e.g., −DR1 direction) opposite to the first horizontal direction (e.g., DR1 direction) to block or reduce the spray path of the first spray port 31 and to block or reduce the deposition of the first deposition material 11. In one or more embodiments, when the deposition apparatus 1 has opened the slide shutter 50, the slide shutter 50 may move in the first horizontal direction (e.g., DR1 direction) to open the spray path of the first spray port 31.

[0063] refer to Figure 2 , by reference Figure 1 The deposition device 1 described above, the auxiliary electron transport layer a-ETL, the mixed layer ETL' and the electron transport layer ETL can be stacked in sequence. Figure 7The second functional layer 225 of the organic light emitting diode OLED described in more detail has a multi-layer structure including an auxiliary electron transport layer a-ETL, a mixed layer ETL′, and an electron transport layer ETL.

[0064] The first to third deposition sources 21, 22, and 23 may reciprocate in a first horizontal direction (e.g., DR1 direction), and deposit the first to third deposition materials 11, 12, and 13 on the deposition substrate 100 to form an auxiliary electron transport layer a-ETL, a mixed layer ETL', and an electron transport layer ETL. When the first to third deposition materials 11, 12, and 13 are respectively sprayed through the first to third injection ports 31, 32, and 33, the first to third injection ports 31, 32, and 33 may reciprocate in a first horizontal direction (e.g., DR1 direction) together with the first to fourth angle limiting plates 40a, 45, 46, and 40b. The first horizontal direction (e.g., DR1 direction) may be a direction from the second injection port 32 to the first injection port 31.

[0065] The emission layer EML can be Figure 2 It is exemplarily shown that they are formed or disposed on the deposition substrate 100, and the auxiliary electron transport layer a-ETL, the mixed layer ETL′, and the electron transport layer ETL may be sequentially stacked on the emission layer EML.

[0066] An auxiliary electron transport layer a-ETL including a first deposition material 11 may be formed or disposed on the emission layer EML. A mixed layer ETL' including first to third deposition materials 11, 12, and 13 may be formed or disposed on the auxiliary electron transport layer a-ETL. The mixed layer ETL' may be arranged between the auxiliary electron transport layer a-ETL and the electron transport layer ETL. An electron transport layer ETL including a second deposition material 12 and a third deposition material 13 may be formed or disposed on the mixed layer ETL'. The electron transport layer ETL may be formed or disposed on the auxiliary electron transport layer a-ETL.

[0067] The thickness of the auxiliary electron transport layer a-ETL may be smaller than the thickness of the electron transport layer ETL.

[0068] The thickness of the mixed layer ETL' may be less than the thickness of the electron transport layer ETL. The thickness of the mixed layer ETL' may be substantially the same as or greater than the thickness of the auxiliary electron transport layer a-ETL, but the present disclosure is not limited thereto. The thickness of the mixed layer ETL' may be, for example, about 20 angstroms. to about When the incident angle is limited by the angle limiting plate of the deposition apparatus 1, as in one or more embodiments of the present disclosure, the thickness of the hybrid layer ETL' may be about to about In one or more embodiments, the thickness of the hybrid layer ETL′ may be, for example, about to about If (for example, when) the thickness of the hybrid layer ETL' is less than Then the electron movement may be relatively difficult and the driving voltage may increase, and if (for example, when) the thickness of the mixed layer ETL' is greater than Then, the thickness of the electron transport layer ETL may become relatively small, thereby deteriorating the characteristics of the electron transport layer ETL.

[0069] In one or more embodiments, when the sliding shutter 50 is opened, the deposition device 1 can move in a first horizontal direction (e.g., DR1 direction) so that the first ejection port 31 faces the deposition substrate 100 including the emission layer EML, thereby sequentially forming the auxiliary electron transport layer a-ETL, the mixed layer ETL', and a portion of the electron transport layer ETL, and when the sliding shutter 50 is closed, the deposition device 1 can move in a second horizontal direction (e.g., -DR1 direction) to form other portions of the electron transport layer ETL. The number of reciprocating movements of the deposition device 1 may vary according to the embodiment.

[0070] refer to Figure 3 , shows the lowest unoccupied molecular orbital (LUMO) energy level of each of the emission layer EML, the auxiliary electron transport layer a-ETL, the mixed layer ETL′, and the electron transport layer ETL.

[0071] The LUMO energy level of the emission layer EML may be higher than the LUMO energy level of the electron transport layer ETL. An absolute value of the LUMO energy level of the emission layer EML may be smaller than an absolute value of the LUMO energy level of the electron transport layer ETL.

[0072] The LUMO energy level of the auxiliary electron transport layer a-ETL may be lower than the LUMO energy level of the emission layer EML and higher than the LUMO energy level of the electron transport layer ETL. The absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL may be greater than the absolute value of the LUMO energy level of the emission layer EML, and may be less than the absolute value of the LUMO energy level of the electron transport layer ETL. The absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL may be, for example, about 1.75 or less. The absolute value of the LUMO energy level of the electron transport layer ETL may be, for example, about 2.0 or greater. The energy gap G1 between the absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL and the absolute value of the LUMO energy level of the electron transport layer ETL may be, for example, about 0.25 eV to about 0.5 eV.

[0073] The LUMO energy level of the mixed layer ETL' may be lower than the LUMO energy level of the auxiliary electron transport layer a-ETL and higher than the LUMO energy level of the electron transport layer ETL. The absolute value of the LUMO energy level of the mixed layer ETL' may be greater than the absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL, and may be less than the absolute value of the LUMO energy level of the electron transport layer ETL. The energy gap G2 between the absolute value of the LUMO energy level of the mixed layer ETL' and the absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL may be less than the energy gap G1 between the absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL and the absolute value of the LUMO energy level of the electron transport layer ETL.

[0074] The mixed layer ETL' can be arranged between the auxiliary electron transport layer a-ETL and the electron transport layer ETL, and has a LUMO energy level value between the LUMO energy level of the auxiliary electron transport layer a-ETL and the LUMO energy level of the electron transport layer ETL, and therefore, the mixed layer ETL' can promote the movement of electrons from the electron transport layer ETL to the auxiliary electron transport layer a-ETL. Accordingly, the movement of electrons from the electron transport layer ETL to the emission layer EML through the auxiliary electron transport layer a-ETL can be promoted, and thus the driving voltage of the light emitting diode can be reduced.

[0075] The auxiliary electron transport layer a-ETL may be referred to as a hole blocking layer. The highest occupied molecular orbital (HOMO) energy level of the auxiliary electron transport layer a-ETL is lower than the HOMO energy level of the emission layer EML, and may be lower than the HOMO energy level of the electron transport layer ETL. The absolute value of the HOMO energy level of the auxiliary electron transport layer a-ETL may be greater than the absolute value of the HOMO energy level of the emission layer EML, and may be greater than or equal to the absolute value of the HOMO energy level of the electron transport layer ETL.

[0076] The HOMO energy level of the mixed layer ETL' may be lower than the HOMO energy level of the auxiliary electron transport layer a-ETL. The absolute value of the HOMO energy level of the mixed layer ETL' may be greater than the absolute value of the HOMO energy level of the auxiliary electron transport layer a-ETL. The HOMO energy level of the mixed layer ETL' may be lower than the HOMO energy level of the electron transport layer ETL. The absolute value of the HOMO energy level of the mixed layer ETL' may be greater than the absolute value of the HOMO energy level of the electron transport layer ETL. The HOMO energy level of the mixed layer ETL' may be lower than the HOMO energy level of the emission layer EML. The absolute value of the HOMO energy level of the mixed layer ETL' may be greater than the absolute value of the HOMO energy level of the emission layer EML.

[0077] Return to reference Figure 2, the auxiliary electron transport layer a-ETL may include a first deposition material 11, so that the absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL is less than the absolute value of the LUMO energy level of the electron transport layer ETL. The absolute value of the LUMO energy level of the layer formed or deposited using the first deposition material 11 may be less than the absolute value of the LUMO energy level of the layer formed or deposited using the second deposition material 12 and the third deposition material 13. The electron mobility of the layer formed or deposited by the first deposition material 11 may be greater than the electron mobility of the layer formed or deposited by the second deposition material 12 and the third deposition material 13. For example, the electron mobility of the auxiliary electron transport layer a-ETL may be greater than the electron mobility of the electron transport layer ETL. The first deposition material 11 may include, for example, triazine compounds, 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP) or 4,7-diphenyl-1,10-phenanthroline (Bphen), etc., but the present disclosure is not limited thereto.

[0078] The electron transport layer ETL may include a second deposition material 12 and a third deposition material 13, so that the absolute value of the LUMO energy level of the electron transport layer ETL is greater than the absolute value of the LUMO energy level of the auxiliary electron transport layer a-ETL. The second deposition material 12 and the third deposition material 13 may include, for example, a triazine compound or an anthracene compound, but the present disclosure is not limited thereto. The first deposition material 11, the second deposition material 12, and the third deposition material 13 may include materials different from each other. For example, the first deposition material 11, the second deposition material 12, and the third deposition material 13 may each include a triazine compound having different substituents. The second deposition material 12 and the third deposition material 13 may include, for example, tris(8-hydroxyquinoline)aluminum (Alq 3 ), 1,3,5-tris[(3-pyridyl)-phenyl-3-yl]benzene, 2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine, 1,3,5-tris(1-phenyl-1H-benzo[d]imidazol-2-yl)phenyl (TPBi), 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP), 4,7-diphenyl-1,10-phenanthroline (Bphen), 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4- triazole (TAZ), 4-(naphthalene-1-yl)-3,5-diphenyl-4H-1,2,4-triazole (NTAZ), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (tBu-PBD), bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq), bis(benzoquinoline-10-hydroxy)beryllium (Bebq2), 9,10-di(naphthalene-2-yl)anthracene (ADN) and / or any suitable mixture thereof.

[0079] The mixed layer ETL' may include a material included in the auxiliary electron transport layer a-ETL and a material included in the electron transport layer ETL. According to one or more embodiments, the second incident angle θ2 at which the first deposition material 11 is incident on the deposition substrate 100 is limited to about 55° to about 65° by the second angle limiting plate 45, and the first deposition material 11 may be formed or deposited together with the second deposition material 12 and the third deposition material 13 to form the mixed layer ETL'.

[0080] Figure 4 is a graph showing a ratio of a first deposition material to a third deposition material according to a thickness of a film formed or deposited by a deposition apparatus according to one or more embodiments of the present disclosure. In detail, Figure 4 A ratio of materials according to the thickness of a layer formed or deposited by a deposition device is shown, in which the first incident angle θ1 is limited to 78°, the second incident angle θ2 is limited to 60°, the third incident angle θ3 is limited to 72°, the fourth incident angle θ4 is limited to 38°, the fifth incident angle θ5 is limited to 50°, and the sixth incident angle θ6 is limited to 53°.

[0081] refer to Figure 4 , only the auxiliary electron transport layer a-ETL deposited with the first deposition material 11 is formed in the lowermost layer of the deposition film. The auxiliary electron transport layer a-ETL has a thickness of about The mixed layer ETL' deposited by the first to third deposition materials 11, 12 and 13 is formed on the auxiliary electron transport layer a-ETL. The mixed layer ETL' has a thickness of about The electron transport layer ETL deposited by the second deposition material 12 and the third deposition material 13 is formed on the mixed layer ETL'. The electron transport layer ETL has a thickness of about Thickness.

[0082] As described above, when the incident angle conditions of the first to third deposition materials 11, 12, and 13 are restricted by the angle restriction plates 40a, 45, 46, and 40b of the deposition apparatus 1 according to one or more embodiments, the mixed layer ETL′ may have to The mixed layer ETL′ promotes the movement of electrons from the electron transport layer ETL to the auxiliary electron transport layer a-ETL, as shown in the reference Figure 3 As described above, and therefore, a light emitting diode formed using the deposition apparatus 1 according to one or more embodiments may have improved electrical characteristics as the driving voltage is reduced, as shown in FIG. Figure 5 Described.

[0083] Figure 5 : is a table showing the driving voltage (Op.V) and the luminance (Cd / A) according to the comparative example and the embodiment. Figure 6 It is shown Figure 5 Graphs of current density versus voltage for Comparative Examples and Examples.

[0084] In comparative examples (a) to (e), the driving voltage, brightness, and current density relative to the voltage were measured at multiple points of a light-emitting diode formed or deposited by a deposition device that performs a reciprocating motion, wherein in the deposition device, the first incident angle θ1 was limited to 78°, the second incident angle θ2 was limited to 74°, the third incident angle θ3 was limited to 72°, the fourth incident angle θ4 was limited to 38°, the fifth incident angle θ5 was limited to 50°, and the sixth incident angle θ6 was limited to 53°.

[0085] In Examples 1a to 1d, the driving voltage, brightness, and current density relative to the voltage are measured at multiple points of a light-emitting diode formed or deposited by a deposition device that performs a reciprocating motion, wherein in the deposition device, the first incident angle θ1 is limited to 78°, the second incident angle θ2 is limited to 60°, the third incident angle θ3 is limited to 72°, the fourth incident angle θ4 is limited to 38°, the fifth incident angle θ5 is limited to 50°, and the sixth incident angle θ6 is limited to 53°.

[0086] In Example 2a and Example 2b, the driving voltage, brightness and current density relative to the voltage are measured at multiple points of a light-emitting diode formed or deposited by a deposition device performing two reciprocating movements, wherein in the deposition device, the first incident angle θ1 is limited to 78°, the second incident angle θ2 is limited to 60°, the third incident angle θ3 is limited to 72°, the fourth incident angle θ4 is limited to 38°, the fifth incident angle θ5 is limited to 50°, and the sixth incident angle θ6 is limited to 53°.

[0087] refer to Figure 5 , the comparative examples and the embodiments show driving voltage values ​​in a substantially similar luminance range in the range of 74Cd / A to 78.9Cd / A. Comparative examples (a) to (e) have driving voltage values ​​in the range of 3.31V to 3.36V. Embodiments 1a to 1d have driving voltage values ​​in the range of 3.24V to 3.25V.

[0088] Example 2a and Example 2b have driving voltage values ​​in the range of 3.24V to 3.25V.

[0089] In the embodiments 1a to 2b where the second incident angle θ2 is 65° or less, lower driving voltage values ​​are exhibited compared to the comparative examples (a) to (e) where the second incident angle θ2 is greater than 65°. Figure 4As described, since the light emitting diode formed by the deposition apparatus having the second incident angle θ2 defined as 65° or less includes the mixed layer ETL′, electron movement is facilitated and thus driving voltage is reduced.

[0090] refer to Figure 6 , in each of Examples 1a to 2b, the value of the current density at the same voltage is greater than the value of the current density of Comparative Examples (a) to (d). For example, the slope of the current density graph of Examples 1a to 2b relative to each voltage is greater than the slope of the current density graph of Comparative Examples (a) to (d) relative to each voltage. As described above, since the current density at the same voltage is increased compared to the comparative example, the electrical characteristics of the embodiment are improved.

[0091] Figure 7 is a schematic cross-sectional view illustrating a display device including a light emitting diode formed by a deposition apparatus according to one or more embodiments of the present disclosure.

[0092] refer to Figure 7 , the display device 1000 may include a light emitting diode that emits light. Figure 7 In the embodiment, the light emitting diode included in the display device 1000 is illustrated as an organic light emitting diode OLED, but the present disclosure is not limited thereto. For example, the light emitting diode may be an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode. Hereinafter, for the convenience of description, the case where the light emitting diode is an organic light emitting diode will be described. The display device 1000 includes a pixel P, and the pixel P may emit light having a specific color by using the organic light emitting diode OLED.

[0093] The organic light emitting diode OLED may be electrically connected to the pixel circuit PC between the substrate 110 and the organic light emitting diode OLED in a direction (eg, z direction in a plan view) orthogonal to the substrate 110 (eg, perpendicular to the substrate 110 ).

[0094] The substrate 110 may include a glass material or a polymer resin. In one or more embodiments, the substrate 110 may have an alternating stacking structure of a base layer including a polymer resin and an isolation layer including an inorganic insulating material (such as silicon oxide or silicon nitride). The polymer resin may include at least one of polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0095] Before forming the pixel circuit PC, a buffer layer 111 may be formed on the substrate 110 to prevent or reduce impurities from penetrating into the pixel circuit PC. The buffer layer 111 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and / or silicon oxide, and may include a single layer or multilayer structure including the inorganic insulating material.

[0096] The pixel circuit PC may include a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer A, a gate electrode G, a source electrode SE, and a drain electrode DE.

[0097] The semiconductor layer A may be formed or disposed on the buffer layer 111. The semiconductor layer A may include polycrystalline silicon. In one or more embodiments, the semiconductor layer A may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. In one or more embodiments, the semiconductor layer A may include a channel region C and a source region S and a drain region D respectively arranged on opposite sides (e.g., both sides) of the channel region C.

[0098] The gate electrode G may overlap the channel region C of the semiconductor layer A. The gate electrode G may include a low-resistance metal material.

[0099] The first inorganic insulating layer 113 may be disposed between the semiconductor layer A and the gate electrode G. The first inorganic insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO).

[0100] The second inorganic insulating layer 115 may cover the gate electrode G. Similar to the first inorganic insulating layer 113, the second inorganic insulating layer 115 may include an inorganic insulating material such as silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and / or zinc oxide (ZnO).

[0101] The upper electrode CE2 of the storage capacitor Cst may be formed or disposed on the second inorganic insulating layer 115. In one or more embodiments, the upper electrode CE2 may overlap the gate electrode G. The gate electrode G and the upper electrode CE2 overlapping each other with the second inorganic insulating layer 115 therebetween may form a storage capacitor Cst. For example, the gate electrode G may serve as the lower electrode CE1 of the storage capacitor Cst. As described above, the storage capacitor Cst and the thin film transistor TFT may overlap each other. In one or more embodiments, the storage capacitor Cst and the thin film transistor TFT may not overlap each other.

[0102] The third inorganic insulating layer 117 may cover the upper electrode CE2. The third inorganic insulating layer 117 may include silicon oxide (SiO 2 ), Silicon Nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 ) etc. The third inorganic insulating layer 117 may be a single layer or a multilayer including the inorganic insulating material described above.

[0103] The source electrode SE and the drain electrode DE may each be formed or disposed on the third inorganic insulating layer 117. At least one of the source electrode SE and / or the drain electrode DE may include a material having good or suitable conductivity. At least one of the source electrode SE or the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be provided as a multilayer or single layer including the materials described above. In one or more embodiments, at least one of the source electrode SE and the drain electrode DE may have a multilayer structure of Ti / Al / Ti.

[0104] The organic insulating layer 119 may be formed or disposed on the third inorganic insulating layer 117. The organic insulating layer 119 may be formed or disposed on the source electrode SE and the drain electrode DE. The organic insulating layer 119 may include an organic material. The organic insulating layer 119 may include an organic insulating material such as a general polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and / or a suitable blend thereof).

[0105] A light emitting diode (e.g., an organic light emitting diode OLED) may be formed or disposed on the organic insulating layer 119. For example, the organic light emitting diode OLED may emit red light, green light, or blue light, or may emit red light, green light, blue light, or white light. The organic light emitting diode OLED may include a pixel electrode 210, an emission layer 220, and an opposing electrode 230. The organic light emitting diode OLED may further include a first functional layer 215 between the pixel electrode 210 and the emission layer 220, and a second functional layer 225 between the emission layer 220 and the opposing electrode 230.

[0106] The pixel electrode 210 may be formed or disposed on the organic insulating layer 119. The pixel electrode 210 may be electrically connected to the thin film transistor TFT. For example, the pixel electrode 210 may be connected to the thin film transistor TFT through a contact hole in the organic insulating layer 119. The pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO). In one or more embodiments, the pixel electrode 210 may include a reflective layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and / or any suitable compound thereof. In one or more embodiments, the pixel electrode 210 may further include a reflective layer containing ITO, IZO, ZnO or In above and / or below the reflective layer described above. 2 O 3 layer.

[0107] A pixel defining layer 130 having an opening 130OP exposing a central portion of the pixel electrode 210 may be formed or disposed on the pixel electrode 210. The pixel defining layer 130 may include an organic insulating material and / or an inorganic insulating material. The opening 130OP of the pixel defining layer 130 may define a light emitting region of light emitted from the organic light emitting diode OLED.

[0108] The emission layer 220 may be disposed in the opening 130OP of the pixel defining layer 130. The emission layer 220 may be disposed on the first functional layer 215. The emission layer 220 may include a polymer or a low-molecular organic material that emits light of a specific color. The emission layer 220 may correspond to the reference Figures 1 to 4 Describe the emission layer EML.

[0109] The first functional layer 215 may be formed or disposed under the emission layer 220. The first functional layer 215 may be formed or disposed on the pixel electrode 210. The first functional layer 215 may include, for example, a hole transport layer (HTL) and a hole injection layer (HIL). The first functional layer 215 may be a common layer formed to completely cover the substrate 110, similar to the opposite electrode 230 to be described in more detail later.

[0110] refer to Figure 1 The described deposition substrate 100 may include a stacked structure including a substrate 110, a thin film transistor TFT on the substrate 110, a pixel electrode 210 electrically connected to the thin film transistor TFT, a first functional layer 215 on the pixel electrode 210, and a Figure 7 The emission layer 220 is on the first functional layer 215 .

[0111] The second functional layer 225 may be formed or disposed on the emission layer 220. The second functional layer 225 may include an auxiliary electron transport layer a-ETL, a mixed layer ETL′, and an electron transport layer ETL, as shown in FIG. Figures 1 to 4 Described. Since the organic light emitting diode OLED according to one or more embodiments includes the second functional layer 225, the second functional layer 225 includes the auxiliary electron transport layer a-ETL, the mixed layer ETL' and the electron transport layer ETL, the electrical characteristics and display quality of the organic light emitting diode OLED can be improved. In one or more embodiments, the second functional layer 225 may further include an electron injection layer (EIL). The second functional layer 225 may be a common layer formed to completely cover the substrate 110, similar to the relative electrode 230 which will be described in more detail later.

[0112] The relative electrode 230 may be formed or disposed on the second functional layer 225. The relative electrode 230 may completely cover the substrate 110. The relative electrode 230 may include a conductive material having a low work function. For example, the relative electrode 230 may include a (semi) transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca and / or any suitable alloy thereof. In one or more embodiments, the relative electrode 230 may further include a conductive material such as ITO, IZO, ZnO and / or In on the (semi) transparent layer comprising the materials described above. 2 O 3 layer.

[0113] In one or more embodiments, the encapsulation layer may be formed or disposed on the organic light emitting diode OLED. The encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer covering the organic light emitting diode OLED. In one or more embodiments, at least one inorganic encapsulation layer and at least one organic encapsulation layer may be alternately stacked. The inorganic encapsulation layer may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), zinc oxide (ZnO x ), silicon oxide (SiO 2 ), Silicon Nitride (SiN x ) and / or silicon oxynitride (SiON) (for example, selected from aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), zinc oxide (ZnO x ), silicon oxide (SiO 2 ), Silicon Nitride (SiN x ) and / or at least one inorganic material of silicon oxynitride (SiON). The organic encapsulation layer may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. In one or more embodiments, the organic encapsulation layer may include acrylate.

[0114] The present disclosure has been described with reference to the embodiments shown in the accompanying drawings, but these embodiments are only for illustrative purposes, and those skilled in the art will appreciate that one or more suitable modifications and other equivalent embodiments are possible. Therefore, the scope of protection of the present disclosure should be determined by the spirit and scope of the appended claims and equivalents.

[0115] According to one or more embodiments, the light-emitting diode includes a mixed layer arranged between the electron transport layer and the auxiliary electron transport layer to promote the movement of electrons from the relative electrode to the emission layer, thereby reducing the driving voltage of the light-emitting diode. In the deposition device according to one or more embodiments, the angle of the angle limiting plate is set so that the mixed layer is formed between the electron transport layer and the auxiliary electron transport layer, thereby reducing (e.g., effectively reducing) the driving voltage of the light-emitting diode formed by the deposition device. However, the scope of the present disclosure is not limited by the effects described above.

[0116] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0117] As used herein, the terms "substantially", "about" and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art will recognize. As used herein, "substantially" includes the stated value and means within the acceptable deviation range of the particular value determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0118] Moreover, any numerical range recorded in this article is intended to include all sub-ranges of the same numerical precision within the recorded range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the recorded minimum value 1.0 and the recorded maximum value 10.0 (and including the recorded minimum value 1.0 and the recorded maximum value 10.0), that is, with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit recorded in this article is intended to include all lower numerical limits contained therein, and any minimum numerical limit recorded in this specification is intended to include all higher numerical limits contained therein. Accordingly, the applicant reserves the right to modify this specification (including claims) to explicitly record any sub-ranges contained within the range explicitly recorded herein.

[0119] Additionally, when describing embodiments of the present disclosure, the use of “may” refers to “one or more embodiments of the present disclosure.”

[0120] Any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware may be used to implement the light emitting device, electronic device, or any other related device or component according to the embodiments of the present disclosure described herein. For example, the various components of the device may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of the device may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of the device may be processes or threads running on one or more processors in one or more computing devices, which execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which may be implemented in a computing device using a standard storage device (e.g., a random access memory (RAM)). The computer program instructions may also be stored in other non-temporary computer-readable media (e.g., a CD-ROM, a flash drive, etc.). Moreover, it should be appreciated by those skilled in the art that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed in one or more other computing devices without departing from the scope of the embodiments of the present disclosure.

[0121] It should be understood that the embodiments described herein should be considered only as descriptive and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Although embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but within the spirit and scope of the present disclosure defined by the claims and their equivalents, one or more suitable changes and modifications may be made by a person of ordinary skill in the art.

Claims

1. A light emitting diode, comprising: Pixel electrode; A first functional layer, on the pixel electrode; an emission layer, on the first functional layer; a second functional layer on the emitting layer; as well as a counter electrode, on the second functional layer, in The second functional layer comprises: an auxiliary electron transport layer on the emissive layer and comprising a first deposited material; a mixed layer on the auxiliary electron transport layer and comprising the first deposition material, the second deposition material and the third deposition material; and The electron transport layer is on the mixed layer and includes the second deposition material and the third deposition material.

2. The light-emitting diode according to claim 1, wherein the lowest unoccupied molecular orbital energy level of the mixed layer is lower than the lowest unoccupied molecular orbital energy level of the auxiliary electron transport layer and higher than the lowest unoccupied molecular orbital energy level of the electron transport layer, The lowest unoccupied molecular orbital energy level of the auxiliary electron transport layer is lower than the lowest unoccupied molecular orbital energy level of the emission layer, and The highest occupied molecular orbital energy level of the mixed layer is lower than the highest occupied molecular orbital energy level of the emission layer and the highest occupied molecular orbital energy level of the electron transport layer.

3. The light emitting diode according to claim 1, wherein the thickness of the mixed layer is smaller than the thickness of the electron transport layer, and The thickness of the mixed layer is equal to or greater than the thickness of the auxiliary electron transport layer.

4. A display device, comprising: substrate; a thin film transistor on the substrate; A pixel electrode electrically connected to the thin film transistor; A first functional layer, on the pixel electrode; an emission layer, on the first functional layer; a second functional layer on the emitting layer; as well as a counter electrode, on the second functional layer, in The second functional layer comprises: an auxiliary electron transport layer on the emissive layer and comprising a first deposited material; a mixed layer on the auxiliary electron transport layer and comprising the first deposition material, the second deposition material and the third deposition material; and The electron transport layer is on the mixed layer and includes the second deposition material and the third deposition material.

5. The display device according to claim 4, wherein the lowest unoccupied molecular orbital energy level of the mixed layer is lower than the lowest unoccupied molecular orbital energy level of the auxiliary electron transport layer and higher than the lowest unoccupied molecular orbital energy level of the electron transport layer, The lowest unoccupied molecular orbital energy level of the auxiliary electron transport layer is lower than the lowest unoccupied molecular orbital energy level of the emission layer, and The highest occupied molecular orbital energy level of the mixed layer is lower than the highest occupied molecular orbital energy level of the emission layer and the highest occupied molecular orbital energy level of the electron transport layer.

6. The display device according to claim 4, wherein the thickness of the mixed layer is smaller than the thickness of the electron transport layer, and The thickness of the mixed layer is 20 angstroms to 70 angstroms.

7. A deposition device for forming a functional layer including an electron transport layer on a deposition substrate, the deposition device comprising: A first deposition source, a second deposition source, and a third deposition source are arranged in a first direction; a first injection port configured to inject a first deposition material from the first deposition source to a first region of the deposition substrate; a second injection port configured to inject a second deposition material from the second deposition source to a second region of the deposition substrate; a third injection port configured to inject a third deposition material from the third deposition source to a third region of the deposition substrate; a first angle limiting plate, located outside the first injection port; a second angle limiting plate, between the first injection port and the second injection port; a third angle limiting plate, between the second injection port and the third injection port; as well as a fourth angle limiting plate, located outside the third injection port, A portion of the first area overlaps with the second area and the third area. The deposition apparatus according to claim 7 , wherein the second region completely overlaps with the third region.

9. The deposition apparatus according to claim 7, wherein the first ejection port is limited by the first angle limiting plate to eject the first deposition material to the deposition substrate at a first incident angle, the first ejection port is limited by the second angle limiting plate to eject the first deposition material to the deposition substrate at a second incident angle, and the first incident angle is greater than the second incident angle, The second injection port is limited by the second angle limiting plate to inject the second deposition material onto the deposition substrate at a third incident angle, and the second incident angle is smaller than the third incident angle. The second ejection port is limited by the third angle limiting plate to eject the second deposition material onto the deposition substrate at a fourth incident angle, The third injection port is limited by the third angle limiting plate to inject the third deposition material onto the deposition substrate at a fifth incident angle. The fourth incident angle is smaller than the third incident angle, The fourth incident angle is smaller than the fifth incident angle, and The fifth incident angle is smaller than the third incident angle.

10. The deposition apparatus according to claim 9, wherein the second incident angle is 55° to 65°, and The third incident angle is 70° to 80°.

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