Task scheduling device, computing system, task scheduling method, and program

Abstract

This task scheduling device (100, 100A) allocates tasks to a core group of a processor in a computing system (1000) in which the operating state of the processor is reduced in stages in accordance with a processing load to reduce the amount of power consumption, and is provided with: a task amount / cycle prediction unit (122) that acquires the usage rate of the processor; and a task CPU allocation unit (123) that, on the basis of the usage rate of the processor acquired by the task amount / cycle prediction unit (122), continuously allocates tasks to the cores or core groups of the processor used at a predetermined frequency or more.

Description

Technical Field

[0001] The invention relates to a task scheduling device, a computing system, a task scheduling method and a program. Background Art

[0002] An overview of the wireless access system is described.

[0003] Fig.19 This is a diagram for explaining the overview of a wireless access system.

[0004] like Fig.19 As shown, the wireless access system includes a user terminal (UE: User Equipment), an antenna (base station antenna) 20 , a base station (BBU: Base Band Unit) 30 , and a core network 40 , which are not shown.

[0005] The antenna 20 is an antenna and a transceiver unit (hereinafter, the antenna, the transceiver unit, and the power supply unit thereof are collectively referred to as “antenna”) for wireless communication with the UE 10. The antenna 20 is connected to the base station 30 via a dedicated cable, for example, to transmit and receive data.

[0006] The base station 30 is a wireless base station that is set up on the ground and does not move, and communicates with the UE 10. The base station (BBU: Broad Band Unit) 30 that performs wireless signal processing is dedicated hardware (dedicated device) that performs wireless signal processing. Alternatively, the base station 30 is a vRAN (virtual Radio Access Network) that uses a general-purpose server to process wireless signal processing for the signal processing aggregation system of LTE (Long Term Evolution) and 5G (fivegeneration). In the vRAN, as the hardware of the base station 30, a general-purpose server that is cheap and available in large quantities can be used.

[0007] The base station 30 has hardware (HW) 31, a CPU (Central Processing Unit) 32 on the hardware, an OS etc. 33, L1, L2, L3 protocol wireless signal processing applications 1-1, 1-2, 1-3 (collectively referred to as APL1), and a task scheduling device 34.

[0008] The core network 40 is EPC (Evolved Packet Core, 4G core network) / (in the following description, " / " means "or") 5GC (5G Core Network, 5G core network) and the like.

[0009] An example of a system requiring real-time performance is a base station (BBU) in a RAN.

[0010] In the BBU that uses the CPU 32 to perform calculations, the task of wireless signal processing is often assigned to the CPU core by the task scheduling device 34 to perform the calculations (Non-Patent Document 1).

[0011] Fig. 20 FIG. 1 is a diagram for explaining an example of task management of wireless access processing of a base station. Fig.19 The same components are denoted by the same reference numerals.

[0012] The base station (BBU) 30 includes a task scheduling device 34. The task scheduling device 34 performs task management, priority assignment, and task allocation.

[0013] The task scheduling device 34 assigns the task of the wireless signal processing of the APL1 to the task queue 37 , and distributes it from the task queue 37 to the CPU cores (CPU core # 0 , CPU core # 1 , . . . ) 32 .

[0014] [LPI (Low Power Idle) hardware control]

[0015] The CPU 32 has a function of controlling the idle state of the CPU 32 by hardware control, which is called LPI. LPI is also often called CPU idle or C-state. Hereinafter, LPI will be described as C-state.

[0016] The C-state attempts to save power by turning off the power of a part of the circuits of the CPU 32 when the CPU load decreases (Non-Patent Document 2).

[0017] Fig.21 This is a diagram showing an example of a C-state state. In addition, since the state definition varies depending on the CPU hardware, Fig.21 Just a reference example.

[0018] like Fig.21 As shown, the CPU idle state has levels C0 to C6, and as the no-load time of the CPU 32 increases, the CPU 32 shifts to a deep sleep state. The CPU power consumption in the deep sleep state decreases, but on the other hand, the time required for recovery is also increased accordingly, which sometimes becomes a problem from the perspective of low latency.

[0019] The state definition of the C-state varies depending on the CPU hardware. For example, there are models that do not have C4 and C5, and models that have C1 followed by C1E.

[0020] As the state becomes deeper, the power saving effect becomes greater, but correspondingly, the time required to resume from the idle state also becomes longer.

[0021] In addition, the depth to which the CPU idle state is transferred is controlled by the CPU hardware and depends on the CPU product (in most cases, it cannot be controlled by software such as the kernel).

[0022] Fig. 22 This is a diagram showing an example of a table showing the maximum values ​​of the time to transition to a state (RESIDENCY) and the time required for recovery (WAKE-UP LATENCY). Fig. 22 Indicates the C-state information of the Intel Xeon CPU E5-26X0 v4(registered trademark).

[0023] [CPU idle state Governor]

[0024] Linux kernel 4 (registered trademark) provides two regulators to manage the CPU idle state (C-state).

[0025] Fig.23 This is a diagram for explaining types of CPU idle regulators.

[0026] like Fig.23 As shown in the figure, the ladder diagram programming language (ladder) is used for systems with a scan cycle (tick), and the menu (menu) function is used for systems without a scan cycle (tickless).

[0027] For example, the menu function used by the scanless system is a method of estimating the depth of the idle state suitable for the next idle period based on the actual results of the most recent idle period. The menu function can be effective for workloads with regular idle times, but has limited effect on irregular workloads.

[0028] Fig.24 This is a diagram that explains the logical outline of the menu function.

[0029] like Fig.24 As shown in the left figure of , the menu function records the closest idle time. Then, as Fig.24 As shown in the middle figure of , the next idle time is estimated. Fig.24 The idle time shown in the left figure is used as the next idle time when the deviation is small. Fig.24As shown in the right figure, the menu function estimates the appropriate idle state depth based on the estimation of the next idle time. For example, if the next idle time estimation value T_avr is the same as the time (exit latency) to recover from the idle state (Cx), it is judged as too deep and transfers to the idle state of Cx-1.

[0030] return Fig.23 , for either of the two regulator ladder programming languages ​​and menu functions, there is no mechanism to pre-awaken the CPU from the idle state when a new task arrives, to restore it and prepare it in advance. Therefore, when the task is assigned in the state of transitioning to the deep state, there is a problem of delay time corresponding to the recovery time.

[0031] Prior art literature

[0032] Non-patent literature

[0033] Non-patent document 1: New API (NAPI), [online], [retrieved on June 6, 2019], Internet 〈URL: https: / / www.kernel.org / doc / html / latest / admin-guide / pm / cpuidle.html〉;

[0034] Non-patent document 2: Daniel Molka & Michael Werner, Wake-up latencies for processor idle states on current x86 processors Robert Schone, [online], [retrieved on June 6, 2019], Internet 〈URL: https: / / link.springer.com / article / 10.1007 / s00450-014-0270-z#citeas〉. Summary of the invention

[0035] Problem that the invention aims to solve

[0036] like Fig.21 As shown, the CPU idle state has a level, and as the CPU is not loaded for a longer time, it shifts to a deep sleep state. The CPU power consumption in the deep sleep state decreases, but on the other hand, the time required to resume is also extended accordingly, which sometimes becomes a problem from the perspective of low latency.

[0037] Fig.25 and Fig.26 This is a schematic diagram of the C-state transition of the CPU core used for calculation. Fig.25It shows the situation where the time without task is short. Fig.26 This shows a situation where there is a long time without a task.

[0038] like Fig.25 As shown in , when there is a short time without tasks, the CPU core is in a shallow sleep state, and the delay time from task generation to recovery is short. Fig.26 As shown in the figure, when there is no task for a long time, the CPU core is in a deep sleep state (CPU idle state: level C6), and the delay time from task generation to recovery is extended. When falling into a deep CPU idle state, it takes a lot of time to recover, which has the problem of damaging real-time performance.

[0039] The above problems are Fig.19 and Fig. 20 This is a problem that cannot be ignored in a system that places top priority on real-time performance, such as the base station (BBU) 30 shown.

[0040] Therefore, in the base station (BBU), countermeasures are adopted such as disabling the C-state or inputting a setting with a limited depth such as limiting the transition of the idle state to C1. In other words, sometimes adjustments are made to target real-time performance at the expense of power saving.

[0041] In existing base stations (BBU), once a BBU falls into a deep C-state, the only option is to wait until recovery. Therefore, a countermeasure is adopted to avoid falling into a deep state at the expense of power saving.

[0042] The present invention has been made in view of such a background, and an object of the present invention is to realize power saving while performing calculations with low latency.

[0043] Solutions for solving problems

[0044] In order to solve the above-mentioned problems, the present invention adopts a task scheduling device, characterized in that it allocates tasks to a core group of a processor in a computing system, and the computing system phase-by-phase reduces the working state of the processor according to the processing load to reduce power consumption. The task scheduling device has: a processor usage acquisition unit, which acquires the usage rate of the processor; and a task allocation unit, which continuously allocates tasks to the core or core group of the processor used at a specified frequency or above based on the usage rate of the processor acquired by the processor usage acquisition unit.

[0045] Effects of the Invention

[0046] According to the present invention, it is possible to realize power saving and perform calculations with low latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic structural diagram of a computing system according to an embodiment of the present invention.

[0048] Figure 2 This is a configuration example in which the task scheduling device of the computing system according to the embodiment of the present invention is arranged in the user space.

[0049] Figure 3 This is a configuration example in which the task scheduling device of the computing system according to the embodiment of the present invention is arranged in the OS.

[0050] Figure 4 This is a diagram showing, in a table, the required number estimation logic of the CPU core group in operation of the task scheduling device of the computing system according to the embodiment of the present invention.

[0051] Figure 5 The diagram is a diagram for explaining the operation of the task amount threshold determination and the CPU usage rate threshold determination of the task scheduling device of the computing system according to the embodiment of the present invention.

[0052] Figure 6 This is a schematic diagram showing the threshold determination based on the task inflow amount by the task scheduling device of the computing system according to the embodiment of the present invention.

[0053] Figure 7 It is a schematic diagram for explaining the threshold determination based on the CPU usage rate of the task scheduling device of the computing system according to the embodiment of the present invention.

[0054] Figure 8 This is a diagram for explaining the C-state upper limit setting of the task scheduling device of the computing system according to the embodiment of the present invention.

[0055] Fig. 9 It is a diagram for explaining a case where the C-state upper limit is not set and a case where the C-state upper limit is set in the operation system according to the embodiment of the present invention.

[0056] Fig.10 This is a diagram for explaining the pooling of CPU cores with high availability in the task scheduling device of the computing system according to the embodiment of the present invention.

[0057] Fig.11 This is a diagram for explaining the pre-wakeup of the task scheduling device of the computing system according to the embodiment of the present invention.

[0058] Fig.12 This is a diagram for explaining the pre-wakeup of the task scheduling device of the computing system according to the embodiment of the present invention.

[0059] Fig.13 This is a flowchart showing the task scheduling process of the task scheduling device of the computing system according to the embodiment of the present invention.

[0060] Fig.14 This is a hardware configuration diagram showing an example of a computer that realizes the function of the task scheduling device of the computing system according to the embodiment of the present invention.

[0061] Fig.15 This is a diagram showing an example of an interrupt model in which the operation system according to the embodiment of the present invention is applied to a general-purpose Linux kernel (registered trademark) and a server virtualization environment of a VM structure.

[0062] Fig.16 This is a diagram showing an example of an interruption model in which the operation system according to the embodiment of the present invention is applied to a server virtualization environment of a container structure.

[0063] Fig.17 This is a diagram showing an example of an interrupt model in which the operation system according to the embodiment of the present invention is applied to a general-purpose Linux kernel (registered trademark) and a server virtualization environment of a VM structure.

[0064] Fig.18 This is a diagram showing an example of an interruption model in which the operation system according to the embodiment of the present invention is applied to a server virtualization environment of a container structure.

[0065] Fig.19 This is a diagram for explaining the overview of a wireless access system.

[0066] Fig. 20 This is a diagram for explaining an example of task management in a wireless access process of a base station.

[0067] Fig.21 This is a diagram showing an example of the state of the C-state in a table.

[0068] Fig. 22 This is a diagram showing an example of a table showing the maximum values ​​of the time to transition to a state (RESIDENCY) and the time required for recovery (WAKE-UPLATENCY).

[0069] Fig.23 This is a diagram for explaining types of CPU idle regulators.

[0070] Fig.24 This is a diagram that explains the logical outline of the menu function.

[0071] Fig.25 This is a schematic diagram of the C-state transition of the CPU core used for calculation.

[0072] Fig.26 This is a schematic diagram of the C-state transition of the CPU core used for calculation. DETAILED DESCRIPTION

[0073] Hereinafter, a calculation system and the like for implementing a mode for implementing the present invention (hereinafter referred to as “the present embodiment”) will be described with reference to the drawings.

[0074] [summary]

[0075] Figure 1 FIG. 1 is a schematic diagram of a computing system according to an embodiment of the present invention. Fig. 20 The same components are denoted by the same reference numerals.

[0076] This embodiment is an example of a CPU as a computing system. In addition to the CPU, it can also be applied to processors such as GPU (Graphic Processing Unit), FPGA (Field Programmable Gate Array), and ASIC (Application Specific Integrated Circuit) when there is an idle state function.

[0077] like Figure 1 As shown, the operating system 1000 has hardware (HW) 31, a CPU core (CPU core #0, CPU core #1, ...) 32 (processor) on the hardware 31, an OS 33, L1, L2, L3 protocol wireless signal processing applications 1-1, 1-2, 1-3 (collectively referred to as APL1), and a task scheduling device 100.

[0078] The computing system 1000 is a computing system that reduces the operating state of the processor in stages according to the processing load to reduce power consumption. In the computing system 1000, the processor has a plurality of core groups, and the computing system 1000 has a task scheduling device 100 that allocates tasks to the core groups of the processor.

[0079] [Task Scheduling Device 100]

[0080] The task scheduling device 100 includes a management unit 110 , a task management unit 120 , and a CPU idle state control unit 130 .

[0081] <Management Department 110>

[0082] The management unit 110 includes a setting unit 111 for operators.

[0083] The operator sets parameters related to the C-state in the operator-oriented setting unit 111. For example, in the operator-oriented setting unit 111, the manager inputs the C-state upper limit setting in advance in consideration of the time lag from inputting the C-state upper limit setting to its reflection.

[0084] <Task Management Department 120>

[0085] The task management unit 120 includes a task priority assigning unit 121 , a task amount / cycle predicting unit 122 (processor usage acquisition unit), and a task CPU allocating unit 123 (task allocating unit).

[0086] The task priority assigning unit 121 assigns a priority to a task sent from the APL 1 as necessary. The task management unit 120 performs priority control for assigning tasks to CPU cores based on the priority.

[0087] Here, the most accurate representation of the CPU status is considered to be "CPU usage per unit time of the CPU core being used". "CPU usage per unit time of the CPU core being used" can be roughly estimated from the task volume. The busyness of the CPU can be estimated by the task volume, but it cannot be measured only by the task volume. It also depends on how much processing the CPU is not good at. Furthermore, in the case where the processor is a GPU, FPGA, or ASIC other than a CPU, the processing that the processor is good at / not good at will also change. In this embodiment, the task volume is used as a physical quantity associated with the "CPU usage per unit time of the CPU core being used".

[0088] The task load and cycle prediction unit 122 obtains the utilization rate of the processor. Specifically, the task load and cycle prediction unit 122 obtains the utilization rate of the processor according to Figure 4 The judgment logic shown measures the amount of tasks per unit time and the CPU usage rate, and determines whether it is necessary to increase / decrease the number of CPU cores used for calculation.

[0089] The task amount and cycle prediction unit 122 pre-awakens the newly used CPU core. If some processing is executed by the CPU core, there are many CPU products whose C-state returns to C0. Therefore, there is a method of executing small calculations and outputting strings in standard output by the CPU core.

[0090] The task CPU allocation unit 123 continuously allocates tasks to the core or core group of the processor used at a predetermined frequency or more based on the processor usage rate obtained by the task amount and cycle prediction unit 122 (processor usage rate acquisition unit). The task CPU allocation unit 123 reduces the used CPU cores, for example. As a method of reducing the CPU cores, a CPU core that will not be used in the future is identified and no tasks are allocated to the CPU core in the future.

[0091] The task CPU allocation unit 123 allocates the arrived tasks to the CPU cores (the allocation to the CPU cores can be performed by polling scheduling of the CPU cores in use, or can be allocated to the CPU core with a small number of remaining tasks in the task queue prepared for each CPU core), and schedules the tasks to the task queue prepared for each CPU core.

[0092] At this time, tasks with higher priorities can also be preferentially allocated to idle CPU cores according to the assigned priorities. In addition, the task queues of each CPU core can be rearranged according to the priorities.

[0093] <CPU Idle State Control Unit 130>

[0094] The CPU Idle State Control Unit 130 has a CPU Pre-Wake-Up Unit 131 (pre-wake-up unit) and a C-State Setting Unit 132 (operating state setting unit).

[0095] When allocating tasks to newly used cores or cores that have not been used for a specified period and are used again, the CPU Pre-Wake-Up Unit 131 performs pre-wake-up to restore the operating state of the processor to its original state (refer to Figure 1 the reference numeral c in the figure).

[0096] The C-State Setting Unit 132 sets an upper limit for the cores or core groups of the processor that are used at a specified frequency or higher, so that the operating state of the processor cannot transition to a deeper state. Specifically, the C-State Setting Unit 132 inputs a C-state upper limit setting for newly used CPU cores. The upper limit state is determined by the setting of the operator (refer to Figure 1 the reference numeral b in the figure).

[0097] In addition, in the case where tasks flow in stably and tasks are continuously allocated, the operating CPU core group does not transition to a deep C-state, so an upper limit setting can sometimes be input.

[0098] Here, instead of performing pre-wake-up, a C-state upper limit setting can be input before allocating tasks to newly used CPU cores to make them return to a shallow state. In this case, considering the time lag from inputting the C-state upper limit setting to its reflection, the C-state upper limit setting is input in advance.

[0099] When a C-state upper limit setting is input, the C-State Setting Unit 132 releases the upper limit setting for the CPU cores determined to be unused.

[0100] The C-State Setting Unit 132 sets the cores or core groups to which the Task CPU Allocation Unit 123 (task allocation unit) does not allocate tasks so that the operating state of the processor can transition to a deeper state.

[0101] [Configuration of the Task Scheduling Device]

[0102] Figure 2 and Figure 3 are diagrams illustrating Figure 1 the configuration of the task scheduling device 100.

[0103] · Configuration of the Task Scheduling Device in the User Space

[0104] Figure 2 Yes Figure 1 The task scheduling device 100 is configured as an example of a structure in the user space.

[0105] exist Figure 2 In the illustrated operation system 1000, a task scheduling device 100 is arranged in a user space 60. The operation system 1000 executes a packet processing APL1 arranged in the user space 60. The operation system 1000 executes the packet processing APL1 on a server having an OS.

[0106] The present invention can be applied to a case where the user space 60 has threads, such as Intel DPDK (Intel Data Plane Development Kit) (DPDK) (registered trademark).

[0107] ·Configuration of the task scheduler to the OS

[0108] Figure 3 Yes Figure 1 This is a configuration example in which the task scheduling device 100 is configured in the OS 50.

[0109] exist Figure 3 In the illustrated operation system 1000, a task scheduling device 100 is provided in an OS 50. The operation system 1000 executes a packet processing APL1 on a server having the OS 50.

[0110] The present invention can be applied to a case where a kernel has threads inside, such as New API (NAPI) (registered trademark) (Non-Patent Document 1) and KBP (kernel-based virtual machine, KVM virtual machine).

[0111] [Logic for estimating the required number of CPU cores in operation]

[0112] For the CPU core group in operation (refer to Figure 1 The required number inference logic of the dotted box a) is explained.

[0113] The present inventors considered continuously allocating tasks to the operating CPU core group and shifting the other CPU cores to a deep C-state to reduce power consumption.

[0114] Therefore, when managing the CPU core group in operation, it is necessary to calculate the number of required CPU cores based on the amount of incoming tasks and the like.

[0115] Figure 4 This is a diagram showing the required number estimation logic of the CPU core group in operation in the form of a table.

[0116] like Figure 4 As shown, the inferred logic judgment includes "1. Judgment based on the arrival pattern of the task" and "2. Judgment based on the CPU usage rate", which are judged by threshold judgment, periodicity, and machine learning respectively.

[0117] like Figure 4 As shown in Figure 2, since each judgment logic has different applicable tasks, we consider Figure 4 The logic is selected and used separately according to the applicability recorded in the right column of the table. In addition, multiple judgment logics can also be used in combination.

[0118] Next, the operation of the operation system 1000 configured as described above will be described.

[0119] [Basic Concept of Operation of Task Scheduling Device 100]

[0120] In the present invention, in a computing system requiring real-time performance, a task scheduler that allocates tasks to CPU cores allocates tasks in consideration of the C-state of the CPU core.

[0121] feature <1> : Continuous task allocation

[0122] By ensuring that the CPU cores with high usage frequency are continuously assigned tasks, the transition to a deep C-state is prevented. Figure 5 to Figure 7 ).

[0123] like Figure 5 As shown in the dashed box a, according to the task volume, Figure 4 The judgment logic shown ensures that the frequently used CPU core group (the CPU core group in operation) is used, and tasks are continuously assigned to the CPU core group. This prevents the transition to a deep C-state and reduces the delay in recovering from the C-state. CPU cores other than the operating CPU cores can be transferred to a deep C-state, which can achieve power saving.

[0124] feature <2> : C-state upper limit setting

[0125] As a countermeasure for the situation where tasks are not continuously assigned, an upper limit of the C-state that can be transferred is set for the CPU core group with high usage frequency ( Figure 8 to Figure 10 ).

[0126] As a countermeasure for a situation where tasks are not continuously assigned to an operating CPU core, an upper limit of the C-state to which the operating CPU core group can be transferred is set to prevent the group from transferring to a deeper C-state, thereby reducing the delay in recovery.

[0127] feature <3> : Pre-wake up

[0128] Before assigning tasks to the CPU core that is transferred to the deep state, the time to resume from the deep state is reduced by waking up in advance ( Figure 11-12 ).

[0129] Before assigning a task to a newly used CPU core (a CPU core that has not been used for a long time), the time for resuming from a deep C-state is reduced by performing pre-wake-up.

[0130] In the following, the features are <1> ,feature <2> ,feature <3> Provide explanation.

[0131] [Task volume threshold judgment and CPU usage threshold judgment] (Feature <1> : Continuous task allocation)

[0132] Figure 5 The diagram is a diagram for explaining the operation of the task amount threshold determination and the CPU usage rate threshold determination of the task scheduling device 100 .

[0133] <Task Volume Threshold Judgment Work>

[0134] First, the task volume threshold determination work is explained.

[0135] The task management unit 120 performs a task amount threshold determination operation.

[0136] like Figure 5 As shown by the dotted arrow d, the task priority assigning unit 121 assigns priorities to tasks as needed.

[0137] The task volume and cycle prediction unit 122 Figure 4 The judgment logic shown measures the amount of tasks per unit time and the CPU usage rate, and determines whether it is necessary to increase / decrease the number of CPU cores used for calculation.

[0138] Figure 6 Schematic diagram showing threshold determination based on the task inflow amount.

[0139] The task management unit 120 Figure 6 The task flow shown manages the CPU core.

[0140] exist Figure 6 In , the task inflow per unit time: W_input corresponds to the number of CPU cores used. For example, when W_input is "dd~ee", the number of CPU cores used is "4", and the CPU core group in operation (refer to Figure 5 The dotted box a) is "4".

[0141] return Figure 5The task CPU allocation unit 123 allocates the arrived tasks to the CPU cores and schedules the tasks to the task queues prepared for each CPU core. At this time, according to the assigned priorities, the tasks with high priorities are preferentially allocated to the idle CPU cores. In addition, the task queues of each CPU core are rearranged according to the priorities.

[0142] The task management unit 120 manages tasks that are to be completed within a fixed time according to Figure 6 The threshold judgment table is used to design the number of CPU cores required for the task inflow calculation corresponding to the task inflow per unit time. In addition, when the task inflow is greater than Figure 6 When the threshold value of the threshold judgment table (the threshold value of W_input) is exceeded, it can be determined whether the number of CPU cores to be used needs to be increased. Figure 6 In the case of dd<W_input<ee, four CPU cores are used. When the task inflow is W_input≥ee, the CPU cores are increased from four to five.

[0143] <Calculation example of the number of required CPU cores>

[0144] Next, an example of calculation of the required number of CPU cores will be described.

[0145] Task management unit 120 ( Figure 5 ) to calculate the number of CPU cores required.

[0146] When the operation time of the task is fixed (or has little variation), if the maximum waiting time Tw allowed by the service is defined, the number of CPU cores N required to meet the maximum waiting time can be calculated using queuing theory. In the following calculation formula (3), the time to recover from the C-state is not taken into consideration, but if the time to recover from the C-state can be made as close to 0 as possible through this embodiment, it does not need to be taken into consideration.

[0147] · Example of calculation of the number of CPU cores required

[0148] λ[pcs / s]: The amount of tasks flowing in per unit time (W_input)

[0149] μ[pcs / s]: The number of tasks that the system can handle per unit time

[0150] Ts[s]: The time required for the system to process a task

[0151] t_s[s]: The time required to use one CPU core to calculate a task

[0152] Tw[s]: The maximum waiting time allowed by the service

[0153] N: The number of CPU cores in use

[0154] ρ = λ / μ: Degree of congestion

[0155] μ = N / t_s

[0156] Ts = 1 / μ = t_s / N

[0157] Tw = (ρ / (1 - ρ)) * Ts…(1)

[0158] Substitute ρ and Ts into the above formula (1) to obtain formula (2).

[0159] Tw = ((λ / μ) / (1 - (λ / μ)) * (t_s / N)…(2)

[0160] Substitute μ into the above formula (2) and solve to obtain formula (3).

[0161] N 2 -λ·t_s·N - λ·t_s 2 / Tw = 0…(3),

[0162] Just find the smallest natural number that satisfies this equation.

[0163] <CPU Usage Threshold Judgment Operation>

[0164] Next, the CPU usage threshold judgment operation will be described.

[0165] Figure 7 It is a schematic diagram showing the threshold judgment based on the CPU usage. The vertical axis is the average CPU usage of the CPU cores in use, and the horizontal axis is time.

[0166] Two thresholds are set relative to 100% of the average CPU usage, namely Threshold_upper (upper limit) (refer to the dotted line e in Figure 7 and Threshold_base (lower limit) (refer to the dotted line f in Figure 7 ).

[0167] The task management unit 120( Figure 5 ) increases the CPU cores in use when the average CPU usage is greater than the upper limit. In addition, if the average CPU usage is less than the lower limit, the CPU cores in use are reduced.

[0168] When the average CPU utilization rate of the CPU cores in use is greater than Threshold_upper (upper limit), it indicates that the CPU cores in use are insufficient, and the number of newly added CPU cores can be determined. On the other hand, when the average CPU utilization rate of the CPU cores in use is less than Threshold_base (lower limit), there are excessive CPU cores, and it can be determined to reduce the CPU cores in use.

[0169] Here, in the case of the number of the newly added CPU cores described above, since the CPU cores have not been used so far, it is assumed that they fall into the deep C-state. In particular, the calculation method of the recovery time in the case of recovering the CPU cores that fall into the deep C-state like this is described in the above <Calculation example of the required number of CPU cores>.

[0170] Above, the task volume threshold judgment and the CPU utilization rate threshold judgment have been described.

[0171] [C-state upper limit setting] (Feature <2>: C-state upper limit setting)

[0172] <C-state upper limit setting operation>

[0173] Figure 8 It is a diagram for explaining the C-state upper limit setting of the task scheduling device 100.

[0174] The C-state setting unit 132 of the CPU idle state control unit 130 sets the upper limit of the C-state that can be transferred for the CPU core group with high usage frequency (refer to Figure 8 the reference numeral b).

[0175] For the CPU cores with high usage frequency, since the possibility of task allocation is high, even if they are transferred to the deep idle state, the residence period of this state is short, and the power saving effect cannot be obtained very much. Whether the power saving effect can be obtained or not, sometimes there will be a disadvantage of the time overhead generated from the recovery from the idle state.

[0176] In the present embodiment, for this problem, for the CPU cores with high usage frequency, the upper limit of the CPU idle state that can be transferred is determined in advance (for example, refer to Fig. 22 C1, C1E, etc.), and it is set that they cannot be transferred to a deeper state than this state. Thus, when tasks are allocated, recovery can be performed from the shallow state, and the recovery delay time can be reduced.

[0177] For the object of the CPU cores for setting / 解除 the upper limit of the CPU idle state, by using Figure 4 the judgment logic shown, the number of CPU cores in use can be judged. The C-state setting unit 132 uses Figure 4The judgment logic shown dynamically sets the upper limit of the CPU idle state.

[0178] Furthermore, when a new (long unused) CPU core is added, the C-state upper limit may be set before allocating tasks to the newly added CPU core, so that the CPU core returns to a shallow C-state in advance.

[0179] Fig. 9 is a schematic diagram illustrating the setting of the upper limit of the C-state. Fig. 9 The above figure shows the case without C-state upper limit setting, Fig. 9 The following figure shows the case with the C-state upper limit set.

[0180] like Fig. 9 As shown in the above figure, without the C-state upper limit setting, the CPU falls into the idle state (level C2) and the delay time to recover to C0 is extended.

[0181] In contrast, Fig. 9 As shown in the figure below, for CPU core groups with high usage frequency, by setting the C-state upper limit (refer to Fig. 9 g) in the figure below, so that it cannot be transferred to the deep state, reducing the recovery delay time when recovering from the shallow state.

[0182] <Pooling of CPU cores with high availability>

[0183] Next, as an extended function of C-state upper limit setting, pooling of CPU cores with high availability will be described.

[0184] Fig.10 This is a diagram for explaining the pooling of CPU cores with high availability in the task scheduling device 100 .

[0185] like Fig.10 As shown, in the case of expected use later, a CPU core group set to only fall into a shallow idle state can also be prepared in advance ( Fig.10 For example, Fig.10 The CPU cores (CPU core #4, CPU core #5) 32 shown in the figure adopt a pre-pooling method that can only be transferred to the CPU core group C1.

[0186] For example, in the case of handling nighttime / daytime traffic fluctuations, when it is predicted that CPU cores with a high probability of being used in the future can be used based on the tendency of tasks, the CPU core group with a high probability of being used ( Fig.10 The dotted box h) is set to be able to transfer only to a shallow idle state (for example, to C1, etc.). Then, the CPU cores in standby operation are pooled and prepared in advance so that they can be used directly when needed.

[0187] In this way, when it is expected to be used later, a method is adopted in which a CPU core group set to fall into only a shallow idle state is prepared in advance (for example, a CPU core group that can only be transferred to C1 is pre-pooled).

[0188] The C-state upper limit setting has been described above.

[0189] [Pre-wake] (Features <3> : Pre-wake up)

[0190] Fig.11 1 is a diagram for explaining the pre-awakening of the task scheduling device 100 .

[0191] The CPU pre-wake-up unit 131 pre-wakes up the CPU core when using the CPU core that has fallen into the deep CPU idle state (C-state) (refer to Fig.11 denoted by reference numeral c).

[0192] Fig.12 It is a diagram for explaining the pre-awakening of the task scheduling device 100 . Fig.12 The above diagram shows a technical situation. Fig.12 The following figure shows the situation of pre-awakening of the task scheduling device 100.

[0193] like Fig.12 As shown in the above figure, in the case of the prior art (without pre-awakening), from the allocation task ( Fig.12 The delay from the reference mark i) in the above figure to the start of the operation is large ( Fig.12 ) in the figure above.

[0194] In contrast, Fig.12 As shown in the figure below, in the case of pre-wake-up, by pre-wake-up ( Fig.12 The reference mark c in the figure below) is low latency from task allocation to operation start ( Fig.12 ) is referenced by the reference numeral k in the following figure.

[0195] In this way, the CPU core with low usage frequency is transferred to the deep C-state, which can reduce power consumption and reduce the influence of the delay time associated with recovery from the deep C-state.

[0196] [Workflow of the Task Scheduling Device 100]

[0197] Fig.13 : is a flowchart showing the task scheduling process of the task scheduling device 100 .

[0198] In step S11, APL1( Figure 1 ) to the task management unit 120( Figure 1 )Register the task.

[0199] In step S12, the task priority assigning unit 121 ( Figure 1 ) assigns priority to tasks as needed. Task CPU allocation unit 123 ( Figure 1 ) Based on the priority, priority control is performed on the CPU core.

[0200] In step S13, the task amount and period prediction unit 122 ( Figure 1 )according to Figure 4 The judgment logic shown measures the amount of tasks per unit time and the CPU usage rate, and determines whether it is necessary to increase / decrease the number of CPU cores used for calculations (the branches after the judgment are the following steps S14 and S15).

[0201] In step S14 , if the number of CPU cores needs to be reduced ( S14 : Yes), the process proceeds to step S17 , and if the number of CPU cores does not need to be reduced ( S14 : No), the process proceeds to step S15 .

[0202] In step S15 , if the number of CPU cores needs to be increased ( S15 : Yes), the process proceeds to step S19 , and if the number of CPU cores does not need to be increased ( S15 : No), the process proceeds to step S16 .

[0203] In step S16, the task CPU allocation unit 123 ( Figure 1 ) The arrived tasks are assigned to the CPU cores, and the tasks are scheduled to the task queues prepared for each CPU core, and the processing of this process is terminated. The assignment to the CPU cores can be performed by polling the CPU cores in use, or can be assigned to the CPU cores with a small number of remaining tasks in the task queues prepared for each CPU core.

[0204] In addition, the task CPU allocation unit 123 ( Figure 1 ) According to the assigned priority, high-priority tasks can be assigned to idle CPU cores first, or the task queue of each CPU core can be rearranged according to the priority.

[0205] If the number of CPU cores needs to be reduced in step S14, in step S17, the task CPU allocation unit 123 ( Figure 1 ) Reduce the number of CPU cores in use. For example, as a method of reducing the number of CPU cores, a CPU core that will not be used in the future is determined, and no tasks are assigned to the CPU core in the future.

[0206] In step S18, the C-state setting unit 132 ( Figure 1 ) If a C-state upper limit setting is input, the C-state upper limit setting is released for the CPU core determined to be unused, and the processing of this flow is terminated.

[0207] When it is necessary to increase the number of CPU cores in step S15 described above, in step S19, the task volume - cycle prediction unit 122 ( Figure 1 ) pre - wakes up the newly used CPU cores.

[0208] The reasons for pre - waking up the newly used CPU cores are as follows. That is, if some processing is executed by the CPU cores, there are many CPU products whose C - state returns to C0. Therefore, by using this CPU core to pre - execute small operations, such as outputting a string in the standard output, etc., the transfer of this CPU core to the deep C - state is suppressed.

[0209] Here, instead of pre - waking up, it is also possible to set the C - state upper limit before allocating tasks to the newly used CPU cores described in <C - state upper limit setting> ( Figure 8 ) to make it return to the shallow state. In this case, considering the time lag from inputting the C - state upper limit setting to its reflection, the C - state upper limit setting is input in advance.

[0210] In step S20, the C - state setting unit 132 inputs the C - state upper limit setting to the newly used CPU cores, and ends the processing of this flow. The upper limit state is determined by being set in advance by the operator.

[0211] In addition, in the case where tasks flow in stably and are continuously allocated tasks, since the operating CPU core group does not transfer to the deep C - state, it is sometimes possible not to input the C - state upper limit setting.

[0212] [Hardware Structure]

[0213] The task scheduling devices 100, 100A ( Figure 1 , Fig.10 ) of the above - described embodiment are implemented, for example, by a computer 900 having a structure as Fig.14 shown.

[0214] Fig.14 FIG. is a hardware structure diagram showing an example of a computer 900 that realizes the functions of the task scheduling devices 100, 100A ( Figure 1 , Fig.10 ).

[0215] The computer 900 has a CPU 901, a ROM 902, a RAM 903, an HDD 904, a communication interface (I / F: Interface) 906, an input / output interface (I / F) 905, and a media interface (I / F) 907.

[0216] The CPU 901 operates based on programs stored in the ROM 902 or the HDD 904, and performs the task scheduling devices 100, 100A ( Figure 1 , Fig.10 ) The ROM 902 stores a boot program executed by the CPU 901 when the computer 900 is started, a program that depends on the hardware of the computer 900, and the like.

[0217] The CPU 901 controls an input device 910 such as a mouse and a keyboard, and an output device 911 such as a display, via an input / output I / F 905. The CPU 901 acquires data from the input device 910 via the input / output I / F 905, and outputs generated data to the output device 911. In addition, a GPU (Graphics Processing Unit) or the like may be used as a processor together with the CPU 901.

[0218] HDD 904 stores programs executed by CPU 901 and data used by the programs, etc. Communication I / F 906 receives data from other devices via a communication network (eg, NW (Network) 920) and outputs it to CPU 901, and also transmits data generated by CPU 901 to other devices via the communication network.

[0219] The media I / F 907 reads the program or data stored in the recording medium 912 and outputs it to the CPU 901 via the RAM 903. The CPU 901 loads the target processing program from the recording medium 912 to the RAM 903 via the media I / F 907, and executes the loaded program. The recording medium 912 is an optical recording medium such as a DVD (Digital Versatile Disc), a PD (Phase change rewritable disk), a magneto-optical recording medium such as an MO (Magneto Optical disk), a magnetic recording medium, a conductor storage tape medium, or a semiconductor memory.

[0220] For example, in the computer 900 as a task scheduling device 100, 100A ( Figure 1 , Fig.10 ) and performs its function, the CPU 901 of the computer 900 implements the function of the task scheduling device 100, 100A by executing the program loaded on the RAM 903. In addition, the data in the RAM 903 is stored in the HDD 904. The CPU 901 reads and executes the program of the target processing from the recording medium 912. In addition, the CPU 901 can also read the program of the target processing from other devices via the communication network (NW 920).

[0221] [Application Examples]

[0222] (A method for configuring a task scheduling device in user space 60)

[0223] like Figure 2 As shown, the configuration example of the task scheduling device 100 can be applied to the user space 60. In this case, the OS is not limited. In addition, it is not limited to the server virtualization environment. Therefore, the computing system can be applied to Fig.15 and Fig.16 The structures shown.

[0224] <Example of application to VM structure>

[0225] With the development of virtualization technology based on NFV (Network Functions Virtualization), systems are being built and operated for each service. In addition, according to the way of building systems for each of the above services, the service functions are divided into reusable module units and operated on independent virtual machine (VM: virtual machine, container, etc.) environments. As a result, the method called SFC (Service Function Chaining) is gradually becoming mainstream, which uses components as needed and improves operability.

[0226] As a technology for forming a virtual machine, a virtual machine monitor (Hypervisor) environment composed of Linux (registered trademark) and KVM (kernel-based virtual machine, KVM virtual machine) is known. In this environment, a host OS (the OS installed on a physical server is called a host OS) in which a KVM module is assembled works as a virtual machine monitor (Hypervisor) in a storage area different from a user space called a kernel space. In this environment, a virtual machine works in a user space, and a guest OS (the OS installed on a virtual machine is called a guest OS) works in the virtual machine.

[0227] The virtual machine where the guest OS runs is different from the physical server where the host OS runs. All HW (hardware) including network devices (such as Ethernet (registered trademark) card devices) becomes the register control required for interrupt processing from HW to the guest OS and writing from the guest OS to the hardware. In such register control, notifications and processing that should have been performed by physical hardware are simulated by software, so the performance is usually lower than that of the host OS environment.

[0228] Fig.15 FIG. 1 is a diagram showing an example of an interrupt model in which the operation system 1000A is applied to a general-purpose Linux kernel (registered trademark) and a server virtualization environment of a VM structure. Figure 1 The same components are denoted by the same reference numerals.

[0229] like Fig.15 As shown, the operating system 1000A has a virtual machine and a host OS 80 in which an external process formed outside the virtual machine can operate, and the host OS 80 has a kernel 81 and a driver 82. In addition, the operating system 1000A has a CPU 71 of a HW 70 connected to the host OS 80, and a KVM module 91 incorporated in a virtual machine monitor (HV) 90. Furthermore, the operating system 1000A has a guest OS 95 operating in the virtual machine, and the guest OS 95 has a kernel 96 and a driver 97.

[0230] Furthermore, the operation system 1000A includes a task scheduling device 100 connected to the guest OS 95 and arranged in the user space 60 .

[0231] By doing so, in a system having a virtual server structure of VM, both the host OS 80 and the guest OS 95 can realize power saving and low-latency calculation.

[0232] <Example of application to container structure>

[0233] Fig.16 FIG. 1 is a diagram showing an example of an interruption model in which the operating system 1000B is applied to a server virtualization environment of a container structure. Figure 1 and Fig.15 The same components are denoted by the same reference numerals.

[0234] like Fig.16 As shown, the computing system 1000B will Fig.15 The guest OS 95 is replaced with a container 98 having a container structure. The container 98 has a vNIC (virtual NIC).

[0235] In a system with a virtual server structure such as a container, it is possible to achieve power saving and low-latency computing.

[0236] The above has described a method of configuring the task scheduling device 100 in the user space 60. Next, a method of configuring the task scheduling device 100 in the kernel will be described.

[0237] (How to configure the task scheduler in the kernel of the OS)

[0238] like Figure 3As shown, it can be applied to a configuration example in which the task scheduling device 100 is configured in the OS 50. In this case, the OS is not limited. In addition, it is not limited to the server virtualization environment. Therefore, the computing system can be applied to Fig.17 and Fig.18 The structures shown.

[0239] <Example of application to VM structure>

[0240] Fig.17 FIG. 1 is a diagram showing an example of an interrupt model in which the operation system 1000C is applied to a server virtualization environment of a general-purpose Linux kernel (registered trademark) and a VM structure. Figure 1 and Fig.15 The same components are denoted by the same reference numerals.

[0241] like Fig.17 As shown, the computing system 1000C has a task scheduling device 100 configured in the kernel 81 of the host OS 80 , and a task scheduling device 100 configured in the kernel 96 of the guest OS 95 .

[0242] By doing so, in a system having a virtual server structure of VM, both the host OS 80 and the guest OS 95 can realize power saving and low-latency calculation.

[0243] <Example of application to container structure>

[0244] Fig.18 FIG. 1 is a diagram showing an example of an interruption model in which the operating system 1000D is applied to a server virtualization environment of a container structure. Figure 1 and Fig.16 The same components are denoted by the same reference numerals.

[0245] like Fig.19 As shown, the operating system 1000D is configured with a task scheduling device 100 in the kernel 81 of the host OS 80 .

[0246] In a system with a virtual server structure such as a container, it is possible to achieve power saving and low-latency computing.

[0247] <Example of application to bare metal structure (non-virtualized structure)>

[0248] The present invention can be applied to a non-virtualized system like a bare metal structure, and can save power and perform calculations with low latency in a non-virtualized system.

[0249] <Applicable to processors other than CPU>

[0250] The present invention can be applied not only to a CPU but also to a processor such as a GPU / FPGA / ASIC having an idle state function.

[0251] <Applied to CPU operating frequency control>

[0252] The present invention can also apply the pre-wake-up of the embodiment to a mechanism for restoring the frequency of the processor before allocating tasks when the operating frequency of the processor becomes low.

[0253] <Functions other than CPU>

[0254] In addition to being applied to the CPU, the present invention can also be applied to functions other than the CPU, such as memory, storage (e.g., HDD, SSD), etc. Furthermore, it can be applied to the following situations: when a component connected to an external peripheral device enters a power saving mode, it can be awakened in advance and prepared for use.

[0255] [Effect]

[0256] As described above, the task scheduling devices 100 and 100A ( Figure 1 , Fig.10 ) in computing system 1000( Figure 1 , Fig.10 ) allocates tasks to the core group of the processor, and the computing system 1000 phases down the working state of the processor according to the processing load to reduce the power consumption. The task scheduling device 100, 100A comprises: a processor usage acquisition unit (task quantity·cycle prediction unit 122), which acquires the usage of the processor; and a task allocation unit (task CPU allocation unit 123), which continuously allocates tasks to the core or core group of the processor used at a specified frequency or above based on the usage of the processor acquired by the processor usage acquisition unit.

[0257] By doing so, depending on the processor usage (e.g., the amount of work), Figure 4 The judgment logic shown ensures that the frequently used CPU core group (the CPU core group in operation) continuously allocates tasks to the CPU core group, thereby preventing the transition to a deep C-state. As a result, the delay in recovering from the C-state can be reduced. On the other hand, since the CPU cores other than the operating CPU cores can be transferred to a deep C-state (e.g., C6), power saving can be achieved. As a result, from the perspective of the computing system 1000 as a whole, power saving can be achieved while performing calculations with low latency.

[0258] For the CPU core, since it can fall into a deep C-state, on the one hand, the power consumption reduction effect can be maximized, and on the other hand, the problem of falling into a deep C-state and taking time to recover can be avoided.

[0259] In addition, since the number of CPU cores used can be dynamically increased or decreased according to the task volume and CPU usage rate, the capacity can be dynamically reduced or expanded according to the task volume.

[0260] In addition, since it is possible to select multiple judgment logics for changing the number of CPU cores to be used according to the task volume and CPU usage ( Figure 4 ), so it can handle a variety of tasks.

[0261] In the task scheduling device 100, 100A ( Figure 1 , Fig.10 ) has a working state setting unit (C-state setting unit 132) which sets an upper limit for the core or core group of the processor used at a frequency above a specified frequency so that the working state of the processor cannot be transferred to a deeper state.

[0262] Thus, for frequently used CPU cores, the upper limit of the CPU idle state that can be transferred is set, so that it cannot be transferred to a deep C-state, reducing the recovery delay. Thus, the delay time from task allocation to the start of operation is suppressed, and high real-time operation can be achieved.

[0263] In particular, it is effective as a countermeasure when tasks cannot be continuously assigned to a CPU core group with a high usage frequency.

[0264] Furthermore, by assigning priorities to tasks, it is possible to preferentially calculate a task that is to be prioritized. The task to be preferentially calculated has, for example, a guarantee of QoS (Quality of Service).

[0265] In the task scheduling device 100, 100A ( Figure 1 , Fig.10 ), the working state setting unit (C-state setting unit 132) sets the core or core group to which the task allocation unit (task CPU allocation unit 123) has not allocated tasks, so that the working state of the processor can be transferred to a deeper state.

[0266] By doing this, tasks are continuously assigned to frequently used CPU core groups (operating CPU core groups), preventing transitions to deep C-states (reducing delays in recovering from C-states), and since CPU cores other than the operating CPU cores can transition to deep C-states, power saving can be achieved.

[0267] In the task scheduling device 100, 100A ( Figure 1 , Fig.10) has a pre-wake-up unit (CPU pre-wake-up unit 131) which, when assigning a task to a newly used core or a core that has not been used for a specified period of time and is used again, performs a pre-wake-up to restore the working state of the processor to its original state.

[0268] As a basic concept, if it takes time from when a task is assigned to when the processing is completed and when the task is restored, the CPU is woken up in advance according to the time until the restoration, and is prepared in advance to a state in which the CPU can be used.

[0269] By doing so, before assigning a task to a CPU core that has been transferred to a deep state, a pre-wake-up is performed, thereby reducing the time to recover from the deep state. It is assumed that a newly used core, or a core that has not been used for a specified time and is used again, is in a deep C-state. Before assigning a task, a pre-wake-up is performed, thereby reducing the time to recover from the deep C-state. For example, when increasing the number of CPU cores used, by waking up the CPU core in advance, even if it falls into a deep CPU idle state, the delay time from the assignment of tasks to the start of calculations can be suppressed, and calculations can be performed with high real-time performance.

[0270] In addition, the computing system 1000 ( Figure 1 , Fig.10 ) The working state of the processor is reduced in stages according to the processing load to reduce power consumption. The processor (CPU) has multiple core groups (CPU cores (CPU core #0, CPU core #1, ...) 32), and the computing system has a task scheduling device 100, 100A ( Figure 1 , Fig.10 ), the task scheduling device 100, 100A has: a processor usage acquisition unit (task amount / cycle prediction unit 122), which acquires the processor usage; and a task allocation unit (task CPU allocation unit 123), which continuously allocates tasks to the core or core group of the processor used at a specified frequency or above based on the processor usage acquired by the processor usage acquisition unit.

[0271] Computing system 1000~1000D( Figure 1 , Fig.10 , Figure 15 to Figure 18 ) is not limited to the task of packet arrival and processing, but is also a technology that can be extended to general tasks such as the calculation of π.

[0272] According to the utilization rate of the processor, by continuously allocating tasks to the frequently used CPU core group (the CPU core group in operation), the transition to a deep C-state is prevented, and the delay in recovering from the C-state can be reduced. On the other hand, since CPU cores other than the operating CPU cores can be transferred to a deep C-state, power saving can be achieved. That is, the delay in recovering from the C-state is reduced, and the pre-wake-up can keep the LPI (C-state) as deep as possible for as long as possible, so that low latency and power saving can be achieved.

[0273] The above-mentioned processor can be applied not only to a CPU but also to a processor such as a GPU / FPGA / ASIC having an idle state function.

[0274] In the computing system 1000 ( Figure 1 , Fig.10 ), low latency can be achieved while also saving power. In particular, by continuously allocating tasks to frequently used CPU core groups (CPU core groups in operation), the problem of a CPU core falling into a deep idle state and causing a longer delay time when recovering can be avoided. Thus, low latency can be guaranteed.

[0275] In addition, in each process described in the above embodiment, all or part of the processes described as automatically performed processes can also be performed manually, or all or part of the processes described as manually performed processes can also be performed automatically by a known method. In addition, the information about the processing sequence, control sequence, specific names, various data, and parameters included in the above article and shown in the drawings can be changed arbitrarily unless otherwise specified.

[0276] In addition, the components of each device shown in the figure are conceptual functions and do not necessarily need to be physically configured as shown in the figure. In other words, the specific distribution and integration of each device is not limited to the figure, and all or part of them can be functionally or physically distributed and integrated in arbitrary units according to load, usage, etc.

[0277] In addition, part or all of the above-mentioned structures, functions, processing parts, processing units, etc. can also be implemented by hardware, such as by designing in an integrated circuit. In addition, the above-mentioned structures, functions, etc. can also be implemented by software for interpreting and executing programs for the processor to implement various functions. Information such as programs, tables, files, etc. that implement various functions can be stored in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or an IC (Integrated Circuit) card, an SD (Secure Digital) card, an optical disk, or other recording media.

[0278] Description of Reference Numerals

[0279] 31: Hardware (HW);

[0280] 32: CPU core (processor);

[0281] 1, 1-1, 1-2, 1-3: Application (APL);

[0282] 100, 100A: task scheduling device;

[0283] 110: Management Department;

[0284] 111: Setting section for operators;

[0285] 120: Task Management Department;

[0286] 121: Task Priority Assignment Department;

[0287] 122: task volume and cycle prediction unit (processor usage acquisition unit);

[0288] 123: task CPU allocation unit (task allocation unit);

[0289] 120: Task Management Department;

[0290] 130: CPU idle state control unit;

[0291] 131: CPU pre-wake-up unit (pre-wake-up unit);

[0292] 132: C-state setting unit (working state setting unit);

[0293] 1000, 1000A, 1000B, 1000C, 1000D: operation system (computing system);

[0294] CPU core #0, CPU core #1, …: CPU cores.

Claims

1. A task scheduling device, characterized in that: The task scheduling device allocates tasks to a core group of a processor in a computing system, wherein the computing system reduces the working state of the processor in stages according to the processing load to reduce power consumption, and the task scheduling device has: A processor usage acquisition unit, which acquires the usage rate of the processor; as well as A task assigning unit continuously assigns tasks to a core or a core group of the processor used at a predetermined frequency or more based on the usage rate of the processor acquired by the processor usage rate acquiring unit.

2. The task scheduling device according to claim 1, characterized in that: have: The operating state setting unit sets an upper limit for a core or a core group of the processor used at a predetermined frequency or more so that the operating state of the processor cannot be transferred to a deeper state.

3. The task scheduling device according to claim 2, characterized in that: The operating state setting unit sets the operating state of the processor to a core or a core group to which no task is assigned by the task assigning unit, so that the operating state of the processor can be transferred to a deeper state.

4. The task scheduling device according to claim 1, characterized in that: have: The pre-awakening unit performs pre-awakening to restore the operating state of the processor to an original state when a task is assigned to a newly used core or a core that has not been used for a predetermined period of time and is used again.

5. A computing system, characterized in that: It reduces the processor's operating state in stages according to the processing load to reduce power consumption. The processor has a plurality of core groups. The computing system has a task scheduling device that allocates tasks to the core group of the processor. The task scheduling device comprises: A processor usage acquisition unit, which acquires the usage rate of the processor; as well as A task assigning unit continuously assigns tasks to a core or a core group of the processor used at a predetermined frequency or more based on the usage rate of the processor acquired by the processor usage rate acquiring unit.

6. A task scheduling method, characterized in that: The task scheduling method of a task scheduling device is described. The task scheduling device allocates tasks to a core group of a processor in a computing system. The computing system reduces the working state of the processor in stages according to the processing load to reduce power consumption. The task scheduling method includes: A step of obtaining the utilization rate of the processor; and A step of continuously allocating tasks to a core or a core group of the processor used at a predetermined frequency or higher based on the acquired usage rate of the processor.

7. A program for causing a computer to function as the task scheduling device according to any one of claims 1 to 4.

Images