A satellite navigation baseband processing device optimized by a coprocessor

Abstract

The present invention relates to a satellite navigation baseband processing device optimized by a coprocessor; the core processing part of the device adopts an implementation architecture of a main processor + a coprocessor; the coprocessor is used to real-time schedule hardware acceleration computing resources under the exchange control of the main processor to complete high-real-time processing tasks such as signal acquisition and tracking loop processing of satellite navigation; the instruction set and external interface of the coprocessor are specifically optimized, the bus bit width and internal storage width of the coprocessor are extended, and the original bit widths of the ALU and registers of the coprocessor are retained; according to the extended state, external port access and internal memory access instructions matching the widened bus are used for bus data access and storage; bus write enable, access instructions and deposit instructions matching the widened internal storage width are used for access and deposit of single register data. The present invention effectively reduces the functional load of the main processor and the implementation cost of the baseband processing device.

Description

Technical Field

[0001] The present invention belongs to the technical fields of system on chip and satellite navigation, and particularly relates to a satellite navigation baseband processing device with optimized coprocessor. Background Art

[0002] A satellite navigation receiver (GNSS receiver) can obtain its own position, velocity, and time (PVT) information by receiving and processing radio frequency signals broadcast by navigation satellites. The process of the GNSS receiver receiving navigation signals can be divided into two stages: First, signal acquisition and tracking processing are performed to detect the presence of satellite navigation signals and allocate a tracking channel to the existing signals for tracking processing. This stage is called the signal processing of satellite navigation. Second, navigation message demodulation, decoding, and ranging information extraction of the tracked satellites are performed. Based on this, user PVT information is calculated, and overall scheduling operations such as receiver time correction and allocation of satellites to be acquired are performed according to the navigation message and PVT information feedback. This stage is called the information processing of satellite navigation. The above two stages are collectively referred to as satellite navigation baseband processing, which is implemented by a satellite navigation baseband processing module (abbreviated as GNSS baseband module) inside the GNSS receiver. This module usually adopts an implementation architecture of an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA) + a processor (CPU) to meet the miniaturization and integration requirements of user terminals.

[0003] In the GNSS baseband module, the information processing of satellite navigation can usually be implemented by a general-purpose processor with strong performance. However, the signal processing of satellite navigation cannot be achieved solely by a general-purpose processor. Instead, it requires high-real-time scheduling of hardware accelerators such as acquisition engines and tracking engines by the processor. Currently, in mainstream GNSS baseband modules, there is an implementation architecture that uses a powerful main processor to concurrently perform the task of scheduling hardware resources in information processing and signal processing, and there is also an implementation architecture that uses a main processor plus a coprocessor. When using the implementation architecture of a main processor plus a coprocessor: the coprocessor can, under the switching control of the main processor, achieve front-end signal processing such as acquisition and tracking of satellite navigation signals by scheduling hardware resources such as tracking channels in real time; the main processor only needs to be responsible for overall scheduling and information processing of satellite navigation. By introducing a coprocessor in the baseband processing of satellite navigation, the following two problems can be solved: First, the coprocessor shares the high-real-time processing tasks of the main processor, reducing the load on the main processor, thereby reducing the requirements for the processing power of the main processor, and effectively reducing the technical threshold and economic cost of implementing the baseband processing module; Second, it effectively reduces the software complexity on the main processor, and can support encapsulation mechanisms such as using an embedded Linux operating system and custom driver modules, facilitating users to perform secondary development of software for specific application scenarios. Therefore, the implementation architecture of satellite navigation baseband processing using a main processor plus a coprocessor is an important technological development trend, and the key to supporting the development of this architecture lies in the optimized design of the coprocessor.

[0004] In the engineering practice of designing and implementing the GNSS baseband processing module, an ARM hard-core processor is usually selected as the main processor, and a soft-core processor is selected as the coprocessor. Among the available soft-core processors, they can be roughly divided into two categories: one category is non-open-source soft-core processors, such as the MicroBlaze soft-core processor of Xilinx Corporation, etc.; the other category is open-source soft-core processors, such as the PicoBlaze of Xilinx Corporation and the PicoRV32 based on the RISC-V instruction set, etc. For non-open-source soft-cores such as MicroBlaze, although they have advantages such as high processing efficiency, complete toolchains, and ease of use, it is difficult to obtain the RTL source code of this processor and it cannot be applied to ASIC implementation. Among the open-source soft-core processors: the PicoBlaze processor with less resource occupancy and easy integration is relatively suitable as a coprocessor for GNSS baseband processing, but its bus bit width is only 8 bits, the processing efficiency is not high enough, and software development is not very convenient; Soft-core processors such as PicoRV32 that comply with the RISC-V specification have sufficient processing power and relatively complete software development toolchains, but the original design intention of such processors is to be used as a main processor, requiring more implementation resources and being difficult to be trimmed and integrated according to the needs of GNSS baseband processing.

[0005] In summary, in view of the requirement of implementing satellite navigation baseband processing for the architecture of the application main processor plus the coprocessor, it is very necessary to optimize the design of a dedicated coprocessor. Summary of the Invention

[0006] In view of the above technical background analysis, the present invention aims to disclose a satellite navigation baseband processing device with optimized coprocessor, so as to solve the problem of optimized design of the coprocessor in implementing satellite navigation baseband processing by using the architecture of the main processor plus the coprocessor.

[0007] On the one hand, the present invention discloses a satellite navigation baseband processing device with optimized coprocessor, including:

[0008] An implementation architecture using a main processor + coprocessor; wherein,

[0009] The main processor is used for overall scheduling and information processing of satellite navigation, and is a processor with a wide bit width;

[0010] The coprocessor is used for real-time scheduling of hardware acceleration computing resources under the exchange control of the main processor, and performing signal acquisition and tracking loop processing of satellite navigation, and is a coprocessor with a narrow bit width;

[0011] Specifically optimize the instruction set and external interface of the coprocessor, expand the bus bit width and internal storage width of the coprocessor, and retain the original bit width of the arithmetic logic unit (ALU) and general registers of the coprocessor; according to the extended state, use external port access and internal memory access instructions matching the widened bus to perform bus data access and storage; use bus write enable, access instructions and store instructions matching the widened internal storage width to perform access and storage of single register data;

[0012] Cooperate with the optimized processor and the main processor to perform satellite navigation baseband processing.

[0013] On the other hand, the present invention discloses a satellite navigation receiver, which uses the satellite navigation baseband processing device with optimized coprocessor as described above to perform satellite navigation baseband processing.

[0014] The present invention can achieve one of the following beneficial effects:

[0015] The present invention utilizes the characteristic that the coprocessor required for satellite navigation baseband signal processing has a stronger requirement for I / O throughput than for arithmetic operations. By innovatively modifying the instruction set and its implementation mechanism of the publicly available PicoBlaze soft-core processor, the problems of insufficient bus access speed of the coprocessor and the mismatch between the bus width of the coprocessor and the bus width of the main processor are solved, and a class of coprocessors suitable for the field of satellite navigation signal processing implementation is formed.

[0016] In addition to inheriting the advantage of the PicoBlaze processor of occupying less hardware resources, the optimized co-processor solves the problem of unequal I / O throughput between the main processor and the co-processor, enabling the co-processor in the baseband processing device to better exert its control and computing efficiency, and the processing performance fully meets the requirements of completing common processing tasks such as tracking and acquisition scheduling in GNSS baseband signal processing. In addition, this type of processor is also implemented with RTL code, has a simple external interface, is easy to integrate and apply, and is convenient to be applied in ASIC design and domestic FPGA, and can replace more complex non-open source processors such as MicroBlaze.

[0017] By adopting the implementation architecture of the main processor plus the co-processor of the present invention in the satellite navigation baseband processing device and applying the co-processor optimized by the present invention, the functional load of the main processor can be effectively reduced, the implementation difficulty of the main processor can be significantly reduced, and thus the implementation cost of the baseband processing device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings are only for the purpose of showing specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components;

[0019] Figure 1 It is a schematic block diagram of the composition and connection of the satellite navigation baseband processing device optimized for the co-processor in the embodiment of the present invention;

[0020] Figure 2 It is a schematic block diagram of the internal composition and connection of the anti-jamming satellite navigation baseband processing device implemented by using a Zynq7035 chip in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The following will specifically describe the preferred embodiments of the present invention with reference to the drawings, wherein the drawings form a part of the present application and are used together with the embodiments of the present invention to explain the principle of the present invention.

[0022] Embodiment 1

[0023] An embodiment of the present invention discloses a satellite navigation baseband processing device optimized for a co-processor, as Figure 1 shown, adopting a main processor + co-processor architecture; wherein,

[0024] The main processor is used for overall scheduling and information processing of satellite navigation, and is a wide-bit-width processor; it mainly performs satellite navigation information processing with relatively low timeliness requirements, signal processing auxiliary calculations, etc.; the main processor is usually a processor with an ARM architecture, and the basic bit width of the bus and data is 32bit;

[0025] A coprocessor, which is used to schedule hardware acceleration computing resources in real time under the switching control of a main processor, perform signal acquisition and tracking loop processing of satellite navigation, and is a narrow-bit-width coprocessor;

[0026] Targetedly optimize the instruction set and external interface of the coprocessor; expand the bus bit width and internal storage width of the coprocessor, and retain the original bit width of the arithmetic logic unit (ALU) and general-purpose registers of the coprocessor; according to the expansion status, adopt external port access and internal memory access instructions that match the widened bus to perform bus data access and storage; adopt bus write enable, access instructions, and store instructions that match the widened internal storage width to perform access and storage of single-register data;

[0027] Cooperate with the optimized processor and the main processor to perform satellite navigation baseband processing.

[0028] The coprocessor includes one coprocessor for acquisition processing and at least one coprocessor for tracking processing; each coprocessor is respectively connected to the high-speed bus of the main processor, and data exchange with the main processor is realized through dual-port RAM.

[0029] In this embodiment, as a coprocessor of the main processor inside the GNSS baseband processing device, it can be implemented in an ASIC or FPGA, and only needs to independently execute a small section of program code under the configuration of the main processor, and does not need to have functions such as code loading and memory management of a complete general-purpose processor.

[0030] Therefore, the implementation purpose of the coprocessor proposed in the embodiment of the present invention is: on the premise of meeting the processing performance requirements, reduce the hardware resources occupied by the coprocessor as much as possible, and simplify the external interface of the coprocessor as much as possible to facilitate design integration.

[0031] Moreover, in the baseband signal processing of satellite navigation, the most typical processing task is the loop filtering processing of signal tracking. Such processing tasks need to implement calculation processing such as a pseudo-code phase discriminator and a carrier phase discriminator, and also need to implement a third-order phase-locked loop and a second-order frequency-locked loop based on fixed-point operation, and have the characteristics of a large number of calculation processing and hardware access control processing.

[0032] Therefore, when the coprocessor is mainly used to implement satellite navigation acquisition and tracking processing tasks, a large number of input and output access operations of hardware peripherals and computing acceleration units are required, and the arithmetic operation function of the coprocessor is mainly used in process and state control and some relatively simple calculations, showing the phenomenon of high requirements for I / O throughput but low requirements for arithmetic operations.

[0033] After analyzing the existing KCPSM3 soft-core processor that can be used as a coprocessor (a type of processor in the PicoBlaze series of Xilinx), it is found that due to the 8-bit width of both the bus and ALU of KCPSM3, its processing power is limited. When using the main processor + coprocessor architecture for GNSS baseband processing, it is difficult to meet the requirements of being used as a satellite signal tracking and scheduling control coprocessor. Although there are practices of using multiple KCPSM3 soft-core processors to parallelly share processing tasks for GNSS baseband processing coprocessors, the difficulty of building and designing the processing system and implementing the software is very high, which is not convenient for wide promotion.

[0034] Therefore, when using existing soft-core processors such as KCPSM3 as coprocessors, it leads to problems of low data throughput rate and slow processing speed.

[0035] The reason is that most of the various data and parameters for signal processing in the main processor are integer types with high bit widths, while the bus bit width of the narrow-bit-width coprocessor is low. The narrow-bit-width ALU of the coprocessor, since it is mainly used in process and state control and some relatively simple calculations, can meet the operation requirements.

[0036] Based on this, on the basis of inheriting the advantage of the PicoBlaze processor of occupying less hardware resources, the coprocessor of the embodiment of the present invention optimizes the coprocessors for acquisition and tracking respectively;

[0037] In the optimization, the bus bit width and the width of the internal storage of the coprocessor are expanded, and the original bit widths of the ALU and registers of the coprocessor are retained;

[0038] By expanding the bus bit width and the width of the internal storage of the coprocessor, its I / O throughput rate is increased, and moreover, the original bit widths of the ALU and registers of the coprocessor are retained, avoiding the waste of instruction space and the rapid increase of processor implementation resources caused by the increase in the bit widths of the ALU and registers;

[0039] And, according to the expansion state, external port access and internal memory access instructions matching the widened bus are adopted to perform bus data access and storage; bus write enable, access instructions and deposit instructions matching the widened internal storage width are adopted to perform access and deposit of single-register data; flexible access and storage of bus data and register data are realized.

[0040] Thus, the problems of the coprocessor's bus access speed not being fast enough and the mismatch between the bus width of the coprocessor and the bus width of the main processor are solved, forming a type of coprocessor suitable for the field of satellite navigation signal processing implementation; on the premise of meeting the processing performance requirements, the hardware resources occupied by the coprocessor are reduced as much as possible, and the external interface of the coprocessor is simplified as much as possible, which is convenient for design and integration.

[0041] In this embodiment, based on a PicoBlaze processor such as KCPSM3, the following specific optimizations and improvements are made to the coprocessor:

[0042] First, change the data bit width of the external bus to twice the bit width of the internal basic register. The bit width of the internal ALU is the same as that of the register, and the width of the internal storage is also changed to twice the register width. Correspondingly, change the actual execution meaning of the two external port access instructions, Input and output, and the two internal memory access instructions, fetch and store, to operate on a group of two adjacent registers simultaneously, while the execution meaning of other instructions remains unchanged;

[0043] When the data bit width of the external bus is changed to twice the register width, when executing instructions including "Op Sx, kk" and "Op Sx, Sy", where Op is one of Input, output, fetch, or store; the accessed registers include Sx and another register Sx' adjacent to Sx. When x is an even number such as 0, 2, 4, etc., x' = x + 1; when x is an odd number such as 1, 3, 5, etc., x' = x - 1;

[0044] For example: when executing the input s2 03 instruction, the data with a bit width twice that of the register read from the external port 03 will be written into the two registers s2 and s3; when executing the output s3 03 instruction, the data with a bit width twice that of the register composed of the two registers {s3, s2} will be written to the external port 03; when executing the fetch s5 05 instruction, the data at the 05 address of the internal memory will be read into the two registers s4 and s5; when executing the store s6 05 instruction, the data with a bit width twice that of the register composed of the two registers {s7, s6} will be written to the 05 address of the internal memory.

[0045] In this way, accessing two registers can be achieved through one instruction, improving the I / O throughput rate.

[0046] Second, change the bus write enable outside the processor to 2-bit high and low. In the instruction set, add a new external port output instruction outHB; used to implement data access operations based on a single register; thus making up for the deficiency that after modifying the execution meaning of the output instruction in the first improvement to operate on two registers, it cannot output the data of a single register alone.

[0047] The external port output instruction outHB includes two forms: "outHB Sx, kk" and "outHB Sx, Sy"; the corresponding meanings are: only output the value of register Sx to the external port whose address is the immediate number kk or the value of register Sy;

[0048] When x is even, the data corresponding to the outHB instruction is output to the lower half of the bus of the external port, and at this time the write enable of the lower bit is effective;

[0049] When x is odd, the data corresponding to the outHB instruction is output to the upper half of the bus of the external port, and at this time the write enable of the higher bit is effective;

[0050] When executing the output instruction that operates on a group of two adjacent registers at the same time, the write enables of the higher and lower 2 bits are both effective.

[0051] For example: the outHB S0 06 instruction will write the value of register S0 to the lower half of port 06; the outHB S1 06 instruction will write the value of register S0 to the upper half of port 06.

[0052] Third, in the instruction set, a new internal RAM data storage instruction storeHB is added to store the data of a single register separately; thus solving the deficiency of software programming applications caused by the modification of the execution meaning of the store instruction in the first improvement, which becomes that only two registers can be stored at the same time and a single register cannot be stored separately.

[0053] The internal RAM data storage instruction storeHB includes two forms: "storeHB Sx, kk" and "storeHB Sx, Sy"; the corresponding meanings are: only store the value of register Sx into the internal RAM memory, and the address is determined by the immediate number kk or the value of register Sy;

[0054] When x is even, the data corresponding to the storeHB instruction is stored in the lower half of the address of the internal RAM;

[0055] When x is odd, the data corresponding to the storeHB instruction is stored in the upper half of the address of the internal RAM.

[0056] For example: the storeHB S2 07 instruction will write the value of register S2 to the lower half of the internal memory address at position 07; the outHB S3 07 instruction will write the value of register S3 to the upper half of the internal memory address at position 07.

[0057] In a specific implementation plan, a satellite navigation baseband processing device with an architecture of 1 main processor + 2 coprocessors is given;

[0058] Among them, the two coprocessors are the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A respectively;

[0059] The first coprocessor is a capture coprocessor, which is used for the front-end signal processing of satellite navigation signal capture and executes the capture program; it is optimized by using a PicoBlaze processor with an instruction data bit width of 8 bits, such as the KCPSM3 processor;

[0060] Through optimization, the capture coprocessor maintains an instruction data bit width of 8 bits, and the bus data width is extended to 16 bits;

[0061] The second coprocessor is a tracking coprocessor, which is used for the front-end signal processing of satellite navigation signal tracking and executes the tracking program; it is optimized by using a PicoBlaze processor with an instruction data bit width of 16 bits;

[0062] Through optimization, the instruction data bit width of the tracking coprocessor is extended to 26 bits, and at the same time the bus data width is extended to 32 bits.

[0063] After the instruction data bit width and bus data width of the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A are extended, the coprocessor decoding method, external port definition and instruction set are optimized, specifically including:

[0064] (1) The first coprocessor WUPSM-3A;

[0065] The instruction bit width of the first coprocessor is 18 bits, the bus width is 16 bits, and the bit width of the ALU is 8 bits. There are 16 8-bit registers inside the processor, numbered S0 to SF, the internal memory bit width is 16 bits, and the depth is configurable (the default is 32, and the configurable range is 32, 64, 128, 256), and the program code space is 1024×18 bits;

[0066] If a single instruction is Instr[17:0], then the decoding methods of each part are as follows:

[0067] Instr[17:14] ---- Instruction main type;

[0068] Instr[13:12] ---- Instruction secondary type;

[0069] Instr[11:10] ---- Whether the jump instruction depends on the Z, NZ, C, NC flag bits;

[0070] Instr[11:8] ---- First operand;

[0071] Instr[7:4] ---- Second operand;

[0072] Instr[7:0] ---- Immediate value.

[0073] The WUPSM-3A processor implements the code implementation at the RTL level. The name of the top-level module is dvanced_lite_pb, and the external port definitions are shown in the following table.

[0074]

[0075] (2) The second coprocessor WUPSM-4A;

[0076] The instruction bit width of the second coprocessor is 26 bits (extended from 18 of PicoBlaze to 26), the bus width is 32 bits, and the bit width of the ALU is 16 bits; there are 16 16-bit registers inside the processor, numbered S0 to SF, the internal memory bit width is 32 bits, and the depth is configurable (the default is 32, and the configurable range is 32, 64, 128, 256... up to 65536), and the storage space for program code is 4096×26 bits;

[0077] If a single instruction is Instr[25:0], the decoding methods for each part are as follows:

[0078] Instr[25:22] ---- Instruction main type;

[0079] Instr[21:20] ---- Instruction secondary type;

[0080] Instr[19:18] ---- Whether it depends on the Z, NZ, C, NC flags;

[0081] Instr[19:16] ---- First operand;

[0082] Instr[15:12] ---- Second operand;

[0083] Instr[15:0] ---- Immediate value.

[0084] The WUPSM-4A processor implements the code implementation at the RTL level. The name of the top-level module is advanced_lite, and the external port definitions are shown in the following table.

[0085]

[0086] (3) Detailed instruction set definitions for the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A

[0087] The detailed instruction set definitions of WUPSM-3A and WUPSM-4A are summarized in the following table.

[0088]

[0089]

[0090]

[0091]

[0092] When performing satellite navigation baseband processing using the satellite navigation baseband processing device with an architecture of 1 main processor + 2 coprocessors in this embodiment,

[0093] The first coprocessor, WUPSM-3A, connects a signal acquisition hardware accelerator (referred to as the acquisition engine) to its external bus. It is used to configure the acquisition engine to start and execute signal acquisition processing according to the signal acquisition instruction initiated by the main processor, and feedback the acquired results to the main processor.

[0094] The first coprocessor mainly completes the scheduling and control tasks of the acquisition engine and does not require complex arithmetic calculations. Therefore, it uses an instruction bit width of 18 bits and a bus width of 16 bits. Combined with the optimized instruction set, it realizes the I / O throughput in the scheduling and control tasks, improves its I / O throughput rate, and performs calculations through an ALU with a bit width of 8 bits. On the basis of meeting the application requirements, it avoids the waste of instruction space and the rapid increase of processor implementation resources caused by the increase in the bit widths of the ALU and registers.

[0095] The second coprocessor, WUPSM-4A, connects a group of signal tracking channels (referred to as the tracking engine), such as 36 channels, to its external bus. It is used to complete the pseudocode despreading and loop filtering processing of a group of signal tracking channels set therein, ensure that the local carrier and pseudocode phase of the tracking channels remain consistent with the true signal being tracked, and at the same time transmit the correlation value information obtained after pseudocode despreading and secondary code stripping of the signal to the main processor, and then the signal processing module in the main processor performs processing such as Doppler estimation, bit synchronization, message synchronization, and message decoding based on FFT.

[0096] In the second coprocessor, it is necessary to not only complete the scheduling and control tasks for the tracking engine, but also implement the loop filtering process for satellite signal tracking. The specific tasks include: implementing computational processes such as the pseudo-code phase discriminator and carrier phase discriminator, and implementing the third-order phase-locked loop and second-order frequency-locked loop processes based on fixed-point operation, etc. In the traditional conventional implementation scheme, such tracking coprocessing tasks are implemented by relatively large-scale soft-core processors with strong processing capabilities, such as MicroBlaze and ARM7. Therefore, compared with the acquisition process, the requirements for I / O throughput and arithmetic calculation are higher, and the real-time requirement is also higher. Therefore, a 26-bit instruction bit width and a 32-bit bus width are adopted, combined with an optimized instruction set, to implement the I / O throughput in the scheduling and control tasks, improve its I / O throughput rate, and perform calculations through an ALU with a bit width of 16 bits.

[0097] In summary, for the satellite navigation baseband signal processing device according to the embodiments of the present invention, by utilizing the characteristic that the coprocessor required for satellite navigation baseband signal processing has a stronger requirement for I / O throughput than for arithmetic operations, through the innovative design of the instruction set and its execution mechanism, and through the innovative modification of the instruction set and its implementation mechanism of the publicly available PicoBlaze soft-core processor, the problems of insufficient bus access speed of the coprocessor and the mismatch between the bus width of the coprocessor and the bus width of the main processor are solved, so that the coprocessor in the baseband processing device can better exert its control and computing efficiency, and the processing performance fully meets the requirements for completing common processing tasks such as tracking and acquisition scheduling in GNSS baseband signal processing. In addition, the designed coprocessor is also implemented using RTL code, has a simple external interface, is convenient for integration and application, and is convenient for application in ASIC design and domestic FPGAs, and can replace more complex non-open-source processors such as MicroBlaze. In such baseband processing devices, by applying highly efficient coprocessing and effectively reducing the functional load of the main processor, the implementation difficulty of the main processor can be significantly reduced, thereby reducing the implementation cost of the baseband processing device.

[0098] Embodiment 2

[0099] This embodiment discloses that in the FPGA prototype design of a low-cost satellite navigation anti-jamming terminal, the satellite navigation baseband processing device is fully implemented on a single Xilinx Zynq7035 chip, and an implementation architecture of a main processor plus multiple coprocessors is adopted; as Figure 2 shown,

[0100] Among them: the main processor of the baseband processing device is the dual-core ARM9 processor in the PS part of the Zynq7035 chip; the first coprocessor and the second coprocessor are implemented in the PL part of the Zynq chip, and both coprocessors realize data exchange with the main processor through dual-port RAM;

[0101] The first coprocessor and the second coprocessor respectively implement the coprocessing scheduling of the capture engine and the tracking engine; respectively implement the scheduling control coprocessing for one capture channel and 36 tracking channels; receive and process the signals of each frequency point of Beidou B1 and B3 and the civil signal of GPS L1 frequency point.

[0102] Preferably, an anti-interference module is further added to the baseband processing device, which is used to implement an array anti-interference algorithm based on 4 array elements. After canceling the interference signals in the received signals, the baseband processing of satellite navigation is carried out, so as to improve the ability of the processing device to adapt to complex interference environments.

[0103] Due to the introduction of the first coprocessor and the second coprocessor, the implementation resources occupied by the baseband processing part are minimized as much as possible in the design. The various resources occupied by the baseband processing device other than the processing array anti-interference are shown in the following table:

[0104]

[0105] As can be seen from the above table, in the baseband processing part, after optimization, a receiver with 36 channels only occupies no more than 60% of the main processing resources, and a large amount of DSP and BRAM resources are reserved for implementing the array anti-interference algorithm. Therefore, based on the method of the present invention, the PL part of a single Zynq7035 device can also simultaneously implement the array anti-interference processing of 4 array elements, and runs stably, realizing the capture, tracking and positioning solution processing of navigation signals on the Zynq chip with limited resources, and at the same time realizing the anti-interference processing, achieving satellite navigation positioning with strong anti-interference ability under low-cost conditions.

[0106] Specifically, it further includes a first program code memory;

[0107] The software for implementing the capture engine scheduling and control processing on the first coprocessor WUPSM-3A coprocessor is written in assembly code (the assembler is modified on the basis of the open-source assembler supporting PicoBlaze), and the length of the compiled binary program code is 394; a 18bitx512 BRAM is used as the first program code memory to store the program code of this coprocessor. After synthesis, the path of the WUPSM-3A processing in the design is:

[0108] U_DIT_LiteUav / U_gnss_main_proc / inst / U_ae / inst / U_acq_top / U_mcu_acq / U_pb_for_acq

[0109] The resources consumed by this processor include: 78 FLOP_LATCH, 164 LUT, 3 CARRY, and 57 DMEM.

[0110] Specifically, it also includes a second program code memory;

[0111] The software for implementing the tracking engine scheduling and control processing on the second coprocessor WUPSM-4A processor is written in assembly code (the assembler is modified based on the open-source assembler that supports PicoBlaze), and the length of the compiled binary program code is 1271; a 26bitx2048 BRAM is used as the first program code memory to store the program code of this coprocessor. After synthesis, the path of the WUPSM-4A processing in the design is:

[0112] U_DIT_LiteUav / U_gnss_main_proc / inst / U_TrackCtrlCp / U_mcu_track / U_pb_for_track

[0113] The resources consumed by this processor include: 124 FLOP_LATCH, 227 LUT, 17 CARRY, and 108 DMEM.

[0114] In summary, it can be seen that the coprocessor designed by the present invention indeed has the advantage of being very resource-saving.

[0115] To further comprehensively illustrate the characteristics of the coprocessor proposed by the present invention, in this embodiment, the second coprocessor WUPSM-4A processor of the present invention is also compared with the mainstream MicroBlaze processor in terms of implementation cost, processing efficiency, and convenience of application software development and debugging.

[0116] Since when the tracking engine uses WUPSM-4A for scheduling the tracking engine, an additional interface control circuit for adapting the tracking engine, a multiplier for accelerating calculations, an arctangent lookup table, etc. are all implemented in the tracking engine module (i.e., the U_TrackCtrlCp module), while for the MicroBlaze processor, only the interface control circuit for adapting the tracking engine is required externally to form the tracking engine module U_TrackCtrlCp. Therefore, a comparison can be made by replacing the implementation of the U_TrackCtrlCp module in the entire PL design.

[0117] The comparison of the resource occupancy is shown in the following table:

[0118]

[0119] As can be seen from the above table, when using WUPSM-4A as a coprocessor, except for the LUT resources used by the tracking engine scheduling module being more than those of MicroBlaze, the remaining resources are less than those of MicroBlaze. Since WUPSM-4A uses assembly code that directly operates on hardware and does not need to use standard C library functions, the volume of the program code is effectively reduced, resulting in a reduction of 2 BRAMs with a capacity of 36 Kbit. Since a 32x32-bit hardware multiplier is configured in MicroBlaze, the number of standard multipliers consumed is 4. When using the WUPSM-4A processor, a 16x32-bit multiplier is optimally used according to the characteristics of the tracking coprocessing, thus achieving a reduction of two standard multipliers in consumption.

[0120] The comparison of processing efficiency is as follows:

[0121] Considering that in the tracking engine scheduling process, the most important algorithms that the coprocessor needs to implement are typical tracking loop processes, including: pseudo-code phase discriminator, carrier phase discriminator, and loop filtering, etc. By constructing a simulation test bench based on system verilog and using a front-end simulation tool for simulation, the number of clock cycles required for one loop process of the two processors is respectively recorded, and the processing efficiency of the two processors can be analyzed and compared. The specific situation is shown in the following table.

[0122]

[0123] As can be seen from the above table, when the working clock frequency is the same at 124 MHz, the coprocessor based on MicroBlaze has a relatively high processing speed, but the processing speed of the coprocessor based on WUPSM-4A can reach about 2 / 3 of that of MicroBlaze. No matter which processor is used, there is enough software processing time margin when performing tracking coprocessing scheduling for 36 channels.

[0124] The comparison of the convenience of application software development and debugging is as follows:

[0125] In the trace co-processor based on MicroBlaze, its software programming can use C / C++ language. In the SDK software provided by Xilinx, software compilation is carried out to form a binary program file that needs to be initialized into the program memory. The programming implementation of the application software is relatively convenient, and the maintainability of the software code is also good. However, due to the need to use standard C library functions, there is a problem that the compiled code size is relatively large. In the trace co-processor based on WUPSM-4A, its software programming uses assembly language that can directly operate the registers in the processor. There are certain limitations in software development, implementation, and the maintainability of software code. However, using assembly language can more directly utilize the characteristics of the processor architecture to minimize the program space and data space as much as possible. In the specific programming implementation, the function functions implemented in the WUPSM-4A processor using assembly language can be compared one by one with the function functions implemented on the MicroBlaze processor to accelerate the verification of software functions. For example: On the MicroBlaze processor, the trace data of each signal trace channel is stored in a data structure as follows:

[0126] typedef struct{

[0127] S64 np_filter;

[0128] S64 wp_filter;

[0129] S32 carr_fault_h;

[0130] S32 carr_fault_l;

[0131] S32 code_fault_h;

[0132] S32 code_fault_l;

[0133] S32 carry_fre_int;

[0134] S32 carry_nco_fre_err;

[0135] S32 dither;

[0136] S32 carry_fre_frac;

[0137] S32 code_nco_fre_err;

[0138] S32 fft_fd;

[0139] S32 MessAcc;

[0140] S32 i_amp_mean;

[0141] S32 q_amp_mean;

[0142] S32 square_corr;

[0143] S16 early_Icorr;

[0144] S16 early_Qcorr;

[0145] S16 punct_Icorr;

[0146] S16 punct_Qcorr;

[0147] S16 late_Icorr;

[0148] S16 late_Qcorr;

[0149] U16 FreSel;

[0150] U16 SatNum;

[0151] U16 BrhId;

[0152] U16 RateType;

[0153] U16 wait_syn_en;

[0154] U16 mess_num;

[0155] U16 cnt;

[0156] U16 nav_bit_cnt;

[0157] U16 req_cnt;

[0158] U16 vld_bit;

[0159] U16 fd_vld;

[0160] U16 trackI_th;

[0161] U16 lock_en;

[0162] U16 carry_lock;

[0163] U16 lock_cnt_optimistic;

[0164] U16 lock_cnt_pessimistic;

[0165] U16 State;

[0166] }STrackPara;

[0167] The size of the storage space occupied by the STrackPara structure is 118 bytes.

[0168] Correspondingly, in the WUPSM-4A processor, in the externally connected RAM memory with a bit width of 32 bits, 30 address spaces will be allocated for each channel to store the above variables, and they will be arranged in the same order as the variables in the STrackPara structure. Thus, for the 32-bit width components of the S32 type in the above structure, the input and output instructions can be directly used for read and write access; for the 64-bit width components of the S64 type in the above structure, the input and output instructions can be called continuously twice for read and write access; for the 16-bit width components of the S16 / U16 type in the above structure, the input instruction can be used for read access, but the outHB instruction can be used for write access. For the data read into the register by the input instruction more, it can be discarded and not used.

[0169] For another example: A C function based on an arctangent lookup table that implements the phase discriminator function on MicroBlaze is as follows,

[0170]

[0171]

[0172]

[0173] Correspondingly, when implementing the tracking coprocessor based on WUPSM-4A, the following program segment with the same function is implemented using assembly code:

[0174]

[0175]

[0176]

[0177]

[0178] During development and implementation, through means such as simulation and code verification, it can be verified that the function to be implemented by the above code is the same as the function implemented by the C function GetPllDetec, and then other higher-level function development can be carried out.

[0179] Based on the above comparisons, when used to construct a coprocessor for satellite navigation signal tracking, the WUPSM-4A processor can reach a level comparable to that of the MicroBlaze in terms of both resource occupancy and processing efficiency. Although the WUPSM-4A processor uses an assembly program to write software, the complexity of its application software development is also within an acceptable range. In addition, due to the more streamlined design of the WUPSM-4A, it is easier to operate under high clock frequencies and is more suitable for application in ASIC design.

[0180] Embodiment 3

[0181] The present invention also discloses a satellite navigation receiver, in which a satellite navigation baseband processing device optimized by the coprocessor described in the above embodiment is used for satellite navigation baseband processing.

[0182] The specific technical details and beneficial effects in this embodiment are the same as those in the above embodiments. For specific reference, they will not be elaborated here one by one.

[0183] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A coprocessor-optimized satellite navigation baseband processing device, characterized in that: It adopts the main processor + coprocessor architecture; The main processor is used for overall scheduling and satellite navigation information processing and is a wide-bit-width processor; The coprocessor is used to schedule hardware accelerated computing resources in real time under the switching control of the main processor, and to perform signal acquisition and tracking loop processing for satellite navigation. It is a narrow bit width coprocessor; Targeted optimization of the coprocessor's instruction set and external interface; expansion of the coprocessor bus width and internal storage width, retaining the original width of the coprocessor ALU and general registers; using external port access and internal storage access instructions that match the widened bus according to the expansion status to access and store bus data; using bus write enable, access instructions and storage instructions that match the widened internal storage width to access and store single register data; Satellite navigation baseband processing is performed through the cooperation of optimized processor and main processor; In the optimization of the coprocessor, the data bit width of the external bus is changed to twice the bit width of the internal basic register, the bit width of the internal ALU is kept the same as the bit width of the register, and the width of the internal storage is also changed to twice the width of the register; accordingly, the actual execution meaning of the two external port access instructions, input and output, and the two internal storage access instructions, fetch and store, are changed to operate on a group of two adjacent registers at the same time, and the execution meaning of other instructions remains unchanged; In the instructions "Op Sx, kk" and "Op Sx, Sy", the Op is one of Input, output, fetch, and store, and the operated registers include Sx and another register Sx' adjacent to Sx; when x is an even number, x' = x+1; when x is an odd number, x' = x-1; Change the bus write enable of the coprocessor's external bus to high and low 2 bits; add a new external port output instruction outHB in the instruction set; used to implement data access operations based on a single general register; The external port output instruction outHB includes two forms: "outHB Sx, kk" and "outHB Sx, Sy". The corresponding meaning is: only output the value of register Sx to the external port with the immediate value kk or the value of register Sy as the address; When x is an even number, the data corresponding to the outHB instruction is output to the lower half of the bus of the external port, and the write enable of the lower bit is valid at this time; When x is an odd number, the data corresponding to the outHB instruction is output to the high half of the bus of the external port, and the write enable of the high bit is valid at this time; When executing an output instruction that operates on a group of two adjacent registers at the same time, both the high and low 2-bit write enables are valid; In the instruction set, a new internal RAM data storage instruction storeHB is added to store single register data separately; The internal RAM data storage instruction storeHB includes two forms: "storeHB Sx, kk" and "storeHB Sx, Sy". The corresponding meaning is: only store the value of register Sx into the internal RAM storage, and the address is determined by the immediate value kk or the value of register Sy. When x is an even number, the data corresponding to the storeHB instruction is stored in the lower half of the address of the internal RAM; When x is an odd number, the data corresponding to the storeHB instruction is stored in the high half of the address of the internal RAM; The satellite navigation baseband processing device adopts a 1 main processor + 2 coprocessor architecture; The two coprocessors are the first coprocessor WUPSM-3A and the second coprocessor WUPSM-4A; The first coprocessor is a capture coprocessor, which is used for front-end signal processing of satellite navigation signal capture and executes the capture program. It is optimized using a PicoBlaze processor with an instruction data bit width of 8 bits. Through optimization, the capture coprocessor maintains the instruction data bit width of 8 bits and expands the bus data width to 16 bits. The second coprocessor is the tracking coprocessor, which is used for front-end signal processing of satellite navigation signal tracking and executes the tracking program. It is optimized using the PicoBlaze processor with an instruction data bit width of 16 bits. Through optimization, the instruction data bit width of the tracking coprocessor is expanded to 26 bits, and the bus data width is expanded to 32 bits.

2. The coprocessor-optimized satellite navigation baseband processing device according to claim 1, characterized in that: The instruction bit width of the first coprocessor is 18 bits, the bus width is 16 bits, and the ALU bit width is 8 bits. The processor has 16 8-bit registers numbered S0 to SF, and the internal memory bit width is 16 bits, and the depth is configured according to the requirements. A single instruction is Instr[17:0], and the decoding method of each part is: Instr[17:14] ---- instruction main type; Instr[13:12] ---- instruction auxiliary type; Instr[11:10] ---- Whether the jump instruction depends on the Z, NZ, C, NC flags; Instr[11:8] ---- first operand; Instr[7:4] ---- second operand; Instr[7:0] ---- immediate value; The external port of the first coprocessor includes the pin write_strobe[1:0]; the corresponding function and timing are described as follows: Write enable signal of external bus, single cycle, high effective; write_strobe[0] corresponds to writing the lower 8 bits; that is, out_port[7:0]; write_strobe[1] corresponds to writing the upper 8 bits; that is, out_port[15:8].

3. The coprocessor-optimized satellite navigation baseband processing device according to claim 1, characterized in that: The instruction width of the second coprocessor is 26 bits, the bus width is 32 bits, and the ALU width is 16 bits. The processor has 16 16-bit registers numbered S0 to SF, the internal memory width is 32 bits, and the depth is configured according to the requirements. The single instruction is Instr[25:0], and the decoding method of each part is: Instr[25:22] ---- instruction main type; Instr[21:20] ---- instruction auxiliary type; Instr[19:18] ---- Whether to rely on Z, NZ, C, NC flags; Instr[19:16] ---- first operand; Instr[15:12] ---- second operand; Instr[15:0] ---- immediate value; The external port of the second coprocessor includes the pin write_strobe[1:0]; the corresponding function and timing are described as follows: Write enable signal of external bus, single cycle, high effective; write_strobe[0] corresponds to writing the lower 16 bits; that is, out_port[15:0]; write_strobe[1] corresponds to writing the upper 16 bits; that is, out_port[31:16].

4. The coprocessor-optimized satellite navigation baseband processing device according to any one of claims 1 to 3, characterized in that: The satellite navigation baseband processing device is implemented on a Xilinx Zynq chip; The main processor of the satellite navigation baseband processing device is a dual-core ARM9 processor in the PS part of the Zynq chip; the first coprocessor and the second coprocessor are implemented in the PL part of the Zynq chip; both coprocessors exchange data with the main processor through dual-port RAM; The first coprocessor and the second coprocessor implement the coprocessing scheduling of the capture engine and the tracking engine respectively; Implement baseband processing of one acquisition channel and 36 tracking channels; Receive and process the Beidou B1 and B3 frequency signals and the GPS L1 frequency civil signal.

5. The coprocessor-optimized satellite navigation baseband processing device according to claim 4, characterized in that: The PL part of a single Zynq device is used to remove the remaining resources occupied by the first coprocessor and the second coprocessor to build an anti-interference module for performing anti-interference on the received satellite navigation signal to achieve array anti-interference processing of 4 array elements.

6. A satellite navigation receiver, characterized in that: The satellite navigation receiver adopts the coprocessor-optimized satellite navigation baseband processing device as described in any one of claims 1 to 5 to perform satellite navigation baseband processing.

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