Time-to-digital conversion method and time converter

Abstract

The invention is suitable for the technical field of automatic measurement, and particularly relates to a time-to-digital conversion method and a time converter, and the method comprises the steps: inputting a to-be-measured signal into a carry chain, and generating a delay signal of the first to-be-measured signal; determining the edge of the to-be-detected signal according to the clock signal and the delay signal of the to-be-detected signal, wherein the edge of the to-be-detected signal comprises a rising edge and a falling edge; determining a coarse time count value of the to-be-measured signal according to the edge of the to-be-measured signal; determining a fine time measurement value of the to-be-measured signal according to the delay signal of the to-be-measured signal; and determining the timestamp of the edge of the to-be-measured signal according to the fine time measurement value of the to-be-measured signal and the coarse time count value of the to-be-measured signal. According to the invention, the rising edge and the falling edge of the first to-be-tested signal are determined to obtain the timestamps of the rising edge and the falling edge on the same time axis, so that the duration time of the to-be-tested signal can be quickly and accurately obtained.

Description

Technical Field

[0001] The present application belongs to the field of automatic measurement technology, and in particular relates to a time-to-digital conversion method and a time converter. Background Art

[0002] Time to digital conversion technology is used to convert time representation from different formats to another format. It can convert time representation from text or string form to computer-readable date and time format, or vice versa. For existing time to digital converters (Time to Digital Converter TDC), how to obtain the duration of the signal is the top priority of signal measurement. In the existing time to digital conversion process, TDC receives a stable clock signal as a reference signal. TDC also receives one or more signals to be measured. The rising edge and falling edge of the signal to be measured respectively represent the start and end of the event to be measured. When the rising edge of the signal to be measured is triggered, TDC starts counting clock pulses. At the same time, when the falling edge of the signal to be measured is triggered, TDC stops counting. By recording the count values ​​at the start and stop times, TDC can determine the duration of the signal. TDC converts the measured duration into digital form and outputs it to the subsequent data processing unit. The output can be a digital count value representing a discrete amount of a time interval, or a digital code or other form of digital representation. However, for high-frequency signals or in an environment with electromagnetic interference, the edges of the signal to be measured are easily distorted, making it difficult to determine the rising and falling edges of the signal to be measured. When the sampling rate is low, the edges of the signal to be measured may be missed, making it difficult to obtain the duration of the signal to be measured.

[0003] At the same time, in some cases, electronic devices need a certain amount of time to complete internal processing or return to working state, and this period of time is called dead time. Dead time may be caused by factors such as switching operation, signal transmission delay, circuit response time, etc. In the process of time-to-digital conversion in each channel, due to the long dead time of time conversion, the waiting time between two time-to-digital conversion tasks is long, which makes the time-to-digital conversion task completion efficiency low. Summary of the invention

[0004] The embodiments of the present application provide a time-to-digital conversion method, a multi-channel time converter, a terminal and a medium, which can solve the problem in the prior art that it is difficult to measure the duration of a signal through a time-to-digital converter.

[0005] In a first aspect, an embodiment of the present application provides a time-to-digital conversion method, comprising:

[0006] Inputting the first signal to be tested into the first carry chain to generate a delayed signal of the first signal to be tested;

[0007] Determine the edge of the first signal to be tested according to the clock signal and the delay signal of the first signal to be tested, wherein the edge of the first signal to be tested includes a rising edge and a falling edge;

[0008] Determine a coarse time count value of the first signal to be measured according to an edge of the first signal to be measured;

[0009] Determine a fine time measurement value of the first signal to be measured according to a delayed signal of the first signal to be measured;

[0010] A time stamp of an edge of the first signal to be measured is determined according to a fine time measurement value of the first signal to be measured and a coarse time count value of the first signal to be measured.

[0011] In an embodiment of the first aspect of the present application, by determining the rising edge and the falling edge of the first signal to be tested, the timestamps of the rising edge and the falling edge on the same time axis are obtained, so that the duration of the signal to be tested can be quickly obtained.

[0012] In a possible implementation manner of the first aspect, the following steps are also included:

[0013] Inputting the second signal to be tested into the second carry chain to generate a delayed signal of the second signal to be tested;

[0014] Determine the edge of the second signal to be tested according to the clock signal and the delay signal of the second signal to be tested, wherein the edge of the second signal to be tested includes a rising edge and a falling edge;

[0015] determining a coarse time count value of the second signal to be measured according to an edge of the second signal to be measured;

[0016] Determine a fine time measurement value of the second signal to be measured according to the delayed signal of the second signal to be measured;

[0017] A timestamp of an edge of the second signal to be measured is determined according to a fine time measurement value of the second signal to be measured and a coarse time count value of the second signal to be measured.

[0018] In a possible implementation manner of the first aspect, the method further includes the following steps:

[0019] A lag time of the second signal to be tested compared with the first signal to be tested is determined according to the timestamp of the edge of the first signal to be tested and the timestamp of the edge of the second signal to be tested.

[0020] In an embodiment of the first aspect of the present application, by calculating rising edge timestamps or falling edge timestamps of different signals to be measured in different channels, it is convenient to calculate the phase difference between two signals to be measured.

[0021] In a possible implementation manner of the first aspect, determining an edge of the first signal to be tested according to a clock signal and a delayed signal of the first signal to be tested includes:

[0022] Before the delay signal of the first signal to be tested triggers the edge trigger, an output value of the first delay signal is obtained, where the first delay signal is a delay signal output by the carry chain at the first rising edge of the clock signal before the delay signal of the first signal to be tested triggers the edge trigger;

[0023] After the delay signal of the first signal to be tested triggers the edge trigger, an output value of the second delay signal is obtained, where the second delay signal is a delay signal output by the carry chain at the first rising edge of the clock signal after the delay signal of the first signal to be tested triggers the edge trigger;

[0024] According to the output value of the first delayed signal and the output value of the second delayed signal, it is determined whether the edge of the signal to be tested is a rising edge or a falling edge.

[0025] In an embodiment of the first aspect of the present application, by comparing the output values ​​at the rising edges of different clock signal cycles before and after the delay signal triggers the edge trigger, it is determined whether the edge of the signal to be tested is a rising edge or a falling edge, without the need for further judgment by technical personnel in this field on the edge type of the signal to be tested.

[0026] In a possible implementation manner of the first aspect, the carry chain includes a plurality of delay units, the delay units are used to delay the first signal to be tested for a preset time and then output a delayed signal of the first signal to be tested, and determining a fine time measurement value of the first signal to be tested according to the delayed signal of the first signal to be tested includes:

[0027] Determine the number of the delay unit according to the time the delay unit delays the first signal to be tested;

[0028] Obtaining an output code of the second delay signal, where the output code is an output value of the second delay signal obtained in sequence according to the number of the delay units;

[0029] The fine time measurement value of the first signal to be measured is determined according to the output code of the second delayed signal.

[0030] In a possible implementation manner of the first aspect, determining a fine time measurement value of the first signal to be measured according to an output code of the second delayed signal includes:

[0031] When the edge of the first signal to be tested is a rising edge, it is determined in turn whether the output value of the delay unit in the output code is 0;

[0032] When the output value of the delay unit is 0, determining the fine time measurement value of the first signal to be measured according to the number of delay units whose output value is 1;

[0033] When the edge of the first signal to be tested is a falling edge, determining in sequence whether the output value of the delay unit in the output code is 1;

[0034] When the output value of the delay unit is 1, the fine time measurement value of the first signal to be measured is determined according to the number of delay units whose output values ​​are not 0.

[0035] In an embodiment of the first aspect of the present application, a fine time measurement value of the signal to be measured is determined by the output value of the delay unit, so that the accurate time of the signal to be measured can be further determined.

[0036] In a possible implementation manner of the first aspect, determining a timestamp of an edge of the first signal to be tested according to a fine time measurement value and a coarse time count value of the first signal to be tested includes:

[0037] The timestamp of the edge of the first signal to be tested satisfies:

[0038] PRT / NRT=CNT*T clock -n*Δd

[0039] Among them, PRT is the timestamp of the rising edge, NRT is the timestamp of the falling edge, CNT is the coarse time count value, T clock is the period of the clock signal, n is the fine time measurement value of the first signal to be measured, and Δd is the delay time between each delay unit.

[0040] It should be understood that when the fine time measurement value of the signal to be tested is determined according to the output code of the second delayed signal, the fine time measurement value of the signal to be tested is determined in a pipeline manner.

[0041] In an embodiment of the first aspect of the present application, a pipeline method is used to determine the time measurement value of the signal to be measured, so as to reduce the dead time of the time-to-digital conversion task.

[0042] In a possible implementation manner of the first aspect, the method further includes the following steps: determining a duration of the first signal to be tested according to a timestamp of an edge of the first signal to be tested.

[0043] In a second aspect, an embodiment of the present application provides a time converter, comprising: a signal measurement channel, a clock generator and a coarse time measurement module, characterized in that:

[0044] The clock generator is used to generate a local clock signal;

[0045] A coarse time measurement module, used to determine a coarse time count value of a first signal to be measured;

[0046] The signal measurement channel is connected to the clock generator and the coarse time measurement module respectively, including a delay module, a decoding module and a calculation module, wherein:

[0047] The delay module includes a carry chain and a latch, wherein the carry chain is used to generate a delay signal of the signal to be tested after receiving the signal to be tested, and the latch is used to obtain an output value of the delay signal according to a local clock signal;

[0048] A decoding module, used to determine the edge of the signal to be measured and the fine time measurement value of the signal to be measured according to the output value of the local clock signal and the delay signal, the edge of the signal to be measured includes a rising edge and a falling edge;

[0049] The calculation module is used to determine the time stamp of the edge of the signal to be measured according to the fine time measurement value and the coarse time count value of the signal to be measured.

[0050] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0051] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the present application distinguishes the edges of the signals to be tested in the channels, so that the rising and falling edges of each channel can be mapped to the same timestamp, thereby solving the problem of the difficulty in measuring the duration of the signals to be tested in a single channel and the synchronization problem between the signals to be tested in multiple channels, thereby ensuring the time consistency of the sampled data of the signals to be tested in each channel. In addition, the problem of the long waiting time between two time-to-digital conversion tasks is solved by pipeline processing of the sampled data. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] Figure 1 It is a flowchart of a time-to-digital conversion method provided by an embodiment of the present application;

[0054] Figure 2 It is a schematic diagram of determining a fine time measurement value by a time-to-digital conversion method provided by an embodiment of the present application;

[0055] Figure 3 This is a schematic diagram of mapping the edges of signals to be tested in different channels onto the same time axis in a time-to-digital conversion method provided by an embodiment of the present application;

[0056] Figure 4 It is a flow chart of an edge detection method of a time-to-digital conversion method provided by an embodiment of the present application;

[0057] Figure 5is a schematic diagram of a flow chart of a pipeline operation of a time-to-digital conversion method provided by another embodiment of the present application;

[0058] Figure 6 It is a structural schematic diagram of a time-to-digital converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0060] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0061] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0062] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0063] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0064] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0065] The duration of a signal refers to the period of time that a signal continues to exist in a certain state or activity. The duration of a signal has various uses in different application fields. The following are some of the common applications:

[0066] Communication systems: In communication systems, the duration of a signal is very important for data transmission and communication efficiency. The duration can be used to determine the signal transmission rate, bandwidth requirements, and channel resource utilization. A shorter duration can increase the data transmission rate, while a longer duration may result in a lower transmission rate.

[0067] Sensors and Measurement: In sensor and measurement applications, the duration of a signal can provide information about the duration of an event, process, or phenomenon. For example, measuring the duration of a voltage pulse with a voltage sensor can provide information about the pulse width, while measuring the duration of a temperature change with a temperature sensor can provide information about the temperature trend.

[0068] Control system: In the control system, the duration of the signal can be used to determine the duration of the control action. By observing the duration of the signal, the appropriate control period and sampling frequency can be determined to achieve a stable control effect.

[0069] Processing and Analysis: In signal processing and data analysis, the duration of a signal can be used to determine the time domain characteristics of the signal. By observing the duration of a signal, operations such as time domain analysis, waveform synthesis, and filter design can be performed to extract relevant features and information of the signal.

[0070] Event detection and identification: In event detection and identification applications, the duration of a signal can be used to determine how long an event has occurred. By observing the duration of a signal, the type, duration, and intensity of an event can be determined, thereby achieving event detection, classification, and identification.

[0071] The duration of a signal is of great significance for various applications, as it can provide information about the signal's temporal characteristics, dynamic behavior, and events. Depending on the specific application requirements, we can use the duration of a signal to perform tasks such as system design, data analysis, control strategy, and event processing. However, it is difficult to directly calculate the duration of a signal using existing time-to-digital converters.

[0072] Therefore, see Figure 1 , Figure 1 A schematic flow chart of a time-to-digital conversion method provided by the present application is shown. As an example but not a limitation, the method can be applied to a multi-channel time-to-digital converter.

[0073] S102: Input a first signal to be tested into a first carry chain to generate a delayed signal of the first signal to be tested.

[0074] It can be understood that the carry chain is a special data path network structure in FPGA (field programmable gate array) for processing the carry in addition operation. FPGA is a programmable hardware device that can be programmed and configured according to specific application requirements. In digital circuits, adders are usually implemented using logic gates. When two binary numbers are added, a carry may be generated, that is, the carry of the previous bit needs to be passed to the operation of the next bit. The carry chain is a data path used to handle this carry transfer. In FPGA, the carry chain is usually composed of a series of cascaded full adders or half adders. Each full adder or half adder has an input for receiving the carry signal from the previous bit, adding it to the input of the current bit, and then generating the result of the current bit and the output carry. Each cascade node in the carry chain passes the carry signal to the next cascade node until the last bit. By using the carry chain, FPGA can efficiently implement large-scale addition operations, while reducing the number of logic gates and delays, and improving overall performance. This is very important for some applications that require high-speed addition operations, such as digital signal processing, cryptography and other fields.

[0075] For example, in the present application, multi-bit adders are connected to form a carry chain. Field programmable logic devices (FPGAs) are increasingly widely used in modern electronics design, with increasingly improved performance and gradually falling prices. They are widely used in various fields. In ordinary FPGAs, in order to achieve fast digital signal processing and algorithms, there are generally fixed dedicated wires with very small delays, which are called dedicated carry wires. These dedicated carry wires are usually used for digital signal processing, but the present application can cleverly use them to form a carry chain. After the input end of the carry chain receives the signal to be tested, the sampling signal of the sampling circuit of the carry chain, i.e., the D flip-flop, is used to generate a blocking signal, and then the sampling circuit of the carry chain is closed.

[0076] S104 . Determine an edge of the first signal to be tested according to the clock signal and the delayed signal of the first signal to be tested, where the edge of the first signal to be tested includes a rising edge and a falling edge.

[0077] It can be understood that at the first rising edge of the clock signal before the input signal to be tested is input into the carry chain, and at the first rising edge of the clock signal after the input signal to be tested is input into the carry chain, the output signal of the carry chain is latched by using the D flip-flop, i.e., the sampling circuit, in the same logic unit corresponding to the carry chain. When the rising edge of the external signal to be tested is input, the output of the multi-bit adder gradually changes from low to high to 1, and when the falling edge of the external signal to be tested is input, the output of the multi-bit adder gradually changes from low to high to 0.

[0078] S106 : Determine a coarse time count value of the first signal to be tested according to the edge of the first signal to be tested.

[0079] It is understandable that the clock cycle count value corresponding to the rising edge or falling edge input measurement channel of the signal to be measured can be obtained through the local clock signal, and the clock cycle count value can be used as the coarse time count value of the rising edge or falling edge of the signal to be measured.

[0080] S108. Determine a fine time measurement value of the first signal to be tested according to the delayed signal of the first signal to be tested.

[0081] It can be understood that the method of determining the fine time measurement value of the present application is based on the principle of time interpolation corresponding to the delay signal output by the carry chain. The delay signal output by the carry chain is equivalent to interpolating a local clock cycle. The number of delay units in the carry chain is equivalent to the number of values ​​interpolated in the clock cycle, thereby greatly improving the accuracy of time digital conversion. For example, if the system clock is 200MHz, that is, the clock cycle is 5ns, then after 60 equal divisions, that is, 50 equal divisions are interpolated, the measurement accuracy that can be achieved is 100ps. If it is divided into 100 equal divisions, the accuracy that can be achieved is 50ps.

[0082] At the first rising edge of the clock signal after the signal to be tested is input into the carry chain, the output signal of the carry chain is latched by the D flip-flop, i.e., the sampling circuit, in the same logic unit corresponding to the time delay line. The time information of the transmission of the signal to be tested on the carry chain can be determined from the latched data. The transmission time of the signal to be tested arriving at different times on the carry chain is different, so the arrival time of the signal to be tested can be measured. In order to ensure the processing time of each signal to be tested, after the signal to be tested is input, the output signal is latched by the D flip-flop corresponding to the first level of the carry chain. At the second rising edge of the clock signal, all the D flip-flops corresponding to the carry chain are closed, and the subsequent input signals are not processed. After the data latched by the D flip-flop is sent to the next level processing unit, all the D flip-flops corresponding to the carry chain are opened to start the edge measurement of the next signal to be tested.

[0083] S110 : Determine a timestamp of an edge of the first signal to be tested according to a fine time measurement value of the first signal to be tested and a coarse time count value of the first signal to be tested.

[0084] In one possible implementation, see Figure 2 , an embodiment of calculating the fine time measurement value of the signal to be measured in the channel in the present application is given. In this embodiment, the output values ​​of the multiple delay units of the carry chain after delaying the signal to be measured are singal_dly[0]~singal_dly[x-1] respectively.

[0085] Before the delay signal of the first signal to be tested triggers the edge trigger, an output value of the first delay signal is obtained, where the first delay signal is a delay signal output by the carry chain at the first rising edge of the clock signal before the delay signal of the first signal to be tested triggers the edge trigger;

[0086] After the delay signal of the first signal to be tested triggers the edge trigger, an output value of the second delay signal is obtained, where the second delay signal is a delay signal output by the carry chain at the first rising edge of the clock signal after the delay signal of the first signal to be tested triggers the edge trigger;

[0087] According to the output value of the first delayed signal and the output value of the second delayed signal, it is determined whether the edge of the signal to be tested is a rising edge or a falling edge.

[0088] Exemplarily, when the edge of the input carry chain of the signal to be measured is a rising edge, the calculation method of the fine time measurement value is as follows:

[0089] At CNTp-1, it is detected that the original signal singal is outputted by the delay unit X carries, and the corresponding delayed signals singal_dly[0]~singal_dly[x-1] are all low level 0. At CNTp, singal_dly[0]~singal_dly[x-1] are not all 0. At this time, it is considered that the signal has detected a rising edge, and CNTp is latched as the coarse measurement coarse_time of the rising edge. At CNTp, it is detected that singal_dly[0]~singal_dly[4] are high level 1, and singal_dly[5]~singal_dly[x-1] are low level 0. It is considered that the value of the fine measurement fine_time is 6 (singal_dly[0]~singal_dly[5]). The rising edge of singal is mapped to the timestamp value posedge_realtime=CNTp*Tclock-6*Δd, where Tclock is the period of the clock clock; Δd is the delay time of a delay unit carry, 25ps.

[0090] Exemplarily, when the edge of the input carry chain of the signal to be measured is a falling edge, the calculation method of the fine time measurement value is as follows:

[0091] At CNTn-1, the original signal singal is detected to be at a high level 1 after passing through the delay unit X carries, and the corresponding delayed signals singal_dly[0]~singal_dly[x-1] are all high level 1. At CNTn, singal_dly[0]~singal_dly[x-1] are not all 1. At this time, it is considered that the signal has detected a falling edge, and CNTn is latched as the coarse measurement coarse_time of the falling edge. At CNTn, singal_dly[0]~singal_dly[3] are detected to be low level 0, and singal_dly[4]~singal_dly[x-1] are high level 1. It is considered that the value of the fine measurement fine_time is 5 (singal_dly[0]~singal_dly[4]). The falling edge of singal is mapped to the timestamp value negedge_realtime=CNTn*Tclock-5*Δd (Tclock is the period of the clock; Δd is the delay time of a delay unit carry, 25ps).

[0092] According to the values ​​mapped to the timestamps corresponding to the rising edge and the falling edge of the signal to be tested singal, the duration of the current signal to be tested can be directly calculated.

[0093] The phase difference between signals refers to the time offset between two signals. It has important applications and significance in signal processing, communication systems, control systems, etc. The following are some uses of the phase difference of signals in different fields:

[0094] Communication system: In the modulation and demodulation process, the phase difference between signals can be used to represent the relative time offset between different signals. In some modulation technologies, the change of phase difference is used to represent digital information or analog information. For example, in phase shift keying (PSK) modulation, different phases represent different digital symbols. In addition, in multi-carrier modulation, the control of phase difference can also affect the spectrum characteristics and transmission performance of the signal.

[0095] Signal processing: In the field of signal processing, phase difference can be used to perform time domain analysis and frequency domain analysis of signals. By calculating the phase difference between signals, operations such as phase correction, signal alignment, and signal synthesis can be performed to accurately process and analyze the signals.

[0096] Control systems: In control systems, phase difference is often used to describe the stability and performance of the control system. For example, in control system design, phase margin is used to evaluate the stability of the system. The larger the phase margin, the better the system's robustness to parameter changes and disturbances.

[0097] AC circuit analysis: In AC circuit analysis, phase difference can be used to describe the time offset between different components in the circuit. By analyzing the phase difference, the phase frequency response characteristics of the circuit can be determined, and the phase delay and phase distortion problems in the circuit can be diagnosed.

[0098] Frequency measurement and synchronization: In the frequency measurement and synchronization process, the phase difference can be used for frequency measurement and clock synchronization. By observing the phase difference between signals, high-precision frequency measurement and clock synchronization can be achieved, which has a wide range of applications in wireless communications, radar systems, GPS positioning and other fields.

[0099] The phase difference between signals is of great significance in the fields of communication, signal processing, control, circuit analysis, etc. It can be used to describe the time relationship, frequency characteristics and stability between signals, and provide an important basis for system design, data processing and performance evaluation.

[0100] Specifically, corresponding to the multi-channel time-to-digital converter, it can have multiple detection channels, each detection channel can input the signal to be tested for time-to-digital conversion of the signal, so as to calculate the phase difference between the signals to be tested input into different channels. For the second signal to be tested input into other detection channels, the time-to-digital conversion is performed as follows:

[0101] Inputting the second signal to be tested into the second carry chain to generate a delayed signal of the second signal to be tested;

[0102] Determine the edge of the second signal to be tested according to the clock signal and the delay signal of the second signal to be tested, wherein the edge of the second signal to be tested includes a rising edge and a falling edge;

[0103] determining a coarse time count value of the second signal to be measured according to an edge of the second signal to be measured;

[0104] Determine a fine time measurement value of the second signal to be measured according to the delayed signal of the second signal to be measured;

[0105] A timestamp of an edge of the second signal to be measured is determined according to a fine time measurement value of the second signal to be measured and a coarse time count value of the second signal to be measured.

[0106] See also Figure 3 , from the mapping values ​​of each channel edge on the timestamp, it can be seen that the rising edge tp2_0 of channel 2 lags behind the rising edge tp1_0 of channel 1, and the rising edge tp1_0 of channel 1 lags behind the rising edge tp0_0 of channel 0. The falling edge tn1_0 of channel 1 lags behind the falling edge tn0_0 of channel 0, and the falling edge tn0_0 of channel 0 lags behind the falling edge tn2_0 of channel 2.

[0107] Exemplarily, the lag time of the second signal to be tested compared to the first signal to be tested is determined based on the timestamp of the edge of the first signal to be tested and the timestamp of the edge of the second signal to be tested. Figure 3 ,include:

[0108] The high level pulse duration of channel 0 is equal to tn0_0-tp0_0;

[0109] The high level pulse duration of channel 1 is equal to tn1_0-tp1_0;

[0110] The high level pulse duration of channel 2 is equal to tn2_0-tp2_0;

[0111] The rising edge of channel 1 lags behind the rising edge of channel 0 by a time equal to tp1_0-tp0_0;

[0112] The rising edge of channel 2 lags behind the rising edge of channel 0 by a time equal to tp2_0-tp0_0;

[0113] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0114] In the embodiment of the present application, as to how to determine the fine time measurement value corresponding to the signal to be measured, the present application adopts the following method:

[0115] Determine the number of the delay unit according to the time the delay unit delays the first signal to be tested;

[0116] Obtaining an output code of the second delay signal, where the output code is an output value of the second delay signal obtained in sequence according to the number of the delay units;

[0117] The fine time measurement value of the first signal to be measured is determined according to the output code of the second delayed signal.

[0118] See also Figure 4 ,Specifically, when a signal edge is detected input into the carry chain, it jumps to the edge detection ,state;

[0119] In the edge detection state, if an edge is detected, the jump action will be triggered, otherwise the current state will be maintained. When the rising edge of the signal is detected, it will jump to the rising edge calculation state, and when the falling edge is detected, it will jump to the falling edge calculation state.

[0120] After the rising edge calculation state is calculated or the falling edge calculation state is calculated, the detection of the signal edge to see if it is input into the carry chain is restarted.

[0121] Exemplarily, when the edge of the first signal to be tested is a rising edge, it is determined in sequence whether the output value of the delay unit in the output code is 0;

[0122] When the output value of the delay unit is 0, determining the fine time measurement value of the first signal to be measured according to the number of delay units whose output value is 1;

[0123] When the edge of the first signal to be tested is a falling edge, determining in sequence whether the output value of the delay unit in the output code is 1;

[0124] When the output value of the delay unit is 1, the fine time measurement value of the first signal to be measured is determined according to the number of delay units whose output values ​​are not 0.

[0125] In one or more embodiments, the fine time measurement value is determined as follows:

[0126] The encoding can be performed using the sequential search encoding scheme commonly used in ordinary analog-to-digital conversion (ADC). According to the basic idea of ​​sequential search, first check the lowest bit of the carry chain output data to determine whether the signal to be tested has arrived there. If it has arrived, continue to output the next bit of data. Repeat this process until the exact end point of the signal to be tested is found, that is, the end point of the signal to be tested on the carry chain when the carry chain is latched, so that the transmission time information of the signal to be tested on the carry chain can be obtained.

[0127] For example, the output data of fine time measurement is 1111110000000000 from low to high. First, determine whether the first bit is 1. If it is 1, check whether the next bit is 1. Since it is 1 and not 0, continue to search whether the third bit is 1. Then determine whether the fourth bit is 1. Since it is 1, continue to search in the next bit until the output value of the bit is 0. Therefore, the end point of the input signal to be measured on the carry chain is the 8th bit. Therefore, the encoded output binary data is 8 from low to high, and the fine time measurement value can be determined to be 9.

[0128] The processing of the measured data of the signal to be tested adopts pipeline technology, see Figure 5 The basic idea of ​​pipeline technology is to decompose a processing process into several processing sub-processes, each of which can be effectively executed simultaneously with other sub-processes on its dedicated functional segment, thereby reducing the dead time of the processing process. In the present invention, pipeline technology is used when encoding the fine time measurement output data. The specific processing process is: under clock control, the first level of processing determines the first step of the encoding scheme, the second level of processing determines the second step of the encoding scheme, and so on, one level at a time, and finally completes the entire sequential search for encoding and outputs the encoded data.

[0129] Corresponding to the time-to-digital conversion method described in the above embodiment, Figure 6 A structural block diagram of a time-to-digital converter provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0130] Reference Figure 6 The present application also provides a time-to-digital converter, which includes a signal measurement channel, a clock generator and a coarse time measurement module, and the above modules can be implemented in an FPGA.

[0131] Among them, the clock generator is used to generate a local clock signal as the reference clock of the signal measurement system to ensure the accuracy and stability of the signal measurement.

[0132] The coarse time measurement module is used to determine the coarse time count value of the first signal to be measured; the coarse time count value is the time difference between the edge of the signal and the measurement start time calculated based on the local clock signal. This count value can be used as a reference value for subsequent fine time measurement.

[0133] The signal measurement channel is connected to the clock generator and the coarse time measurement module respectively, and includes a delay module, a decoding module and a calculation module. The signal measurement channel is used to measure the time difference between the first signal to be measured and the local clock signal, and calculate the timestamp of the first signal to be measured.

[0134] The delay module receives the signal to be tested and generates a delay signal according to the signal. The delay module includes a carry chain and a latch. The carry chain is used to generate a delay signal of the signal to be tested after receiving the signal to be tested, and the latch is used to obtain the output value of the delay signal according to the local clock signal.

[0135] The decoding module is used to determine the edge of the signal to be tested and the fine time measurement value of the signal to be tested according to the output value of the local clock signal and the delay signal. The edge of the signal to be tested includes the rising edge and the falling edge. The decoding module uses the local clock signal and the delay signal to determine the edge of the signal to be tested, including the rising edge and the falling edge, and calculates the fine time measurement value of the signal to be tested. This fine time measurement value is the time difference between the signal to be tested and the reference clock. The fine time measurement value and the coarse time count value are sent to the calculation module for processing.

[0136] The calculation module is used to determine the time stamp of the edge of the signal to be measured according to the fine time measurement value and the coarse time count value of the signal to be measured. The calculation module uses the fine time measurement value and the coarse time count value of the signal to be measured to determine the time stamp of the edge of the signal to be measured. This time stamp represents the precise time point of the signal to be measured relative to the start time of the measurement.

[0137] In one or more embodiments, the time-to-digital converter provided by the present application may include multiple signal measurement channels, each of which may share a clock generator and a coarse time measurement module, so that the edge of the signal to be measured measured by each signal measurement channel may be mapped to the timestamp of the same clock, so that the measurement results of each signal measurement channel can be conveniently and directly compared, thereby obtaining the phase difference between each signal to be measured.

[0138] In one or more embodiments, the carry chain may include a plurality of delay units, the delay units are used to delay the first signal to be tested for a preset time and then output a delayed signal of the first signal to be tested. When the decoding module determines the edge of the signal to be tested, the output value of the first delayed signal is obtained before the delayed signal of the first signal to be tested triggers the edge trigger, and the output value of the second delayed signal is obtained after the delayed signal of the first signal to be tested triggers the edge trigger, and the edge of the signal to be tested is determined to be a rising edge or a falling edge according to the output value of the first delayed signal and the output value of the second delayed signal. In the case of a rising edge, it is sequentially determined whether the output value of the delay unit in the output code is 0, and when the output value of the delay unit is 0, the fine time measurement value of the first signal to be tested is determined according to the number of delay units whose output value is 1; in the case of a falling edge, it is sequentially determined whether the output value of the delay unit in the output code is 1, and when the output value of the delay unit is 1, the fine time measurement value of the first signal to be tested is determined according to the number of delay units whose output value is not 0.

[0139] In one or more embodiments, the signal measurement channel of the present application uses a pipeline method to determine the fine time measurement value of the signal to be measured. Specifically, a FIFO can be used to cache complete time measurement information, and the fine time measurement value is determined externally in a pipeline form according to the read timing of the FIFO, thereby reducing the problem of too long dead time in the signal measurement process.

[0140] It should be noted that the information interaction, execution process and other contents between the above-mentioned modules are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0141] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0142] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0143] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0144] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0145] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A time-to-digital conversion method, characterized in that: include: Inputting a first signal to be tested into a first carry chain to generate a delay signal of the first signal to be tested; Determining an edge of the first signal to be tested according to a clock signal and a delay signal of the first signal to be tested, wherein the edge of the first signal to be tested includes a rising edge and a falling edge; determining a coarse time count value of the first signal to be measured according to an edge of the first signal to be measured; Determining a fine time measurement value of the first signal to be tested according to a delayed signal of the first signal to be tested; A timestamp of an edge of the first signal to be tested is determined according to a fine time measurement value of the first signal to be tested and a coarse time count value of the first signal to be tested.

2. The method according to claim 1, characterized in that The following steps are also included: Inputting a second signal to be tested into a second carry chain to generate a delayed signal of the second signal to be tested; Determining an edge of the second signal to be tested according to the clock signal and a delay signal of the second signal to be tested, wherein the edge of the second signal to be tested includes a rising edge and a falling edge; determining a coarse time count value of the second signal to be tested according to an edge of the second signal to be tested; Determining a fine time measurement value of the second signal to be tested according to a delayed signal of the second signal to be tested; A timestamp of an edge of the second signal to be tested is determined according to a fine time measurement value of the second signal to be tested and a coarse time count value of the second signal to be tested.

3. The method according to claim 2, characterized in that The method further comprises: A lag time of the second signal to be tested compared with the first signal to be tested is determined according to a timestamp of an edge of the first signal to be tested and a timestamp of an edge of the second signal to be tested.

4. The method according to any one of claims 1 to 3, characterized in that: The step of determining the edge of the first signal to be tested according to the clock signal and the delayed signal of the first signal to be tested comprises: Before the delay signal of the first signal to be tested triggers the edge trigger, obtaining an output value of the first delay signal, the first delay signal being a delay signal output by the carry chain at the first rising edge of the clock signal before the delay signal of the first signal to be tested triggers the edge trigger; After the delay signal of the first signal to be tested triggers the edge trigger, obtaining an output value of a second delay signal, wherein the second delay signal is a delay signal output by the carry chain at the first rising edge of the clock signal after the delay signal of the first signal to be tested triggers the edge trigger; It is determined whether the edge of the signal to be tested is a rising edge or a falling edge according to the output value of the first delayed signal and the output value of the second delayed signal.

5. The method according to claim 4, characterized in that The carry chain includes a plurality of delay units, and the delay units are used to delay the first signal to be tested by a preset time and then output a delayed signal of the first signal to be tested. The determining of the fine time measurement value of the first signal to be tested according to the delayed signal of the first signal to be tested includes: Determine the serial number of the delay unit according to the time that the delay unit delays the first signal to be tested; Obtaining an output code of the second delay signal, where the output code is an output value of the second delay signal obtained in sequence according to the number of the delay unit; A fine time measurement value of the first signal to be measured is determined according to the output code of the second delayed signal.

6. The method according to claim 5, characterized in that The step of determining the fine time measurement value of the first signal to be measured according to the output code of the second delayed signal comprises: When the edge of the first signal to be tested is a rising edge, determining in sequence whether the output value of the delay unit in the output code is 0; When the output value of the delay unit is 0, determining the fine time measurement value of the first signal to be measured according to the number of delay units whose output value is 1; When the edge of the first signal to be tested is a falling edge, determining in sequence whether the output value of the delay unit in the output code is 1; When the output value of the delay unit is 1, the fine time measurement value of the first signal to be measured is determined according to the number of delay units whose output values ​​are not 0.

7. The method according to claim 6, characterized in that The step of determining the time stamp of the edge of the first signal to be tested according to the fine time measurement value and the coarse time count value of the first signal to be tested comprises: The timestamp of the edge of the first signal to be tested satisfies: PRT / NRT=CNT*T clock -n*Δd Wherein, PRT is the timestamp of the rising edge, NRT is the timestamp of the falling edge, CNT is the coarse time count value, T clock is the period of the clock signal, n is the fine time measurement value of the first signal to be measured, and Δd is the delay time between each delay unit.

8. The method according to claim 7, characterized in that When determining the fine time measurement value of the signal to be tested according to the output code of the second delayed signal, the fine time measurement value of the signal to be tested is determined in a pipeline manner.

9. The method according to claim 8, characterized in that The following steps are also included: The duration of the first signal to be tested is determined according to the timestamp of the edge of the first signal to be tested.

10. A time converter, comprising a signal measurement channel, a clock generator and a coarse time measurement module, characterized in that: The clock generator is used to generate a local clock signal; The coarse time measurement module is used to determine the coarse time count value of the first signal to be measured; The signal measurement channel is connected to the clock generator and the coarse time measurement module respectively, and the signal measurement channel includes a delay module, a decoding module and a calculation module, wherein: The delay module includes a carry chain and a latch, wherein the carry chain is used to generate a delay signal of the signal to be tested after receiving the signal to be tested, and the latch is used to obtain an output value of the delay signal according to the local clock signal; The decoding module is used to determine the edge of the signal to be measured and the fine time measurement value of the signal to be measured according to the output value of the local clock signal and the delay signal, and the edge of the signal to be measured includes a rising edge and a falling edge; The calculation module is used to determine the time stamp of the edge of the signal to be tested according to the fine time measurement value and the coarse time count value of the signal to be tested.

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