A fast start-up circuit suitable for bandgap reference circuits

Abstract

This invention discloses a fast start-up circuit suitable for a bandgap reference circuit. The source of a first PMOS switch, one end of a first control switch, one end of a capacitor, and the source of a second PMOS switch are all connected to the power supply voltage. The gate of the first PMOS switch is connected to the other end of the first control switch, one end of the second control switch, and the drain of the second PMOS switch, respectively. The other end of the second control switch is grounded. The drain of the first PMOS switch is connected to an NMOS current mirror. The output of the NMOS current mirror and the gate of the second PMOS switch together serve as the output of the fast start-up circuit and are connected to the current replication node of the bandgap reference circuit. The other end of the capacitor is connected to one end of a third control switch, the control end of the first control switch, and the control end of the second control switch, respectively. The other end of the third control switch is grounded. The control end of the third control switch is connected to one end of a first single-pole single-throw switch. The other end of the first single-pole single-throw switch is connected to the output of the bandgap reference circuit.

Description

Technical Field

[0001] This invention relates to the fields of analog circuit technology and semiconductor integration technology, and more specifically, to a fast startup circuit suitable for bandgap reference circuits. Background Technology

[0002] The bandgap reference circuit provides stable reference current and voltage for all modules of the chip. When the chip is powered on and off, the bandgap reference circuit needs to respond promptly and quickly and reliably turn the reference current and voltage on or off. As a crucial component of the bandgap reference circuit, the startup circuit needs to quickly move the bandgap reference away from its degeneracy point to prevent circuit lock-up when the chip is powered on. After power-on, the startup circuit needs to automatically shut down to avoid affecting the normal operation of the bandgap reference circuit.

[0003] In the prior art, some startup circuits use the threshold voltages of two sets of MOSFETs as the threshold of the startup circuit. When the power-on voltage of the chip exceeds the threshold voltage of the first set of MOSFETs, the MOSFETs are turned on, pulling down the bias node of the bandgap reference away from the degeneracy point. When the output voltage of the bandgap reference circuit is started up and exceeds the threshold voltage of the second set of MOSFETs, the startup circuit is turned off. The advantage of this technique is that the startup circuit only operates during the startup of the bandgap reference circuit, and there is no static power consumption after startup. However, the disadvantage is that the threshold voltage of the MOSFET varies significantly with process technology and temperature, resulting in a significant reduction in startup speed under slow processes or low temperatures. Furthermore, if there is residual voltage when the chip is powered down, the startup speed will also be slower upon power-up due to residual charge within the startup circuit. Another startup circuit uses the voltage drop across a large resistor as the control voltage. When the chip starts to power on, there is no current in the large resistor, so its voltage drop is approximately zero. This voltage drop controls the conduction of the P-type current source, pulling down the bias node of the bandgap reference away from the degeneracy point. After the bandgap reference circuit has finished startup, the voltage drop across the large resistor approaches the supply voltage, turning off the current source and completing the startup. The advantage of this technique is that the startup threshold is not affected by the MOSFET, so the startup speed is not significantly reduced under slow processes or low temperatures. However, the disadvantage is that after startup, the large resistor needs static current to maintain the voltage drop, and reducing the static current requires increasing the resistor value, leading to an increase in resistor area, which is detrimental to low-power and low-cost designs. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a fast startup circuit suitable for bandgap reference circuits, which can achieve fast startup of bandgap reference circuits under various voltages, processes and temperatures, with virtually no quiescent current and a small chip area footprint.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a fast start-up circuit suitable for bandgap reference circuits, comprising: a first PMOS switch, an NMOS current mirror, a second PMOS switch, a capacitor, a first control switch, a second control switch, a third control switch, and a first single-pole single-throw switch. The source of the first PMOS switch, one end of the first control switch, one end of the capacitor, and the source of the second PMOS switch are all connected to the power supply voltage VDD. The gate of the first PMOS switch is connected to the other end of the first control switch, one end of the second control switch, and the drain of the second PMOS switch, respectively. The other end of the second control switch is grounded. The drain of the first PMOS switch is connected to an NMOS current mirror. The output of the NMOS current mirror and the gate of the second PMOS switch together serve as the output of the fast-start circuit and are connected to the current replication node A of the bandgap reference circuit. The other end of the capacitor is connected to one end of the third control switch, the control terminal of the first control switch, and the control terminal of the second control switch, respectively. The other end of the third control switch is grounded. The control terminal of the third control switch is connected to one end of the first single-pole single-throw switch. The other end of the first single-pole single-throw switch is connected to the output terminal BG of the bandgap reference circuit. OUT connect.

[0006] Furthermore, the NMOS current mirror includes: a first NMOS switch and a second NMOS switch. The drain and gate of the first NMOS switch are connected to the drain of the first PMOS switch and the gate of the second NMOS switch, respectively. The source of the first NMOS switch and the source of the second NMOS switch are both grounded. The drain of the second NMOS switch and the gate of the second PMOS switch together serve as the output terminal of the fast start-up circuit and are connected to the current replication node A of the bandgap reference circuit.

[0007] Furthermore, it also includes an inverter, the input terminal of which is connected to the other end of the capacitor and is used to control the control terminal of the second control switch, and the output terminal of the inverter is used to control the control terminal of the first control switch.

[0008] Furthermore, the first control switch is a third PMOS switch, the source of the third PMOS switch is connected to the power supply voltage VDD, the gate of the third PMOS switch is connected to the other end of the capacitor, and the drain of the third PMOS switch is connected to one end of the second control switch, the gate of the first PMOS switch, and the drain of the second PMOS switch, respectively.

[0009] Furthermore, the second control switch is a third NMOS switch, the gate of the third NMOS switch is connected to the other end of the capacitor, the source of the third NMOS switch is grounded, and the drain of the third NMOS switch is connected to the drain of the second PMOS switch, the drain of the third PMOS switch, and the gate of the first PMOS switch, respectively.

[0010] Furthermore, the third control switch is a fourth NMOS switch, the gate of the fourth NMOS switch is connected to one end of the first single-pole single-throw switch, the source of the fourth NMOS switch is grounded, and the drain of the fourth NMOS switch is connected to the other end of the capacitor.

[0011] Furthermore, it also includes: a fourth control switch and a quantization inverter, one end of the fourth control switch and the input end of the quantization inverter are both connected to the power supply voltage VDD, the output end of the quantization inverter is used to control the control end of the fourth control switch, and the other end of the fourth control switch is connected to the other end of the capacitor.

[0012] Furthermore, the fourth control switch is a fifth NMOS switch, and the quantization inverter includes: a fourth PMOS switch, a sixth NMOS switch, a second single-pole single-throw switch, and a third single-pole single-throw switch. One end of the third single-pole single-throw switch, the gate of the sixth NMOS switch, the source of the fourth PMOS switch, and the drain of the fifth NMOS switch are all connected to the power supply voltage VDD. The other end of the third single-pole single-throw switch and one end of the second single-pole single-throw switch are both connected to the gate of the fourth PMOS switch. The drain of the fourth PMOS switch is connected to the drain of the sixth NMOS switch and the gate of the fifth NMOS switch, respectively. The source of the sixth NMOS switch is grounded. The other end of the second single-pole single-throw switch is connected to the current replication node A of the bandgap reference circuit. The substrate and source of the fifth NMOS switch are both connected to the other end of a capacitor.

[0013] Furthermore, it also includes a level shifter connected in parallel with a first single-pole single-throw switch, the input of which is connected to the output terminal BG of a bandgap reference circuit. OUT The output of the level shifter is used to control the gate voltage of the fourth NMOS switch.

[0014] Furthermore, the level shifter includes a seventh NMOS switch and a fifth PMOS switch. The drain of the seventh NMOS switch is connected to the power supply voltage VDD. The sources of the seventh NMOS switch and the fifth PMOS switch are both connected to the gate of the fourth NMOS switch and one end of the first single-pole single-throw switch. The gate of the seventh NMOS switch, the other end of the first single-pole single-throw switch, and the gate of the fifth PMOS switch are all connected to the output terminal BG of the bandgap reference circuit. OUT Connection; the drain of the fifth PMOS switch is grounded.

[0015] Compared with existing technologies, the present invention has the following advantages: The fast startup circuit of the present invention, applicable to bandgap reference circuits, has virtually no static current after startup and does not require large-area resistors, exhibiting low power consumption and low cost. Furthermore, addressing the issue of residual voltage when the chip is powered down, the present invention introduces a fourth control switch and a quantization inverter to discharge the charge of residual voltage in the capacitor, thereby improving the startup speed of the next startup and broadening its applicability. Additionally, addressing the situation where the third control switch's turn-on threshold is low under rapid process or high-temperature conditions, leading to premature shutdown of the startup circuit, the present invention introduces a level shifter to increase the shutdown threshold of the startup circuit, thereby improving the startup speed of the bandgap reference circuit. In summary, the fast startup circuit of the present invention, applicable to bandgap reference circuits, enables rapid startup of the bandgap reference circuit under various voltages, processes, and temperatures, and this circuit is also applicable to other situations requiring a startup circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the implementation principle of a bandgap reference circuit.

[0017] Figure 2 This is a schematic diagram of the fast start-up circuit principle applicable to bandgap reference circuits of the present invention;

[0018] Figure 3 This is a schematic diagram of the specific circuit structure of the fast start-up circuit applicable to bandgap reference circuits according to the present invention. Detailed Implementation

[0019] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.

[0020] like Figure 1This is a schematic diagram illustrating the implementation principle of a bandgap reference circuit. The bandgap reference circuit includes: a first PMOS current mirror 101, a second PMOS current mirror 102, a first NPN bipolar transistor 103, a second NPN bipolar transistor 104, a first resistor 105, a second resistor 106, and a startup circuit 107. The sources of the first PMOS current mirror 101 and the second PMOS current mirror 102 are both connected to the power supply voltage VDD. The gate of the first PMOS current mirror 101, the drain of the first PMOS current mirror 101, the gate of the second PMOS current mirror 102, and the first NPN bipolar transistor 104 are also connected. The collectors of transistors 03 and 104 serve as the current replication node A of the bandgap reference circuit, connected to the output of the startup circuit. The emitter of the first NPN bipolar transistor 103 is connected to one end of the first resistor 105. The other end of the first resistor 105 is connected to one end of the second resistor 106 and the emitter of the second NPN bipolar transistor 104. The other end of the second resistor 106 is grounded. The bases of the first NPN bipolar transistor 103 and 104, the collectors of the second NPN bipolar transistor 104, and the drain of the second PMOS current mirror transistor 102 together serve as the output BG of the bandgap reference circuit. OUT Connect to the startup circuit.

[0021] When the chip is powered on, there are two possible states for the bandgap reference circuit. The first, correct state, occurs when the voltage at current replication node A is lower than the supply voltage VDD, and all branches of the bandgap reference circuit have current. In this case, the output voltage of the bandgap reference circuit is BG. OUT The expression is as follows:

[0022]

[0023] Where R1 is the resistance of the first resistor 105, R2 is the resistance of the second resistor 106, and ΔV BE V is the difference between the base-emitter voltage of the first NPN bipolar transistor 103 and the base-emitter voltage of the second NPN bipolar transistor 104. BE2 This is the base-emitter voltage of the second NPN bipolar transistor 104.

[0024] The second solution is a degenerate solution, meaning the voltage at node A, where the current replication point, is equal to the supply voltage VDD, and the output voltage BG at the output terminal of the bandgap reference circuit is... OUTWhen the value equals 0, all branches of the bandgap reference circuit are turned off, and there is no current. Therefore, in order to prevent the bandgap reference circuit from entering the second solution state during power-up, the startup circuit needs to quickly pull down the voltage of the current replication node A to be away from the power supply voltage VDD during power-up. At this time, the first PMOS current mirror 101 and the second PMOS current mirror 102 are turned on, and current will be generated in each branch of the bandgap reference circuit, and the circuit will leave the degenerate state. Then, the connection between the startup circuit and the current replication node A is disconnected, and the bandgap reference circuit will stabilize to the correct solution state.

[0025] As can be seen from the working principle of the bandgap reference circuit described above, the startup circuit needs to pull the voltage of the current replication node A down to the point where the first PMOS current mirror 101 is turned on. The faster the voltage of the current replication node A is pulled down and the lower its value, the faster the bandgap reference circuit starts up. After startup, the startup circuit needs to disconnect from the current replication node A; otherwise, not only will there be static power consumption, but the voltage of the current replication node A will also be too low, leading to abnormal circuit conditions. Furthermore, in practical applications, there may be residual voltage when the chip is powered down, i.e., the power supply voltage VDD is greater than 0. This residual voltage must not affect the startup of the bandgap reference circuit upon the next power-up.

[0026] To meet the design requirements of the aforementioned startup circuit, this invention provides a fast startup circuit suitable for bandgap reference circuits, the principle of which is as follows: Figure 2As shown, the fast-start circuit includes: a first PMOS switch 201, an NMOS current mirror, a second PMOS switch 204, a capacitor 205, a first control switch 207, a second control switch 208, a third control switch 211, and a first single-pole single-throw switch 213. The source of the first PMOS switch 201, one end of the first control switch 207, one end of the capacitor 205, and the source of the second PMOS switch 204 are all connected to the power supply voltage VDD. The gate of the first PMOS switch 201 is connected to the other end of the first control switch 207, one end of the second control switch 208, and the drain of the second PMOS switch 204, respectively. The other end of switch 208 is grounded. The drain of the first PMOS switch 201 is connected to the NMOS current mirror. The output of the NMOS current mirror and the gate of the second PMOS switch 204 are connected to the current replication node A of the bandgap reference circuit as the output of the fast start circuit. The other end B of capacitor 205 is connected to one end of the third control switch 211, the control end of the first control switch 207, and the control end of the second control switch 208, respectively. The other end of the third control switch 211 is grounded. The control end of the third control switch 211 is connected to one end of the first single-pole single-throw switch 213. The other end of the first single-pole single-throw switch 213 is connected to the output of the bandgap reference circuit. To ensure that the second control switch 208 is open when the first control switch 207 is on, or the second control switch 208 is on when the first control switch 207 is off, an inverter 206 is provided. The input terminal of the inverter 206 is connected to the other end of the capacitor 205 to control the control terminal of the second control switch 208, and the output terminal of the inverter 206 is used to control the control terminal of the first control switch 207. In addition, the first single-pole single-throw switch 213 is closed by default in the fast start circuit.

[0027] When the chip is powered on, due to the conservation of charge across capacitor 205, the voltage at the other end B of capacitor 205 rises along with the power supply voltage VDD. When the voltage at the other end B of capacitor 205 rises to the threshold of the second control switch 208, the second control switch 208 closes. Simultaneously, the output of inverter 206 goes low, and the first control switch 207 turns off. Therefore, the gate of the first PMOS switch 201 is grounded and turned on. The generated current provides a current path to the current replication node A after passing through the NMOS current mirror. As a result, the voltage of the current replication node A is pulled down, and the bandgap reference circuit leaves the degeneracy point and enters the normal setup process. At the same time, the first single-pole single-throw switch 213 is closed by default. After the bandgap reference circuit is established, its output voltage BG OUTIf the threshold of the third control switch 211 is exceeded, the third control switch 211 is closed, causing the other end B of capacitor 205 to be pulled down to 0. The second control switch 208 is turned off, and the first control switch 207 is closed. At this time, the first PMOS switch 201 is turned off, there is no current on the NMOS current mirror, the entire startup circuit is turned off, and no static power consumption is generated.

[0028] The NMOS current mirror in this invention includes: a first NMOS switch 202 and a second NMOS switch 203. The drain and gate of the first NMOS switch 202 are connected to the drain of the first PMOS switch 201 and the gate of the second NMOS switch 203, respectively. The source of the first NMOS switch 202 and the source of the second NMOS switch 203 are both grounded. The drain of the second NMOS switch 203 and the gate of the second PMOS switch 204 together serve as the output terminal of the fast start-up circuit and are connected to the current replication node A of the bandgap reference circuit.

[0029] like Figure 3 In this invention, the first control switch 207 is a third PMOS switch 301. The source of the third PMOS switch 301 is connected to the power supply voltage VDD, the gate of the third PMOS switch 301 is connected to the other end of the capacitor 205, and the drain of the third PMOS switch 301 is connected to one end of the second control switch 208, the gate of the first PMOS switch 201, and the drain of the second PMOS switch 204, respectively.

[0030] In this invention, the second control switch 208 is a third NMOS switch 302. The gate of the third NMOS switch 302 is connected to the other end of the capacitor 205. The source of the third NMOS switch 302 is grounded. The drain of the third NMOS switch 302 is connected to the drain of the second PMOS switch 204, the drain of the third PMOS switch 301, and the gate of the first PMOS switch 201, respectively.

[0031] In this invention, the third control switch 211 is the fourth NMOS switch 308. The gate of the fourth NMOS switch 308 is connected to one end of the first single-pole single-throw switch 213, the source of the fourth NMOS switch 308 is grounded, and the drain of the fourth NMOS switch 308 is connected to the other end of the capacitor 205.

[0032] In practical applications, a residual voltage V may remain on the power supply voltage VDD after the chip is powered off. RES Meanwhile, the voltage at the other end B of capacitor 205 remains 0, therefore capacitor 205 stores a voltage equal to the residual voltage V. RES The related charge. When power is restored, the voltage rise at the other end B of capacitor 205 is equal to the difference between the power supply voltage VDD and the residual voltage V. RESDue to the difference in power supply voltage (VDD), the second control switch 208 has a higher turn-on threshold under slow processes or low temperatures. If the voltage at the other end (B) of capacitor 205 is low, the voltage may be insufficient to turn on the second control switch 208 or may delay its turn-on, resulting in failure to start or a slower start-up speed upon power-up. To solve this problem, a fourth control switch 209 and a quantization inverter 210 are introduced, such as... Figure 2 One end of the fourth control switch 209 and the input end of the quantizer inverter 210 are both connected to the power supply voltage VDD. The output end of the quantizer inverter 210 is used to control the control terminal of the fourth control switch 209. The other end of the fourth control switch 209 is connected to the other end of the capacitor 205. The judgment threshold of the quantizer inverter 210 is half of the normal power supply voltage VDD. When the chip is powered on normally, the power supply voltage VDD is high, higher than the judgment threshold, so the quantizer outputs 0, therefore the fourth control switch 209 is turned off, and the other end B of the capacitor 205 remains pulled low. When the chip is powered off, the power supply voltage VDD drops to the residual voltage V. RES If the value is below the judgment threshold, the quantization inverter outputs V. RES Therefore, the fourth control switch 209 is turned on, raising the voltage at the other end B of capacitor 205 to V. RES This discharges the charge stored in capacitor 205, allowing the voltage at the other end B of capacitor 205 to return to the power supply voltage VDD upon the next power-on, thus improving the power-on startup speed.

[0033] Specifically, such as Figure 3 The fourth control switch 209 is the fifth NMOS switch 303. The quantization inverter 210 includes: a fourth PMOS switch 304, a sixth NMOS switch 305, a second single-pole single-throw switch 306, and a third single-pole single-throw switch 307. One end of the third single-pole single-throw switch 307, the gate of the sixth NMOS switch 305, the source of the fourth PMOS switch 304, and the drain of the fifth NMOS switch 303 are all connected to the power supply voltage VDD. The other end of the third single-pole single-throw switch 307 and one end of the second single-pole single-throw switch 306 are also connected to the power supply voltage VDD. The gate of the fourth PMOS switch 304 is connected, and the drain of the fourth PMOS switch 304 is connected to the drain of the sixth NMOS switch 305 and the gate of the fifth NMOS switch 303, respectively. The source of the sixth NMOS switch 305 is grounded. The other end of the second single-pole single-throw switch 306 is connected to the current replication node A of the bandgap reference circuit. The substrate and source of the fifth NMOS switch 303 are both connected to the other end of the capacitor 205. The second single-pole single-throw switch 306 is closed, and the third single-pole single-throw switch 307 is open. When the chip is powered off, there is a residual voltage V. RES At that time, due to the output voltage BG of the bandgap reference circuit OUTLarge filter capacitors are often connected, therefore the output voltage BG of the bandgap reference circuit is... OUT Approximate residual voltage V RES This results in a small amount of current still flowing through the first NPN bipolar transistor 103 and the second NPN bipolar transistor 104 in the bandgap reference circuit. To maintain this current, the first PMOS current mirror transistor 101 and the second PMOS current mirror transistor 102 in the bandgap reference circuit are slightly turned on. Therefore, the voltage at the current replication node A is close to 0. At this time, the gate-source voltages of the fourth PMOS switch 304 and the sixth NMOS switch 305 are approximately the residual voltage V. RES By adjusting the relative drive capability of the fourth PMOS switch 304 and the sixth NMOS switch 305, making the pull-up capability of the fourth PMOS switch 304 stronger, the voltage at node D will approach the residual voltage V. RES Furthermore, the source and substrate of the fifth NMOS switch 303 are short-circuited, reducing the threshold voltage and increasing the pull-down capability. This allows the voltage at the other end (B) of capacitor 205 to be pulled high, discharging the charge stored in capacitor 205. Upon the next power-on, the voltage rise at the other end (B) of capacitor 205 will be closer to the power supply voltage VDD, thus improving the power-on startup speed. After normal power-on, the gate-source voltage of the fourth PMOS switch 304 is equal to the gate-source voltage of the first PMOS current mirror 101 in the bandgap reference main circuit, while the gate-source voltage of the sixth NMOS switch 305 is the power supply voltage VDD. Therefore, the pull-down capability of the sixth NMOS switch 305 is stronger than the pull-up capability of the fourth PMOS switch 304. The voltage at node D, formed by the drain of the fourth PMOS switch 304 and the drain of the sixth NMOS switch 305, is 0, causing the fifth NMOS switch 303 to turn off, thus not affecting the normal operation of the bandgap reference circuit. In addition, reducing the width-to-length ratio of the fourth PMOS switch 304 and the sixth NMOS switch 305 can reduce the static current of this branch after power-on.

[0034] Under rapid processing or high temperature conditions, the turn-on threshold of the third control switch 211 decreases. When the chip is powered off, BG OUT With V RES Approximately equal, the third control switch 211 is slightly turned on; upon power-on again, BG OUT A slight increase in voltage will fully turn on the third control switch 211, prematurely pulling the other end B of capacitor 205 down to 0, turning off the startup circuit. Consequently, the current replication node A of the bandgap reference circuit cannot be pulled down quickly, resulting in a slower startup speed. To solve this problem, the turn-on threshold of the third control switch 211 needs to be increased; therefore, a level shifter 212 is introduced, such as... Figure 2 The level shifter 212 is connected in parallel with the first single-pole single-throw switch 213, and the input terminal of the level shifter 212 is connected to the output terminal BG of the bandgap reference circuit.OUT The output of level shifter 212 is used to control the gate voltage of the fourth NMOS switch 308. At this time, the first single-pole single-throw switch 213 is open, and the output of level shifter 212 is lower than the threshold voltage of approximately one MOS transistor. That is, the control voltage of the third control switch 211 is BG. OUT Subtracting the threshold voltage, the output of the bandgap reference circuit can be BG. OUT When the voltage is increased to a higher level, the third control switch 211 is turned on and pulls down the voltage at the other end B of capacitor 205.

[0035] Specifically, such as Figure 3 The level shifter 212 includes a seventh NMOS switch 309 and a fifth PMOS switch 310. The drain of the seventh NMOS switch 309 is connected to the power supply voltage VDD. The sources of the seventh NMOS switch 309 and the fifth PMOS switch 310 are both connected to the gate of the fourth NMOS switch 308 and one end of the first single-pole single-throw switch 213 as node E. The gate of the seventh NMOS switch 309, the other end of the first single-pole single-throw switch 213, and the gate of the fifth PMOS switch 310 are all connected to the output terminal of the bandgap reference circuit. The drain of the fifth PMOS switch 310 is grounded. When the chip is powered down to the residual voltage VDD... RES At this time, the fifth PMOS switch 310 is turned off to prevent the voltage at node E from being pulled up by the seventh NMOS switch 309. Therefore, the fourth NMOS switch 308 remains off to prevent the startup circuit from turning on prematurely. When the chip recovers from the residual voltage V... RES Upon power-up, the voltage at node E is reduced to the output terminal BG of the bandgap reference circuit. OUT The difference between the gate-source voltage of the seventh NMOS switch 309 and the fourth NMOS switch 308 delays the turn-on time. The voltage at the other end B of capacitor 205 will not be pulled down too early, and the startup circuit will continue to work until the voltage at node E exceeds the threshold of the fourth NMOS switch 308, effectively improving the startup speed.

[0036] When the chip is powered on, due to the conservation of charge across capacitor 205, the voltage at the other end B of capacitor 205 rises along with the power supply voltage VDD. When the voltage at the other end B of capacitor 205 rises to the turn-on threshold of the third NMOS switch 302, the third NMOS switch 302 turns on, using the gate of the first PMOS switch 201, the drain of the third PMOS switch 301, the drain of the second PMOS switch 204, and the drain of the third NMOS switch 302 as node C. The voltage at node C is pulled down to 0, the first PMOS switch 201 turns on, and the resulting current, after passing through the NMOS current mirror, provides a current path to the current replication node A of the bandgap reference circuit. Therefore, the voltage at the current replication node A is pulled down, and the bandgap reference circuit leaves the degeneracy point and enters the normal setup process. When the chip is powered off, there is no residual voltage VDD. RES At this time, because the third single-pole single-throw switch 307 is closed, the gate of the fourth PMOS switch 304 is connected to the power supply voltage VDD, and the gate-source voltage of the sixth NMOS switch 305 is also the power supply voltage VDD. Therefore, the voltage at node D is 0, the fifth NMOS switch 303 is turned off, the voltage at the other end B of capacitor 205 is unaffected, and the branches of the fifth NMOS switch 303, the fourth PMOS switch 304, and the sixth NMOS switch 305 have no static power consumption. After the bandgap reference is established, because the first single-pole single-throw switch 213 is closed, the output voltage BG of the bandgap reference circuit... OUT When the threshold of the fourth NMOS switch 308 is exceeded, the fourth NMOS switch 308 is turned on, the other end B of capacitor 205 is pulled down to 0, the third NMOS switch 302 is turned off, the third PMOS switch 301 is turned on, pulling the voltage of node C up to the power supply voltage VDD, the first PMOS switch 201 is turned off, the entire startup circuit is shut down, and no static power consumption is generated.

[0037] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A fast start-up circuit suitable for bandgap reference circuits, characterized in that, include: The system includes a first PMOS switch (201), an NMOS current mirror, a second PMOS switch (204), a capacitor (205), a first control switch (207), a second control switch (208), a third control switch (211), and a first single-pole single-throw switch (213). The source of the first PMOS switch (201), one end of the first control switch (207), one end of the capacitor (205), and the source of the second PMOS switch (204) are all connected to the power supply voltage VDD. The gate of the first PMOS switch (201) is connected to the other end of the first control switch (207), one end of the second control switch (208), and the drain of the second PMOS switch (204), respectively. The second control switch (207) is connected to the first control switch (208), one end of the second control switch (208), and the drain of the second PMOS switch (204). The other end of the capacitor (208) is grounded. The drain of the first PMOS switch (201) is connected to the NMOS current mirror. The output terminal of the NMOS current mirror and the gate of the second PMOS switch (204) are connected to the current replication node A of the bandgap reference circuit as the output terminal of the fast start circuit. The other end of the capacitor (205) is connected to one end of the third control switch (211), the control terminal of the first control switch (207), and the control terminal of the second control switch (208). The other end of the third control switch (211) is grounded. The control terminal of the third control switch (211) is connected to one end of the first single-pole single-throw switch (213). The other end of the first single-pole single-throw switch (213) is connected to the output terminal BG of the bandgap reference circuit. OUT connect.

2. The fast start-up circuit suitable for bandgap reference circuits according to claim 1, characterized in that, The NMOS current mirror includes a first NMOS switch (202) and a second NMOS switch (203). The drain and gate of the first NMOS switch (202) are connected to the drain of the first PMOS switch (201) and the gate of the second NMOS switch (203), respectively. The source of the first NMOS switch (202) and the source of the second NMOS switch (203) are both grounded. The drain of the second NMOS switch (203) and the gate of the second PMOS switch (204) are connected together as the output terminal of the fast start circuit to the current replication node A of the bandgap reference circuit.

3. A fast start-up circuit suitable for bandgap reference circuits according to claim 2, characterized in that, It also includes an inverter (206), the input of which is connected to the other end of a capacitor (205) to control the control terminal of a second control switch (208), and the output of which is used to control the control terminal of a first control switch (207).

4. A fast start-up circuit suitable for bandgap reference circuits according to claim 2, characterized in that, The first control switch (207) is a third PMOS switch (301). The source of the third PMOS switch (301) is connected to the power supply voltage VDD. The gate of the third PMOS switch (301) is connected to the other end of the capacitor (205). The drain of the third PMOS switch (301) is connected to one end of the second control switch (208), the gate of the first PMOS switch (201), and the drain of the second PMOS switch (204), respectively.

5. A fast start-up circuit suitable for bandgap reference circuits according to claim 4, characterized in that, The second control switch (208) is a third NMOS switch (302). The gate of the third NMOS switch (302) is connected to the other end of the capacitor (205). The source of the third NMOS switch (302) is grounded. The drain of the third NMOS switch (302) is connected to the drain of the second PMOS switch (204), the drain of the third PMOS switch (301), and the gate of the first PMOS switch (201), respectively.

6. A fast start-up circuit suitable for bandgap reference circuits according to claim 5, characterized in that, The third control switch (211) is a fourth NMOS switch (308). The gate of the fourth NMOS switch (308) is connected to one end of the first single-pole single-throw switch (213). The source of the fourth NMOS switch (308) is grounded. The drain of the fourth NMOS switch (308) is connected to the other end of the capacitor (205).

7. A fast start-up circuit suitable for bandgap reference circuits according to claim 6, characterized in that, Also includes: The fourth control switch (209) and the quantization inverter (210) are connected to the power supply voltage VDD at one end of the fourth control switch (209) and the input terminal of the quantization inverter (210). The output terminal of the quantization inverter (210) is used to control the control terminal of the fourth control switch (209). The other end of the fourth control switch (209) is connected to the other end of the capacitor (205).

8. A fast start-up circuit suitable for bandgap reference circuits according to claim 7, characterized in that, The fourth control switch (209) is the fifth NMOS switch (303). The quantization inverter (210) includes: a fourth PMOS switch (304), a sixth NMOS switch (305), a second single-pole single-throw switch (306), and a third single-pole single-throw switch (307). One end of the third single-pole single-throw switch (307), the gate of the sixth NMOS switch (305), the source of the fourth PMOS switch (304), and the drain of the fifth NMOS switch (303) are all connected to the power supply voltage VDD. The third single-pole single-throw switch (307) The other end of the second single-pole single-throw switch (306) and one end of the second single-pole single-throw switch (306) are both connected to the gate of the fourth PMOS switch (304). The drain of the fourth PMOS switch (304) is connected to the drain of the sixth NMOS switch (305) and the gate of the fifth NMOS switch (303), respectively. The source of the sixth NMOS switch (305) is grounded. The other end of the second single-pole single-throw switch (306) is connected to the current replication node A of the bandgap reference circuit. The substrate and source of the fifth NMOS switch (303) are both connected to the other end of the capacitor (205).

9. A fast start-up circuit suitable for bandgap reference circuits according to claim 8, characterized in that, It also includes a level shifter (212), which is connected in parallel with the first single-pole single-throw switch (213), and the input terminal of the level shifter (212) is connected to the output terminal BG of the bandgap reference circuit. OUT The output of the level shifter (212) is used to control the gate voltage of the fourth NMOS switch (308).

10. A fast start-up circuit suitable for bandgap reference circuits according to claim 9, characterized in that, The level shifter (212) includes a seventh NMOS switch (309) and a fifth PMOS switch (310). The drain of the seventh NMOS switch (309) is connected to the power supply voltage VDD. The sources of the seventh NMOS switch (309) and the fifth PMOS switch (310) are both connected to the gate of the fourth NMOS switch (308) and one end of the first single-pole single-throw switch (213). The gate of the seventh NMOS switch (309), the other end of the first single-pole single-throw switch (213), and the gate of the fifth PMOS switch (310) are all connected to the output terminal BG of the bandgap reference circuit. OUT Connection; the drain of the fifth PMOS switch (310) is grounded.

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