Cold and hot data migration method, processor, equipment and system

Abstract

The invention discloses a cold and hot data migration method, a processor, equipment and a system, and relates to the field of computers. The method comprises the steps of sampling a plurality of memory channels according to a sampling strategy in a scene that a processor in computer equipment accesses a memory medium in an interleaving mode, and determining the access frequency of a page where interleaved data blocks are located in the memory medium according to the access frequency of the interleaved data blocks in the sampled memory channels, therefore, the access heat of the page is determined according to the access frequency of the page, and data migration is triggered according to the access heat. The whole access frequency of the page is determined based on the partial access frequency of the page, the accuracy of the access frequency of the page where the interleaved data blocks are located is improved, the statistical data volume of the access frequency of the page is reduced, a processor can obtain the access frequency of the page as quickly as possible, and when data migration is triggered according to the access heat of the page, the data migration efficiency is improved. The data processing speed of the system is improved, and the data processing time delay is reduced.

Description

[0001] This application is a divisional application. The application number of the original application is 202310363679.X, and the original application date is March 31, 2023. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computers, and in particular to a method, processor, device and system for migrating hot and cold data. Background Art

[0003] At present, the processor in the computer device reads or writes the memory in an interleaved manner, that is, the data accessed to the memory is evenly distributed to multiple memory channels according to the unit storage space (for example, cache line), and the multiple memories are read or written to improve the access performance of the system. However, in the application scenario where the processor accesses the memory in an interleaved manner, the memory access heat is determined based on the access frequency of the page. Since more counters are required to count the page access frequency of each memory channel, the statistical data of the page access frequency is large, especially for small pages (such as 4 kilobyte (KB) pages). As a result, the processor may not be able to obtain the page access frequency in time, which may cause the memory with fast access speed to store infrequently accessed data, or cause the memory with slow access speed to store frequently accessed data, affecting the data processing speed and latency of the system. Summary of the invention

[0004] The present application provides a hot and cold data migration method, processor, device and system, thereby improving the data processing speed of the system and reducing the data processing delay.

[0005] In a first aspect, a memory data migration method is provided, which is applied to a hybrid memory system, wherein the hybrid memory system includes multiple processors and multiple different types of memory media, and the processor is associated with at least two different types of memory media. The method includes: in a scenario where a processor in a computer device accesses a memory medium in an interleaved manner, sampling multiple memory channels according to a sampling strategy, and determining the access frequency of a page where an interleaved data block in the memory medium is located according to the access frequency of the interleaved data block in the sampled memory channel, so as to determine the access heat of the page according to the access frequency of the page, and trigger data migration according to the access heat. Among them, the access frequency intuitively indicates the frequency with which a data block is accessed by an application. The more times a data block is accessed by an application, the more frequently the data block is accessed by the application, and the hotter the access heat of the data block; the fewer times a data block is accessed by an application, the less frequently the data block is accessed by the application, and the colder the access heat of the data block.

[0006] In this way, the memory data migration method provided by the present application performs multi-dimensional sampling of the memory channel based on the spatial dimension and time dimension indicated by the sampling strategy, thereby ensuring that the access frequency of the interleaved data block in the sampled memory channel is representative, and realizing the determination of the access frequency of the page where the interleaved data block is located based on the access frequency of the interleaved data block in the sampled memory channel, that is, determining the total access frequency of the page based on the partial access frequency of the page, thereby improving the accuracy of the access frequency of the page where the interleaved data block is located, and reducing the statistical data amount of the page access frequency, so that the processor can obtain the page access frequency as quickly as possible. When triggering data migration based on the access heat of the page, hot data can be migrated to near memory (near memory), and cold data can be migrated to far memory (far memory), so that the processor can obtain frequently accessed data from the near memory as quickly as possible, thereby improving the data processing speed of the system and reducing the data processing delay.

[0007] The access speed of the near-end memory is greater than the access speed of the far-end memory. For example, the near-end memory may be a dynamic random access memory (DRAM) or a double data rate synchronous dynamic random access memory (DDR SDRAM). The far-end memory may be a storage-class-memory (SCM).

[0008] The multiple different types of memory media include a first memory medium and a second memory medium, the memory medium associated with the processor includes the first memory medium and the second memory medium, the access speed of the first memory medium is greater than the access speed of the second memory medium, and the access delay of the first memory medium is less than the access delay of the second memory medium. For example, the first memory medium may be a near-end memory, and the second memory medium may be a far-end memory.

[0009] In a possible implementation, sampling multiple memory channels in a computer device according to a sampling strategy includes: sampling multiple memory channels to obtain sampled memory channels according to page identifiers and spatial distribution of memory channels indicated by the sampling strategy.

[0010] In a possible implementation, sampling from multiple memory channels to obtain sampled memory channels according to the spatial distribution of page identifiers and memory channels indicated by the sampling strategy includes: sampling from multiple memory channels to obtain sampled memory channels according to the correspondence between page identifiers and memory channels.

[0011] Therefore, based on the spatial distribution characteristics of pages and memory channels, spatial sampling is performed on the memory channels, and the access frequency of part of the storage space in the page represents the access frequency of the complete page, that is, the access frequency recorded by the counter in a memory channel represents the access frequency of a page. This not only improves the accuracy of the access frequency of the page where the interleaved data block is located, but also reduces the amount of statistical data on the access frequency of the page.

[0012] In a possible implementation, multiple memory channels in a computer device are sampled according to a sampling strategy, including: sampling the sampled memory channel from the multiple memory channels according to a rotation sampling method indicated by the sampling strategy, the rotation sampling method being used to indicate a change in a correspondence between a page identifier and a memory channel.

[0013] Therefore, the memory channel is sampled based on the spatial dimension and the temporal dimension, and the corresponding relationship between the page identifier and the memory channel is changed by rotating the sampling method, so as to improve the representativeness of the access frequency of the interleaved data block in the sampled memory channel and reduce the distortion caused by sampling.

[0014] In a possible implementation, sampling multiple memory channels in a computer device according to a sampling strategy includes: sampling multiple memory channels to obtain sampled memory channels according to a correspondence between a time period indicated by the sampling strategy and a storage space of a memory medium.

[0015] In one possible implementation, multiple memory channels in a computer device are sampled according to a sampling strategy, including: sampling the sampled memory channel from the multiple memory channels according to a rotational sampling method indicated by the sampling strategy, the rotational sampling method being used to indicate a change in the correspondence between a time period and a storage space of a memory medium.

[0016] Therefore, the memory channel is sampled based on the spatial dimension and the temporal dimension, and the corresponding relationship between the time period and the storage space of the memory medium is changed by rotating the sampling method, thereby improving the representativeness of the access frequency of the interleaved data blocks in the sampled memory channel and reducing the distortion caused by sampling.

[0017] In one possible implementation, sampling multiple memory channels in a computer device according to a sampling strategy includes: sampling multiple memory channels corresponding to addresses indicated by access requests according to the sampling strategy, where the access requests are used to indicate operations on a memory medium by an application program running on a processor in the computer device.

[0018] In a possible implementation, the size of the interleaved data block is a multiple of a cache line when the processor accesses the memory medium.

[0019] In a possible implementation, the size of a page is 4 kilobytes (KB). Since the memory data migration method provided by the present application can improve the accuracy of the access frequency of the page where the interleaved data block is located, and reduce the statistical data amount of the page access frequency, the processor can obtain the page access frequency as quickly as possible. For smaller pages, the statistical data amount of the access frequency of the small page is reduced and the statistical accuracy is improved, thereby obtaining higher data migration accuracy.

[0020] In a second aspect, a memory data migration device is provided, the memory data migration device comprising modules for executing the memory data migration method in the first aspect or any possible design of the first aspect.

[0021] In a third aspect, a memory is provided, the memory comprising a storage medium and a controller, the storage medium being used to store a set of computer instructions; when the controller executes the set of computer instructions, the operating steps of the method in the first aspect or any possible implementation of the first aspect are executed to realize the identification of the access frequency of the data block in the memory by the application program.

[0022] In a fourth aspect, a chip is provided, comprising: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; and the processor is used to execute the operating steps of the method in the first aspect or any possible implementation of the first aspect to realize the identification of the access frequency of a data block in a memory by an application program.

[0023] In a fifth aspect, a processor is provided, the processor including at least two different types of memory media associated therewith, and the processor is used to execute the operating steps of the method in the first aspect or any possible implementation of the first aspect to identify the access frequency of data blocks in the memory medium by applications.

[0024] In a sixth aspect, a computer device is provided, which includes a memory, a plurality of different types of memory media, and a processor, wherein the memory is used to store a set of computer instructions; when the processor executes the set of computer instructions, the processor is used to execute the operating steps of the method in the first aspect or any possible implementation of the first aspect to realize the identification of the access frequency of a data block in the memory by an application program.

[0025] In the seventh aspect, a computer-readable storage medium is provided, comprising: computer software instructions; when the computer software instructions are executed in a processor, the processor executes the operating steps of the method described in the first aspect or any possible implementation of the first aspect.

[0026] In an eighth aspect, a computer program product is provided. When the computer program product is run on a computer, the computer is caused to execute the operation steps of the method described in the first aspect or any possible implementation manner of the first aspect.

[0027] The technical effects brought about by any design method in the second to eighth aspects can refer to the technical effects brought about by the first aspect or different design methods in the first aspect, and will not be repeated here.

[0028] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the composition of a computer device provided for this application; Figure 2 A schematic diagram of memory interleaving provided for this application; Figure 3 A schematic diagram of a memory access heat statistics scenario provided for this application; Figure 4 A flowchart of a memory data migration method provided in this application; Figure 5 A schematic diagram of memory access heat statistics based on spatial dimension provided for this application; Figure 6 A schematic diagram of memory access heat statistics based on the time dimension provided for this application; Figure 7 A flowchart of a memory access heat statistics method provided in this application; Figure 8 A flow chart of a sampling strategy adjustment method provided in this application; Fig. 9 A schematic diagram of the structure of a memory data migration device provided in this application. DETAILED DESCRIPTION

[0030] For ease of description, the terms involved in this application are first briefly introduced.

[0031] In the hierarchy of computer storage systems, the closer the memory is to the processor, the faster the access speed and the smaller the storage capacity. Based on the order from closest to farthest from the processor, the memory is divided into: registers, cache memory, main memory, external memory.

[0032] Main memory, also known as internal memory, is abbreviated as main memory or memory. Main memory is an important component of the computer system, that is, the bridge for communication between external memory and processor. Main memory is used to temporarily store the calculation data in the processor and the data exchanged between the processor and external memory such as hard disk. For example, when the computer starts running, the data to be calculated is loaded from the main memory to the processor for calculation. After the calculation is completed, the processor stores the calculation result in the main memory. For example, main memory includes dynamic random access memory (DRAM) and double data rate synchronous DRAM (DDR SDRAM).

[0033] External storage, also known as auxiliary storage, is abbreviated as external storage or auxiliary storage. Compared with main memory, external storage has a large storage capacity and a slow access speed. For example, external storage includes network storage, solid state disk (SSD), and hard disk drive (HDD).

[0034] Cache memory is a high-speed, small-capacity memory between the processor and the main memory. Cache memory is referred to as cache. Compared with the main memory, the cache has a small storage capacity and a fast access speed. Cache includes L1 cache, L2 cache, and L3 cache. L1 cache is set inside the processor core. L2 cache can be set inside or outside the processor core. L1 cache and L2 cache are usually exclusive to the processor core they are located in. L3 cache is generally set outside the processor core and shared by multiple processor cores.

[0035] A register is a small memory inside a processor that is used to temporarily store data and results of operations. A register can be a commonly used sequential logic circuit.

[0036] Hierarchical Storage Technology (HST) stores data in different storage devices with different performances in different ways according to data importance, access frequency, retention time, storage capacity, performance and other indicators, and realizes automatic migration of data between storage devices through hierarchical storage management.

[0037] Hot data refers to data that is frequently accessed by the processor. If hot data is stored in near-end memory, the processor can obtain the data as quickly as possible, which increases the data processing speed of the system and reduces the data processing latency, significantly improving the access performance of the system.

[0038] Cold data refers to data that is not frequently accessed by the processor. If cold data is stored in remote memory (farmemory), more data can be stored, and the local memory can store more hot data, thereby improving the resource utilization of the local memory and reducing system costs. The access speed of the local memory is greater than that of the remote memory. For example, the cache memory is relative to the main memory, the cache memory is the local memory, and the main memory is the remote memory. For another example, the main memory is relative to the external memory, the main memory is the local memory, and the external memory is the remote memory.

[0039] A cache line is a unit of memory storage space that a computer device uses to read or write data. The size of a cache line can be 64 bytes (bytes, B).

[0040] Page refers to the unit in which a computer device manages the storage space of memory. For example, the page size (pagesize) is 4 KB, 2 megabytes (MB), or other byte sizes. A 4KB page can be called a small page. A 2MB page can be called a large page. The smaller the page, the more resources the computer device needs to manage memory; the larger the page, the fewer resources the computer device needs to manage memory. A page can include multiple cache lines, that is, the page size is a multiple of the cache line size.

[0041] Interleaving means that the data accessing the memory is evenly distributed to multiple memory channels according to the unit storage space (for example, cache line). The interleaving mode can be configured by the system administrator. It can be interleaved between multiple memory channels connected to a processor or between multiple memory channels of multiple processors.

[0042] Memory channels refer to multiple memories connected to a processor in a computer device. The processor can use interleaving technology to operate the memory. For example, the processor evenly distributes the data to be written to the memory to multiple memory channels according to the size of the cache line. Then, the processor reads data from multiple memory channels according to the size of the cache line. Thus, data processing is performed based on multiple memory channels to improve the memory bandwidth utilization and processing performance of the computer device.

[0043] In order to improve the data processing speed of the system and reduce the data processing delay, the present application provides a memory data migration method, which is applied to a hybrid memory system, wherein the hybrid memory system includes multiple processors and multiple different types of memory media, and the processor is associated with at least two different types of memory media. The method includes: in a scenario where the processor in a computer device accesses the memory medium in an interleaved manner, sampling multiple memory channels according to a sampling strategy, determining the access frequency of the page where the interleaved data block in the memory medium is located according to the access frequency of the interleaved data block in the sampled memory channel, so as to determine the access heat of the page according to the access frequency of the page, and triggering data migration according to the access heat.

[0044] The memory data migration method provided by the present application performs multi-dimensional sampling of memory channels based on the spatial dimension and time dimension indicated by the sampling strategy, thereby ensuring that the access frequency of the interleaved data block in the sampled memory channel is representative, and realizing the determination of the access frequency of the page where the interleaved data block is located based on the access frequency of the interleaved data block in the sampled memory channel, that is, determining the total access frequency of the page based on the partial access frequency of the page, thereby improving the accuracy of the access frequency of the page where the interleaved data block is located, and reducing the statistical data amount of the page access frequency, so that the processor can obtain the page access frequency as quickly as possible. When triggering data migration based on the access heat of the page, hot data can be migrated to the near-end memory, and cold data can be migrated to the far-end memory, so that the processor can obtain frequently accessed data from the near-end memory as quickly as possible, thereby improving the data processing speed of the system and reducing the data processing delay.

[0045] The memory data migration method provided in this application can be applied to fields such as artificial intelligence, big data, cloud computing, and scenarios containing multiple types of storage media, such as high-performance, large-capacity storage systems.

[0046] The implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0047] Figure 1 A schematic diagram of the composition of a computer device provided in this application. Figure 1 As shown, computer device 100 includes a processor 110 .

[0048] The processor 110 is the control center of the computer device 100. The processor 110 may be a computing unit with computing power, such as a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a neural processing unit (NPU), and an embedded neural network processor (NPU). The processor 110 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), systems on chip (SoC) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. For ease of description, the following embodiments are described by taking the processor 110 as a CPU as an example.

[0049] Figure 1 The computer device 100 may include one or more processors (eg, processor 110 and processor 130). The processor may be a multi-core processor, that is, the processor includes one processor core or multiple processor cores. For example, Figure 1 The processor 110 shown in FIG. 1 includes N processor cores. A processor herein may refer to one or more devices, circuits, and / or computing units for processing data (eg, computer program instructions).

[0050] As the number of cores in a single processor increases, the computing speed of the processor also increases, and the processor's demand for memory access speed and memory capacity also increases. In a possible implementation, multiple different types of storage media are used together as the main memory (referred to as: memory or main memory) of a computer device to increase memory capacity, and allocate as much memory resources and memory bandwidth as possible from the memory to each processor core to meet the processor's demand for memory access speed and memory capacity. A system that uses multiple different types of storage media as memory can be called a hybrid memory system. The storage medium used as memory in a hybrid memory system can be called a memory medium. A processor can be associated with at least one type of memory medium, that is, some processors are associated with one type of memory medium, and some processors are associated with two or more types of memory medium.

[0051] For example, a computer device includes multiple different types of memory media. The multiple different types of memory media include a first memory medium and a second memory medium, the storage capacity of the first memory medium is lower than the storage capacity of the second memory medium, the access speed of the first memory medium is higher than the access speed of the second memory medium, the access delay of the first memory medium is lower than the access delay of the second memory medium, and the cost of the first memory medium is higher than the cost of the second memory medium.

[0052] The first memory medium may include dynamic random access memory (DRAM). The second memory medium is storage-class memory (SCM), and SCM includes at least one of phase-change memory (PCM), magnetic random access memory (MRAM), resistive random access memory (RRAM / ReRAM), ferroelectric random access memory (FRAM), fast NAND or nano-RAM (Nano-RAM, NRAM).

[0053] By way of example, the various types of memory media used as the main memory 120 in the computer device 100 include DRAM 121 and SCM 122. The processor 110 is connected to the DRAM 121 and the SCM 122 via an interface supporting memory semantics.

[0054] The processor 110 is used to run an application program to perform a read operation or a write operation on a memory medium (eg, DRAM 121, SCM 122), and trigger data migration according to the access hotness or coldness of the memory medium.

[0055] Triggering data migration based on the access hotness of the memory medium can be alternatively described as triggering data migration based on the access hotness of the data stored in the memory medium. Data migration includes migrating cold data to the next level memory medium and migrating hot data to the previous level memory medium.

[0056] For example, when the cache line is cold data, the memory medium where the cache line is located is DRAM, and the cache line is migrated to the SCM.

[0057] For another example, when the cache line is hot data, the memory medium where the cache line is located is SCM, and the cache line is migrated to DRAM.

[0058] Understandably, any level of memory medium in the computer device can trigger data migration based on the degree of data access. Each memory medium migrates data level by level based on the degree of data access. Compared with the current memory medium, the storage capacity of the next level of memory medium is larger; the access speed of the previous level of memory medium is faster.

[0059] In some embodiments, the computer device counts the access frequency of the page at the granularity of the page (such as 4KB page, 2MB page), which is compatible with the page management method of the computer device for the memory, making the memory data migration method easy to use. For example, the processor operates the memory medium at the granularity of the cache line, and the cache line belongs to a certain page under management. The cache line in the memory medium is operated once, and the page to which the cache line belongs is also read and written once. The controller counts the access frequency of the page to which the cache line operated belongs, effectively improving the recognition accuracy of the access heat of the page.

[0060] In other embodiments, when the application program executed by the processor 110 operates the memory medium of the computer device in an interleaved manner, the data accessing the memory medium is evenly distributed to multiple memory channels according to the unit storage space (for example, cache line) to improve the access speed. Wherein, each memory channel can only obtain a partial space address within a page, and the access frequency of the page includes the access frequency of the data block contained in the page on the interleaved multiple memory channels.

[0061] For example, Figure 2As shown in the figure, a 2MB page includes 512 4KB pages, a cache line size is 64B, and a 4KB page includes 64 cache lines. A 2MB page includes 512*64 cache lines evenly divided into less than 8 memory channels, and each memory channel is allocated 512*512B cache lines. Each memory channel contains a 256KB interleaved data block.

[0062] For example, the page size is 4KB (X page size =4KB), data is interleaved across 8 memory channels at the granularity of cache lines (N channel =8), the size of the interleaved data block of each memory channel is 512B. If the memory storage capacity is 128GB, 32K counters are required without interleaving, and 32K * 8 = 256K counters are required when 8 memory channels are interleaved.

[0063] For example, the page size is 2MB (X page size = 2MB), data is interleaved across 4 memory channels at the granularity of cache lines (N channel =4), the size of the interleaved data block of each memory channel is 512KB. If the memory storage capacity is 128GB, 64K counters are required without interleaving, and 64K*4=256K counters are required when 4 memory channels are interleaved.

[0064] In the present application, the processor 110 is used to sample multiple memory channels according to a sampling strategy in a scenario where the memory medium is accessed in an interleaved manner, and determine the access frequency of the page where the interleaved data block is located in the memory medium according to the access frequency of the interleaved data block in the sampled memory channel, so as to determine the access popularity of the page according to the access frequency of the page, and trigger data migration according to the access popularity.

[0065] In addition, the present application does not limit the execution subject of the memory access heat statistics, and the execution subject includes the medium module in the computer device, other hardware modules or processors with computing functions in the computer device.

[0066] For example, Figure 3 As shown in (a), the acquisition of access requests, sampling of memory channels, statistical counting and storage of access frequencies are implemented in the medium module. The medium module can be any of a variety of different types of memory media. For example, the medium module can be DRAM or SCM.

[0067] The processor in the computer device sends an access request to the media module, indicating that a write operation or a read operation is to be performed on the media module. The controller in the media module (such as the Register Clock Driver (RCD)) can collect the access request, sample the memory channel indicated by the access request, and count the access frequency of the interleaved data block in the sampled memory channel, store the access frequency of the interleaved data block; and then, feedback the access frequency of the interleaved data block to the processor in an in-band or out-of-band manner.

[0068] like Figure 3 As shown in (b) of Figure 3 The difference from (a) in the figure is that other hardware modules in the computer device collect access requests, sample memory channels, count and store access frequencies, and feed back the access frequencies of interleaved data blocks to the processor in an in-band or out-of-band manner. The hardware module can be a memory controller or a peripheral (e.g., a complex programmable logical device (CPLD), FPGA), etc.

[0069] like Figure 3 As shown in (c) of Figure 3 The difference from (a) is that the processor in the computer device collects access requests, samples memory channels, counts statistics, and stores access frequencies, and the processor core can obtain the access frequency of the interleaved data block by reading the register in the processor.

[0070] Computer device 100 may also include cache memory and registers.

[0071] The cache memory is used to store instructions or data that may be accessed multiple times by the processor core in the processor 110 , thereby increasing the speed at which the processor processes data and preventing the processor from frequently accessing the main memory 120 .

[0072] In physical form, cache memory can be random access memory (RAM), static random-access memory (SRAM), dynamic RAM (DRAM), or other types of storage devices that can store information and instructions.

[0073] In terms of logical form, a cache memory can be a level 1 cache (L1 cache), a level 2 cache (L2 cache), a level 3 cache (L3 cache), or any level of cache device. For example, a cache memory disposed inside a processor core can be a level 1 cache (L1 cache) and a level 2 cache (L2 cache). A cache memory disposed outside a processor core can be a level 3 cache (L3 cache).

[0074] The register is used to store instructions or data that may be accessed multiple times by the processor core in the processor 110. Since the access speed of the register is higher than the access speed of the cache memory, the instructions or data that may be accessed multiple times by the processor core can be stored in the register first, which can further improve the speed of the processor processing data.

[0075] The processor core is connected to other devices in the processor (such as the processor core, cache memory, and main memory 120) through the bus 111, and accesses other devices through the bus 111. For example, the processor core, cache memory, and main memory 120 transmit access frequencies through the bus 111. For another example, the processor core transmits a write instruction or a read instruction to the main memory 120 through the bus 111, so that the main memory 120 performs a write operation on the cache line according to the write instruction or performs a read operation on the cache line according to the read instruction. The bus 111 can be an industry standard architecture (ISA) bus, a peripheral component interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc., or a private bus standard of a non-standard system. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0076] Figure 1The connection method between the processor core and other devices in the processor is only a schematic illustration. In one possible implementation, the processor core is connected to other devices in the processor through a ring bus, and accesses other devices in the processor through the ring bus. In another possible implementation, the processor core and other devices in the processor are connected through a mesh bus, and the processor core accesses other devices in the processor through the mesh bus.

[0077] The processor 110 is connected to the main memory 120 through a memory controller (MC) 112. The processor 110 can perform various functions of the computer device 100 by running or executing software programs stored in the main memory 120 and calling data stored in the main memory 120. For example, the processor 110 collects access requests, samples memory channels, and counts and stores access frequencies through the memory controller 112.

[0078] The main memory 120 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), etc. The main memory 120 is also used to store programs related to the present embodiment.

[0079] The processor 110 may also include an external device 140 and an external device management module 113. The external device 140 is connected to the external device management module 113 via the bus 111. The external device 140 may be an application specific integrated circuit (ASIC). For example: a microprocessor (digital signal processor, DSP), or one or more field programmable gate arrays (field programmable gate array, FPGA), or a graphics processing unit (graphics processing unit, GPU), or a neural network processing unit (neural-network processing unit, NPU). The external device 140 may also collect access requests, sample memory channels, count statistics and store access frequencies, and feed back access frequencies to the processor core via the bus 111, so that the processor core triggers data migration according to the access hotness or coldness of the data.

[0080] Figure 1 The device structure shown in the figure does not constitute a limitation on the computer device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0081] Next, the memory data migration method provided by the present application is described in detail with reference to the accompanying drawings.

[0082] For ease of explanation, Figure 3 The media module statistics scenario shown in (a) in the figure is used as an example to implement the collection of access requests, sampling memory channels, statistical counting and storage access frequency in the memory medium. Figure 4 , Figure 4 This is a flow chart of a memory data migration method provided by this application. Figure 4 As shown, the method includes the following steps.

[0083] Step 410: The processor accesses the memory medium in an interleaved manner and sends access requests to multiple memory media.

[0084] When the processor accesses the memory medium in an interleaved manner, the data accessing the memory medium is evenly distributed to multiple memory channels according to the unit storage space (for example, cache line). It should be understood that the data accessing the memory medium is evenly distributed to multiple memory channels according to the unit storage space, that is, the data accessing the memory medium is evenly distributed to multiple memory media according to the unit storage space. For example, the processor sends an access request to multiple memory media, and the access request indicates to perform a read operation or a write operation on the memory medium according to the unit storage space (for example, cache line). The size of the unit storage space can be the size of the cache line when the processor accesses the memory.

[0085] Step 420: The memory medium samples multiple memory channels in the computer device according to the sampling strategy to determine the access frequency of the interleaved data blocks in the sampled memory channels.

[0086] The memory medium receives the access request sent by the processor, and the access request is used to instruct the application program running on the processor to operate the memory medium of the computer device. The memory medium decodes the access request to obtain the physical address and operation instruction indicated by the access request.

[0087] When the processor uses an interleaved method to access multiple memory media, the physical address indicates a storage space in one of the multiple memory channels. The size of the storage space can be the size of one or more cache lines, that is, the size of the interleaved data block is a multiple of the cache line when the processor accesses the memory medium. The operation instruction is used to indicate a read operation or a write operation on the storage space.

[0088] Understandably, when the processor accesses multiple memory media in an interleaved manner, each of the multiple memory media determines that the same page is accessed. In order to reduce the amount of data for statistically analyzing the page access frequency, the memory medium samples multiple memory channels according to a sampling strategy, and counts the access frequency of the interleaved data blocks in the sampled memory channels. The sampling strategy is used to indicate that the memory channels are sampled based on the spatial dimension and the temporal dimension.

[0089] The following describes how the memory medium samples multiple memory channels.

[0090] Method 1: The memory samples the sampled memory channels from multiple memory channels according to the spatial distribution of the page identifier and memory channels indicated by the sampling strategy. Since the access frequencies of the storage spaces accessed in the multiple memory media are similar when the processor accesses multiple memory media in an interleaved manner, and the storage spaces accessed in the multiple memory media belong to different address segments of the same page, the corresponding relationship between the page identifier and the memory channel can be pre-configured based on this rule.

[0091] In some embodiments, a memory medium receives an access request, determines the page accessed by the processor and the address segment indicated by the physical address in the page according to the physical address indicated by the access request; determines the memory channel corresponding to the accessed page according to the correspondence between the page identifier and the memory channel; determines whether the memory channel receiving the access request is the same as the memory channel corresponding to the accessed page, and if so, counts the access frequency of the interleaved data block in the memory channel receiving the access request; if not, there is no need to count the access frequency of the interleaved data block in the memory channel receiving the access request, thereby sampling multiple memory channels to obtain a sampled memory channel, and counting the access frequency of the interleaved data block in the sampled memory channel.

[0092] For example, the correspondence between the page identifier and the memory channel indicates that the page identifier and the memory channel identifier have a correspondence when they are the same, that is, the access frequency of the interleaved data block is counted in the memory channel with the same page identifier. For example, page 0 corresponds to memory channel 0, and the access frequency of the interleaved data block in page 0 is counted in memory channel 0. Page 1 corresponds to memory channel 1, and the access frequency of the interleaved data block in page 1 is counted in memory channel 1. If memory channel 0 receives an access request, it is determined that the processor accesses page 0 according to the physical address indicated by the access request, and the access frequency of the interleaved data block in page 0 is counted in memory channel 0; if it is determined that the processor accesses page 1 according to the physical address indicated by the access request, it is not necessary to count the access frequency of the interleaved data block in page 1 in memory channel 0. If memory channel 1 receives an access request, it is determined that the processor accesses page 0 according to the physical address indicated by the access request, and it is not necessary to count the access frequency of the interleaved data block in page 0 in memory channel 1.

[0093] For another example, the correspondence between the page identifier and the memory channel indicates that the memory channel having the same operation result as the page identifier has a correspondence.

[0094] For example, Figure 5 As shown in (a), the processor uses a 4-way interleaving method to access four memory media, that is, the data accessed by the memory is evenly distributed to four memory channels according to the unit storage space, including memory channel 0 to memory channel 3. Each memory channel includes the storage space of the address segment of five pages. If the access frequency of the five pages is counted on each memory channel, a counter for one page needs to be deployed on all four memory channels.

[0095] like Figure 5 As shown in (b), it is assumed that the correspondence between the page identifier and the memory channel indicates that the memory channel with the same modulo 4 operation result as the page identifier has a correspondence, that is, the access frequency of the interleaved data block in the page is counted in the memory channel with the same modulo 4 operation result as the page identifier. Page 0 corresponds to memory channel 0, and the access frequency of the interleaved data block in page 0 is counted in memory channel 0. Page 1 corresponds to memory channel 1, and the access frequency of the interleaved data block in page 1 is counted in memory channel 1. Similarly, page 4 corresponds to memory channel 0, and the access frequency of the interleaved data block in page 4 is counted in memory channel 0.

[0096] In other embodiments, due to the statistics of the access frequency of the interleaved data block in the sampled memory channel, some access frequency features will be lost, which may cause the access frequency of the interleaved data block in the sampled memory channel to fail to fully represent the access frequency of the page. The memory obtains the sampled memory channel by sampling from multiple memory channels in a rotational sampling manner indicated by the sampling strategy. The rotational sampling manner is used to indicate the change manner of the correspondence between the page identifier and the memory channel.

[0097] For example, the rotating sampling method is used to correspond to the page identifiers and memory channels at different times. Figure 5 As shown in (c), at time 0, page 0 corresponds to memory channel 0, and the access frequency of the interleaved data blocks in page 0 is counted in memory channel 0; at time 1, page 0 corresponds to memory channel 1, and the access frequency of the interleaved data blocks in page 0 is counted in memory channel 1; at time 2, page 0 corresponds to memory channel 2, and the access frequency of the interleaved data blocks in page 0 is counted in memory channel 2; at time 3, page 0 corresponds to memory channel 3, and the access frequency of the interleaved data blocks in page 0 is counted in memory channel 3.

[0098] Method 2: The memory samples the sampled memory channel from multiple memory channels according to the correspondence between the time period indicated by the sampling strategy and the storage space of the memory. It can be understood that the storage space of the memory medium is divided into multiple partial spaces, and the multiple partial spaces have a correspondence with multiple time periods. When the memory medium receives an access request, it determines whether the page accessed by the processor and the address segment indicated by the physical address in the page belong to the partial space corresponding to the time period. If so, the access frequency statistics of the address segment in the page are performed; if not, there is no need to perform access frequency statistics on the address segment in the page.

[0099] For example, Figure 6 As shown in (a), at time 0, the 0th part of the space is counted; at time 1, the 1st part of the space is counted; at time 2, the 2nd part of the space is counted; at time 3, the 3rd part of the space is counted. Assuming that at time 0, the memory medium receives an access request and determines that the page accessed by the processor and the address segment indicated by the physical address in the page belong to the 0th part of the space, the access frequency statistics of the address segment in the page are performed. If the memory medium determines that the page accessed by the processor and the address segment indicated by the physical address in the page belong to the 1st part of the space, there is no need to perform access frequency statistics on the address segment in the page.

[0100] In other embodiments, since some frequency features may be lost when sampling based on the time dimension, the access frequency of the interleaved data block in the sampled memory channel may not fully represent the access frequency of the page. The memory medium samples from multiple memory channels according to the rotation sampling method indicated by the sampling strategy to obtain the sampled memory channel. The rotation sampling method is used to indicate the change of the corresponding relationship between the time period and the storage space of the memory medium, that is, to change the order of time sampling on different storage spaces.

[0101] For example, the rotation sampling method is used based on the correspondence between different time periods and the storage space of the memory medium. Figure 6 As shown in (b) of Figure 6 The difference from (a) in the above is that in the second cycle, the partial space corresponding to each moment is replaced. For example, at moment 0, the third partial space is counted; at moment 1, the 0th partial space is counted; at moment 2, the 1st partial space is counted; at moment 3, the 2nd partial space is counted. Assuming that at moment 0, the memory medium receives an access request, and determines that the page accessed by the processor and the address segment indicated by the physical address in the page belong to the third partial space, the access frequency of the address segment in the page is counted.

[0102] Among them, the present application does not limit the variation of the rotation sampling method based on the spatial dimension and the time dimension. When sampling the memory channel based on the spatial dimension and the time dimension, the rotation sampling method increases the possibility of the corresponding relationship, improves the representativeness of the access frequency of the interleaved data block in the sampled memory channel, and reduces the distortion caused by sampling.

[0103] It should be noted that when the processor accesses multiple memory media in an interleaved manner, each memory medium can perform memory channel sampling based on the memory data migration method provided by the present application, count the access frequency of the interleaved data block in the sampled memory channel, and trigger data migration between at least two different types of memory media based on the access heat of the page determined by the access frequency of the page where the interleaved data block is located. In addition, the memory access heat statistics provided by the present application can be executed by the RCD in the memory medium. The memory medium can sample multiple memory channels according to the sampling strategy each time it receives an access request; it can also sample multiple memory channels according to the sampling strategy after receiving multiple access requests based on the sampling period.

[0104] In this way, by sampling the memory channel based on the spatial dimension and the temporal dimension, it is possible to obtain a smaller page access frequency while using fewer counters (requiring less RAM storage resources for storing access frequencies). In addition, a rotation sampling method is used to compensate for some distortion effects caused by sampling.

[0105] For example, if the storage capacity of the memory medium is 128 GB and the page size is 4 KB, only 128M counters are needed when 4 memory channels are interleaved.

[0106] Step 430: The processor determines the access frequency of the page where the interleaved data block is located in the memory medium according to the access frequency of the interleaved data block fed back by the memory medium.

[0107] Since the access frequency of the interleaved data block fed back by the memory medium is the access frequency of the interleaved data block in the sampled memory channel, that is, the access frequency of part of the storage space in the page. When the processor uses the interleaved method to access multiple memory media, the access frequencies of the storage spaces of the multiple memory media are similar. The processor determines the access frequency of the page where the interleaved data block is located in the memory medium according to the access frequency of the interleaved data block and the number of interleaving paths.

[0108] For example, the processor accesses four memory media in a 4-way interleaving manner, and the access frequency of the page where the interleaved data block is located in one of the memory media is 10,000 times, and the access frequency of the page where the interleaved data block is located is approximately 40,000 times.

[0109] Step 440: The processor determines the access popularity of the page according to the access frequency and triggers data migration.

[0110] The processor determines the access heat of the page based on the access frequency of the page where the data block is located after interleaving, and triggers data migration. For example, if the access frequency is greater than or equal to the threshold, the data block is determined to be hot; if the cold access frequency is less than the threshold, the data block is determined to be cold. When data migration is triggered based on the access heat of the page, hot data can be migrated to the near-end memory, and cold data can be migrated to the far-end memory.

[0111] Optionally, the present application does not limit the order of the steps in the above embodiment, and the order of the steps can be adjusted. For example, the memory medium determines the access heat of the page according to the access frequency of the interleaved data block, feeds back the access heat of the page to the processor, and the processor triggers data migration according to the fed-back access heat of the page. Alternatively, the memory medium feeds back the access frequency of the interleaved data block to the processor, and the processor determines the access heat of the page according to the access frequency of the page where the interleaved data block is located, and then triggers data migration according to the access heat of the page.

[0112] Due to the spatial dimension and time dimension indicated by the sampling strategy, the memory channel is sampled in multiple dimensions to ensure that the access frequency of the interleaved data block in the sampled memory channel is representative, and the access frequency of the page where the interleaved data block is located is determined based on the access frequency of the interleaved data block in the sampled memory channel, that is, the total access frequency of the page is determined based on the partial access frequency of the page, thereby improving the accuracy of the access frequency of the page where the interleaved data block is located, and reducing the statistical data amount of the page access frequency, so that the processor can obtain the page access frequency as quickly as possible. When triggering data migration based on the access heat of the page, hot data can be migrated to the near-end memory, and cold data can be migrated to the far-end memory, so that the processor can obtain frequently accessed data from the near-end memory as quickly as possible, thereby improving the data processing speed of the system, and reducing the data processing delay, and significantly improving the access performance of the system.

[0113] Figure 7 A flowchart of a memory access heat statistics method provided by the present application. The processor receives the configuration operation indicated by the user through the interface, configures the filtering mode in the sampling filtering module, that is, configures the sampling strategy (step 710). The processor enables the sampling filtering module, collects access requests and performs sampling operations (step 720). The counting module distributes to the corresponding counter according to the address sampled by the collection filtering module and performs counting operations. All count values ​​will be stored in RAM (step 730). After the sampling period, the processor issues a stop sampling instruction, stops counting, and all count values ​​are stored in RAM (step 740). The processor reads all count values ​​in RAM and stores them in the memory space (step 750). The processor determines whether all pages have completed the collection (step 760). If all pages have not been collected, step 710 is executed to continue the sampling operation. If all pages have been collected, the process ends. The specific sampling process can refer to the description of the above embodiment and will not be repeated.

[0114] Figure 8 A flowchart of a sampling strategy adjustment method provided for the present application. The processor determines whether the memory access performance is less than a threshold value (step 810). If the memory access performance is less than the threshold value, the sampling filter mode is changed (step 820), for example, the sampling strategy is changed from sampling the memory channel based on the spatial dimension to sampling the memory channel based on the time dimension; or, a rotation sampling method is used to sample multiple memory channels; if the memory access performance is greater than or equal to the threshold value, the sampling operation continues. Memory access performance includes the data processing speed and data processing delay when the processor accesses the memory. The method for sampling memory channels described in steps 830 to 860 can refer to the description of steps 720 to 750 above.

[0115] It is worth noting that for Figure 3(b) and Figure 3 For the memory access heat statistics scenario in the hardware module shown in (c) and the memory access heat statistics scenario in the processor, the data processing process is the same as Figure 3 The processing of (a) in is similar. Figure 3 The scenario (a) in Figure 1 is used as an example to illustrate the data processing process of other scenarios. Figure 3 The data processing process shown is similar and will not be repeated here.

[0116] It is understandable that, in order to implement the functions in the above-mentioned embodiments, the processor includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0117] Combined with the above Figures 1 to 8 , describes in detail the memory data migration method provided according to this embodiment, and will now be combined with Fig. 9 , describing the memory data migration device provided according to this embodiment.

[0118] Fig. 9 The following is a schematic diagram of the structure of a possible memory data migration device provided in this embodiment. These memory data migration devices can be used to implement the function of the memory medium in the above method embodiment, and thus can also achieve the beneficial effects possessed by the above method embodiment. In this embodiment, the memory data migration device can be as follows: Figure 4 The first memory medium shown may also be a module (such as a chip) applied to a processor.

[0119] like Fig. 9 As shown, the memory data migration device 900 includes a communication module 910, a sampling module 920, a statistics module 930, a migration module 940 and a storage module 950. The memory data migration device 900 is used to implement the above Figure 4 The functions of the memory and the processor are shown in the method embodiments.

[0120] The communication module 910 is used to obtain an access request, which is used to instruct the application program running on the processor of the computer device to operate the memory medium. Figure 4 Step 410.

[0121] The sampling module 920 is used to sample multiple memory channels in the computer device according to a sampling strategy, where the sampling strategy is used to indicate a sampling rule for the memory channels based on a spatial dimension and a temporal dimension. For example, the sampling module 920 is used to perform Figure 4 Step 420.

[0122] The statistical module 930 is used to determine the access frequency of the interleaved data block in the sampled memory channel. For example, the statistical module 930 is used to perform Figure 4 Step 420.

[0123] The statistical module 930 is further used to determine the access frequency of the page where the interleaved data block is located in the memory medium according to the access frequency of the interleaved data block, and the access frequency of the page where the interleaved data block is located is used to determine the access popularity of the page. Figure 4 Step 430.

[0124] The migration module 940 is used to trigger data migration between at least two different types of memory media according to access popularity. Figure 4 Step 440.

[0125] Optionally, the sampling module 920 is specifically configured to obtain a sampled memory channel by sampling from multiple memory channels according to the page identifiers indicated by the sampling strategy and the spatial distribution of the memory channels.

[0126] Optionally, the sampling module 920 is specifically configured to obtain a sampled memory channel by sampling from a plurality of memory channels according to a correspondence between a time period indicated by a sampling strategy and a storage space of a memory medium.

[0127] Optionally, the sampling module 920 is specifically configured to obtain a sampled memory channel by sampling from a plurality of memory channels according to a rotation sampling method indicated by the sampling strategy, wherein the rotation sampling method is used to indicate a change method of a correspondence between a page identifier and a memory channel.

[0128] Optionally, the sampling module 920 is specifically configured to obtain a sampled memory channel by sampling from a plurality of memory channels according to a rotation sampling method indicated by the sampling strategy, wherein the rotation sampling method is used to indicate a change manner of a correspondence between a time period and a storage space of a memory medium.

[0129] The storage module 950 is used to store sampling strategies and access frequencies, so that the sampling module 920 can sample multiple memory channels when the processor in the computer device accesses the memory medium in an interleaved manner.

[0130] It should be understood that the memory data migration device 900 of the embodiment of the present application can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), and the PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. It can also be implemented by software. Figure 4 The memory data migration shown and its various modules may also be software modules, and the memory data migration device 900 and its various modules may also be software modules.

[0131] The memory data migration device 900 according to the embodiment of the present application may correspond to executing the method described in the embodiment of the present application, and the above and other operations and / or functions of each unit in the memory data migration device 900 are respectively to implement Figure 4 For the sake of brevity, the corresponding processes of each method in are not repeated here.

[0132] The present application also provides a processor, which includes a memory and at least two processor cores. The processor is associated with at least two different types of memory media, and the memory is used to store a group of computer instructions. When the processor core executes the group of computer instructions, the operating steps of the methods described in the above embodiments are executed to identify the access frequency of data blocks in the memory medium by applications.

[0133] The present application also provides a chip, including: a processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; and the processor is used to execute the operation steps of the methods described in the above embodiments to realize the identification of the access frequency of a data block in a memory accessed by an application program.

[0134] The present application also provides a computer system, which includes multiple computer devices, and the computer devices are used to execute the operating steps of the methods described in the above embodiments.

[0135] The method steps in this embodiment can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a computer device. Of course, the processor and the storage medium can also exist in a computer device as discrete components.

[0136] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc (DVD); it may also be a semiconductor medium, for example, a solid state drive (SSD). The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for migrating cold and hot data, characterized in that: The method is executed by a processor, the processor accesses a first memory medium and a second memory medium in an interleaved manner, the access speed of the first memory medium is higher than that of the second memory medium, and the method includes: Sending a first access request to the first memory medium, where the first access request is used to access a first storage space, where the first storage space is located in the first memory medium, and where a size of the first storage space is the same as a size of a cache line; Acquire a first access frequency to the first storage space, where the first access frequency is used to indicate that data stored in the first storage space is cold data; Migrating data in the first storage space to the second memory medium; When the data stored in the second storage space is hot data, the data in the second storage space is migrated to the first memory medium, wherein the second storage space is located in the second memory medium, and the size of the second storage space is the same as the size of a cache line.

2. The method according to claim 1, characterized in that The first access frequency is counted by a memory controller in the processor.

3. The method according to claim 1 or 2, characterized in that: The first memory medium and the second memory medium are located external to the processor.

4. The method according to claim 1, characterized in that: The first memory medium is a dynamic random access memory DRAM.

5. The method according to claim 1, characterized in that: The second memory medium is storage-class memory SCM.

6. The method according to claim 1, characterized in that When the data stored in the second storage space is hot data, migrating the data in the second storage space to the first memory medium includes: Sending a second access request to the second storage medium, where the second access request is used to access the second storage space; Acquire a second access frequency to the second storage space, where the second access frequency is used to indicate that data stored in the second storage space is hot data; Migrate the data in the second storage space to the first memory medium.

7. A processor, characterized in that: The processor accesses a first memory medium and a second memory medium in an interleaved manner, the access speed of the first memory medium is higher than that of the second memory medium, and the processor is used to: Sending a first access request to the first memory medium, where the first access request is used to access a first storage space, where the first storage space is located in the first memory medium, and where a size of the first storage space is the same as a size of a cache line; Acquire a first access frequency to the first storage space, where the first access frequency is used to indicate that data stored in the first storage space is cold data; Migrating data in the first storage space to the second memory medium; The processor is further configured to: When the data stored in the second storage space is hot data, the data in the second storage space is migrated to the first memory medium, wherein the second storage space is located in the second memory medium, and the size of the second storage space is the same as the size of a cache line.

8. The processor according to claim 7, characterized in that The processor also includes a memory controller, and the memory controller is used to count the access frequency of the first storage space.

9. The processor according to claim 7 or 8, characterized in that: The first memory medium and the second memory medium are located external to the processor.

10. The processor according to claim 7, characterized in that The first memory medium is a dynamic random access memory DRAM.

11. The processor according to claim 7, characterized in that The second memory medium is storage-class memory SCM.

12. The processor according to claim 7, characterized in that When the data stored in the second storage space is hot data, migrating the data in the second storage space to the first memory medium includes: Sending a second access request to the second storage medium, where the second access request is used to access the second storage space; Acquire a second access frequency to the second storage space, where the second access frequency is used to indicate that data stored in the second storage space is hot data; Migrate the data in the second storage space to the first memory medium.

13. A computer device, characterized in that: The computer device is a processor as described in any one of claims 7-12, so as to perform cold-hot data migration between a first memory medium and a second memory medium.

14. A computer system, characterized in that: The computer device includes a first memory medium, a second memory medium, and a processor according to any one of claims 7 to 12 to perform cold and hot data migration between the first memory medium and the second memory medium.

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