A method, system, device and storage medium for remote updating of an FPGA device

Abstract

The application discloses a FPGA device remote updating method, system, device and storage medium, which is used for simplifying the updating process of the FPGA device and reducing the updating and maintenance cost. The method comprises the following steps: a test instrument receives an updating file and an updating instruction issued by an upper computer through a network port; an ARM processor of the test instrument analyzes the updating file according to the updating instruction and encapsulates the analysis result into message information in a preset format; the ARM processor sends the message information to an FPGA of the test instrument through a serial communication interface; the FPGA analyzes the received message information and generates a Flash standard instruction, and performs a read-write operation on a Flash memory through the Flash standard instruction to update the code of the FPGA.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded technology, in particular to a FPGA device remote updating method, system, device and storage medium. BACKGROUND

[0002] In electronic instrument equipment, FPGA (Field Programmable Gate Array) devices are widely used in display panel testing industry due to their high flexibility and customizability. The excellent scalability of FPGA devices can support various video interface standards such as VGA, DVI, HDMI, etc., and can be customized and expanded as needed, so that designers can quickly respond to market demand and develop display solutions that meet specific application requirements.

[0003] Currently, electronic instruments using FPGA on the market do not frequently update FPGA code due to their single function. However, in the display panel testing industry, measurement instruments are non-standard customized products, and there are hundreds of display products to be tested. In order to adapt the test instrument to different display products to be tested, it is necessary to frequently update the FPGA code.

[0004] In the prior art, FPGA code is usually updated by a burner and specified burning software, or updated through a specified hardware interface of the device, such as spi, iic, etc. However, in actual use environment, the test instrument is installed together with the automation equipment. Each time the update needs to be disassembled and reconnected with the hardware, the whole updating process is very inconvenient and time-consuming. Especially in aging or OTP equipment, the number of test instrument clusters is large, which greatly increases the workload of FPGA code updating, resulting in low updating efficiency. SUMMARY

[0005] The present application provides a FPGA device remote updating method, system, device and storage medium, which is used to simplify the updating process of FPGA device and reduce the updating and maintenance cost.

[0006] The first aspect of the present application provides a FPGA device remote updating method, comprising:

[0007] The test instrument receives the update file and update instruction issued by the host computer through the network port;

[0008] The ARM processor of the test instrument parses the update file according to the update instruction and encapsulates the parsing result into packet information according to a preset format;

[0009] The ARM processor sends the packet information to the FPGA of the test instrument through a serial communication interface;

[0010] The FPGA parses the received message information and generates a Flash standard instruction, and performs read-write operation on the Flash memory through the Flash standard instruction to update the code of the FPGA.

[0011] Optionally, the ARM processor of the test instrument parses the update file according to the update instruction and encapsulates the parsing result into message information in a preset format, including:

[0012] The ARM processor of the test instrument unpacks the update file according to the update instruction to obtain a plurality of data blocks according to a preset Page size.

[0013] The ARM processor encapsulates the control instruction and the data block into message information, and the control instruction includes an address configuration instruction, a data write operation cache instruction and a trigger instruction.

[0014] Optionally, the FPGA parses the received message information to obtain a Flash standard instruction, and performs read-write operation on the Flash memory through the Flash standard instruction, including:

[0015] The FPGA parses the received message information to obtain the write address of the Flash memory and the data block.

[0016] The FPGA generates a Flash standard instruction according to the write address of the Flash memory and the data block, and triggers the write operation of the Flash memory through the trigger instruction, and the write operation is used to write the data block into a target address.

[0017] Optionally, after the FPGA writes the data block into the target address, the method further includes:

[0018] The FPGA fills the address configuration instruction according to the target address, and triggers the read operation of the Flash memory through the trigger instruction.

[0019] The FPGA compares the read data returned by the read operation with the write data to determine whether the read-write data is consistent.

[0020] If yes, the write operation of the next data block is performed.

[0021] If no, the update is interrupted and error information is returned to the host computer.

[0022] Optionally, the method further includes:

[0023] The test instrument returns an updating progress to the host computer in real time, so that the host computer displays the updating progress through a progress bar of a UI interface.

[0024] Optionally, the updating progress is a percentage of a current updated data size to a data size of the entire updating file.

[0025] Optionally, the Flash memory adopts a QSPI interface.

[0026] The second aspect of the application provides a system for remote updating of an FPGA device, comprising a host computer, an instruction processing unit and a Flash memory unit, wherein the instruction processing unit and the Flash memory unit are arranged on a test instrument, the instruction processing unit comprises an ARM processing module and an FPGA processing module.

[0027] The host computer is configured to issue an updating file and an updating instruction to the instruction processing unit through a network port.

[0028] The ARM processing module is configured to parse the updating file according to the updating instruction and encapsulate a parsing result into a message information in a preset format by pages; and send the message information to the FPGA processing module through a serial communication interface.

[0029] The FPGA processing module is configured to parse the received message information and generate a Flash standard instruction, and perform a read-write operation on the Flash memory unit through the Flash standard instruction to update a code of the FPGA.

[0030] Optionally, the ARM processing module is further configured to:

[0031] According to the updating instruction, the updating file is unpacked to obtain a plurality of data blocks according to a preset Page size.

[0032] The ARM processor encapsulates a control instruction and the data blocks into the message information, wherein the control instruction comprises an address configuration instruction, a data write operation cache instruction and a trigger instruction.

[0033] Optionally, the FPGA processing module is further configured to:

[0034] The FPGA processing module is configured to parse the received message information and generate a Flash standard instruction, and perform a read-write operation on the Flash memory unit through the Flash standard instruction to update a code of the FPGA.

[0035] According to the Flash memory unit's write address and the data blocks, a Flash standard instruction is generated, and a write operation of the Flash memory unit is triggered through the trigger instruction, wherein the write operation is configured to write the data blocks into a target address.

[0036] Optionally, the FPGA processing module is further configured to:

[0037] fill the address configuration instruction according to the target address, and trigger a read operation of the Flash storage unit through the trigger instruction;

[0038] compare the read data returned by the read operation with the write data to determine whether the read and write data are consistent;

[0039] if yes, perform a write operation of a next data block;

[0040] if no, interrupt the updating and return error information to the upper computer.

[0041] Optionally, the instruction processing unit is configured to return an updating progress to the upper computer in real time, so that the upper computer displays the updating progress through a progress bar of a UI interface.

[0042] Optionally, the updating progress is a percentage of a size of currently updated data to a size of the entire updating file.

[0043] Optionally, the Flash storage unit adopts a QSPI interface.

[0044] The third aspect of the present application provides a device for remote updating of an FPGA device, and the device comprises:

[0045] a processor, a memory, an input / output unit and a bus;

[0046] the processor is connected with the memory, the input / output unit and the bus;

[0047] the memory stores a program, and the processor invokes the program to execute the method for remote updating of the FPGA device according to the first aspect and any optional method according to the first aspect.

[0048] The fourth aspect of the present application provides a computer readable storage medium, and the computer readable storage medium stores a program, and the program is executed on a computer to execute the method for remote updating of the FPGA device according to the first aspect and any optional method according to the first aspect.

[0049] As can be seen from the above technical solutions, the present application has the following advantages:

[0050] The test instrument remotely receives the update file and the update instruction through a network port, the ARM processor of the test instrument automatically parses the update file and encapsulates the update file into a message, the FPGA automatically executes the update after receiving the message, the whole update process does not need complex manual intervention, the operation difficulty is reduced, and the FPGA of multiple test instruments can be remotely updated at the same time through a local area network, so that the human and time costs required for updating are significantly reduced. Moreover, the updating method provided in the application does not need to use a special burning device and software, and does not depend on a specific FPGA device platform, and the FPGA can be updated by using a general serial interface, so that the additional hardware and software costs are reduced, and the updating method has good compatibility and scalability. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0052] Figure 1 An embodiment flowchart of the FPGA device remote updating method provided in the application is shown in the figure.

[0053] Figure 2 An embodiment hardware connection diagram of the FPGA device remote updating method provided in the application is shown in the figure.

[0054] Figure 3 Another embodiment flowchart of the FPGA device remote updating method provided in the application is shown in the figure.

[0055] Figure 4 An embodiment structure diagram of the FPGA device remote updating system provided in the application is shown in the figure.

[0056] Figure 5 A function block diagram of the FPGA device remote updating system provided in the application is shown in the figure.

[0057] Figure 6 An embodiment structure diagram of the FPGA device remote updating device provided in the application is shown in the figure. DETAILED DESCRIPTION

[0058] The application provides a FPGA device remote updating method, system, device and storage medium, which is used for simplifying the updating process of the FPGA device and reducing the updating and maintenance cost.

[0059] Please refer to Figure 1 , Figure 1 An embodiment of the FPGA device remote updating method provided in the application comprises:

[0060] 101、The test instrument receives the update file and update instruction issued by the host computer through the network port;

[0061] In this embodiment, the host computer serves as the control and execution unit of the update process, receives instructions from the UI software, and communicates with the test instrument (lower computer) to complete the transmission of the update file, the issuance of instructions, and other operations. The UI software, i.e., the user interface software, is a part running on the host computer. The UI software can provide a graphical user interface to help users intuitively operate and control the entire update process.

[0062] Specifically, the host computer can simultaneously communicate with multiple test instruments through the network port. The network port provides a high-speed and reliable data transmission channel, supporting the host computer to send update files to the test instruments in batches. The host computer first initiates a connection request and transmits the update file to the test instrument through the FTP protocol. After the file transmission is completed, the host computer will also send an update instruction to notify the test instrument to start processing the update file. After receiving the FTP file transmission request from the host computer, the test instrument will receive and store the update file in the specified storage area. After receiving the update file, the test instrument will start the update process upon receiving the update instruction and begin to execute the subsequent update steps.

[0063] 102、The ARM processor of the test instrument parses the update file according to the update instruction and encapsulates the parsing result into message information in pages according to a preset format;

[0064] After receiving the update instruction from the host computer, the ARM processor of the test instrument will trigger the update process. The ARM processor parses the received update file according to the preset format agreed in advance. The purpose of parsing is to extract the valid data in the update file, i.e., the data to be written into the FPGA, to ensure that the file can be correctly divided and encapsulated into message suitable for transmission. The update file is usually large, so the ARM processor will perform page processing according to the preset page size (Page size) to split the update file into multiple data blocks, and each data block will represent a part of the update file. Thereafter, the ARM processor encapsulates each data block into message information according to the requirements of the communication protocol, and the message information contains the content of the data block, address information, and control instructions, etc. Each message information represents a part of the update file, and the FPGA will write the data into the Flash memory according to the content in the message information after receiving these messages.

[0065] 103、The ARM processor sends the message information to the FPGA of the test instrument through the serial communication interface;

[0066] In embedded systems, ARM processors typically work in conjunction with FPGAs to achieve efficient data processing and control. During the remote update process of the FPGA device in this embodiment, the ARM processor is primarily responsible for receiving update commands, parsing update files, and generating corresponding message information, while the FPGA is responsible for updating its own firmware or configuration based on this message information. Therefore, the ARM processor needs to send the encapsulated message to the FPGA via a serial communication interface.

[0067] It should be noted that the ARM processor can ensure the successful transmission of each message through an acknowledgment mechanism during the transmission process. If an error occurs, it will retransmit or terminate the update process.

[0068] 104. The FPGA parses the received message information and generates Flash standard instructions. It then uses these instructions to read and write to the Flash memory to update the FPGA's code.

[0069] FPGAs store firmware code via external Flash memory, allowing them to read and configure the code from Flash after power-on. When the FPGA receives a message from the ARM processor, it first parses the message and generates corresponding Flash standard instructions based on the parsing results. These Flash standard instructions conform to the standard Flash memory protocol, including write, erase, and read instructions. The FPGA then translates the custom instructions from the ARM processor into standard Flash operation instructions. The FPGA then communicates with the Flash memory to execute the specific read and write operations, writing the update file to the designated location in the Flash memory, thereby updating the FPGA code.

[0070] In some specific embodiments, the FPGA connects to the Flash memory via a QSPI interface. Compared to traditional SPI, QSPI uses four data lines for parallel transmission, significantly improving data write and read speeds. Please refer to [link to relevant documentation]. Figure 2 , Figure 2A schematic diagram of hardware connection between the host computer, ARM processor (embedded system), FPGA and flash memory, wherein the host computer communicates with the ARM processor through the network, and data transmission is performed between the two through Ethernet or other network protocols. The ARM processor is connected with the FPGA through a custom interface, which can be designed according to specific communication requirements. The custom interface allows the ARM processor to send instructions and data to the FPGA. The FPGA is connected with the flash memory through a QSPI interface. QSPI is a high-speed serial communication interface that allows the FPGA to communicate with the flash memory at a high data transfer rate, thereby achieving fast read and write operations and improving update efficiency.

[0071] In this embodiment, the test instrument remotely receives the update file and the update instruction through the network port, the ARM processor of the test instrument automatically parses the update file and encapsulates it into a message, and the FPGA automatically executes the update after receiving the message. The entire update process does not require complex manual intervention, reduces the operation difficulty, and supports simultaneous remote update of multiple test instrument FPGAs through the local area network, significantly reducing the manpower and time cost required for updating. Moreover, the update method of the present application does not require the use of dedicated burning equipment and software, nor does it depend on a specific FPGA device platform. The update of the FPGA can be realized using a general serial interface, reducing the additional hardware and software costs, and having good compatibility and scalability.

[0072] The FPGA device remote update method provided by the present application will be described in detail below. Please refer to Figure 3 , Figure 3 Another embodiment of the FPGA device remote update method provided by the present application is provided, which comprises:

[0073] 301. The test instrument receives the update file and the update instruction issued by the host computer through the network port;

[0074] In this embodiment, step 301 is similar to step 101 of the foregoing embodiment, which will not be described here.

[0075] 302. The ARM processor of the test instrument unpacks the update file according to the update instruction and according to the preset Page size to obtain a plurality of data blocks;

[0076] In order to effectively write the update file into the Flash memory, the data must be unpacked and transmitted in batches according to the appropriate size. In the embodiment, the ARM processor needs to unpack the update file received from the host computer according to the preset Page size to obtain a plurality of data blocks. Each unpacked data block is called a Page, and each Page contains a part of data that needs to be written into the Flash memory. The ARM processor sends the data blocks to the FPGA for processing page by page.

[0077] In some specific embodiments, for example, the size of the update file is fixed at 64 MB, and the preset Page size is fixed at 256 bytes. According to these parameters, the ARM processor splits the 64 MB update file into a plurality of 256 byte data blocks, i.e. a total of 262,144 Pages. The corresponding ARM processor needs to initiate 262,144 write operations, each time writing a Page of data to the specified address of the Flash memory.

[0078] 303, the ARM processor encapsulates the control instructions and the data block into a message information, the control instructions including address configuration instructions, data write operation cache instructions and trigger instructions;

[0079] When performing the Flash memory write operation, the ARM processor not only needs to split the data block, but also needs to configure the address and cache the data according to the operation protocol of the Flash memory. In order to ensure the correctness and efficiency of the data, the ARM processor will use a series of basic control instructions, such as address configuration instructions, trigger instructions, and data write operation cache instructions. These instructions can ensure the accurate address positioning and data caching of each write operation, so as to realize the correct writing of the update file in the Flash. The ARM processor encapsulates the control instructions and the actual data block into a message, which is transmitted to the FPGA through the serial interface. Each message will contain complete address and data information, ensuring that the FPGA can correctly parse and execute the Flash write operation. The encapsulation and transmission of the message simplify the communication process between the ARM processor and the FPGA, and improve the overall update efficiency.

[0080] Specifically, the basic commands are as shown in the following table:

[0081]

[0082] In this embodiment, the ARM processor uses an address configuration instruction (0x20) to set the write address of the Flash memory. The address configuration instruction requires four parameters: Addr0, Addr1, Addr2, and Addr3, which represent specific address bits in the Flash memory. These address parameters allow the ARM processor to precisely locate the storage position of each data block in the Flash memory. Through this address configuration method, the ARM processor can ensure that each write operation begins at the correct address, avoiding data write misalignment.

[0083] To improve write efficiency, the ARM processor pre-caches the data block to be written before performing the actual write operation. That is, the data block is cached in the specified cache area through the data write operation cache instruction (0x58) and waits for the final write trigger.

[0084] Furthermore, after the data buffering is complete, the ARM processor uses a trigger instruction (0x63) to initiate a write operation to the Flash memory by the FPGA. The trigger instruction tells the FPGA to perform the actual write operation and returns status information upon completion. The parameter of the trigger instruction is 1 or 0: passing 1 initiates the write operation; passing 0 completes the operation.

[0085] The ARM processor combines each data block with its associated control instructions and encapsulates them into a unified message. This message is transmitted to the FPGA via a serial interface, where the FPGA executes the write operation to Flash based on the message content. By encapsulating control instructions and data blocks, the ARM processor simplifies communication and control processes, ensuring that each operation is executed smoothly on the FPGA.

[0086] 304. The ARM processor sends the message information to the FPGA of the test instrument through the serial communication interface;

[0087] In this embodiment, step 304 is similar to step 103 in the previous embodiment, and will not be described again here.

[0088] 305. The FPGA parses the received message information to obtain the write address and data block of the Flash memory;

[0089] The FPGA parses the received message information, extracting control instructions and data blocks. These control instructions contain specific opcodes and parameters used to control the interaction between the FPGA and the Flash memory. The Flash memory typically supports a set of standard instructions used to perform basic operations such as reading, writing, and erasing data. These standard instructions are commands that the Flash memory can understand and execute.

[0090] In the embodiment, the FPGA parses the received message information, and the write address of the Flash memory can be obtained through the address configuration instruction carried in the message information, and the data block is pre-cached through the data write operation cache instruction carried in the message information.

[0091] 306、The FPGA generates a Flash standard instruction according to the write address of the Flash memory and the data block, and triggers the write operation of the Flash memory through the trigger instruction, and the write operation is used for writing the data block to the target address.

[0092] The FPGA parses the received message information, and extracts the write address and the data block. The write address specifies the position in the Flash memory where the data should be written, and the data block contains the actual data to be written. The write address and the data block can be used to generate a corresponding Flash standard instruction to control the Flash memory to write the data block to the target address. In actual application, the FPGA can directly convert the control instruction into a Flash standard instruction according to a predefined mapping rule according to the parsed control instruction.

[0093] The message information also contains a trigger instruction, and the FPGA starts the write operation of the Flash memory through the trigger instruction. Under the action of the trigger instruction, the Flash memory starts to execute the write operation, and the FPGA writes the data in the data block to the target address.

[0094] 307、The FPGA fills the address configuration instruction according to the target address, and triggers the read operation of the Flash memory through the trigger instruction;

[0095] After the write operation is completed, checking and verification are still needed to ensure that the updated data is correctly written into the Flash memory, so as to ensure the accuracy and reliability of the FPGA remote update. Specifically, the FPGA fills the address configuration instruction (0x20) according to the target address, and then the FPGA starts the read operation of the Flash memory through the trigger instruction (0x63).

[0096] 308、The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent;

[0097] The FPGA reads the read data returned from the target address from the Flash memory, and compares the read data with the original write data block to determine whether the read and write data are consistent. If the read and write data are consistent, step 309 is executed to continue the update. If the read and write data are inconsistent, the FPGA will execute step 310 to interrupt the update process.

[0098] 309、Write operation of the next data block;

[0099] If it is determined that the read and write data are consistent, the FPGA will continue to perform the updating process, process the write operation of the next data block according to the message information, and continue the subsequent updating process.

[0100] 310, interrupt the updating and return error information to the host computer;

[0101] If the read data is inconsistent with the write data, the FPGA will interrupt the updating process to prevent the use of incorrect data for subsequent operations, ensuring the stability and reliability of the system. In addition, the FPGA also needs to return error information to the host computer to trigger error handling processes such as retrying the update, recording error logs, or notifying maintenance personnel, which are not limited here.

[0102] 311, the test instrument returns the updating progress to the host computer in real time to enable the host computer to display the updating progress through the progress bar of the UI interface.

[0103] During the entire remote updating process, each test instrument can return the updating progress to the host computer in real time, and the updating progress can be intuitively displayed through the progress bar of the UI interface of the host computer, enhancing user experience and making the updating process more transparent and controllable. Specifically, the updating progress can be the percentage of the size of the data that has been updated to the size of the entire updating file, that is, the test instrument calculates the size of the data that has been updated by tracking the amount of data that has been written to the Flash memory during the updating process, and then calculates the progress percentage, thereby achieving synchronization with the actual updating progress.

[0104] In this embodiment, the ARM processor encapsulates the control instructions and data blocks into message information, and the FPGA parses the received message information to extract the control instructions and data blocks, and then parses and converts the control instructions into standard instructions of the Flash memory, and uses the standard instruction set for operation, finally realizing the read and write operations of the ARM processor on the Flash memory device. By mapping the control instructions to the standard instructions of the Flash memory, the FPGA improves the compatibility between different devices and memories, reduces the dependence on specific hardware, reduces development and maintenance costs, and enables the method to be more widely applied to various combinations of FPGAs and Flash memories.

[0105] The FPGA device remote updating system provided by the present application will be described in detail below. Please refer to Figure 4 , Figure 4 Another embodiment of the FPGA device remote updating system provided by the present application is provided, and the system comprises:

[0106] The host computer 401, the instruction processing unit 402 and the Flash storage unit 403 are arranged on the test instrument, the instruction processing unit 402 comprises an ARM processing module 4021 and an FPGA processing module 4022;

[0107] The host computer 401 is configured to issue an update file and an update instruction to the instruction processing unit 402 through a network port;

[0108] The ARM processing module 4021 is configured to parse the update file according to the update instruction and encapsulate the parsed result into message information in a preset format, and send the message information to the FPGA processing module 4022 through a serial communication interface;

[0109] The FPGA processing module 4022 is configured to parse the received message information and generate a Flash standard instruction, and perform read-write operation on the Flash storage unit 403 through the Flash standard instruction to update the code of the FPGA.

[0110] Optionally, the ARM processing module 4021 is specifically configured to:

[0111] According to the update instruction, the update file is unpacked to obtain a plurality of data blocks according to a preset Page size;

[0112] The ARM processor encapsulates the control instruction and the data block into the message information, and the control instruction comprises an address configuration instruction, a data write operation cache instruction and a trigger instruction.

[0113] Optionally, the FPGA processing module 4022 is specifically configured to:

[0114] The received message information is parsed to obtain a write address and a data block of the Flash storage unit 403;

[0115] The Flash standard instruction is generated according to the write address and the data block of the Flash storage unit 403, and the write operation of the Flash storage unit 403 is triggered through the trigger instruction, and the write operation is configured to write the data block into the target address.

[0116] Optionally, the FPGA processing module 4022 is further configured to:

[0117] The address configuration instruction is filled according to the target address, and the read operation of the Flash storage unit 403 is triggered through the trigger instruction;

[0118] The read data returned by the read operation is compared with the write data to determine whether the read and write data are consistent;

[0119] If yes, the write operation of the next data block is performed;

[0120] If no, interrupt the update and return error information to the host computer 401.

[0121] Optionally, the instruction processing unit 402 is configured to return the update progress to the host computer 401 in real time, so that the host computer 401 displays the update progress through a progress bar of a UI interface.

[0122] Optionally, the update progress is a percentage of a data size of the currently updated data to a data size of the entire update file.

[0123] Optionally, the Flash storage unit 403 adopts a QSPI interface.

[0124] In the system of the embodiment, the functions of the units and modules correspond to the steps in the method embodiments shown in the foregoing Figure 1 or Figure 3 The description will not be repeated here. Figure 5 The function block diagram of the host computer 401, the instruction processing unit 402 and the Flash storage unit 403 in the system for remote update of an FPGA device provided in the application.

[0125] The entire update process will be described below in combination with the host computer 401, the instruction processing unit 402 and the Flash storage unit 403:

[0126] The host computer 401 issues an update file and sends an update instruction, and in addition, the host computer 401 can further check and determine whether the update file is reasonable, and if not, the UI software prompts an error and interrupts the update;

[0127] The instruction processing unit 402 splits the update file, fills a Page data to a 0x58 instruction, fills a write address to a 0x20 instruction, and fills a trigger 1 to a 0x63 instruction;

[0128] The Flash storage unit 403 parses the write instruction and writes the data to the corresponding address;

[0129] The instruction processing unit 402 fills a read address to a 0x20 instruction, and by default, reads a Page length at a time; fills a trigger 1 to a 0x63 instruction;

[0130] The Flash storage unit 403 parses the read instruction and returns the data of the corresponding address to the FPGA cache;

[0131] The instruction processing unit 402 compares whether the read data and the write data are consistent, and if so, fills the next Page data; if not, interrupts the update and prompts an error information.

[0132] The application further provides a device for remote update of an FPGA device, which will be described below with reference to Figure 6 , Figure 6An embodiment of the device for FPGA device remote update provided in the application comprises:

[0133] The processor 601, the memory 602, the input output unit 603 and the bus 604;

[0134] The processor 601 is connected with the memory 602, the input output unit 603 and the bus 604;

[0135] The memory 602 stores a program, and the processor 601 invokes the program to execute any of the above FPGA device remote update methods.

[0136] The application also relates to a computer readable storage medium, which stores a program, and when the program runs on a computer, the computer executes any of the above FPGA device remote update methods.

[0137] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0138] In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of units is only a logical function division, and actual implementation can have another division mode, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0139] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment scheme.

[0140] In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0141] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or in other words, the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the various embodiments of the method of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a magnetic disk or an optical disk, and various media that can store program codes.

Claims

1. A method for remote updating of an FPGA device, characterized in that, The method comprises: The test instrument receives the update file and the update instruction issued in batches by the host computer through a network port; The ARM processor of the test instrument unpacks the update file according to the update instruction and according to a preset Page size to obtain a plurality of data blocks; The ARM processor encapsulates control instructions and the data blocks into message information, the control instructions being used for controlling the interaction between the FPGA and the Flash memory, the control instructions comprising address configuration instructions, data write operation cache instructions and trigger instructions, the address configuration instructions being used for setting the write address of the Flash memory, the data write operation cache instructions being used for pre-caching the data blocks to be written, and the trigger instructions comprising a write 1 signal used for starting an operation and a write 0 signal used for completing an operation; The ARM processor sends the message information to the FPGA of the test instrument through a self-defined serial communication interface; The FPGA analyzes the received message information to obtain the write address of the Flash memory and the data blocks; The FPGA generates Flash standard instructions according to the write address of the Flash memory and the data blocks, and starts the write operation of the Flash memory through the write 1 signal in the trigger instructions, the write operation being used for writing the data blocks into a target address to update the code of the FPGA; The FPGA fills the address configuration instructions according to the target address, and starts the read operation of the Flash memory through the trigger instructions; The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent; If yes, the write operation of the next data block is performed; If no, the update is interrupted, and error information is returned to the host computer.

2. The method of claim 1, wherein, The method further comprises: The test instrument returns the update progress to the host computer in real time, so that the host computer displays the update progress through a progress bar of a UI interface.

3. The method of claim 2, wherein, The update progress is the percentage of the size of the currently updated data to the size of the entire update file.

4. The method according to any one of claims 1 to 3, characterized in that, The Flash memory adopts a QSPI interface.

5. A system for remote updating of FPGA devices, characterized in that, The system comprises a host computer, an instruction processing unit and a Flash storage unit, the instruction processing unit and the Flash storage unit being arranged on a test instrument, the instruction processing unit comprising an ARM processing module and an FPGA processing module; The host computer is used for issuing an update file and an update instruction in batches to the instruction processing unit through a network port; The ARM processing module is configured to unpack the update file according to the update instruction to obtain a plurality of data blocks according to a preset Page size; encapsulate control instructions and the data blocks into message information, the control instructions being used for controlling interaction between the FPGA and the Flash memory, the control instructions including address configuration instructions, data write operation cache instructions and trigger instructions, the address configuration instructions being used for setting a write address of the Flash memory, the data write operation cache instructions being used for pre-caching data blocks to be written, and the trigger instructions including a write 1 signal used for starting an operation and a write 0 signal used for completing the operation; and send the message information to the FPGA of the test instrument through a self-defined serial communication interface. The FPGA processing module is configured to parse the received message information to obtain the write address of the Flash memory and the data blocks; generate a Flash standard instruction according to the write address of the Flash memory and the data blocks, and start a write operation of the Flash memory through the write 1 signal in the trigger instructions, the write operation being used for writing the data blocks into a target address to update the code of the FPGA; fill the address configuration instructions according to the target address, and start a read operation of the Flash memory through the trigger instructions; compare read data returned by the read operation with write data to determine whether the read data and the write data are consistent; if yes, perform a write operation of a next data block; and if no, interrupt the update and return error information to the host computer.

6. An apparatus for remote updating of an FPGA device, the apparatus comprising: The device comprises: a processor, a memory, an input / output unit and a bus; the processor is connected with the memory, the input / output unit and the bus; the memory stores a program, and the processor invokes the program to execute the method in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a program, and the program executes the method in any one of claims 1 to 4 when executed on a computer.

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