Instruction operation method, instruction operation device, electronic device, and storage medium

Abstract

An instruction operation method, an instruction operation device, an electronic device, and a storage medium. The instruction operation method includes receiving a plurality of operation instructions, wherein each of the plurality of operation instructions includes an instruction part; in response to at least one object operation instruction of the plurality of operation instructions further including a constant operand, performing compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and storing the plurality of operation instructions according to the at least one compressed constant operand. The instruction operation method can reduce wasted instruction storage space through compression processing of the constant operand.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to an instruction operation method, an instruction operation apparatus, an electronic device, and a storage medium. BACKGROUND

[0002] With the advent of the era of big data and artificial intelligence, the processing performance requirements of computer systems are becoming higher and higher. In order to improve the processing performance of the processor, the processor front end needs to provide more instructions to the processor for execution faster. SUMMARY

[0003] At least one embodiment of the present disclosure provides an instruction operation method, which comprises: receiving a plurality of operation instructions, wherein each of the plurality of operation instructions comprises an instruction part; in response to at least one object operation instruction in the plurality of operation instructions further comprising a constant operand, performing compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and storing the plurality of operation instructions according to the at least one compressed constant operand.

[0004] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the plurality of operation instructions are microinstructions; and the storing of the plurality of operation instructions according to the at least one compressed constant operand comprises storing the plurality of operation instructions in a microinstruction cache.

[0005] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the storing of the plurality of operation instructions according to the at least one compressed constant operand further comprises merging the plurality of operation instructions into one logical storage item for arrangement.

[0006] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the logical storage item is established according to a preset constraint rule, and the preset constraint rule is used to determine the arrangement mode of the plurality of operation instructions in the logical storage item respectively.

[0007] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the merging of the plurality of operation instructions into one logical storage item for arrangement comprises storing the logical storage item in a corresponding physical cache item in the microinstruction cache.

[0008] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the at least one object operation instruction comprises a plurality of object operation instructions; and the logical storage item comprises a plurality of instruction domains and a plurality of constant storage domains, the plurality of instruction domains respectively arranging the instruction parts of the plurality of object operation instructions, and the plurality of constant storage domains respectively arranging the compressed constant operands of the plurality of object operation instructions.

[0009] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the storing the plurality of operation instructions according to the at least one compressed constant operand comprises: determining an arrangement form of the plurality of compressed constant operands in the constant storage domain according to a data size of the compressed constant operands of the plurality of object operation instructions, and according to an arrangement capacity of each of the plurality of constant storage domains.

[0010] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the arrangement form of the plurality of compressed constant operands in the constant storage domain comprises: arranging the plurality of compressed constant operands in a same object constant storage domain in the plurality of constant storage domains.

[0011] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the storing the plurality of operation instructions according to the at least one compressed constant operand comprises: determining an arrangement order of the plurality of compressed constant operands in the object constant storage domain according to an instruction order of the plurality of object operation instructions.

[0012] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the constant operand comprises an immediate number and / or a shift number.

[0013] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the compressing the constant operand of the at least one object operation instruction comprises: removing a sign extension bit of the constant operand to compress the constant operand.

[0014] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the receiving the plurality of operation instructions comprises: receiving the plurality of operation instructions from a decoding unit.

[0015] Some embodiments of the present disclosure further provide an instruction operation apparatus, which comprises a receiving module, a compressing module and a storing module; the receiving module is configured to receive a plurality of operation instructions, wherein each of the plurality of operation instructions comprises an instruction part; the compressing module is configured to, in response to at least one object operation instruction in the plurality of operation instructions further comprising a constant operand, compress the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and the storing module is configured to store the plurality of operation instructions according to the at least one compressed constant operand.

[0016] Some embodiments of the present disclosure further provide an instruction operation apparatus, which comprises at least one storage unit and at least one processing unit; the at least one storage unit stores computer executable instructions; and the at least one processing unit is configured to execute the computer executable instructions, and the computer executable instructions, when executed by the at least one processing unit, implement the instruction operation method provided by any of the embodiments of the present disclosure.

[0017] The electronic device includes a decoding unit and a microinstruction cache configured to: receive a plurality of operation instructions from the decoding unit, wherein each of the plurality of operation instructions includes an instruction part; in response to at least one object operation instruction of the plurality of operation instructions further including a constant operand, perform compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and store the plurality of operation instructions according to the at least one compressed constant operand.

[0018] The non-transitory storage medium non-transitively stores computer executable instructions, and when the computer executable instructions are executed by at least one processor, implement the instruction operation method provided by any one of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only related to some of the embodiments of the present disclosure, but not limited to the present disclosure.

[0020] Figure 1 A basic structure division schematic diagram of a processor is shown;

[0021] Figure 2A A scene schematic diagram of the processor fetching an instruction is shown;

[0022] Figure 2B A flowchart of an instruction operation method provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 3 A structure schematic diagram of a logical storage item and a physical cache item provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 4 An assembler corresponding to an operation instruction provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 5 An arrangement schematic diagram of an operation instruction in a logical item is shown;

[0026] Figure 6 An arrangement schematic diagram of an operation instruction in a logical storage item provided by at least one embodiment of the present disclosure is shown;

[0027] Figure 7 A block schematic diagram of an instruction operation device provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 8FIG. 1 shows a block schematic diagram of another instruction operation apparatus provided by at least one embodiment of the present disclosure;

[0029] Figure 9 FIG. 1 shows a block schematic diagram of another instruction operation apparatus provided by at least one embodiment of the present disclosure;

[0030] Figure 10 FIG. 1 shows a block schematic diagram of another instruction operation apparatus provided by at least one embodiment of the present disclosure;

[0031] Figure 11 FIG. 1 shows a block schematic diagram of another instruction operation apparatus provided by at least one embodiment of the present disclosure; DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the range of the present disclosure.

[0033] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one", "a" or "the" or similar terms do not denote quantity restriction, but mean that there is at least one. The terms "include", "comprise" or similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like only represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships may also be changed accordingly.

[0034] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is denoted by the same or similar reference numeral in each drawing.

[0035] The terms used in the present disclosure are those general terms currently widely used in the art in consideration of functions in the present disclosure, but those terms can vary according to the intention of those of ordinary skill in the art, precedents, or new technology in the art. Also, specific terms can be chosen by the applicant, and in this case, their detailed meanings are described in the detailed description of the present disclosure. Therefore, the terms used in the specification should be understood not simply as the names of things but based on the meanings of the terms and the overall description of the present disclosure.

[0036] Flowcharts are used in the present disclosure to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in sequence. Rather, various steps can be processed in reverse order or simultaneously, as desired. Also, other operations can be added to these processes, or one or more steps can be removed from these processes. The pipeline of a processor performing instruction processing includes multiple pipeline stages, such as Branch prediction, Instruction fetch, Decode, Dispatch, Execute, Retire, etc.

[0037] To improve the performance of the processor pipeline in the front end providing instructions to the back end, two aspects can be improved: one is to increase the bandwidth of the processor front end fetching instructions, and the other is to reduce the delay of the processor fetching instructions.

[0038] Figure 1 A schematic diagram is divided for the basic structure of a processor. The processor 500 includes at least one processor core 503, and the processor core 503 includes a pipeline for instruction processing, for example, the pipeline of the processor core 503 includes a front end 501 and a back end 502.

[0039] For example, the processor can store instructions in the front end 501 by setting up an instruction cache. Since the processor can quickly obtain instructions from the instruction cache in the instruction fetch stage, the processor front end performance can be optimized by optimizing the instruction cache. The obtained instructions can be decoded to microinstructions in the instruction decode stage, and the microinstructions are dispatched to wait for execution. For example, in addition to the instruction cache, the processor can also increase a microinstruction cache (UopCache) in the front end 501. The microinstruction cache is used to store microinstructions frequently used by the processor recently, so that the processor can directly call the microinstructions frequently used recently from the microinstruction cache in the instruction fetch stage, thereby improving the instruction processing speed of the processor and reducing power consumption.

[0040] For storing the micro-instructions into the micro-instruction cache, for example, at least one micro-instruction can be determined according to the frequency of use of the micro-instructions obtained from the instruction sequence executed by the processor, and then the micro-instruction can be stored according to the minimum storage unit of the micro-instruction cache. For example, the minimum storage unit of the micro-instruction cache is a physical cache entry. For example, the at least one micro-instruction is arranged in a logical entry according to a certain rule, and each logical entry is stored in the corresponding physical cache entry of the micro-instruction cache, so as to store the at least one micro-instruction in the micro-instruction cache.

[0041] With the increasing number of processing cores in the processor, the way of calling micro-instructions from the micro-instruction cache is more obvious for the improvement of the instruction processing speed of the processor and the reduction of the system power consumption. Therefore, it is very important to store more micro-instructions in the micro-instruction cache for the improvement of the instruction processing performance of the processor. However, due to the limited chip size, the storage capacity of the micro-instruction cache cannot be expanded indefinitely, and therefore, how to store more micro-instructions in the limited instruction storage space of the micro-instruction cache is a problem to be solved. For example, when the micro-instructions are stored in the corresponding physical cache entry of the micro-instruction cache through the logical entry, there may be a case that the arrangement of the micro-instructions in the logical entry is not full, resulting in a large number of fragmented logical entries.

[0042] The inventors of the present disclosure have noticed that two storage compression methods for storing micro-instructions have been proposed to store more micro-instructions in the micro-instruction cache.

[0043] The first storage compression method is that when the micro-instructions are arranged into a logical entry according to a certain rule, the instruction items arranged in the instruction part and the constant items arranged in the constant operand are distinguished in the logical entry. If the arrangement space of the instruction items in the fragmented logical entry is not full, and the arrangement space of the constant items is not enough for arrangement, then the storage space of the instruction items can be squeezed to arrange the constant operands in the arrangement space of the instruction items until the space is full, so that more micro-instructions can be arranged in one logical entry.

[0044] The second storage compression method is that before being stored in the physical cache entry, all the fragmented logical entries are compressed and merged two by two, and the merged logical entries are stored in the corresponding physical cache entry, so as to reduce the waste of instruction storage space in the micro-instruction cache caused by the fragmented logical entries, improve the utilization rate of the micro-instruction cache, and store more micro-instructions in the micro-instruction cache.

[0045] However, the above method only compresses the fragmented logical entries, but does not compress other non-fragmented logical entries. Therefore, the above method does not compress all the logical entries as a whole, and the effect of improving the utilization rate of the micro-instruction cache is not obvious, and further, the effect of improving the instruction processing speed of the processor and reducing the overall power consumption is not obvious.

[0046] The instruction operation method includes: receiving a plurality of operation instructions, wherein each of the plurality of operation instructions includes an instruction part; in response to at least one object operation instruction of the plurality of operation instructions further including a constant operand, performing compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and storing the plurality of operation instructions according to the at least one compressed constant operand.

[0047] In the instruction operation method of the above-mentioned embodiments of the present disclosure, by performing compression processing on the constant operand included in the object operation instruction in the plurality of operation instructions, compression processing can be performed on each operation instruction to be stored as a whole. On the one hand, this reduces the waste of instruction storage space, better utilizes the limited instruction storage space, and improves the performance of the processor front end in providing instructions to the processor back end; on the other hand, it improves the instruction processing speed of the processor and reduces the power consumption of the system.

[0048] The various embodiments of the present disclosure will be described below in conjunction with specific examples.

[0049] Figure 2A A scenario diagram of a processor fetching instructions according to at least one embodiment of the present disclosure is shown.

[0050] As Figure 2A The instruction fetching architecture of the processor front end includes a branch predictor (BranchPredictor) 01, an instruction fetching task queue 02, a microinstruction queue 03, and a scheduler 04.

[0051] The branch predictor 01 can perform branch prediction operations on a plurality of operation instructions, for example, branch prediction on the jump destination address of a branch instruction (such as an if statement, a for loop statement, etc.) in the currently executed instruction sequence, generate prediction information, and generate an instruction fetching task based on the branch prediction information.

[0052] The instruction fetching task queue 02 stores branch prediction information for the instruction fetching unit to perform instruction fetching operations on corresponding operation instructions. For example, the processor front end can select an instruction fetching mode according to the hit situation of the microinstruction obtained after decoding the operation instruction in the microinstruction cache 20, the instruction fetching mode including an instruction instruction fetching mode and a microinstruction instruction fetching mode. The instruction instruction fetching mode is the default selection.

[0053] For example, in the instruction fetch mode, after the fetch unit fetches the target instruction from the instruction cache 11 according to the fetch task in the fetch task queue 02, the decode unit 12 decodes the target instruction to obtain one or more microinstructions, which are sent to the microinstruction queue 03 and also cached in the microinstruction cache 20. If a microinstruction is found to have been cached in the microinstruction cache 20 during the process of caching the microinstruction in the microinstruction cache 20, it is said that the microinstruction hits in the microinstruction cache 20, otherwise, it is said that the microinstruction misses in the microinstruction cache 20, i.e. the microinstruction is not cached in the microinstruction cache 20. Here, the "target instruction" is used to refer to the instruction in the plurality of instructions stored in the instruction cache 11 that is used as the description object and has not been decoded by the decode unit 12.

[0054] For example, if the microinstructions obtained by the decode unit 12 all hit in the microinstruction cache 20 within a certain time, it can be assumed that the subsequent microinstructions can also hit, and thus the instruction fetch mode is switched to the microinstruction fetch mode, and the fetch unit directly fetches the microinstructions from the microinstruction cache 20 according to the fetch task in the fetch task queue 02. If the fetch unit does not hit the microinstruction in the microinstruction cache 20, the instruction fetch mode is switched back to the instruction fetch mode.

[0055] The microinstruction queue 03 is used to store the microinstructions that are to be allocated to the execution units.

[0056] The scheduler 04 determines the execution units on which the microinstructions in the microinstruction queue 03 are executed, for example, by allocating the operation instructions to the execution units such as the integer unit and the floating point unit.

[0057] Figure 2B A flowchart of an instruction operation method provided by at least one embodiment of the present disclosure is shown. The instruction operation method is, for example, used in the processor core of a processor (single-core processor or multi-core processor).

[0058] As shown in FIG. 3, in some embodiments of the present disclosure, the instruction operation method includes steps S30, S31 and S32. Figure 2B

[0059] Step S30: receiving a plurality of operation instructions.

[0060] ​An operation instruction includes an opcode and operands. The opcode is used to indicate the type of operation to be performed, and the operands are data required to perform the operation instruction, for example, the operands can include a register address or a memory address as a variable operand, and for example, the operands can also include an immediate number and a shift count as a constant operand. The immediate number represents a specific numerical value, which can be directly used when the operation instruction is executed, for example, the immediate number is included in an operation instruction of the type of data transfer, arithmetic operation or logical operation. The shift count is used in a bit shift operation instruction to specify the number of bits of the bit shift operation.

[0061] For example, a microinstruction cache in a front end of a processor pipeline receives a plurality of operation instructions, for example, microinstructions. The front end of the pipeline includes, for example, a fetch unit, a decode unit, an instruction cache, a microinstruction cache, an instruction queue, and the like. For example, instructions that can be used during execution of a program are cached in the instruction cache, and the decode unit obtains the instructions to be operated from the instruction cache according to a fetch address, and then decodes the instructions to obtain a plurality of microinstructions, which are sent to the microinstruction cache. In an embodiment of the present disclosure, each of the plurality of operation instructions includes an instruction part.

[0062] In the present disclosure, the instruction part includes an opcode and a variable operand. As described above, the opcode is a part of the operation instruction that indicates the type of operation to be performed, and is used to tell the processor what operation needs to be performed, such as addition, subtraction, data transfer, logical operation, and the like.

[0063] When the variable operand is, for example, a register address or a memory address, the processor performs the operation of the constant operand according to the memory address represented by the variable operand when the operation instruction is executed.

[0064] For example, in some embodiments of the present disclosure, step S30 in the above instruction operation method further includes step S300.

[0065] Step S300: receiving a plurality of operation instructions from the decode unit.

[0066] The decode unit receives the instruction obtained according to the fetch address from the instruction cache, analyzes the opcode and the operands in the instruction, and generates a plurality of corresponding microinstructions. For example, a data transfer instruction can be implemented by reading two microinstructions of the source operand and the write target position; for example, a data transfer request instruction can generate a microinstruction of reading the source operand and a microinstruction of writing the target position.

[0067] Step S31: in response to the fact that at least one object operation instruction in the plurality of operation instructions further comprises a constant operand, performing compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand.

[0068] In the plurality of operation instructions, some operation instructions can comprise a constant operand, and the constant operand is directly embedded in the operation instruction. Here, the “object operation instruction” is used to refer to an instruction in the plurality of operation instructions that describes an object.

[0069] In some embodiments of the present disclosure, the constant operand in the above instruction operation method comprises an immediate number and / or a shift number.

[0070] For example, the object operation instruction comprising the constant operand can be compressed by a compression algorithm, so that at least one compressed constant operand in the operation instruction can be obtained. For example, Huffman Coding can be used to make the most commonly used operation instruction use a shorter code, thereby reducing the total length of the operation instruction. For another example, the LZ77 algorithm can be used to identify and replace repeated operation patterns corresponding to operation codes, thereby reducing the redundancy of the operation instruction, and other compression algorithms and combinations of multiple compression algorithms. It should be noted that the embodiments of the present disclosure do not limit the specific compression algorithm.

[0071] After the compression processing on the constant operand of at least one object operation instruction in the plurality of operation instructions, at least one compressed constant operand can be obtained. After the compression processing on the constant operand of each object operation instruction in the plurality of operation instructions, all compressed constant operands of the plurality of operation instructions can be obtained.

[0072] It should be noted that the object operation instruction to be compressed can be selected according to the storage requirement. For example, only a part of the object operation instructions in the plurality of operation instructions can be subjected to the compression processing of the constant operand, and another part of the object operation instructions can not be subjected to the compression processing of the constant operand or subjected to the compression processing by using other compression algorithms.

[0073] Step S32: storing the plurality of operation instructions according to the at least one compressed constant operand.

[0074] For example, the instruction storage space for storing the operation instruction can be divided into an instruction space and a constant space. The instruction space is used to store the instruction part corresponding to the operation instruction, and the constant space is used to store the constant part corresponding to the operation instruction. For example, the plurality of operation instructions can be directly stored in the corresponding instruction storage space according to the at least one compressed constant operand. For example, the instruction storage space can be a cache, such as a microinstruction cache.

[0075] In storing the plurality of operation instructions, for example, all of the compressed constant operands in the plurality of operation instructions can be stored; for example, part of the compressed constant operands and the constant operands without compression processing can be stored together.

[0076] For example, in some embodiments of the present disclosure, step S31 in the above instruction operation method further includes step S310.

[0077] Step S310: removing the sign extension bit of the constant operand to compress the constant operand.

[0078] In storing any operation instruction in the plurality of operation instructions, the instruction part and the constant operand included in the operation instruction can be stored correspondingly. For example, the instruction part is stored in the instruction space, and the constant operand is stored in the constant space.

[0079] The storage of the constant operand can be stored in the granularity of the operation instruction. For example, in the x86 architecture processor, the basic unit (also known as granularity) of data storage and processing is 32 bits (Bit), so the constant operand (immediate number or shift number) is stored in the format of 32-bit data. For example, even if the actual size of some constant operands is less than 32 bits, they will be expanded to 32 bits to maintain a consistent storage format for operation instructions. For example, there is an immediate number with a size of 8 bits (1 Byte) in the operation instruction, which needs to be expanded to 32 bits and occupy 32-bit storage space.

[0080] For example, the storage of the constant operand can maintain the correct storage of the constant operand through the sign extension bit. For example, the granularity in the constant storage space is 32 bits (Bit), and the constant operand is 8 bits (Bit). For example, the constant operand is a binary number 0b10000001 (decimal -127). For example, when directly expanded to 32 bits without using the sign extension bit, the expanded binary number 0b00000000 00000000 00000000 10000001 (decimal 129) is obtained, which causes expansion error; for example, when expanded to 32 bits through the sign extension bit, 0b11111111 11111111 1111111110000001 (decimal -127) is obtained, which makes the expansion correct.

[0081] Although storing the instructions according to their granularity can maintain a consistent storage format, the addition of the sign-extension bit will waste some storage space. Therefore, by removing the sign-extension bit of the constant operand to obtain a compressed constant operand, the compressed constant operand can be stored in the constant storage space, thereby making more efficient use of the constant storage space.

[0082] For example, when an operation instruction includes an immediate number and / or a displacement number, the immediate number and / or displacement number after expansion according to the granularity is identified, the bits with actual numerical significance are retained, and the sign extension bit is directly removed. For example, if the immediate number after expansion according to the granularity in an operation instruction is 0x00000008, occupying 32 bits, then by removing the sign extension bit, the immediate number can be compressed to 0x08, occupying only 8 bits of storage space. For example, if the immediate number after expansion according to the granularity in an operation instruction is 0xfffffff8, then by removing the sign extension bit, the immediate number is compressed to 0xf8.

[0083] Decoding Microinstruction Fetch Mode In some embodiments of the present disclosure, the plurality of operation instructions in the above instruction operation method are microinstructions, and step S32 includes step S320 .

[0084] Step S320: Store the plurality of operation instructions into the microinstruction cache.

[0085] As mentioned above, the operation instructions are microinstructions. Figure 2A As shown, when the instruction fetch mode is instruction fetch decode mode, the instruction fetch unit retrieves the target instruction from the instruction cache 11 based on the instruction fetch task stored in the instruction fetch task queue 02. The decoder unit 12 then decodes the target instruction into one or more microinstructions. The one or more microinstructions obtained from the decoder unit 12 are sent to the microinstruction queue 03 for scheduling by the scheduler 04. Simultaneously, the one or more microinstructions obtained from the decoder unit 12 are cached in the microinstruction cache 20. The instruction cache 11 is used to store at least one recently used target instruction to reduce the time it takes to retrieve instructions from memory. The decoder unit 12 is used to decode the target instruction retrieved from the instruction cache 11 into microinstructions.

[0086] For example, Figure 2A As shown, in the microinstruction instruction fetch mode, the instruction fetch unit directly obtains one or more microinstructions from the microinstruction cache 20 through the microinstruction cache instruction fetch queue 21 according to the instruction fetch task in the instruction fetch task queue 02, and the one or more microinstructions are transmitted to the microinstruction queue 03 for storage through the microinstruction cache pipeline 22, so that the scheduler 04 can schedule the microinstructions to the corresponding execution unit for execution.

[0087] For example, in some embodiments of the present disclosure, the microinstruction cache 20 is a hardware module that has been completely designed and laid out.

[0088] For example, the microinstruction cache 20 can include a plurality of cache lines, each of which can include a plurality of physical cache entries 200, each of which includes a tag field for identifying the cache entry for indexing. The cache lines are mapped, for example, in a set-associative, direct-associative, or the like manner. Embodiments of the present disclosure do not limit the specific implementation of the microinstruction cache.

[0089] The time period for completing a tick operation in the above processor pipeline is a clock cycle, also known as a machine cycle.

[0090] The microinstruction fetch mode has at least three advantages over the decoded instruction fetch mode:

[0091] First, the bandwidth is higher. The microinstruction fetch mode can send more operation instructions to the microinstruction queue 03 in each machine cycle than the decoded instruction fetch mode. For example, in the same machine cycle, the microinstruction fetch mode can send 8 microinstructions to the microinstruction queue 03, while the decoded instruction fetch mode can only decode and send 4 microinstructions to the microinstruction queue 03.

[0092] Second, the delay is lower. The speed of obtaining the microinstruction corresponding to the prediction information from receiving the prediction information in the microinstruction fetch mode is faster than the speed of obtaining the microinstruction corresponding to the prediction information through the instruction cache and the decoding unit after receiving the prediction information in the decoded instruction fetch mode.

[0093] Third, the power consumption is lower. In the microinstruction fetch mode, the instructions can be directly sent from the microinstruction cache to the dispatch stage corresponding to the microinstruction queue, without going through the complex circuit of the instruction cache and the decoding unit in the decoded instruction fetch mode. Therefore, the power consumption of the fetch process in the microinstruction fetch mode is lower.

[0094] Therefore, by storing the microinstruction including the compressed constant operand to the microinstruction cache 20, the microinstruction cache 20 can store more microinstructions, so that the processor front end can process operation instructions more quickly and efficiently. The microinstruction cache 20 can store more microinstructions, which also improves the possibility of the microinstruction cache 20 being hit. Thus, the fetch process of the processor can work in the microinstruction fetch mode for more time, which can further improve the performance of the entire processor to some extent.

[0095] In some embodiments of the present disclosure, for a plurality of operation instructions that can be frequently used, after decoding by the decoding unit 12, the plurality of micro instructions obtained by decoding can be stored in the micro instruction cache 20 to build the micro instruction cache 20, so as to further improve the hit rate of the micro instruction cache 20.

[0096] In some embodiments of the present disclosure, the above instruction operation method can further include step S220.

[0097] Step S220: Establishing a logical storage item according to a preset constraint rule.

[0098] For example, according to at least one compressed constant operand, a plurality of operation instructions can be stored to the micro instruction cache through the logical storage item.

[0099] Figure 3 A structure diagram of a logical storage item and a physical cache item provided by at least one embodiment of the present disclosure is shown.

[0100] As shown in Figure 3 The logical storage item includes a plurality of instruction domains and a plurality of constant storage domains.

[0101] According to the preset constraint rule, the number of instruction domains and constant storage domains in the logical storage item and the arrangement capacity size of each instruction domain and each constant storage domain are determined. The arrangement capacity is used to represent the data size that can be arranged in each instruction domain and each constant storage domain, for example, the arrangement capacity can be 32 Bits, 64 Bits, etc., which is not limited in the present disclosure.

[0102] For example, in some embodiments of the present disclosure, the preset constraint rule is used to constrain the maximum number of instruction domains of the instruction domains arranged in an instruction part of a logical storage item and the maximum number of constant domains of the constant storage domains arranged with constant operands, etc.

[0103] For example, when establishing the logical storage item according to the preset constraint rule, the preset constraint rule provides that:

[0104] (a) A logical storage item includes at most 8 instruction domains arranged with 8 instruction parts;

[0105] (b) A logical storage item includes at most 4 constant storage domains arranged with 4 constant operands.

[0106] In some embodiments of the present disclosure, the preset constraint rule can further include more constraint rules, for example, the arrangement rules of the instruction part and the constant operand can be agreed, for example, when all the constant storage domains are arranged full and there are at least 2 empty instruction domains in a logical storage item, the constant operand can occupy the space of the instruction domain for arrangement until the space of a logical storage item cannot arrange operation instructions any more.

[0107] For example, the logical storage item can be constructed according to a preset constraint rule. For example, a logical storage item 100 including 8 instruction domains Uop and 4 constant storage domains ID is constructed according to a preset constraint rule.

[0108] In some embodiments of the present disclosure, the logical storage item 100 further includes head data Misc info, for example, the size of the head data Misc info is 16 bits, and the head data Misc info is used to indicate the information of the instruction domains and the information of the constant storage domains in the logical storage item 100.

[0109] As shown in FIG. 2, the microinstruction cache 20 includes a plurality of physical cache items 200. Each physical cache item 200 can have a plurality of physical cache banks 210 with equal storage capacity. For example, the storage capacity of each physical cache bank is nBits, where n is a positive integer. For example, one physical cache item 200 is composed of 8 physical cache banks 210, and the storage capacity of the physical cache item 200 is nBits*8. Figure 3 For example, the microinstruction cache 20 is composed of a plurality of cache modules, for example, the microinstruction cache 20 is composed of two cache modules each having 256 physical cache items. It should be noted that although two cache modules with the same storage capacity are combined to form the microinstruction cache, the microinstruction cache can also be composed of a plurality of cache modules with different storage capacities, and the embodiments of the present disclosure do not limit the number of cache modules and the storage capacity of the cache modules.

[0110] In some embodiments of the present disclosure, the preset constraint rule is used to determine the arrangement manner of the plurality of operation instructions in the logical storage item.

[0111] After the logical storage item is created according to the preset constraint rule, the arrangement manner of the plurality of operation instructions to be stored in the microinstruction cache in the logical storage item is determined.

[0112] For example, according to the preset constraint rule, the arrangement manner of the plurality of instruction parts in the plurality of operation instructions and the at least one compressed constant operand is determined.

[0113] For example, in some embodiments of the present disclosure, the at least one object operation instruction in the above-mentioned instruction operation method includes a plurality of object operation instructions; the logical storage item includes a plurality of instruction domains and a plurality of constant storage domains, the plurality of instruction domains respectively arrange the instruction parts of the plurality of object operation instructions, and the plurality of constant storage domains respectively arrange the compressed constant operands of the plurality of object operation instructions.

[0114]

[0115] ​For example, when multiple operation instructions are arranged in a logical storage item, if any part of the multiple instruction fields or multiple constant storage fields in the logical storage item is full, the overflowing operation instructions are arranged to the next logical storage item.

[0116] In some embodiments of the present disclosure, step S32 in the above instruction operation method further includes step S321.

[0117] Step S321: combine multiple operation instructions into a logical storage item and arrange them.

[0118] refer to Figure 3 , 8 instruction fields Uop and 4 constant storage field IDs are planned according to the preset constraint rules. When some operation instructions are fully arranged in any part of the 8 instruction fields Uop or 4 constant storage field IDs in a logical storage item, the remaining multiple operation instructions are transferred to the next logical storage item for arrangement.

[0119] For example, each of the multiple operation instructions needs to be arranged in the same logical storage item. For example, for an operation instruction, its instruction portion and constant operand need to be arranged in the same logical storage item. If the current logical storage item only has the instruction field or the constant field remaining, the operation instructions that have not been arranged will be arranged in the next logical storage item based on the principle that the operation instructions are arranged in the same logical storage item.

[0120] In some embodiments of the present disclosure, step S321 in the above instruction operation method also includes step S3210.

[0121] Step S3210: Store the logical storage item in the corresponding physical cache item in the microinstruction cache.

[0122] For example, Figure 3 As shown, when the logical storage item 100 in which the operation instructions are arranged is stored in the physical cache item 200, since the hardware structure of the physical cache item 200 is not exactly the same as the construction form of the logical storage item 100, when the logical storage item 100 is mapped and stored in the physical cache item 200, the operation instructions arranged in the logical cache item 100 can be mapped to each physical cache slot 210 of the physical cache item 200 for storage according to the arrangement capacity size in the logical storage item 100.

[0123] For example, the mapping relationship between the storage logical item 100 and each physical cache slot 210 in the physical cache item 200 can be determined according to the arrangement capacity in the logical storage item 100 divided by the number of the physical cache slots 210 in the physical cache item 200. For example, the logical storage item 100 includes 8 instruction domains Uop with an arrangement capacity of 32 bits and 4 constant storage domains ID with an arrangement capacity of 32 bits, and the physical cache item 200 includes 8 physical cache slots 210 with a storage capacity of n bits, then the mapping relationship between each physical cache slot 210 and 48 bits of data in the logical storage item 100 can be determined according to (8*32+4*32) / 8=48 (bits), where n is greater than or equal to 48.

[0124] Figure 4 An assembler corresponding to an operation instruction is shown.

[0125] Each assembler corresponds to at least one machine instruction, for example, the machine instruction can be represented by a binary code or a hexadecimal code, each machine instruction corresponds to an operation instruction, and each operation instruction is composed of an operation code, a variable operand and a constant operand. According to the execution order of the assembler, the instruction order of each operation instruction can be determined.

[0126] As shown in the assembler, Figure 4 the operation code, the variable operand and the constant operand corresponding to each operation instruction are shown in Table 1, and the machine instruction shown in Table 1 is represented by a hexadecimal code.

[0127] Table 1

[0128]

[0129] Figure 5 An arrangement diagram of an operation instruction in a logical item is shown.

[0130] As shown in the assembler, Figure 5 the operation instruction of the assembler shown in Table 1 is arranged.

[0131] For example, the instruction part and the constant operand of an operation instruction need to be arranged in the same logical item, and when the instruction item or the constant item is arranged in a logical item, it needs to be arranged in the next logical item.

[0132] For example, logical item A and logical item B both include 8 instruction items and 4 constant items ID. For example, in the 8 operation instructions shown in Table 1, since the constant operands in the operation instructions of instruction order 1~instruction order 7 have already included 4 constant operands, all the constant items of logical item A will be occupied, thus, the operation instruction of instruction order 8 needs to be arranged in the next logical item B.

[0133] For example, in logical item A, the instruction parts of the operation instructions of instruction order 1~instruction order 7 are arranged in the instruction items of the logical item respectively; and the constant operands of the operation instructions of instruction order 4~instruction order 7 are arranged in the constant items of the logical item respectively (the operation instructions corresponding to instruction order 1~instruction order 3 have no constant operands); in logical item B, the operation instruction corresponding to instruction order 8 is arranged.

[0134] For example, when arranging the operation instructions in the logical item, the constant operands of the operation instructions are arranged after being encoded according to the actual storage mode in the physical cache item. For example, in the logical item corresponding to the x86-64 architecture, each constant item is usually 32 bits wide. For example, the physical cache item can be stored in the way of Little Endian. Thus, when the constant operand is an 8-bit immediate number 0x8, it can be encoded as 32 bits, which will be placed in the lowest 8 bits of the 32-bit word, and the remaining bits are filled with sign extension bits.

[0135] For example, in the instruction items of logical item A, there are arranged instruction part 5c8 push, instruction part 5ca push, instruction part 5cb mov, instruction part 5ce movl, instruction part 6d5 movl, instruction part 6dc sub and instruction part 6e0 sar. For example, the constant operands are arranged according to the format of storage in the way of Little Endian after being sign-extended. For example, the constant operand $0x8 corresponding to instruction part 5ce movl is sign-extended as 0x00000008 and arranged in the constant item as 08000000; the constant operand $0xc corresponding to instruction part 6d5 movl is sign-extended as 0x0000000c and arranged in the constant item as 0c000000; the constant operand $0x8 corresponding to instruction part 6dc sub is sign-extended as 0x00000008 and arranged in the constant item as 08000000; the constant operand $0x3 corresponding to instruction part 6e0 sar is sign-extended as 0x00000003 and arranged in the constant item as 03000000. In the instruction items of logical item B, there is arranged instruction part 6e3 lea, the corresponding constant operand 0x2007be is sign-extended as 0x2007be00 and arranged in the constant item according to the format of storage in the way of Little Endian as be072000.

[0136] At this point, there is still an empty instruction item in logic item A, but because all constant items in logic item A are already occupied, the operation instruction with instruction sequence 8 needs to be arranged in the next logic item B. Therefore, the 8 operation instructions in arrangement table 1 need to use 2 logic storage items.

[0137] In some embodiments of the present disclosure, step S32 in the above instruction operation method further includes step S322.

[0138] Step S322: determining an arrangement of the plurality of compressed constant operands in the constant storage domain according to the data size of the compressed constant operands of the plurality of object operation instructions and the arrangement capacity of each of the plurality of constant storage domains.

[0139] For example, multiple compressed constant operands may be combined into at least one data having a size equal to the arrangement capacity in the constant storage field according to the instruction sequence, so as to arrange the multiple compressed constant operands in one constant storage field.

[0140] It should be noted that, although the instruction part is represented by the operation address and the operation code in the above embodiment, it does not represent a limitation on the arrangement of the content of the instruction part in the instruction field.

[0141] In some embodiments of the present disclosure, in the above-mentioned instruction operation method, the arrangement of multiple compressed constant operands in the constant storage field includes: arranging the multiple compressed constant operands in the same object constant storage field in multiple constant storage fields.

[0142] Figure 6 A schematic diagram illustrating the arrangement of an operation instruction in a logical storage item provided by at least one embodiment of the present disclosure is shown.

[0143] like Figure 6 As shown, the operation instructions of the assembly program shown in Table 1 are arranged. For example, the logical storage item 100 includes 8 instruction fields and 4 constant storage fields with an arrangement capacity of 32 bits.

[0144] For example, the compression of the constant operand can be performed by removing the sign extension bits of the constant operand. For example, for the operation instruction of instruction sequence 1~instruction sequence 7, the constant operand 0x00000008 corresponding to instruction part 5 ce movl is compressed to 0x08; the constant operand 0x0000000c corresponding to instruction part 6 d5 movl is compressed to 0x0c; the constant operand $0x8 corresponding to instruction part 6 dc sub is sign-extended to 0x00000008 and compressed to 0x08; and the constant operand 0x00000003 corresponding to instruction part 6 e0 sar is compressed to 0x03. The data size of the above plurality of compressed constant operands is compressed from 32 bits to 8 bits, and the arrangement capacity of each constant storage domain is 32 bits.

[0145] For example, the constant operands in the logical storage item can be arranged according to the format stored in the Little Endian.

[0146] In some embodiments of the present disclosure, step S32 of the above instruction operation method further includes step S323.

[0147] Step S323: determining the arrangement order of the plurality of compressed constant operands in the object constant storage domain according to the instruction sequence of the plurality of object operation instructions.

[0148] For example, the compressed constant operands 0x08, 0x0c, 0x08 and 0x03 can be arranged in the object constant storage domain according to the order of the instruction sequence from high bit to low bit, that is, the first 8 high bits of the object constant storage domain are arranged with the constant operand 0x08 which is earlier in the instruction sequence, and then the constant operands 0x0c, 0x08 and 0x03 are sequentially arranged in the corresponding bits.

[0149] For example, the above four compressed constant operands can be merged into one data with the same size as the arrangement capacity in the constant storage domain according to the instruction sequence, so as to determine the arrangement order of the plurality of compressed constant operands in the object constant storage domain. For example, the compressed constant operands 0x08, 0x0c, 0x08 and 0x03 are merged into 0x080c0803 according to the instruction sequence and arranged in one constant storage domain.

[0150] After the operation instructions of instruction sequence 1 to instruction sequence 7 are arranged in the logical storage item 100, the logical storage item 100 still has 1 instruction domain and 3 constant storage domains. Therefore, the operation instruction of instruction sequence 8 can continue to be arranged in the logical storage item 100. The above-mentioned manner can make the 8 operation instructions originally arranged in two logical items (the logical item A and the logical item B) arranged in one logical storage item, save the arrangement space of the logical storage item, and further improve the storage utilization of the microinstruction cache, so that more operation instructions can be stored in the microinstruction cache with the same capacity.

[0151] In some embodiments of the present disclosure, the compression of the constant operands can also be performed by removing part of the sign extension bits.

[0152] For example, for the operation instructions of instruction sequence 1 to instruction sequence 7, the constant operand 0x00000008 corresponding to the instruction part 5ce movl is compressed to 0x0008; the constant operand 0x0000000c corresponding to the instruction part 6d5 movl is compressed to 0x000c; the constant operand $0x8 corresponding to the instruction part 6dc sub is sign-extended to 0x00000008 and compressed to 0x0008; and the constant operand 0x00000003 corresponding to the instruction part 6e0 sar is compressed to 0x0003.

[0153] For example, the compressed constant operands 0x0008 and 0x000c are combined into 0x0008000c, and the compressed constant operands 0x0008 and 0x0003 are combined according to the instruction sequence into 0x00080003.

[0154] The data size of the above-mentioned plurality of compressed constant operands is compressed from 32 bits to 16 bits. According to the arrangement capacity size 32 bits of each constant storage domain, each two compressed constant operands can be arranged in one constant storage domain. In this way, the original 4 constant operands can be changed from occupying 4 constant storage domains to occupying 2 constant storage domains.

[0155] After the operation instructions of instruction sequence 1 to instruction sequence 7 are arranged in the logical storage item 100, the logical storage item 100 still has 1 instruction domain and 2 constant storage domains, and the operation instruction of instruction sequence 8 can continue to be arranged in the logical storage item 100.

[0156] Through the above-mentioned two exemplary compression manners, the plurality of compressed constant operands can be arranged in the same object constant storage domain in the plurality of constant storage domains, the utilization rate of the constant storage domain in the logical storage item is improved; the storage utilization of the microinstruction cache is also improved by storing such logical storage item into the physical cache item, so that more operation instructions can be stored in the microinstruction cache with the same capacity.

[0157] Figure 7 A block diagram of an instruction operation apparatus is shown.

[0158] As Figure 7 shown, the instruction operation apparatus 800 comprises a receiving module 801, a compression module 802 and a storage module 803.

[0159] The receiving module 801 is configured to receive a plurality of operation instructions, wherein each of the plurality of operation instructions comprises an instruction part.

[0160] The compression module 802 is configured to, in response to at least one object operation instruction in the plurality of operation instructions further comprising a constant operand, perform compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand.

[0161] The storage module 803 is configured to store the plurality of operation instructions according to the at least one compressed constant operand.

[0162] In some embodiments of the present disclosure, the storage module 803 is configured to perform the storage operation in a microinstruction cache (for example, see Figure 2A ).

[0163] In some embodiments of the present disclosure, the storage module 803 further comprises an arrangement module 804. The arrangement module 804 is configured to arrange the plurality of operation instructions into one logical storage item.

[0164] In some embodiments of the present disclosure, the instruction operation apparatus 800 further comprises an establishment module 805. The establishment module 805 is configured to establish the logical storage item according to a preset constraint rule, and the preset constraint rule is used to determine the arrangement manner of the plurality of operation instructions in the logical storage item respectively.

[0165] In some embodiments of the present disclosure, the arrangement module 804 further comprises a cache item storage module 8040. The cache item storage module 8040 is configured to store the logical storage item in a corresponding physical cache item in the microinstruction cache.

[0166] In some embodiments of the present disclosure, the compression module 802 further comprises an extension bit removal module 8020. The extension bit removal module 8020 is configured to remove a sign extension bit of the constant operand to compress the constant operand.

[0167] The technical effects of the instruction operation apparatus of the above-mentioned embodiments of the present disclosure are the same as those of the above-mentioned instruction operation method, and thus will not be repeated.

[0168] Figure 8A block diagram of another instruction operation apparatus provided by at least one embodiment of the present disclosure is shown.

[0169] As shown in Figure 8 At least one embodiment of the present disclosure further provides an instruction operation apparatus 600, which comprises at least one storage unit 610 and at least one processing unit 620.

[0170] The at least one storage unit 610 is configured to store computer executable instructions. The at least one processing unit 620 is configured to execute the computer executable instructions, wherein the computer executable instructions, when executed by the at least one processing unit, implement the instruction operation method provided by any embodiment of the present disclosure. The processing unit may, for example, be any processing circuitry having processing capability, which may be implemented by hardware or firmware, such as a processor (CPU) and the like. The storage unit may, for example, comprise a semiconductor storage unit. Embodiments of the present disclosure do not limit the implementation manner of the storage unit 610 and the processing unit 620.

[0171] The technical effects of the instruction operation apparatus of the above-mentioned embodiments of the present disclosure are the same as those of the above-mentioned instruction operation method, and thus will not be described again.

[0172] Figure 9 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0173] As shown in Figure 9 At least one embodiment of the present disclosure further provides an electronic device 700, which comprises a decoding unit 701 and a micro instruction cache 702.

[0174] The micro instruction cache 702 is configured to receive a plurality of operation instructions from the decoding unit, wherein each of the plurality of operation instructions comprises an instruction part; in response to at least one object operation instruction of the plurality of operation instructions further comprising a constant operand, perform compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and store the plurality of operation instructions according to the at least one compressed constant operand.

[0175] For example, the electronic device is a processor core, which may be a single-core processor or a multi-core processor. The processor core comprises a pipeline for instruction processing, which comprises a front end and a back end. The front end comprises, in addition to the decoding unit and the micro instruction cache, a branch prediction unit, an instruction cache and the like. Embodiments of the present disclosure do not limit the instruction set (such as X86 instruction set, ARM instruction set, RSIC-V instruction set and the like) applicable to the processor core and the micro architecture adopted.

[0176] The technical effects of the electronic device of the above-described embodiments of the disclosure are the same as those of the above-described instruction operation method, and thus will not be described again.

[0177] The at least one embodiment of the disclosure also provides another electronic device, wherein the electronic device includes the instruction operation device described in the at least one embodiment.

[0178] Figure 10 A schematic block diagram of an electronic device provided in at least one embodiment of the disclosure.

[0179] The electronic device in the embodiments of the disclosure can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a car terminal (for example, a car navigation terminal), and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like. Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitation on the functions and use range of the embodiments of the disclosure.

[0180] For example, referring to Figure 10 In some examples, the electronic device 1000 includes a processing device (for example, a central processor, a graphic processor, and the like) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 into a random access memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the computer system are also stored. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other by an interconnection network 1004. An input / output (I / O) interface 1005 is also connected to the interconnection network 1004.

[0181] For example, the processing device 1001, for example Figure 9 The example of the electronic device shown includes a microinstruction cache and a microinstruction cache operation device.

[0182] For example, the following components can be connected to the I / O interface 1005: input devices 1006 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; output devices 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, and the like; storage devices 1008 including, for example, a magnetic tape, a hard disk, and the like; and communication devices 1009 including, for example, a LAN card, a modem, and the like. The communication devices 1009 can allow the electronic device 1000 to wirelessly or wiredly communicate with other devices to exchange data, perform communication processing via a network such as the Internet. Drivers 1010 are also connected to the I / O interface 1005 as necessary. Removable media 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like are mounted on the drive 1010 as necessary, so that a computer program read out therefrom is installed in the storage devices 1008 as necessary. Although Figure 10 The electronic device 1000 is shown to include various devices, but it is understood that not all of the shown devices are required to be implemented or included. More or fewer devices can alternatively be implemented or included.

[0183] For example, the electronic device 1000 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, for example, a USB interface, a lightning interface, and the like. The communication devices 1009 can communicate with networks and other devices through wireless communication, the network being, for example, the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any of a plurality of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (for example, based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0184] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, and the like, and can be any combination of data processing apparatuses and hardware, and embodiments of the present disclosure are not limited thereto.

[0185] At least one of the embodiments of the present disclosure further provides a non-transitory storage medium which non-transitorily stores computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, an instruction operation method provided by at least one of the embodiments of the present disclosure is implemented.

[0186] Figure 11 FIG. 9 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. As shown in FIG. 9, the non-transitory storage medium 900 can non-transitorily store computer-executable instructions 910 which, when executed by a computer, implement an instruction operation method provided by any of the embodiments of the present disclosure. Figure 11

[0187] For the present disclosure, the following points need to be explained:

[0188] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can be referred to the general design.

[0189] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0190] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.​

Claims

1. An instruction operation method, comprising: receiving a plurality of operation instructions, wherein each of the plurality of operation instructions comprises an instruction part; in response to at least one object operation instruction of the plurality of operation instructions further comprising a constant operand, performing compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; storing the plurality of operation instructions according to the at least one compressed constant operand; wherein the plurality of operation instructions are microinstructions, the storing the plurality of operation instructions according to the at least one compressed constant operand comprises storing the plurality of operation instructions into a microinstruction cache.

2. The method of claim 1, wherein, the storing the plurality of operation instructions according to the at least one compressed constant operand further comprises: merging the plurality of operation instructions into one logical storage item for arrangement.

3. The instruction operation method of claim 2, further comprising: establishing the logical storage item according to a preset constraint rule, wherein the preset constraint rule is used to determine an arrangement manner of the plurality of operation instructions in the logical storage item respectively.

4. The method of claim 2, wherein, the merging the plurality of operation instructions into one logical storage item for arrangement comprises: storing the logical storage item in a corresponding physical cache item in the microinstruction cache.

5. The method of claim 2, wherein, the at least one object operation instruction comprises a plurality of object operation instructions; the logical storage item comprises a plurality of instruction domains and a plurality of constant storage domains, the plurality of instruction domains respectively arrange instruction parts of the plurality of object operation instructions, and the plurality of constant storage domains respectively arrange the compressed constant operands of the plurality of object operation instructions.

6. The method of claim 5, wherein, the storing the plurality of operation instructions according to the at least one compressed constant operand further comprises: determining an arrangement form of the plurality of compressed constant operands in the constant storage domains according to data sizes of the compressed constant operands of the plurality of object operation instructions and according to arrangement capacities of each of the plurality of constant storage domains.

7. The method of claim 6, wherein, the arrangement form of the plurality of compressed constant operands in the constant storage domains comprises: arranging the plurality of compressed constant operands in a same object constant storage domain in the plurality of constant storage domains.

8. The method of claim 7, wherein, the storing the plurality of operation instructions according to the at least one compressed constant operand further comprises: determining an arrangement order of the plurality of compressed constant operands in the object constant storage domain according to an instruction order of the plurality of object operation instructions.

9. The method of claim 1-8, wherein, the constant operand comprises an immediate number and / or a shift number.

10. The method of claim 1-8, wherein, the performing compression processing on the constant operand of the at least one object operation instruction comprises: removing a sign extension bit of the constant operand to compress the constant operand.

11. The method of claim 1-8, wherein, the receiving the plurality of operation instructions comprises: receiving the plurality of operation instructions from a decoding unit.

12. An instruction operation apparatus, comprising: a receiving module configured to receive a plurality of operation instructions, wherein each of the plurality of operation instructions comprises an instruction part; The compression module is configured to, in response to at least one object operation instruction in the plurality of operation instructions further comprising a constant operand, perform compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; The storage module is configured to store the plurality of operation instructions according to the at least one compressed constant operand; The plurality of operation instructions are micro-instructions. The storage module is further configured to store the plurality of operation instructions into a micro-instruction cache.

13. An instruction operation apparatus, comprising: at least one storage unit storing computer executable instructions; and at least one processing unit configured to execute the computer executable instructions, wherein the computer executable instructions, when executed by the at least one processing unit, implement the instruction operation method according to any one of claims 1-11. The micro-instruction cache is configured to:

14. An electronic device comprising a decode unit and a microinstruction cache, wherein, receive a plurality of operation instructions from the decoding unit, wherein each of the plurality of operation instructions comprises an instruction portion; in response to at least one object operation instruction in the plurality of operation instructions further comprising a constant operand, perform compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; store the plurality of operation instructions according to the at least one compressed constant operand, wherein the plurality of operation instructions are micro-instructions. The computer executable instructions, when executed by the at least one processing unit, implement the instruction operation method according to any one of claims 1-11.

15. A non-transitory storage medium non-transitorily storing computer- executable instructions, wherein, ​

Images