Multi-core DSP inter-core data sharing method based on shared memory
By adopting a shared memory-based inter-core data sharing method in multi-core DSP, the problems of frequent interruptions between core communications and shared memory cache consistency are solved, and efficient and reliable inter-core data sharing is achieved, improving system performance and stability.
Patent Information
- Application Number
- CN202411683417.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-02-28
AI Technical Summary
In the development of multi-core DSP, the existing inter-core communication methods need to rely on inter-core interruptions, resulting in increased overhead and decreased system performance during frequent communications; while the shared memory method needs to consider the consistency of multi-core cache to avoid system abnormalities and performance degradation caused by data out-of-synchronization and memory access blocking.
The data sharing method between multi-core DSP cores based on shared memory is adopted. By dividing the storage address segment of shared data in the DSP multi-core shared memory, the shared data sending core allows the data to be written to the specified address, updated the log data, and the receiving core cycles to check the log data to read the shared data to ensure cache consistency.
It realizes efficient and reliable data sharing between cores, avoids frequent interruption overhead of traditional inter-core communication, meets the consistency requirements of multi-core cache, prevents system abnormalities and performance degradation caused by data out-of-synchronization and memory access blocking, and makes the signal processing process efficient, stable and reliable.
Smart Images
Figure CN119537058A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of multi-core DSP application software development, and in particular to a multi-core DSP inter-core data sharing method based on shared memory. Background Art
[0002] Data sharing between multiple cores is an issue that must be addressed in the development of multi-core DSPs. Data received from the outside needs to be passed to the required cores through inter-core data sharing, and the results generated during data processing also need to be passed through inter-core data sharing.
[0003] There are two ways to share data between cores of multi-core DSP: inter-core communication and shared memory. Inter-core communication requires the use of inter-core interrupts to transmit information. When inter-core communication is frequent, the overhead will increase, resulting in system performance degradation. When sharing data in the shared memory mode, the consistency of multi-core caches must usually be considered to avoid system anomalies and performance degradation caused by inter-core data asynchrony and inter-core memory access blocking. Therefore, how to achieve efficient and reliable inter-core data sharing is extremely important for multi-core DSP development.
[0004] Therefore, it is necessary to provide a multi-core DSP inter-core data sharing method based on shared memory to solve the above problems. Summary of the invention
[0005] In order to achieve efficient and reliable inter-core data sharing, the present invention provides a multi-core DSP inter-core data sharing method based on shared memory. The method only uses inter-core shared memory and does not use inter-core communication to solve the problem that the existing inter-core communication needs to rely on inter-core interrupts to transmit information. When the inter-core communication is more frequent, the overhead will increase, resulting in system performance degradation. When sharing data in a shared memory manner, the consistency of multi-core caches must usually be considered to avoid system anomalies and performance degradation caused by inter-core data asynchrony and inter-core memory access blocking.
[0006] A multi-core DSP inter-core data sharing method based on shared memory of the present invention adopts the following technical solution, including: A storage address segment of agreed shared data is divided in the DSP multi-core shared memory, wherein the storage address segment includes a plurality of storage addresses, and each storage address is used to store the shared data for each sharing; The shared data sending core writes the shared data to be shared into the storage address in the agreed storage address segment each time; The shared data sending core updates the log data of the shared data storage address in the storage address segment; The shared data receiving core cyclically checks the log data at the storage address; When the shared data receiving core detects that there is shared data update in the log data, the shared data is read.
[0007] Preferably, the storage address segment of the same shared data segment can only be written by one of the multiple cores, and the remaining cores in the multiple cores can only read the data but cannot write it.
[0008] Preferably, the log data of the storage address of the current latest shared data should be aligned according to the cache line size of the chip.
[0009] Preferably, the cache is written back after the log data at the storage address is updated.
[0010] Preferably, the cache is released first when reading shared data.
[0011] The beneficial effects of the present invention are: The inter-core data sharing of the present invention adopts a shared memory method, which is simple, flexible and reliable, avoiding the frequent interruption overhead caused by using traditional inter-core communication; and has no restrictions on the length and type of shared data, which is very flexible; by following the memory address allocation of CacheLine, the consistency of multi-core cache (Cache) is met; the system anomaly and performance degradation caused by inter-core data asynchrony and inter-core memory access blocking are prevented, making the signal processing process efficient, stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0013] Figure 1 A flow chart of a multi-core DSP inter-core data sharing method based on shared memory of the present invention; Figure 2 A schematic diagram of a shared address segment in a shared memory of the present invention; Figure 3 A schematic diagram of addresses stored in one of the shared address segments of the present invention. DETAILED DESCRIPTION
[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0015] An embodiment of a multi-core DSP inter-core data sharing method based on shared memory of the present invention is as follows: Figure 1 As shown, including: S1. The sending core writes the shared data into the storage address in the storage address segment agreed upon by the shared memory; like Figure 2 and Figure 3 As shown, a plurality of storage address segments of agreed shared data are divided in the DSP multi-core shared memory, the sizes of the plurality of storage address segments may be the same or different, the storage address segments include a plurality of storage addresses, and the storage addresses are used to store the shared data; the shared data sending core writes the shared data to be shared each time into the storage address in the agreed storage address segment.
[0016] S2, sending log data of the storage address of the core updated shared data; The shared data sending core updates the log data (WriteLog) of the storage address of the shared data in the storage address segment. To prevent inter-core memory access blocking, the log data (WriteLog) of the storage address of the latest shared data must be aligned according to the chip's cache line (CacheLine) size. After updating the log data of the storage address, the cache (Cache) must be written back; Figure 3 Log data of the storage address of the latest shared data. This storage address will be frequently accessed by multiple cores and cached. Therefore, the allocation of this storage address must comply with the CacheLine size rule of the chip to avoid data asynchrony between cores and memory access blocking between cores.
[0017] S3, receiving nuclear cycle check log data; The shared data receiving core cyclically checks the log data of the storage address (WriteLog); S4, the receiving core reads the shared data; When the shared data receiving core detects that there is shared data update in the log data, the shared data is read.
[0018] It should be noted that in the present invention, the storage address segment of the same shared data can only be written by one of the multi-cores, and the remaining cores in the multi-cores can only read data but not write; when reading shared data, the cache must be released first.
[0019] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A multi-core DSP inter-core data sharing method based on shared memory, characterized in that: include: A plurality of storage address segments of agreed shared data are divided in the DSP multi-core shared memory, wherein the storage address segments include a plurality of storage addresses, and the storage addresses are used to store the shared data for each sharing; The shared data sending core writes the shared data to be shared into the storage address in the agreed storage address segment each time; The shared data sending core updates the log data of the shared data storage address in the storage address segment; The shared data receiving core cyclically checks the log data at the storage address; When the shared data receiving core detects that there is shared data update in the log data, the shared data is read.
2. The method for sharing data among multi-core DSP cores based on shared memory according to claim 1, characterized in that: The storage address segment of the same shared data can only be written by one of the cores in the multi-cores, and the other cores in the multi-cores can only read the data but cannot write it.
3. The method for sharing data among multi-core DSP cores based on shared memory according to claim 1, characterized in that: The log data of the storage address of the current latest shared data must be aligned according to the cache line size of the chip.
4. The method for sharing data among multi-core DSP cores based on shared memory according to claim 1, characterized in that: The cache is written back after the log data at the storage address is updated.
5. The method for sharing data among multi-core DSP cores based on shared memory according to claim 1, characterized in that: When reading shared data, release the cache first.