Host error control matrix

Abstract

The invention relates to a host error control matrix. A host device may implement a parity check matrix for generating error control information, where a multi-bit error in a codeword associated with the error control information is relatively low likely to be mistaken as a unit error. The host device may implement a parity check matrix that is patterned such that when the error control information is generated, an error code generated by a comparison of the error control information will generate an indication of a unit error when a multi-bit error occurs is relatively low in likelihood. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using a result of the comparison.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 579,147, filed by Schaefer et al. on August 28, 2023, entitled “HOST ERROR CONTROL MATRIX,” and U.S. Patent Application No. 18 / 775,974, filed by Schaefer et al. on July 17, 2024, entitled “HOST ERROR CONTROL MATRIX,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to host error control matrices. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, which are typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) a state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain a stored logic state for an extended period of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose a stored state when disconnected from an external power source. Summary of the invention

[0006] A method is described. The method may include: generating, by an error control engine of a host device, error control information by applying a parity check matrix to data for storage in a memory device, the parity check matrix being used to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition; transmitting the data to the memory device over one or more data lanes and transmitting the error control information to the memory device over a dedicated error control channel based at least in part on generating the error control information; receiving the data from the memory device over the one or more data lanes and receiving the error control information from the memory device over the dedicated error control channel based at least in part on transmitting the data and the error control information; and generating second error control information at the error control engine by applying the parity check matrix to the data received from the memory device.

[0007] An automotive memory system is described. The automotive memory system may include: a memory device including a plurality of memory cells configured to store data; and a host system coupled to the memory device and configured to communicate data through one or more data channels and to communicate error control information through a dedicated error control channel, the host system further comprising: an error control engine implementing a parity check matrix configured to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition.

[0008] An apparatus is described. The apparatus may include: a controller associated with a host device, wherein the controller is configured to cause the apparatus to: generate, by an error control engine of the host device, error control information by applying a parity check matrix to data for storage in a memory device, the parity check matrix being used to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition; transmit the data to the memory device through one or more data channels and transmit the error control information to the memory device through a dedicated error control channel based at least in part on generating the error control information; receive the data from the memory device through the one or more data channels and receive the error control information from the memory device through the dedicated error control channel based at least in part on transmitting the data and the error control information; and generate second error control information at the error control engine by applying the parity check matrix to the data received from the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting a host error control matrix according to examples as disclosed herein is described.

[0010] Figure 2 An example of an error correction map supporting a host error control matrix according to examples as disclosed herein is illustrated.

[0011] Figure 3 An example of a parity check matrix supporting a host error control matrix according to examples as disclosed herein is illustrated.

[0012] Figure 4 An example of a parity check matrix supporting a host error control matrix according to examples as disclosed herein is illustrated.

[0013] Figure 5 An example of a detection result graph supporting a host error control matrix according to examples as disclosed herein is illustrated.

[0014] Figure 6 A block diagram illustrating a host device supporting a host error control matrix according to examples as disclosed herein.

[0015] Figure 7 The description shows a flow chart of one or several methods of supporting a host error control matrix according to examples as disclosed herein. DETAILED DESCRIPTION

[0016] The host device may be configured to communicate with the memory device such that data and error control information (e.g., parity bits) may be transmitted between the host device and the memory device for error detection and correction. For example, the host device may compare the error control information transmitted and received from the memory device to determine whether there is an error in the data associated with the error control information. The host device may generate an error code to indicate the number of errors in the data based on comparing the transmitted and received error control information. In some cases, the error code may indicate a multi-bit error in the data (e.g., 3 or more bit errors), however, due to overlap (e.g., aliasing) between the error codes for multi-bit errors and single-bit errors, the error code may be interpreted (e.g., by the host device) as indicating a single-bit error in the data (e.g., 1-bit error). In some such cases, the host system may correct the interpreted single-bit error, thereby introducing additional errors into the data.

[0017] According to an example as described herein, a host device may implement a parity check matrix (e.g., an H matrix) for generating error control information, wherein the probability of a multi-bit error being mistaken for a single-bit error is reduced. For example, the host device may implement a parity check matrix that is patterned so that when generating error control information, the probability that an error code generated by comparison of the error control information will generate an indication of a single-bit error when a multi-bit error occurs is relatively low. In some cases, the host device may use the parity check matrix to generate first error control information for data, and transmit the data and the first error control information to a memory device. The memory device may transmit the data and the first error control information back to the host device, wherein the host device may use the parity check matrix to generate second error control information for the received data. The host device may compare the first error control information with the second error control information and use the comparison result to generate an error code. In some such cases, the error code generated due to the use of the parity check matrix may support 100% correction of single-bit errors, 100% detection of double-bit errors, at least 99.1% detection of triple-bit errors, and at least 99.5% detection of the remaining multi-bit errors. Thus, implementing a parity check matrix as described herein may reduce overlap between error codes and improve error detection of multi-bit errors, among other advantages.

[0018] First, in the reference Figure 1 The features of the present disclosure are described in the context of the described system. Figures 2 to 5 Features of the present disclosure are described in the context of the error correction graph, parity check matrix, and detection result graph described herein. Figure 6 and 7 The described host error control matrix-related device diagrams and flow charts are further illustrated and referenced to describe these and other features of the present disclosure.

[0019] Figure 1 An example of a system 100 supporting a host error control matrix according to examples as disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0020] System 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of system 100 that is operable to store data for one or more other components of system 100.

[0021] Portions of system 100 may be instances of host device 105. Host device 105 may be an instance of a processor (e.g., circuitry, processing circuitry, processing component) within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host (e.g., host device 105).

[0022] Memory device 110 may be a stand-alone device or component that is operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes used to modulate signals, various pin configurations for communicating signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other functions.

[0023] Memory device 110 may be operable to store data for components of host device 105. In some examples, memory device 110 (e.g., operating as a secondary device to host device 105, operating as a slave device to host device 105) may respond to and execute commands provided by host device 105 through external memory controller 120. Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0024] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0025] The processor 125 may be operable to provide functionality (e.g., control functionality) for the system 100 or the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, the processor 125 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 may be implemented by the processor 125 or may be part of the processor 125.

[0026] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include instructions (e.g., programs, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0027] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity (e.g., expected capacity, specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more storage bodies, one or more tiles, one or more sectors), wherein each memory cell is operable to store one or more data bits. A memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0028] The device memory controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0029] In some examples, memory device 110 can communicate information (e.g., data, commands, or both) with host device 105. For example, memory device 110 can receive a write command indicating that memory device 110 is to store data received from host device 105, or receive a read command indicating that memory device 110 is to provide data stored in memory die 160 to host device 105, among other types of information communications.

[0030] The local memory controller 165 (e.g., local to the memory die 160) may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 may not include the device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other components operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0031] The external memory controller 120 may be operable to enable communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105 (e.g., the processor 125) and the memory device 110). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120, or other components of the system 100 or the host device 105, or the functions thereof described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0032] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device 110. Each channel 115 may include one or more signal paths (e.g., transmission media, conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at host device 105 and a second terminal at memory device 110. A terminal may be an example of a conductive input or output point of a device of system 100, and a terminal may be operable to serve as part of a channel.

[0033] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or any combination thereof. In some examples, signaling may be conveyed through the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0034] In some examples, CA channel 186 may be operable to communicate commands, including control information (e.g., address information) associated with the commands, between host device 105 and memory device 110. For example, a command carried by CA channel 186 may include a read command with an address of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) used to communicate control information (e.g., commands or addresses).

[0035] In some examples, data channel 190 may be operable to transfer information (e.g., data, control information) between host device 105 and memory device 110. For example, data channel 190 may transfer information to be written to memory device 110 (e.g., bidirectionally) or information to be read from memory device 110.

[0036] In some examples, the one or more other channels 192 may include one or more error detection code (EDC) channels. The EDC channels may be operable to transmit error detection signals (eg, checksums) to improve system reliability. The EDC channels may include any number of signal paths.

[0037] According to examples as described herein, the host device 105 may implement a parity check matrix (e.g., an H matrix) for generating error control information, wherein the probability that an error code indicating a multi-bit error is mistaken for a single-bit error is reduced. For example, the host device 105 may implement a parity check matrix that is patterned so that when generating error control information, the probability that the error code generated by the comparison of the error control information will generate an indication of a single-bit error when a multi-bit error occurs is relatively low. In some cases, the host device 105 may use the parity check matrix to generate first error control information for the data, and transmit the data and the first error control information to the memory device 110. The memory device 110 may transmit the data and the first error control information back to the host device 105, wherein the host device 105 may use the parity check matrix to generate second error control information for the received data. The host device 105 may compare the first error control information with the second error control information and use the comparison result to generate an error code. In some such cases, the error codes generated by using the parity check matrix can support 100% correction of single-bit errors, 100% detection of double-bit errors, and at least 99.1% detection of triple-bit errors. Thus, implementing a parity check matrix as described herein can reduce overlap between error codes and improve error detection of multi-bit errors, among other advantages.

[0038] In addition to applicability in the memory systems described herein, the techniques supporting the host error control matrix may be generally implemented to improve the security and / or authentication features of various electronic devices and systems. As the use of electronic devices to handle private, user or other sensitive information becomes more prevalent, electronic devices and systems have become the target of increasingly frequent and sophisticated attacks. In addition, unauthorized access or modification of data in safety-critical devices (such as vehicles, healthcare devices, and others) may be particularly concerning. Implementation of the techniques described herein may improve the security of electronic devices and systems by reducing the likelihood that multi-bit errors are mistaken for single-bit errors, thereby improving the error detection and correction capabilities of electronic devices and systems, and preventing or mitigating unauthorized access to data or other information, as well as other advantages.

[0039] Figure 2 An example of an error correction map 200 supporting a host error control matrix according to an example disclosed herein is illustrated. The error correction map 200 may implement aspects or operations of the system 100, as described with reference to Figure 1 For example, error correction diagram 200 may depict operations at a host device, which may be an example of host device 105, as described in reference Figure 1 Error correction diagram 200 illustrates an example of a situation where an error code 210 may be generated after a multi-bit error is detected, but the host device may interpret the error code 210 as a single-bit error.

[0040] The host device may be configured to communicate with a memory device (e.g., a volatile memory device) coupled to the host device so that a codeword may be transmitted between the host device and the memory device. The codeword may include a certain number of unit intervals (UIs) 205 (e.g., 16) transmitted between the host device and the memory device. In some cases, error control information may be used to protect data bits transmitted between the host device and the memory device. If multiple signal paths are used to transmit symbols in parallel during a single UI, each UI 205 may include a certain number of data bits 206 (e.g., payload data bits) associated with host data (e.g., data for reading or writing to the memory device). In some cases, one or more parity bits 207 (e.g., error control information) associated with supporting error detection and correction may be transmitted concurrently with the transmission of the data bits 206. For example, a UI 205 may include 16 data bits 206 and 1 parity bit 207. Therefore, a total of 256 data bits 206 and 16 parity bits 207 may be transmitted through 16 UIs. In other examples, the data bits 206 and parity bits 207 may be transmitted in different bursts, such that the data bits 206 may be communicated in a single UI 205 and then the parity bits 207 may be communicated in a separate UI 205. In still other examples, the parity bits 207 may not be communicated between the host device and the memory device, but instead the parity bits may be generated and stored by their respective devices (e.g., the host device or the memory device). In some implementations, 1 parity bit 207 may support error detection and correction of 16 data bits 206 associated with a UI 205, or error detection and correction of data bits 206 associated with another of the 16 UIs 205. The host device and the memory device may support dynamic link error control code (ECC) protocol (DLEP) configuration of a channel between the host device and the memory device, such that data bits 206 of UI 205 may be transmitted between the host device and the memory device via a data channel, and one or more parity bits 207 of UI 205 may be transmitted between the host device and the memory device via a dedicated error control channel.

[0041] In some cases, the host device may include an error control engine configured to generate one or more parity bits 207 associated with the data bits 206 and / or associated with the UI 205. The error control engine may use a parity check matrix (e.g., an H matrix) to generate the one or more parity check bits 207 (e.g., first error control information). After the one or more parity check bits 207 have been generated using the parity check matrix, the host device may transmit the data bits 206 as part of the one or more UIs 205 (e.g., 16 UIs) to the memory device. In some cases, the host device may be configured such that the error control engine is coupled with a dedicated error control channel, thereby supporting direct transmission of the one or more parity check bits 207 to and / or from the error control engine via the dedicated error control channel. The one or more data bits 206 received from the host device may be stored to the memory device. The one or more data bits 206 may be transmitted from the memory device back to the host device (e.g., via a data channel and a dedicated error control channel), where an error control engine may generate one or more additional parity bits 207 (e.g., second error control information) corresponding to the data bits 206 received from the memory device. The error control engine may use a parity check matrix to generate the one or more additional parity bits 207. The error control engine may compare the one or more parity bits 207 transmitted to the memory device with the one or more additional parity bits 207 generated based on the UI 205 received from the memory device.

[0042] The error control engine may detect one or more errors in the one or more UIs 205 based on comparing the one or more parity bits 207 with the one or more additional parity bits 207. The error control engine may generate an error code 210, which may indicate the one or more errors in the one or more UIs 205 and the addresses of the one or more errors within the one or more UIs 205. The host device may use the error code 210 to correct or record the one or more errors within the one or more UIs 205. For example, the host device may be able to correct single-bit errors (e.g., one error in the one or more UIs) and detect multi-bit errors (e.g., two or more errors in the one or more UIs). In some implementations, correcting a single-bit error may include determining which bit (e.g., data bit 206 or parity bit 207) of the one or more UIs 205 is responsible for the error and changing the logic value associated with the bit. For example, correcting a single-bit error may include determining an error at the first data bit 206 and flipping the logic value of the first data bit 206 (e.g., from 0 to 1, from 1 to 0). However, in some implementations, due to an inability to determine the exact location of the error in one or more UIs 205, multi-bit errors may be detected but not corrected.

[0043] In some cases, such as Figure 2, the error control engine may detect multi-bit errors (e.g., triple errors) in one or more UIs (e.g., on a single UI error control basis, or as part of performing error control for 16 UIs). For example, the error control engine may detect multi-bit errors in UI 205 based on comparing parity bits 207 generated before transmitting UI 205 to the memory device with additional parity bits 207 generated after receiving UI 205 from the memory device. In some such cases, a conventional parity check matrix (e.g., as used in the previous implementation) may have been used to generate parity bits 207 and additional parity bits 207. The error control engine may generate error code 210 to indicate the multi-bit error in UI 205 to the host device. However, in some cases, error code 210 may overlap with an error code indicating a single-bit error (e.g., which may be at a different location than the triple error), as depicted in UI 215. Therefore, the host device may interpret error code 210 as indicating a single-bit error, rather than a multi-bit error detected by the error control engine. For example, there may be three errors at the first data bit 206-a, the second data bit 206-b, and the third data bit 206-c, as shown in UI 205, but the host device may interpret from error code 210 that there is a single error at the fourth data bit 206-d, as shown in UI 215.

[0044] In some implementations, the host device may use error code 210 to correct the interpreted single-bit error at UI 215 (e.g., due to the host device's ability to correct single-bit errors) even though a multi-bit error was detected in UI 205 (e.g., possibly at different locations in the codeword). For example, correcting the interpreted single-bit error may result in corrected UI 216, as interpreted by the host device. However, in some such implementations, correcting the interpreted single-bit error may result in another error being introduced into UI 205. For example, the host device may flip the logic value at fourth data bit 206-d, as shown in corrected UI 216, thereby causing UI 205 to have four errors at first data bit 206-a, second data bit 206-b, third data bit 206-c, and fourth data bit 206-d, even though fourth data bit 206-d does not include an actual error, as shown in resulting UI 220. Thus, instead of detecting the multi-bit error, the host device may introduce additional errors, as shown in UI 205 , thereby further propagating the multi-bit error, as shown in the resulting UI 220 .

[0045] In some cases, failure to correctly detect multi-bit errors may be disadvantageous. For example, in automotive applications, it may be desirable to have a relatively high error detection rate (e.g., relatively high diagnostic coverage) due to a relatively high number of operating cycles. In some such applications, if multi-bit errors are not correctly detected, the resulting results may include risk or damage to the automotive system or a user of the automotive system. Therefore, a relatively high error detection rate may be coupled with a relatively high number of operating cycles to ensure proper functionality of the automotive system. Therefore, it may be desirable to reduce the likelihood of erroneously detecting multi-bit errors.

[0046] However, according to examples as described herein, the host device may implement an improved parity check matrix (e.g., an H matrix) that may reduce the likelihood of mistaking a multi-bit error for a single-bit error. For example, the improved parity check matrix may be patterned so that when the improved parity check matrix is ​​used to generate one or more parity bits 207 (e.g., generated before transmitting UI 205 to the memory device) and one or more additional parity bits 207 (e.g., generated after receiving UI 205 from the memory device), the error code generated based on the result of comparing the one or more parity bits 207 with the one or more additional parity bits 207 is relatively less likely to be interpreted by the host device as a single-bit error when a multi-bit error occurs (e.g., compared to previous implementations).

[0047] For example, the error control engine may use the improved parity check matrix to generate one or more parity check bits 207 and transmit the one or more UIs to the memory device. The memory device may then transmit the one or more UIs back to the host device, where the error control engine may use the improved parity check matrix to generate one or more additional parity check bits 207. The error control engine may compare the one or more parity check bits 207 with the one or more additional parity check bits 207 and use the comparison result to generate an error code. In some such examples, the error code generated as a result of using the improved parity check matrix to generate the one or more parity check bits 207 and the one or more additional parity check bits 207 may support 100% correction of single-bit errors, 100% detection of double-bit errors, and at least 99.1% detection of triple-bit errors (e.g., with or without a parity check envelope). Thus, implementing an improved parity check matrix as described herein may reduce overlap between erroneous codes, thereby reducing the likelihood of falsely detecting multi-bit errors while also improving error detection of multi-bit errors, among other advantages.

[0048] Figure 3 An example of a parity check matrix 300 supporting a host error control matrix according to an example disclosed herein is illustrated. The parity check matrix 300 may be implemented by the system 100, as described with reference to Figure 1Additionally, parity check matrix 300 may be an example of a parity check matrix used in the operations described in error correction diagram 200, as described with reference to FIG. Figure 2 Parity check matrix 300 may be used to generate codewords (eg, including one or more UIs) having data bits and parity bits, wherein the probability that a multi-bit error in the codeword is mistaken for a single-bit error is relatively reduced.

[0049] Parity check matrix 300 may be used to generate a codeword having a certain number of data bits and one or more parity check bits, which may be examples of data bits 206 and parity check bits 207, as described in reference to Figure 2 As described. For example, parity check matrix 300 illustrates a codeword with 16 UIs, each UI including 16 data bits and one parity bit, for a total of 256 data bits, 15 parity bits, and 1 parity envelope. Each data bit and each parity bit may be configured to store a binary logic value (e.g., 0 or 1). Parity check matrix 300 may be used to generate parity bits, however, each parity bit may or may not support error detection and correction of the data bits of the corresponding UI.

[0050] For example, parity check matrix 300 illustrates a code that may be applied to 16 information bursts (e.g., segments numbered 0 to 15). Each information burst may include 16 unit intervals (UIs) (e.g., columns numbered 0 to 15), where each UI is configured to pass a binary logic value of 0 (e.g., indicated by a blank cell) or 1 (e.g., indicated by an "X") through 16 channels. The parity bits may include 15 parity bits (e.g., rows numbered P0 to P14) and 1 parity wrapper (PW) channel. Parity check matrix 300 also illustrates a parity bit segment that includes a parity bit position for each data channel and a parity wrapper for the parity bits. The parity bit segment may be used in conjunction with the information burst to generate the parity bits for a given codeword, such that each UI may be generated with 16 data bits and 1 parity bit based on the value and position of the data bits. Therefore, the codeword may describe 256 data bits and 15 parity bits, and 1 parity envelope.

[0051] Optimization techniques may be used to generate the parity check matrix 300 to reduce the likelihood that an error code generated for a multi-bit error in a codeword will be mistaken for a single-bit error in the codeword. Figure 2As described in , after comparing the initial parity bits of the codeword (e.g., transmitted to the memory device) with the additional parity bits of the codeword (e.g., received from the memory device) and identifying differences, an error code can be generated based on identifying one or more errors in the codeword. However, due to the use of the parity check matrix 300 to generate the initial parity bits and the additional parity bits, the error codes generated for errors in the codeword can have a relatively reduced overlap for error codes indicating multi-bit errors and error codes indicating single-bit errors. Therefore, when the parity check matrix 300 is used for error detection, the likelihood that a multi-bit error can be interpreted as a single-bit error is reduced.

[0052] Figure 4 An example of a parity check matrix 400 supporting a host error control matrix according to an example disclosed herein is illustrated. The parity check matrix 400 may be implemented by the system 100, as described with reference to Figure 1 Additionally, parity check matrix 400 may be an example of a parity check matrix used in the operations described in error correction diagram 200, as described with reference to FIG. Figure 2 The parity check matrix 400 can be used to generate a codeword having data bits and parity check bits, wherein the probability that a multi-bit error in the codeword is mistaken for a single-bit error is relatively reduced.

[0053] Parity check matrix 400 may be used to generate a codeword having a certain number of data bits and one or more parity check bits, which may be examples of data bits 206 and parity check bits 207, as described with reference to FIG. Figure 2 As described above. For example, parity check matrix 400 illustrates a codeword with 16 UIs, each UI including 16 data bits and one parity bit. Each data bit and each parity bit may be configured to store a binary logic value (e.g., 0 or 1). Parity check bits may be generated using parity check matrix 400 for a given codeword based on the logic values ​​stored in the data bits of the codeword.

[0054] For example, parity check matrix 400 illustrates code that defines error detection logic for 16 parity check bits that detects 100% DBE without the use of a parity check envelope. A binary logic value of 0 indicates no connection (e.g., indicated by a blank cell) or 1 (e.g., indicated by an "X") indicates connection for each parity check bit. For example, parity check bit P0 is decoded from parity check matrix 400 as follows: P0 = UI0DQ0 ^ UI0DQ4 ^ UI0DQ5 ^ UI0DQ6 ^ UI0DQ7 ^ UI0DQ8 ^ UI0DQ11 ^ UI0DQ13 ^ UI0DQ14 ^ UI1DQ0 ^ UI1DQ2 ^ UI1DQ5 ^ UI1DQ9 ^ UI1DQ10 ^ UI1DQ11 ^ UI1DQ12 ^ UI1DQ15 ^ UI2DQ 0^UI2DQ1^UI2DQ2^UI2DQ4^UI2DQ5^UI2DQ6^UI2DQ7^UI2DQ8^UI2DQ12^UI2DQ13^ UI2DQ15^UI3DQ3^UI3DQ7^UI3DQ11^UI3DQ12^UI3DQ13^UI4DQ0^UI4DQ2^UI4DQ5^ UI4DQ6^UI4DQ8^UI4DQ9^UI4DQ11^UI4DQ13^UI5DQ1^UI5DQ3^UI5DQ5^UI5DQ7^UI5DQ8^UI5DQ12^UI6DQ0^UI6DQ1^UI6DQ6^UI6DQ7^UI6DQ10^UI6DQ11^UI6DQ12^UI 6DQ13^UI7DQ1^UI7DQ2^UI7DQ3^UI7DQ4^UI7DQ9^UI7DQ10^UI7DQ12^UI7DQ15^UI 8DQ0^UI8DQ1^UI8DQ2^UI8DQ3^UI8DQ5^UI8DQ7^UI8DQ8^UI8DQ10^UI8DQ12^UI9DQ0^UI9DQ2^UI9DQ3^UI9DQ9^U I9DQ10^UI9DQ12^UI9DQ14^UI9DQ15^UI10DQ4^UI10DQ7^UI10DQ15^UI11DQ1^UI11DQ5^UI11DQ10^UI11DQ11^UI1 1DQ13^UI12DQ2^UI12DQ8^UI12DQ10^UI12DQ13^UI13DQ3^UI13DQ4^UI13DQ9^UI13DQ12^UI13DQ14^UI14DQ1^UI14DQ7^UI14DQ10^UI14DQ12^UI15DQ1^UI15DQ2^UI15DQ3^UI15DQ4^UI15DQ5^UI15DQ9^UI15DQ13; wherein “^” indicates an XOR function.

[0055] Optimization techniques may be used to generate the parity check matrix 400 to reduce the likelihood that an error code generated for a multi-bit error in a codeword will be mistaken for a single-bit error in the codeword. Figure 2 As described in , after comparing the initial parity bits of the codeword (e.g., transmitted to the memory device) with the additional parity bits of the codeword (e.g., received from the memory device) and identifying differences, an error code can be generated based on identifying one or more errors in the codeword. However, due to the use of parity check matrix 400 to generate the initial parity bits and the additional parity bits, the error codes generated for errors in the codeword can have a relatively reduced overlap for error codes indicating multi-bit errors and error codes indicating single-bit errors. Therefore, when parity check matrix 400 is used for error detection, the likelihood that a multi-bit error can be interpreted as a single-bit error is reduced.

[0056] Figure 5 An example of a detection result graph 500 for supporting a host error control matrix according to an example as disclosed herein. The detection result graph 500 may illustrate the result of implementing the parity check matrix 300 in the system 100, as respectively referred to in Figure 3 and 1 For example, detection result graph 500 may depict the results of generating a codeword at an error control engine using parity check matrix 300. Specifically, detection result graph 500 illustrates the difference in error detection capabilities of a system that implements a previous parity check matrix (e.g., uses the previous parity check matrix to generate parity bits for comparison) and a system that implements parity check matrix 300 (e.g., uses parity check matrix 300 to generate parity bits for comparison).

[0057] Detection result graph 500 illustrates on a first axis (e.g., y-axis) the percentage of bit errors detected at a system implementing a previous parity check matrix or parity check matrix 300 for a number of bit errors represented along a second axis (e.g., x-axis). For example, detection result graph 500 illustrates that a system implementing a previous parity check matrix may have the ability to detect 100% of single-bit errors, and a system implementing parity check matrix 300 may have the ability to detect 100% of single-bit errors. In some cases, implementing a system such as reference Figure 4The system of the described parity check matrix 400 may have the ability to detect 100% of double bit errors. Similarly, the detection result graph 500 illustrates that the system implementing the previous parity check matrix may have the ability to detect 97.8% of double bit errors, and the system implementing the parity check matrix 300 may have the ability to detect 100% of double bit errors. In some cases, the system implementing the parity check matrix 400 may have the ability to detect 100% of double bit errors. In addition, the detection result graph 500 illustrates that the system implementing the previous parity check matrix may have the ability to detect 91.5% of three-bit errors, and the system implementing the parity check matrix 300 may have the ability to detect 99.18% of three-bit errors. In some cases, the system implementing the parity check matrix 400 may have the ability to detect 99.21% of three-bit errors. In some cases, the system implementing the previous parity check matrix may have a total diagnostic coverage of 99.54% (e.g., the ability to detect any number of errors), however, the system implementing the parity check matrix 300 may have a total diagnostic coverage of 99.61%. In some cases, a system implementing parity check matrix 400 may have an overall diagnostic coverage of 99.59%.

[0058] In some cases, due to the relatively high detection rate of double-bit errors and triple-bit errors, it may be advantageous to implement parity check matrix 300 (e.g., or parity check matrix 400). For example, in automotive applications, due to the relatively high number of operating cycles, it may be desirable to have a relatively high error detection rate (e.g., relatively high diagnostic coverage). In some such applications, if multi-bit errors are not correctly detected, the results may include risk or damage to the automotive system or the user of the automotive system. Therefore, the relatively high error detection rate of parity check matrix 300 (e.g., or parity check matrix 400) can be coupled with a relatively high number of operating cycles to ensure proper functionality of the automotive system.

[0059] Figure 6 A block diagram 600 illustrates a host device 620 supporting a host error control matrix according to examples as disclosed herein. The host device 620 may be a Figures 1 to 5 6. The host device 620 or its various components may be examples of means for performing various aspects of the host error control matrix as described herein. For example, the host device 620 may include a generation component 625, a transmission component 630, a reception component 635, a comparison component 640, a determination component 645, a correction component 650, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0060] The generating component 625 may be configured to or otherwise support means for generating error control information by an error control engine of a host device by applying a parity check matrix to data for storage in a memory device, the parity check matrix being used to reduce the probability that the value of the error control information is associated with both a single-bit error condition and a multi-bit error condition. The transmitting component 630 may be configured to or otherwise support means for transmitting data to a memory device through one or more data channels and a channel-specific error control channel transmitting error control information to the memory device based at least in part on generating the error control information. The receiving component 635 may be configured to or otherwise support means for receiving data from a memory device through one or more data channels and receiving error control information from the memory device through a dedicated error control channel based at least in part on transmitting the data and the error control information. In some examples, the generating component 625 may be configured to or otherwise support means for generating second error control information at the error control engine by applying a parity check matrix to data received from the memory device.

[0061] In some examples, comparison component 640 can be configured or otherwise support means for comparing the error control information to the second error control information based at least in part on generating the second error control information.

[0062] In some examples, generation component 625 can be configured or otherwise support means for generating an error code based at least in part on comparing the error control information to the second error control information.

[0063] In some examples, determination component 645 can be configured or otherwise support means for determining whether an error in the data is a single-bit error or a multi-bit error based at least in part on a value of an error code.

[0064] In some examples, correction component 650 can be configured or otherwise support means for correcting errors in the data based at least in part on determining that the errors in the data are single-bit errors.

[0065] In some examples, determination component 645 can be configured or otherwise support means for determining that an error in the data is a multi-bit error.

[0066] In some examples, the error codes are configured to indicate a triple error instead of a single-bit error.

[0067] In some examples, the data includes 256 bits and the error control information includes 16 parity bits corresponding to the 256 bits.

[0068] Figure 7The description shows a flow chart of a method 700 for supporting a host error control matrix according to an example as disclosed herein. The operations of the method 700 may be implemented by a host device or components thereof as described herein. For example, the operations of the method 700 may be implemented by a host device or components thereof as described herein. Figures 1 to 6 The host device described herein may be executed by the host device. In some examples, the host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

[0069] At 705, the method may include generating, by an error control engine of a host device, error control information by applying a parity check matrix to data for storage in a memory device, the parity check matrix being used to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition. The operations of 705 may be performed according to examples as disclosed herein. In some examples, the operations of 705 may be performed by an error control engine as described in reference to Figure 6 Aspects of the operations of generating component 625 performing 705 are described.

[0070] At 710, the method may include transmitting data to a memory device through one or more data channels and transmitting error control information to the memory device through a dedicated error control channel based at least in part on generating error control information. The operation of 710 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by a memory device as described in reference to Figure 6 The transport component 630 is described to perform aspects of the operations of 710 .

[0071] At 715, the method may include receiving data from the memory device through one or more data channels and receiving error control information from the memory device through a dedicated error control channel based at least in part on the transmission data and the error control information. The operation of 715 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by a memory device as described in reference to Figure 6 Aspects of the operations of receiving component 635 performing 715 are described.

[0072] At 720, the method may include generating second error control information at an error control engine by applying a parity check matrix to data received from a memory device. The operation of 720 may be performed according to examples as disclosed herein. In some examples, the operation may be performed by a processor as described in reference to Figure 6 Aspects of the operations of the generation component 625 performing 720 are described.

[0073] In some examples, an apparatus as described herein may perform one or several methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0074] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions for each of the following, or any combination thereof: generating error control information by an error control engine of a host device by applying a parity check matrix to data for storage in a memory device, the parity check matrix being used to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition; transmitting the data to the memory device through one or more data channels and transmitting the error control information to the memory device through a dedicated error control channel based at least in part on generating the error control information; receiving the data from the memory device through the one or more data channels and receiving the error control information from the memory device through the dedicated error control channel based at least in part on transmitting the data and the error control information; and generating second error control information at the error control engine by applying the parity check matrix to the data received from the memory device.

[0075] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for comparing the error control information with the second error control information based at least in part on generating the second error control information.

[0076] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for generating an error code based at least in part on comparing the error control information with the second error control information.

[0077] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of Aspect 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining whether an error in the data is a single-bit error or a multi-bit error based at least in part on the value of the error code.

[0078] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of Aspect 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for correcting the error in the data based at least in part on determining that the error in the data is a single-bit error.

[0079] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 4 to 5, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for determining that the error in the data is a multi-bit error.

[0080] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of aspect 6, wherein the error code is configured to indicate a triple error instead of a single-bit error.

[0081] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any one of aspects 1 to 7, wherein the data comprises 256 bits and the error control information comprises 16 parity bits corresponding to the 256 bits.

[0082] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0083] An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

[0084] Aspect 9: An automotive memory system comprising: a memory device comprising a plurality of memory cells configured to store data; and a host system coupled to the memory device and configured to transfer data through one or more data channels and to transfer error control information through a dedicated error control channel, the host system further comprising: an error control engine implementing a parity check matrix configured to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition.

[0085] Aspect 10: The automotive memory system of aspect 9, wherein the error control engine is configured to use the error control information to detect one or more errors in the data and to generate an error code based on detecting the one or more errors in the data.

[0086] Aspect 11: The automotive memory system of aspect 10, wherein the error control engine is configured to determine whether the error in the data is a single-bit error or a multi-bit error based at least in part on a value of the error code.

[0087] Aspect 12: The automotive memory system of aspect 11, wherein the parity check matrix is ​​configured to provide a 100% error correction rate based on determining that the error in the data is a single-bit error.

[0088] Aspect 13: The automotive memory system according to any one of aspects 11 to 12, wherein the parity check matrix is ​​configured to provide a 100% rate of detecting that the error in the data is a double-bit error.

[0089] Aspect 14: The automotive memory system of any one of aspects 11 to 13, wherein the parity check matrix is ​​configured to provide at least a 99.1% rate of detecting that the error in the data is a three-bit error.

[0090] Aspect 15: The automotive memory system according to any one of aspects 11 to 14, wherein the data comprises 256 bits and the error control information comprises 16 parity bits corresponding to the 256 bits.

[0091] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0092] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with (e.g., in conductive contact with, connected to, coupled to) each other if there is any electrical path (e.g., a conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, the conductive paths between components that are in electronic communication with (e.g., in conductive contact with, connected to, coupled to) each other may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0093] The term "coupled" (e.g., "electrically coupled") may refer to moving from an open circuit relationship between components, where signals cannot currently be passed between the components (e.g., through a conductive path), to a closed circuit relationship between the components, where signals can be passed between the components (e.g., through a conductive path). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components through conductive paths that previously did not permit signal flow.

[0094] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conduction path that previously permitted the signal to flow.

[0095] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0096] The switch components (e.g., transistors) discussed herein may represent field effect transistors (FETs) and may include a three-terminal component including a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components by conductive materials (e.g., metals, alloys). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by doped (e.g., lightly doped) semiconductor regions or channels. If the channel is n-type (e.g., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0097] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein is intended to mean "serving as an example, instance, or illustration" rather than "preferred" or "advantageous over other examples." The detailed description includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0098] In the drawings, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label without regard to the second reference label.

[0099] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions (e.g., code) on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0100] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a processor designed to perform the functions described herein (e.g., a DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof). A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0101] As used herein, "or" as used in a list of items (for example, a list of items preceded by a phrase such as "at least one of..." or "one or more of...") in the claims includes indicating an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0102] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0103] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: generating, by an error control engine of the host device, error control information by applying a parity check matrix to data for storage in the memory device, the parity check matrix being used to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition; transmitting the data to the memory device over one or more data channels and transmitting the error control information to the memory device over a dedicated error control channel based at least in part on generating the error control information; receiving the data from the memory device over the one or more data channels and receiving the error control information from the memory device over the dedicated error control channel based at least in part on transmitting the data and the error control information; and Second error control information is generated at the error control engine by applying the parity check matrix to the data received from the memory device.

2. The method according to claim 1, further comprising: The error control information is compared to the second error control information based at least in part on generating the second error control information.

3. The method according to claim 2, further comprising: An error code is generated based at least in part on comparing the error control information to the second error control information.

4. The method according to claim 3, further comprising: A determination is made based at least in part on the value of the error code whether the error in the data is a single-bit error or a multi-bit error.

5. The method according to claim 4, further comprising: The error in the data is corrected based at least in part on determining that the error in the data is a single-bit error.

6. The method according to claim 4, further comprising: The error in the data is determined to be a multi-bit error.

7. The method of claim 6, wherein the error code is configured to indicate a triple error instead of a single-bit error.

8. The method of claim 1, wherein the data comprises 256 bits and the error control information comprises 16 parity bits corresponding to the 256 bits.

9. An automotive memory system, comprising: a memory device comprising a plurality of memory cells configured to store data; and a host system coupled to the memory device and configured to communicate data through one or more data channels and error control information through a dedicated error control channel, the host system further comprising: An error control engine implements a parity check matrix configured to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition.

10. The automotive memory system of claim 9, wherein the error control engine is configured to use the error control information to detect one or more errors in the data and to generate an error code based on detecting the one or more errors in the data.

11. The automotive memory system of claim 10, wherein the error control engine is configured to determine whether an error in the data is a single-bit error or a multi-bit error based at least in part on a value of the error code.

12. The automotive memory system of claim 11, wherein the parity check matrix is ​​configured to provide a 100% error correction rate based on determining that the error in the data is a single-bit error.

13. The automotive memory system of claim 11, wherein the parity check matrix is ​​configured to provide a 100% rate of detecting that the error in the data is a double bit error.

14. The automotive memory system of claim 11, wherein the parity check matrix is ​​configured to provide at least a 99.1% rate of detecting that the errors in the data are triple errors. 15 . The automotive memory system of claim 11 , wherein the data includes 256 bits and the error control information includes 16 parity bits corresponding to the 256 bits.

16. An apparatus comprising: a controller associated with a host device, wherein the controller is configured to cause the apparatus to: generating, by an error control engine of the host device, error control information by applying a parity check matrix to data for storage in a memory device, the parity check matrix being used to reduce the likelihood that a value of the error control information is associated with both a single-bit error condition and a multi-bit error condition; transmitting the data to the memory device over one or more data channels and transmitting the error control information to the memory device over a dedicated error control channel based at least in part on generating the error control information; receiving the data from the memory device over the one or more data channels and receiving the error control information from the memory device over the dedicated error control channel based at least in part on transmitting the data and the error control information; and Second error control information is generated at the error control engine by applying the parity check matrix to the data received from the memory device.

17. The apparatus of claim 16, wherein the controller is further configured to cause the apparatus to: The error control information is compared to the second error control information based at least in part on generating the second error control information.

18. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to: An error code is generated based at least in part on comparing the error control information to the second error control information.

19. The apparatus of claim 18, wherein the controller is further configured to cause the apparatus to: A determination is made based at least in part on the value of the error code whether the error in the data is a single-bit error or a multi-bit error.

20. The apparatus of claim 19, wherein the controller is further configured to cause the apparatus to: The error in the data is corrected based at least in part on determining that the error in the data is a single-bit error.

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