Interface circuits and systems for neural signal reception

Abstract

This disclosure proposes an interface circuit and system for receiving neural signals. The interface circuit for receiving neural signals includes a first clock domain, a second clock domain, and a memory. The first clock domain receives neural signals acquired from multiple channels. The first clock domain uses a lower sampling frequency to acquire the corresponding neural signals. The lower sampling frequency reduces the power consumption of the interface circuit, thereby avoiding inaccurate neural signals due to temperature increases during signal acquisition. Furthermore, the second clock domain integrates the signals from the first clock domain to obtain high-speed neural signals. Therefore, the combination of the first and second clock domains achieves low-power, high-speed sampling of neural signals, improving the accuracy of the neural signals.

Description

Technical Field

[0001] This disclosure relates to the field of information processing technology, and specifically to an interface circuit and system for receiving neural signals. Background Technology

[0002] Acquiring neural signals and simultaneously recording the electrical activity of neurons in multiple brain regions helps in understanding brain function. Decoding neural potentials can reveal the relationship between the coordinated activity and behavior of ensembles of neurons. Precise decoding of neural activity relies on neural signals with high spatiotemporal resolution, and invasive acquisition devices are a commonly used method for obtaining these signals.

[0003] However, living organisms are highly sensitive to the heat generated by invasive implants used in invasive acquisition devices, and the heat generated by these devices is related to their power consumption; higher power consumption results in more heat generation. In order to achieve low power consumption, neural signal acquisition devices in related technologies have reduced the number of acquisition channels or lowered the sampling frequency, thus failing to meet the requirements for high spatiotemporal resolution. Summary of the Invention

[0004] This disclosure proposes an interface circuit and system for receiving neural signals.

[0005] The first aspect of this disclosure provides an interface circuit for receiving neural signals, characterized in that the interface circuit includes a first clock domain, a second clock domain, and a memory, wherein the first clock domain is connected to the second clock domain, the second clock domain is connected to the memory, and the sampling frequency of the first clock domain is lower than the sampling frequency of the second clock domain.

[0006] The first clock domain is used to acquire neural signals from the subject through acquisition electrodes;

[0007] The second clock domain is used to acquire the neural signals from the first clock domain and store the neural signals in the memory.

[0008] In this embodiment of the disclosure, the interface circuit further includes a signal processing unit, the output of which is connected to the inputs of the first clock domain and the second clock domain respectively, for generating a clock signal of a preset target frequency so as to synchronize the sampling frequencies of the first clock domain and the second clock.

[0009] In this embodiment of the disclosure, the interface circuit further includes a synchronization register, the output of the first clock domain is the input of the synchronization register, the output of the synchronization register is the input of the second clock domain, and the synchronization register is used to merge the parallel multi-channel neural signals output from the first clock domain into a serial neural signal.

[0010] In this embodiment of the disclosure, the interface circuit further includes acquisition electrodes for acquiring neural signals from the subject.

[0011] In this embodiment of the disclosure, the interface circuit further includes a filter and an analog-to-digital converter. The filter is located between the sampling electrode and the first clock domain, and the analog-to-digital converter is connected to the first clock domain after the filter.

[0012] The filter is used to filter the neural signals acquired by the sampling electrodes before transmitting them to the filter.

[0013] The analog-to-digital converter is used to convert the received signal and transmit the resulting digital signal to the first clock domain.

[0014] In this embodiment of the disclosure, the interface circuit further includes a wireless transmission unit connected to the memory for transmitting neural signals from the memory to the analysis platform.

[0015] In this embodiment of the disclosure, the interface circuit further includes a power supply, which is used to supply power to each unit in the interface circuit and to regulate the power supply of each power supply.

[0016] An embodiment of the second aspect of this disclosure provides a neural signal receiving and analysis system, including an interface circuit and analysis device for neural signal receiving as described in the first aspect above. The analysis device includes a wireless transmission unit, a signal analysis unit, and a display unit.

[0017] The wireless transmission unit is used to receive neural signals sent by the interface circuit through the wireless transmission unit.

[0018] The signal analysis unit is used to analyze the neural signals;

[0019] The display unit is used to display the analysis results.

[0020] The technical solutions provided in this disclosure have at least the following technical effects or advantages:

[0021] The interface circuit for receiving neural signals includes a first clock domain, a second clock domain, and a memory. The first clock domain receives neural signals acquired from multiple channels. It uses a lower sampling frequency to acquire the corresponding neural signals, reducing power consumption and preventing inaccurate neural signal acquisition due to temperature increases during signal acquisition. Furthermore, the second clock domain integrates the signals from the first clock domain to obtain high-speed neural signals. Therefore, the combination of the first and second clock domains achieves low-power, high-speed sampling of neural signals, improving their accuracy.

[0022] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of this disclosure. Attached Figure Description

[0023] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0024] In the attached diagram:

[0025] Figure 1 A schematic diagram of an interface circuit for receiving neural signals provided in an embodiment of this disclosure is shown;

[0026] Figure 2 A schematic diagram of data acquisition for an interface circuit for receiving neural signals provided in an embodiment of this disclosure is shown.

[0027] Figure 3 A schematic diagram of a neural signal receiving and analysis system provided in an embodiment of this disclosure is shown;

[0028] Figure 4 A schematic diagram of a neural signal receiving and analysis system provided in an embodiment of this disclosure is shown. Detailed Implementation

[0029] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0030] It should be noted that, unless otherwise stated, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0031] High-density neural signal acquisition plays a crucial role in neuroscience research. Simultaneously recording the electrical activity of neurons in multiple brain regions helps to gain deeper insights into brain function. Decoding neural potentials reveals the relationship between the coordinated activity of ensembles of neurons and behavior. As the number of channels increases, high-density recording techniques enable researchers to explore the spatiotemporal dynamics and connectivity patterns of neural networks, thereby advancing our understanding of sensory, motor, and cognitive processes.

[0032] High-resolution and high-density neural signals can decode complex brain-computer interface tasks. For example, restoring dexterous user movements, such as high-degree-of-freedom hand movements, or fine motor skills, such as handwriting or language abilities, requires recordings from hundreds of electrodes. This large-scale recording provides crucial data for understanding the self-organization and dysfunction of neural networks, supporting the development of clinical applications. High anatomical spatial coverage and high temporal resolution are key features for acquiring precise cap structures and analyzing complex neural activity.

[0033] Biological organisms are sensitive to the heat generated by invasive implants used for data acquisition, increasing the demand for compact, low-power chips. Neural Tree SoCs offer ultra-low sampling power and chip area, and their high channel count enables finger motion classification. However, their limited sampling rate of only 2,000 samples per second (sps) and lack of high-bandwidth action potential recording capabilities restrict their application in complex tasks such as motion decoding. AIC's 512-channel data acquisition device achieves a sampling rate of 30 ksps and can detect action potentials and field potentials, theoretically enabling sophisticated neural decoding, but its 125 milliwatt power consumption limits its application in brain implants. Related technologies also include a neural signal processor with an integrated on-chip neural network accelerator, supporting direct on-chip decoding, but its application is limited by its 16 channels. Furthermore, wired connections increase the risk of infection and restrict the freedom of the tested object, while wireless data transmission can enhance device flexibility and reduce the overall interface size.

[0034] In view of this, embodiments of the present disclosure propose an interface circuit for receiving neural signals, such as... Figure 1 As shown, it includes a first clock domain 101, a second clock domain 102, and a memory 103. The first clock domain 101 is connected to the second clock domain 102, and the second clock domain 102 is connected to the memory 103. The sampling frequency of the first clock domain 101 is lower than the sampling frequency of the second clock domain 102. The first clock domain 101 is used to acquire the neural signals of the subject through acquisition electrodes. The second clock domain 102 is used to acquire the neural signals of the first clock domain 101 and store the neural signals in the memory 103.

[0035] The first clock domain 101 and the second clock are combined to realize multi-channel low-power high-speed neural signal sampling. In this embodiment, 128-channel neural signal sampling is realized.

[0036] The interface circuit further includes a signal processing unit. The output of the signal processing unit is connected to the inputs of the first clock domain 101 and the second clock domain 102, respectively, to generate a clock signal with a preset target frequency, so as to synchronize the sampling frequencies of the first clock domain 101 and the second clock domain. The signal processing unit can be a voltage-controlled oscillator with an input reference noise of 0.66μVrms in the range of 0.5-60Hz.

[0037] It also includes a synchronization register, the output of the first clock domain 101 is the input of the synchronization register, and the output of the synchronization register is the input of the second clock domain 102. The synchronization register is used to combine the parallel multi-channel neural signals output by the first clock domain 101 into a serial neural signal.

[0038] The interface circuit also includes acquisition electrodes for acquiring neural signals from the subject. It can simultaneously acquire 128 points, supports 16-bit resolution and a maximum acquisition rate of 32 ksps, with a power consumption of 3.43 mW and an area of ​​6.27 mm². 2 Compared to previously reported technologies, it achieves the lowest normalized energy consumption of 0.84 μW / ch / ksps.

[0039] The interface circuit further includes a filter and an analog-to-digital converter (ADC). The filter is located between the sampling electrode and the first clock domain 101. The ADC is connected to the first clock domain 101 after the filter. The filter is used to filter the neural signals acquired by the sampling electrode before transmitting them to the filter. The ADC is used to convert the received signal into a digital signal before transmitting it to the first clock domain 101. The filter can be an on-chip CIC filter, which can eliminate out-of-band noise, reduce the impact on neural signals, and improve the accuracy of the acquired signals. In this embodiment, the interface circuit is implanted into the cerebral cortex of the subject and can measure its electrocorticography (ECoG) signals.

[0040] The interface circuit also includes a wireless transmission unit connected to the memory 103 for transmitting neural signals from the memory 103 to the analysis platform. The wireless transmission unit can be a Wi-Fi module connected to the recorder circuit via a QSPI interface, enabling wireless control and data transmission. The interface circuit also includes a power supply for powering and regulating the power supply to each unit in the interface circuit. Electrodes are connected to the neural acquisition sites. The acquired neural signals are quantized into 16-bit digital signals by a VCO. The acquired signals are temporarily stored in an on-chip FIFO by the data control unit. The Wi-Fi module reads the signals from the FIFO via a QSPI serial interface and wirelessly transmits the data to the host for further processing.

[0041] The first clock domain 101 is a slow sampling clock domain, and the second clock domain 102 is a high-speed data transmission clock domain. 16-bit data from 128 channels is acquired on the rising edge of the sampling clock in each slow sampling clock domain. Depending on the configuration, the data can be filtered by a CIC filter or output directly. A synchronization register facilitates the synchronization of data from the slow clock domain to the high-speed clock domain. In the high-speed clock domain, the data control unit updates the synchronization register, sequentially scanning data from all 128 channels. This process converts the parallel data obtained from the 128 channels into serial data. The serial data is then written into a FIFO. Figure 2 As shown, to ensure that data from different sampling periods is correctly identified, a frame identifier is written into the FIFO before the data from channel 1 at the rising edge of each sampling clock. This allows the system to clearly describe the start point of data for each channel. The frame identifier increments by 1 after each full cycle of 128 channels. The frame identifier also serves as a frame counter to detect any packet loss during off-chip data decoding.

[0042] A sine wave signal can be used as the input to 128 channels, and a logic analyzer can be used to read the QSPI output to verify the accuracy of the data stream. The power consumption is 3.43mW at 32ksps. In this verification, the power consumption per thousand samples per channel (power / ch / ksps) was used as a normalized metric to evaluate neural interface characteristics with varying power efficiencies. This normalization allows for a fair comparison of systems with different numbers of channels and sampling rates. Table 1 compares the acquisition chips in embodiments of this disclosure with those in related technologies.

[0043]

[0044] Embodiments of this disclosure propose a neural signal receiving and analysis system, such as Figure 3 As shown, the device includes an interface circuit 301 for receiving neural signals and an analysis device 302, wherein the analysis device 302 includes a wireless transmission unit 3021, a signal processing unit 3022, and a display unit 3023.

[0045] The wireless transmission unit 3021 is used to receive neural signals transmitted by the interface circuit through the wireless transmission unit; the signal analysis unit 3022 is used to analyze the neural signals; and the display unit 3023 is used to display the analysis results.

[0046] like Figure 4The diagram shown is a schematic representation of a specific example of the aforementioned neural signal receiving and analysis system. The voltage-controlled oscillator (VCO) serves as the signal processing unit; the digital quantizer converts continuous analog signals into discrete digital signals; the multiplexer (MUX) selects one of multiple input signals and transmits it to a single output electronic device or circuit; the filter (CIC) removes noise from the received neural signals; and the synchronizer ensures that the data transmission frequencies between the first and second clock domains are the same. The acquired neural signals are then processed by the data control unit and stored in a Ping-Pong FIFO memory. Finally, the wireless transmission unit (WIFI Module) reads the neural signals stored in the memory via QSPI and sends them to the analysis device. The analysis device can analyze, process, and display the neural signals.

[0047] It should be noted that:

[0048] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known structures and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0049] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this disclosure, various features of this disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting a schematic diagram in which the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this disclosure.

[0050] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this disclosure and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0051] The above description is merely a preferred embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An interface circuit for neural signal reception, characterized by, The interface circuit comprises a first clock domain, a second clock domain and a memory, the first clock domain is connected with the second clock domain, the second clock domain is connected with the memory, the sampling frequency of the first clock domain is less than the sampling frequency of the second clock domain, wherein the first clock domain is configured to collect signals at a low sampling frequency to reduce power consumption, thereby avoiding the influence of heat generated by the interface circuit on the accuracy of neural signals; the second clock domain is configured to integrate and transmit the neural signals from the first clock domain at a high sampling frequency; the interface circuit is used for receiving the neural signals of the brain collected invasively; The first clock domain is used for obtaining the neural signals of the measured object through the acquisition electrode; The second clock domain is used for obtaining the neural signals of the first clock domain and storing the neural signals into the memory; The signal processing unit is connected with the inputs of the first clock domain and the second clock domain respectively, and is used for generating a clock signal of a preset target frequency, so as to synchronize the sampling frequencies of the first clock domain and the second clock.

2. The interface circuit of claim 1, wherein, The interface circuit further comprises a synchronization register, the output of the first clock domain is the input of the synchronization register, the output of the synchronization register is the input of the second clock domain, and the synchronization register is used for merging the parallel multi-channel neural signals output by the first clock domain into serial neural signals.

3. The interface circuit of claim 1, wherein, The interface circuit further comprises an acquisition electrode used for collecting the neural signals of the measured object.

4. The interface circuit of claim 3, wherein, The interface circuit further comprises a filter and an analog-to-digital converter, the filter is between the acquisition electrode and the first clock domain, and the analog-to-digital converter is connected with the first clock domain after the filter, The filter is used for transmitting the neural signals obtained by the acquisition electrode after filtering processing; The analog-to-digital converter is used for converting the received signals and transmitting the obtained digital signals to the first clock domain.

5. The interface circuit of claim 1, wherein, The interface circuit further comprises a wireless transmission unit connected with the memory, and is used for sending the neural signals in the memory to an analysis platform.

6. The interface circuit of claim 1, wherein, The interface circuit further comprises a power supply, which is used for supplying power to each unit in the interface circuit and adjusting the power supply of each power supply.

7. A neural signal receiving and analyzing system, comprising the interface circuit for receiving neural signals according to any one of claims 1 to 6 and an analysis device, wherein the analysis device comprises a wireless transmission unit, a signal processing unit and a display unit, The wireless transmission unit is used for receiving the neural signals sent by the interface circuit through the wireless transmission unit; The signal processing unit is used for analyzing the neural signals; The display unit is used for displaying the results after analysis.

Images