Method, device, processor and equipment for generating grid chart of multi-level butterfly operation

Abstract

The embodiment of the invention relates to a method and device for generating a grid chart of multi-level butterfly operation, a processor and computing equipment. The method comprises the following steps: firstly, acquiring a group of input data from a digital signal, and representing a serial number of the input data by using a binary bit sequence; the method then determines output data corresponding to the input data and represents a sequence number of the output data with a bit sequence in a process of processing the set of input data by a multi-level butterfly operation. Further, the method establishes a grid map with the bit sequence of the input data and the bit sequence of the output data such that a life cycle of a product of bits in the bit sequence of the input data and bits in the bit sequence of the output data is represented by grids in the grid map.

Description

Technical Field

[0001] The embodiments of the present specification generally relate to the field of digital signal processing, and more specifically to a method, apparatus, processor, and computing device for generating a grid diagram of a multi-stage butterfly operation. Background Art

[0002] Butterfly operation is a calculation method based on Fast Fourier Transform (FFT) and Fast Number Theoretic Transform (NTT). Butterfly operation can reduce the complexity of the transformation process through in-situ operation and recursion, so it has a wide range of applications in digital signal processing, image processing, communication, chip encryption and other fields.

[0003] In polynomial multiplication, transformations such as FFT and NTT are the most critical steps. Given the characteristics of complex unit roots, transformations such as FFT and NTT based on butterfly operations can convert the multiplication of two polynomials into the multiplication result of the points in corresponding positions. Therefore, how to show the change of points and point multiplication operations during the transformation process becomes the key to improving the interpretability of transformations such as FFT and NTT. Summary of the invention

[0004] The embodiments of the present specification provide a method, apparatus, processor, and computing device for generating a grid diagram of a multi-stage butterfly operation.

[0005] In a first aspect of the present specification, a method for generating a grid diagram of a multi-stage butterfly operation is provided. The method includes obtaining a first bit sequence of first data for the multi-stage butterfly operation from a digital signal, the first bit sequence indicating the sequence number of the first data in a plurality of first data for the multi-stage butterfly operation. The method also includes generating a grid diagram associated with a first bit in the first bit sequence and a second bit in a second bit sequence, the second bit sequence indicating the sequence number of the second data in a plurality of second data after the multi-stage butterfly operation, and the grid in the grid diagram indicating the life cycle of the product of the corresponding first bit and the second bit in the multi-stage butterfly operation.

[0006] In a second aspect of the present specification, a device for generating a grid diagram of a multi-stage butterfly operation is provided. The device includes a first bit sequence acquisition module, configured to acquire a first bit sequence of first data for multi-stage butterfly operation from a digital signal, the first bit sequence indicating the sequence number of the first data in a plurality of first data for multi-stage butterfly operation. The device also includes a grid diagram generation module, configured to generate a grid diagram related to a first bit in the first bit sequence and a second bit in the second bit sequence, the second bit sequence indicating the sequence number of the second data in a plurality of second data after multi-stage butterfly operation, and a grid in the grid diagram indicating the life cycle of the product of the corresponding first bit and the second bit in the multi-stage butterfly operation.

[0007] In a third aspect of the present specification, a processor is provided, which is configured to execute the method according to the first aspect of the present specification.

[0008] In a fourth aspect of the present specification, a computing device is provided. The computing device includes a memory. The computing device also includes a processor according to the third aspect of the present specification.

[0009] It should be understood that the contents described in the Summary of the Invention are not intended to limit the key or important features of the embodiments of this specification, nor are they intended to limit the scope of this disclosure. Other features of this specification will become easy to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present specification will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0011] Figure 1 A schematic diagram illustrating an example environment in which some embodiments of the present specification may be implemented;

[0012] Figure 2 A flowchart showing a method for generating a grid diagram of a multi-stage butterfly operation according to some embodiments of the present specification;

[0013] Figure 3 A schematic diagram showing the process of butterfly operation in some embodiments of the present specification;

[0014] Figure 4 A schematic diagram showing a process of multi-stage butterfly operation in some embodiments of the present specification;

[0015] Figure 5 A schematic diagram showing a grid diagram of a multi-stage butterfly operation according to some embodiments of the present specification;

[0016] Figure 6A schematic diagram showing another grid diagram of multi-stage butterfly operations according to some embodiments of the present specification;

[0017] Figure 7 A combined diagram of a schematic diagram and a grid diagram showing a process of multi-stage butterfly operations according to some embodiments of the present specification; and

[0018] Figure 8 A schematic block diagram of a computing device is shown that illustrates some embodiments of the present description.

[0019] Throughout the drawings, the same or similar reference numbers denote the same or similar elements. DETAILED DESCRIPTION

[0020] The embodiments of the present specification will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present specification are shown in the accompanying drawings, it should be understood that the present specification can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present specification. It should be understood that the drawings and embodiments of the present specification are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0021] In the description of the embodiments of this specification, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] As mentioned above, how to display the point changes and point multiplication operations in the transformation process of FFT and NTT is the key to improving the interpretability of the transformation process. In order to improve the interpretability of the transformation, the relevant technology uses data flow to represent all operations in the transformation process, so as to represent the multiplication operations in each level of butterfly operation. However, this method is only applicable to situations with low point numbers. When the point number is too high, the data flow representation diagram is too complicated and lacks the scalability of high point number representation. The relevant technology also uses formulas, matrices, binary trees, and triangular rectangles to represent situations with high point numbers. However, this method can only represent high point numbers and lacks specific data flow information, which makes it inconvenient to read. Therefore, the representation method in the relevant method cannot take into account both scalability and readability.

[0023] To this end, a method for generating a grid diagram of a multi-stage butterfly operation is provided in an embodiment of the present specification. First, a set of input data is obtained from a digital signal, and a binary bit sequence is used to represent the sequence number (i.e., the number of points) of the input data. Then, in the process of processing the set of input data through a multi-stage butterfly operation, the output data corresponding to the input data is determined and the sequence number of the output data is represented by a bit sequence. Further, a grid diagram is established with the bit sequence of the input data (as one dimension) and the bit sequence of the output data (as another dimension), so that the grid in the grid diagram represents the life span of the product of the bit in the bit sequence of the input data and the bit in the bit sequence of the output data.

[0024] In this way, the sequence number of the input data can be converted into a bit sequence, so that the high sequence number can be represented by the bit sequence of the low digit, which improves the scalability of the transformation process. And the grid in the grid diagram can be used to represent the life cycle of the product of the bit of the input data sequence number and the bit of the output data sequence number, thereby covering the flow information of the bit product from low to high, revealing the operation essence behind each level of butterfly operation, and improving the richness of information and the convenience of reading. Therefore, the embodiments of this specification can take into account the scalability and readability of the multi-level butterfly operation interpretation.

[0025] Figure 1 A schematic diagram of an example environment 100 is shown in which some embodiments of the present specification may be implemented. Figure 1 , the example environment 100 includes a computing device 102, which includes but is not limited to a communication device, a computing chip, a computing system, a single server, a distributed server, or a cloud-based server. In some embodiments, the computing device 102 can be used as a communication device to perform FFT transformation, thereby converting a digital signal from the time domain to the frequency domain. Alternatively or additionally, the computing device 102 can be used as a fully homomorphic hardware acceleration chip to perform NTT transformation, thereby accelerating the polynomial multiplication of digital signals under a finite field during encryption.

[0026] In some embodiments, the computing device 102 may determine an input data group 104 (which may be referred to as a plurality of first data), for example, 16 input data, based on a digital signal, and iteratively calculate an output data group 114 (which may be referred to as a plurality of second data) through a multi-stage butterfly operation 106. The multi-stage butterfly operation 106 includes a 0-stage butterfly operation 108, a 1-stage butterfly operation 110, ..., an n-1-stage butterfly operation 112, where n is an integer greater than 1. It should be understood that based on the characteristics of the butterfly operation in the FFT operation or the NTT operation, the number of input data in the input data group 104 and the number of output data in the output data group 106 are both N=2. n .

[0027] In some embodiments, the computing device 102 may determine the bits existing in each stage of the butterfly operation during the multi-stage butterfly operation 106, wherein the existing bits include: bits in a bit sequence (which may be referred to as a first bit sequence) representing the sequence number of the input data, and bits in a bit sequence (which may be referred to as a second bit sequence) representing the sequence number of the output data. The existing bits 116 in the multi-stage butterfly operation 106 include: surviving level 0 bits 118 in the level 0 butterfly operation 108, surviving level 1 bits 120 in the level 1 butterfly operation 110, and surviving level n-1 bits 122 in the level n-1 butterfly operation 112.

[0028] Then, the computing device 102 can establish the grid map 124 according to the bits that survive each level of butterfly operation in the bits 116. In the process of establishing the grid map 124, the computing device 102 uses the bit sequence of the input data as the first dimension of the grid map 124 and the bit sequence of the output data as the second dimension of the grid map 124, so that a grid can be located in the grid map 124 through a bit in the bit sequence of the input data and a bit in the bit sequence of the output data.

[0029] It should be understood that in the process of multi-stage butterfly operation 106, the rotation factors in each stage of butterfly operation involve the product operation of the sequence number of input data and the sequence number of output data. When a bit in the bit sequence of input data and a bit in the bit sequence of output data exist simultaneously in a certain stage of butterfly operation, the multiplication operation of the two bits is involved. Therefore, a grid in the grid diagram 124 can represent the product of the corresponding two bits. In addition, the grid can also add attributes to represent the life cycle of the product of the two bits, where the life cycle is used to indicate in which stages of the multi-stage butterfly operation 106 the two bits exist simultaneously. Therefore, a grid can be used to represent: the life cycle of the product of a bit in the bit sequence of input data and a bit in the bit sequence of output data.

[0030] In this way, the computing device 102 can convert the sequence number of the input data into a bit sequence, so that the high sequence number can be represented by the bit sequence of the low digit, which improves the scalability of the transformation process. And the computing device 102 can represent the life cycle of the product of the bit of the input data sequence number and the bit of the output data sequence number through the grid in the grid diagram 124, thereby covering the flow information of the bit product from low to high, revealing the operation essence behind each level of butterfly operation, and improving the richness of information and the convenience of reading. Therefore, this embodiment can take into account the scalability and readability of the multi-level butterfly operation interpretation.

[0031] It should be understood that the architecture and functions in the example environment 100 are described for exemplary purposes only and do not imply any limitation on the scope of the present description. The embodiments of the present description may also be applied to other environments with different structures and / or functions.

[0032] The following will combine Figures 2 to 8 The process according to the embodiment of this specification is described in detail. For ease of understanding, the specific data mentioned in the following description are exemplary and are not intended to limit the scope of protection of the present disclosure. It should be understood that the embodiments described below may also include additional actions not shown and / or may omit the actions shown, and the scope of the present disclosure is not limited in this respect.

[0033] Figure 2 FIG. 2 is a flowchart showing a method 200 for generating a grid diagram of a multi-stage butterfly operation in some embodiments of the present specification. Figure 1 In the example environment 100 shown in , the method 200 can be performed by the computing device 102. It should be understood that although the following content is described with the computing device 102 as the execution subject, the method 200 can also be performed by other devices. The method 200 can also include additional actions not shown and / or can omit the actions shown, and the scope of the present disclosure is not limited in this respect.

[0034] At step 202, a first bit sequence of first data used for multi-stage butterfly operation is obtained from a digital signal, where the first bit sequence indicates a sequence number of the first data in a plurality of first data used for multi-stage butterfly operation.

[0035] In some embodiments, the computing device 102 may determine the input data group 104 (which may be referred to as a plurality of first data), for example, 16 input data, based on the digital signal. Furthermore, the computing device 102 may represent the sequence number of the input data in the input data group 104 through a bit sequence (which may be referred to as a first bit sequence). The multi-stage butterfly operation 106 includes a 0-stage butterfly operation 108, a 1-stage butterfly operation 110, ..., an n-1-stage butterfly operation 112, where n is an integer greater than 1.

[0036] At step 204, a grid diagram associated with a first bit in a first bit sequence and a second bit in a second bit sequence is generated, wherein the second bit sequence indicates a sequence number of the second data in a plurality of second data after multi-stage butterfly operations, and a grid in the grid diagram indicates a life cycle of a product of a corresponding first bit and a second bit in the multi-stage butterfly operations.

[0037] In some embodiments, during the process of the multi - level butterfly operation 106, the computing device 102 can determine the bits existing in each level of the butterfly operation. The existing bits include: the bits in the bit sequence representing the serial number of the input data and the bits in the bit sequence (which can be referred to as the second bit sequence) representing the serial number of the output data. Then, the computing device 102 can establish the trellis diagram 124 according to the bits existing in each level of the butterfly operation in the bit - bit 116. During the process of establishing the trellis diagram 124, the computing device 102 uses the bit sequence of the input data as the first dimension of the trellis diagram 124 and the bit sequence of the output data as the second dimension of the trellis diagram 124.

[0038] In some embodiments, a grid in the trellis diagram 124 can represent the product of the corresponding two bits. In addition, attributes can be added to the grid to represent the life cycle of the product of the two bits, where the life cycle is used to represent in which stages of the multi - level butterfly operation 106 the two bits exist simultaneously. Therefore, a grid can be used to represent: the life cycle of the product of a bit in the bit sequence of the input data and a bit in the bit sequence of the output data.

[0039] In the embodiments of this specification, the serial number of the input data can be converted into a bit sequence, so that the high serial number can be represented by the low - order bit sequence, improving the scalability of the transformation process. And the life cycle of the product of the bits representing the serial number of the input data and the bits representing the serial number of the output data can be represented by the grids in the trellis diagram, thus covering the flow information of the bit products from low to high, revealing the operation essence behind each level of the butterfly operation, and improving the richness of information and the convenience of reading. Therefore, the embodiments of this specification can balance the scalability and readability of the explanation of the multi - level butterfly operation.

[0040] In some embodiments, the FFT transform and the NTT transform are used to transform N input data x0, x1, …, x i , …, x N-1 into N output data X0, X1, …, X o , …, X N-1 , where 0 ≤ i, o < N. The formulas of the FFT transform and the NTT transform are shown in Equations (1) and (2) respectively:

[0041]

[0042] Among them, the subscripts i and o respectively represent the order of the serial number of the input data among the N input data and the N output data. represents the rotation factor, and mod represents the modulo operation. The rotation factor contains the complex unit root w N , which satisfies while where 1 ≤ k < N. The rotation factor also includes the exponent io, which is the product of the sequence numbers of the input data and the output data. In the complex domain, the multiplication is complex multiplication, and in the finite field, the multiplication is modular multiplication. Since the multiplication expressions in the complex domain and the finite field are similar, the following mainly describes the process of the multi-level butterfly operation 106 and the generation of the mesh graph 124 based on the FFT transform. For convenience in corresponding with the formulas during the description, the following will use subscripts to replace the sequence numbers of the input data and the output data.

[0043] In some embodiments, compared with calculating N output data respectively through N input data, the FFT transform can reduce the amount of calculation by sharing intermediate results. The following takes the Cooley-Tukey (CT) algorithm as an example to describe the butterfly operation in the FFT transform. Figure 3 FIG. shows a schematic diagram of the process 300 of the butterfly operation of some embodiments of the present specification, where the process 300 is the butterfly operation in the CT algorithm. In some embodiments, in the CT algorithm, Equation (1) can be converted into expressions shown in Equation (3) and Equation (4) as follows:

[0044]

[0045] where where, among the N input data, the even-term input 302 is the odd-term input 304 is Among the N output data, the first-half output 310 is X o , and the second-half output 312 is X o+N / 2 , and the multiplication operation 306 represents multiplying by In the addition operation 308-1, the odd-term input 304 first performs the multiplication operation 306, and then is added to the even-term input 302 to obtain the first-half output 310. In the subtraction operation 308-2, the odd-term input 304 first performs the multiplication operation 306, and then the even-term input 302 subtracts the result of the odd-term input 304 after performing the multiplication operation 306 to obtain the second-half output 312.

[0046] In some embodiments, different symbols can be used to represent different stages of each level of butterfly operation in process 300. For example, stage 1 is used to represent addition operation 308-1 and subtraction operation 308-2, and stage 1L (the left side of stage 1) is used to represent multiplication operation 306. In the CT algorithm, stage 1R (the right side of stage 1) does not perform any processing. It should be understood that the CT algorithm in this embodiment is merely an example for explaining the multi-level butterfly operation 106, and other algorithms such as the Gentleman-Sande (GS) algorithm (similar to the CT algorithm, except that the multiplication operation appears on the right side of the addition and subtraction operations) are also within the scope of the multi-level butterfly operation 106 in this specification.

[0047] Figure 4 FIG. 400 is a schematic diagram showing the process of the multi-level butterfly operation according to some embodiments of this specification, where process 400 is a multi-level butterfly operation 106 based on the CT algorithm. In process 400, N is 16, n is 4, the inputs are x1, …, x o , …, x 15 , and the outputs are X0, X1, …, X i , …, X 15 , where 0 ≤ i, o < 16. Process 400 includes a level-0 butterfly operation, a level-1 butterfly operation, a level-2 butterfly operation, and a level-3 butterfly operation. Taking the level-1 butterfly operation as an example, it includes stage 1L, stage 1, and stage 1R. Since process 400 is based on the CT algorithm, multiplication operations are performed in stage 1L, and no operations are performed in stage 1R (if it is the GS algorithm, no operations are performed in stage 1L, and multiplication operations are performed in stage 1R), and addition and subtraction operations are performed in stage 1.

[0048] The above content introduces the process of the multi-level butterfly operation 106 by taking the CT algorithm as an example. Next, the binary expressions of the subscripts i and o of the input data and output data in the multi-level butterfly operation 106 and the life cycle of each binary number will be introduced. In some embodiments, the subscript i can be represented by an n-bit binary number i n-1 , i n-2 , …, i p , …, i0, and the subscript o can be represented by o n-1 , o n-2 , …, o q , …, o0, so as to obtain the bit sequence of subscript i (which can be called the first bit sequence) and the bit sequence of subscript o (which can be called the second bit sequence) respectively. Among them, 0 ≤ p, q < n. In this way, the subscripts i and o can be represented by equations (5) respectively. Further, the exponent io of the rotation factor can be represented by the product of the bit sequences, as shown in equation (6).

[0049]

[0050] In some embodiments, based on the characteristics of the rotation factor, i.e. Therefore, the computing device 102 can perform a modulo operation on the exponent io, that is, perform io mod 2 n In the process of modulo operation, the coefficient in formula (6) is greater than or equal to 2 n The term of can be ignored. Thus, equation (7) can be obtained. According to equation (7), in the process of multi-stage butterfly operation 106, the index io of the rotation factor can be recorded as the parameter k shown in equation (8).

[0051]

[0052] k=Σ p+q≤n-1 i p o q 2 p+q , k≡ N io (8)

[0053] It should be understood that for each level of butterfly operation, the exponent io of the rotation factor in its multiplication operation can be decomposed into multiple i p o q For some i p o q , whose life cycle is used to represent i p o q Which stages of the butterfly operations of which stages exist in the multi-stage butterfly operations 106. For example, if i p o q It may appear after stage 0 in the 0th level butterfly operation 108 and before stage 1 in the 1st level butterfly operation 110, or after stage 1 in the 1st level butterfly operation 110 and before stage 2 in the 2nd level butterfly operation. p o q The life cycle is recorded as [0R, 2L].

[0054] Referring to equation (8), in some embodiments, when p+q=n-1, p=n-1-q, so the computing device 102 can p o q The corresponding rotation factor term is expressed as shown in formula (9). n-1:0 Can be disassembled into n-2:0 and i n-1 , so that the computing device 102 converts the output X of the multi-stage butterfly operation 106 o It is expanded into formula (10).

[0055]

[0056] In some embodiments, according to equations (9) and (10), for the 0-level butterfly operation 108, that is, q=0, then substituting q into equation (9), we obtain For the two different output data of the 0-level butterfly operation 108, they are respectively recorded as and The corresponding expressions can be obtained as shown in equations (11) and (12).

[0057]

[0058] In some embodiments, according to equations (11) and (12), the input data of the 0-level butterfly operation 108 includes and The difference between the two subscripts is that i n-1 For the addition operation in the 0th level butterfly operation 108, the input data The subscripted storage address is used to calculate the output data And input data The subscripted storage address is used to calculate the output data It can be seen that after the 0-level butterfly operation 108, the bit sequence i in the storage address n-1 ,i n-2 ,…,i p ,…,i0 becomes o0,i n-2 ,…,i p ,…,i0.

[0059] Similarly, after the first stage of butterfly operation 110, the bit sequence in the storage address becomes o0, o1, i n-3 ,…,i p ,…,i0. After n-1 levels of butterfly operations 112, the bit sequence in the storage address becomes o0, o1, o2,…, o q ,…,o n-1 . It can be seen that when the storage address of the input data subscript is i n-1 ,i n-2 ,…,i p ,…,i0, the storage address of the output data subscript is o0,o1,o2,…,o q ,…,o n-1 . Accordingly, when the storage address of the input data index is i0,i1,…,i p ,…,i n-1 When the storage address of the output data subscript is o n-1 ,o n-2 ,…,o q ,…,o0.

[0060] It should be understood that after the 0-stage butterfly operation 108, i n-1 is replaced by o0, in the storage address of the subscript i n-1 For the 1st level butterfly operation 110, the 2nd level butterfly operation, ..., the n-1th level butterfly operation 112, the transformation process of the subscripts of the input data and the output data is similar to that of the 0th level butterfly operation, that is, in the 1st level butterfly operation 110, i n-2 Replaced by o1, i in the 2nd level butterfly operation n-3 is replaced by o2, ..., in the n-1 stage butterfly operation 112, i0 is replaced by o n-1 Therefore, after q levels of butterfly operations, i n-1-q By q Replaced by, the storage address of the subscript i n-1-q Eliminated q This is what happened.

[0061] From this we can see that n-1 o0 only exists in the 0th level butterfly operation 108, and its life cycle is stage 0; i n-2 o1 exists only in the 1st level butterfly operation 110, and its life cycle is stage 1, i n-3 o2 only exists in the 2nd level butterfly operation, and its life cycle is stage 2, ..., i0o n-1 It only exists in the n-1 stage butterfly operation 112, and its life cycle is stage n-1. Therefore, in the case of p+q=n-1, i n-1-q o q It only exists in the q-level butterfly operation, and its life cycle is stage q.

[0062] In some embodiments, computing device 102 may obtain i p (which can be called the first bit) in the bit sequence i n-1 ,i n-2 ,…,i p ,…, sequence number p (which may be called the first sequence number) in i0 (which may be called the first bit sequence), and o q (which may be called the second bit) in the bit sequence o n-1 ,o n-2 ,…,o q ,…,o0 (which may be called the second bit sequence) in the sequence number q (which may be called the second sequence number). Then, the computing device 102 may determine whether the sum of p and q is equal to n-1 (which may be called the maximum sequence number). If it is equal to n-1, the computing device 102 may determine i p o q(which can be referred to as the product of the first bit and the second bit) has a life cycle of stage q (which can be referred to as the first stage number) of the q - stage butterfly operation (which can be referred to as the corresponding butterfly operation) in the multi - stage butterfly operation 106. Further, the computing device 102 can take i p and o q The attribute of the corresponding grid (which can be referred to as the first attribute) is represented as stage q. In this way, the computing device 102 can quickly determine the product of the bits corresponding to the grid based on the generated grid diagram, that is, i p o q , and in which stage of the multi - stage butterfly operation 106 it exists, thereby improving the efficiency of the interpretation during the butterfly operation process.

[0063] In some embodiments, for one - stage butterfly operation in the multi - stage butterfly operation 106 in the CT algorithm, it includes a multiplication operation between the input data and the rotation factor (such as Figure 3 the multiplication operation 306 shown in Figure 3 ), and addition and subtraction operations between the input data (such as p the addition operation 308 - 1 and the subtraction operation 308 - 2 shown in q ). In the case of p + q=n - 1, the product of the bits, that is, i

[0064] o n-2:0 and o0; after stage 1, the existing bits include i n-3:0 and o 1:0 ; after the 2 - stage butterfly operation, the existing bits include i n-4:0 and o 2:0 ;...; after the (n - 2) - stage butterfly operation, the existing bits include i0 and o n-2:0 . That is, the life cycle of i n-2 o0 is stage [0R, 1L], the life cycle of i n-3 o1 is stage [1R, 2L], the life cycle of i n-4 o2 is stage [2R, 3L],..., the life cycle of i0o n-2 is stage [(n - 2)R, (n - 1)L], and the life cycles of the remaining products can all be determined according to the stages where the bits exist. For example, the life cycle of i n-3 o0 is stage [0R, 2L], and this embodiment will not list them one by one. Therefore, in the case of p + q < n - 1, the life cycle of i p o q is [qR, (n - 1 - p)L].

[0065] In some embodiments, the computing device 102 may obtain i p (which may be referred to as the first bit) in the bit sequence i n-1 , i n-2 , …, i p , …, i0 (which may be referred to as the first bit sequence), the sequence number p (which may be referred to as the first sequence number), and o q (which may be referred to as the second bit) in the bit sequence o n-1 , o n-2 , …, o q , …, o0 (which may be referred to as the second bit sequence), the sequence number q (which may be referred to as the second sequence number). Then, the computing device 102 may determine whether the sum of p and q is less than n - 1 (which may be referred to as the maximum sequence number). If it is less than n - 1, the computing device 102 may determine that the life cycle of i p o q (which may be referred to as the product of the first bit and the second bit) is from stage qR of the q - th stage butterfly operation to stage (n - 1 - p)L of the (n - 1 - p)-th stage butterfly operation in the multi - stage butterfly operation 106 (the q - th stage butterfly operation and the (n - 1 - p)-th stage butterfly operation may be referred to as the corresponding butterfly operations, and stage qR and stage (n - 1 - p)L may be referred to as the second stage numbers). Further, the computing device 102 may represent the attributes of the corresponding grid of i p and o q (which may be referred to as the second attribute) as [qR, (n - 1 - p)L]. In this way, the computing device 102 can quickly determine, based on the generated grid diagram, in which stages of the multi - stage butterfly operation 106 the product of the bits corresponding to the grid, that is, i p o q , exists, thereby improving the efficiency of the explanation during the butterfly operation process.

[0066] In some embodiments, for one of the stages of the multi - stage butterfly operation 106 in the CT algorithm, it includes a multiplication operation between the input data and the rotation factor (such as Figure 3 the multiplication operation 306 shown in Figure 3 ), and an addition and subtraction operation between the input data (such as p the addition operation 308 - 1 and the subtraction operation 308 - 2 shown in q ). In the case of p + q < n - 1, the product of the bits, that is, i p o q , exists in the multiplication operation (specifically, refer to Equation (3) and Equation (4) and the related descriptions), and this multiplication operation corresponds to the stage [qR, (n - 1 - p)L] from the q - th stage butterfly operation to the (n - 1 - p)-th stage butterfly operation.

[0067] In some embodiments, if the sum of p and q is less than n - 1, when the computing device 102 determines i po q In which stages of the butterfly operation are present, we can first determine i p and q Does it exist in the multiplication operation of butterfly operation? n-3 Taking o0 as an example, for the multiplication operation in stage 1L, i n-3 and o0 exist (o0 is generated after stage 0, i n-3 Eliminated after stage 2). Then, if i p and q Both exist in the multiplication operation of the butterfly operation, then the computing device 102 can determine i p o q The life cycle is from the stage qR of the q-stage butterfly operation to the stage (n-1-p)L of the (n-1-p)-stage butterfly operation in the multi-stage butterfly operation 106. In this way, the computing device 102 can quickly determine the stage in which every two bits exist, and then determine the life cycle of the product of the two bits, thereby improving the generation efficiency of the grid map.

[0068] Figure 5 A schematic diagram of a grid diagram 500 of multi-stage butterfly operations of some embodiments of the present specification is shown. In some embodiments, the computing device 102 may be based on i n-1 ,i n-2 ,…,i p ,…,i0 (which may be referred to as the first bit sequence) to determine the vertical axis (which may be referred to as the first dimension) of the grid diagram 500, that is, the vertical axis represents the bit position a of the address from top to bottom. n-1 ,a n-2 ,…,a0, which are used to place the input data x i Bit i of index i n-1 ,i n-2 ,…,i0. Conversely, the computing device 102 may be based on o n-1 ,o n-2 ,…,o0 (which may be referred to as the second bit sequence) to determine the horizontal axis (which may be referred to as the second dimension) of the grid diagram 500, that is, the horizontal axis represents the bit position a of the address from left to right. n-1 ,a n-2 ,…,a0, are used to place the output data X o The bits o0, o1, ..., o of the index o n-1 .

[0069] For a grid in the grid diagram 500, it represents the corresponding i p and q The product of i p o q. In the grid graph 500, the diagonal grid satisfies p + q = n - 1. For example, when p = 0, q = n - 1, and when p = n - 2, q = 1. Therefore, the computing device 102 can determine the content (which can be referred to as the first attribute) in the diagonal grid i p o q to be q (which can be referred to as the first series). For example, the content in the diagonal grid corresponding to i n-2 o1 is 1. It should be understood that q represents the addition and subtraction operations in stage q of the q-stage butterfly operation in the multi-stage butterfly operation 106. The life cycle of i p o q is the stage q of the q-stage butterfly operation. The process of determining the content in the diagonal grid has been described in detail in the previous embodiments of this specification.

[0070] In the grid graph 500, the non-diagonal grid satisfies p + q < n - 1. For example, when p = 0, q = 0, and when p = n - 3, q = 1. Therefore, the computing device 102 can determine the content (which can be referred to as the second attribute) in the non-diagonal grid i p o q to be [qR, (n - 1 - p)L] (which can be referred to as the second series). For example, the content in the grid of i0o0 is [0R, (n - 1)L]. It should be understood that [qR, (n - 1 - p)L] represents the stages from stage qR of the q-stage butterfly operation to stage (n - 1 - p)L of the (n - 1 - p)-stage butterfly operation in the multi-stage butterfly operation 106. The life cycle of i p o q is the stage [qR, (n - 1 - p)L], that is, i p o q can be processed at any stage within the stage [qR, (n - 1 - p)L]. The process of determining the content in the non-diagonal grid has been described in detail in the previous embodiments of this specification.

[0071] Figure 6 FIG. shows a schematic diagram of another grid graph 600 of the multi-stage butterfly operation according to some embodiments of this specification. In some embodiments, the computing device 102 can determine the vertical axis (which can be referred to as the first dimension) of the grid graph 600 based on the bit reverse order of i n-1 , i n-2 , …, i p , …, i0 (which can be referred to as the first bit sequence), that is, the vertical axis represents the bit positions a n-1 , a n-2 , …, a0 of the address from top to bottom in sequence, which are used to place the subscripts i0, i1, …, i i of the input data x n-1 . Conversely, the computing device 102 can be based on o n-1 , o n-2,…,o0 (which may be referred to as the second bit sequence) to determine the horizontal axis (which may be referred to as the second dimension) of the grid diagram 600, that is, the horizontal axis represents the bit position a of the address from left to right. n-1 ,a n-2 ,…,a0, are used to place the output data X o Bit o of subscript o n-1 ,o n-2 ,…,o0, thereby forming a representation different from the grid diagram 500. The process of determining the contents in the diagonal grids and the non-diagonal grids in the grid diagram 600 is similar to that of the grid diagram 500 and will not be described in detail herein.

[0072] In this way, the computing device 102 can represent the bit sequence of the input data subscripts and the bit sequence of the output data subscripts in the two dimensions of the grid diagram in natural order and bit reverse order, respectively, so that the diagonal grids in the grid diagram can represent the stages of addition and subtraction operations in the multi-stage butterfly operation 106, and the non-diagonal grids can represent the stages of multiplication operations in the multi-stage butterfly operation 106, thereby making the life cycle of the bit products represented by different types of grids more intuitive.

[0073] In some embodiments, when determining a grid map (e.g. Figure 5 Grid map 500 or Figure 6 After obtaining the grid diagram 600 in FIG. 1 , the computing device 102 can determine the content (which can be referred to as the second attribute) in the non-diagonal grid, and the bit position of the subscript i (which can be referred to as the first bit position) and the bit position of the subscript o (which can be referred to as the second bit position) corresponding to the non-diagonal grid from the grid diagram. Then, the computing device 102 can determine the index io of the corresponding rotation factor according to the content in the non-diagonal grid, the bit position of the subscript i, and the bit position of the subscript o. For example, i p o q Corresponding to the rotation factor term The computing device 102 can obtain the rotation factor in each stage by merging the rotation factor items corresponding to the multiple bit products in each stage. It should be understood that complex multiplication is used in the FFT transformation, while modular multiplication is used in the NTT transformation. In this way, the computing device 102 can quickly determine the rotation factor in the butterfly operation based on the generated grid diagram, thereby improving the efficiency of the butterfly operation.

[0074] Figure 7A combined diagram 700 of a schematic diagram and a grid diagram of a multi-stage butterfly operation process of some embodiments of the present specification is shown, and the combined diagram 700 includes a schematic diagram and a grid diagram 701 of the multi-stage butterfly operation process 400, and also includes a box 702 describing the multi-stage butterfly operation process. In some embodiments, the input data group 104 includes 16 input data, and the output data group 114 includes 16 output data, that is, N=16, n=4. Referring to box 702, the multi-stage butterfly operation process 400 includes a 0-stage butterfly operation (including stage 0 and stage 0R), a 1-stage butterfly operation (including stage 1L, stage 1, and stage 1R), a 2-stage butterfly operation (including stage 2L, stage 2, and stage 2R), and a 3-stage butterfly operation (including stage 3L and stage 3).

[0075] In some embodiments, in the grid diagram 701 in the combined diagram 700, the vertical axis is a3, a2, a1, a0 from top to bottom, which are used to place the bits i3, i2, i1, i0 of the natural order of the subscript i, and the horizontal axis is a3, a2, a1, a0 from left to right, which are used to place the bits o0, o1, o2, o3 of the reverse order of the subscript o. p and q Satisfying p+q=3, in the off-diagonal grid, i p and q Satisfies p+q<3. Among them, 0≤p,q<3.

[0076] In some embodiments, referring to block 702, as the multi-stage butterfly operation process 400 proceeds, i n-1-q The address bits are gradually replaced by o q That is, after stage 0, the bit sequence i3, i2, i1, i0 becomes o0, i2, i1, i0; after stage 1, the bit sequence o0, i2, i1, i0 becomes o0, o1, i1, i0; after stage 2, the bit sequence o0, o1, i1, i0 becomes o0, o1, o2, i0; after stage 3, the bit sequence o0, o1, o2, i0 becomes o0, o1, o2, o3.

[0077] In some embodiments, the grid diagram 701 represents the product of corresponding bits, such as i3o0. When p+q=3, i3o0 needs to be processed at level 0, so the corresponding diagonal grid is marked with 0, corresponding to stage 0 in box 702. i2o1 needs to be processed at level 1, so the corresponding diagonal grid is marked with 1, corresponding to stage 1 in box 702. i1o2 needs to be processed at level 2, so the corresponding diagonal grid is marked with 2, corresponding to stage 2 in box 702. i0o3 needs to be processed at level 3, so the corresponding diagonal grid is marked with 3, corresponding to stage 3 in box 702. Where i p o q The coefficients are both 2 p+q =2 3 =8.

[0078] In some embodiments, in the grid diagram 701, for non-diagonal grids, i.e., when p+q<3, i p o q It has a life cycle and can be processed at any stage in the stage [qR, (n-1-p)L]. Among them, i0o0 can appear in any stage of the stages 0R, 1L, 1R, 2L, 2R, 3L. To simplify the grid diagram 701, the last stage, 3L, can be recorded in the corresponding grid. Similarly, the grids corresponding to i0o1 and i0o2 are also recorded as 3L, the grids corresponding to i1o0 and i1o1 are recorded as 2L, and i2o0 is recorded as 1L. Based on the characteristics of the CT algorithm, no operations are performed in stages 0R, 1R, and 2R.

[0079] In some embodiments, based on the grid diagram 701, the computing device 102 may determine that the 3L stage includes the products i0o0, i0o1 and i0o2, and the corresponding rotation factor terms are respectively and When i0o0, i0o1 and i0o2 are all in stage 3L, the three rotation factor terms can be merged into the corresponding rotation factor Similarly, computing device 102 may obtain the rotation factor in stage 2L as The rotation factors in stage 1L are

[0080] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, processor embodiment, and computing device embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0081] Figure 8 The block diagram of a computing device 800 suitable for implementing an embodiment of the present invention is schematically shown. The computing device 800 can be used to implement the computing device 102. The computing device 800 can be used to implement the execution Figure 2 The method 200 is shown in the apparatus. Figure 8 As shown, the computing device 800 includes a processing unit (CPU) 801, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 802 or computer program instructions loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the computing device 800 can also be stored. The CPU 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0082] Multiple components in the computing device 800 are connected to the I / O interface 805, including: an input unit 806, an output unit 807, and a storage unit 808. The processing unit 801 performs the various methods and processes described above, such as executing the method 200. For example, in some embodiments, the various processes or operations described above can be implemented as a computer software program, which is stored in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the computing device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the CPU 801, the various methods and processes described above can be executed, such as executing one or more operations of the method 200. Alternatively, in other embodiments, the CPU 801 can be configured to execute the various methods and processes described above, such as executing one or more actions of the method 200, by any other appropriate means (for example, by means of firmware).

[0083] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0084] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0085] These computer-readable program instructions can be provided to a processor in a voice interaction device, a general-purpose computer, a special-purpose computer, or a processing unit of other programmable data processing devices, thereby producing a machine, so that when these instructions are executed by the processing unit of a computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other device to work in a specific manner.

[0086] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0087] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0088] The above are only optional embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for generating a grid graph of a multi-level butterfly operation, comprising: Acquire a first bit sequence of first data used for the multi-stage butterfly operation from a digital signal, wherein the first bit sequence indicates a sequence number of the first data among a plurality of first data used for the multi-stage butterfly operation; as well as Generate a grid diagram related to a first bit in the first bit sequence and a second bit in the second bit sequence, wherein the second bit sequence indicates a sequence number of the second data in a plurality of second data after the multi-stage butterfly operation, and a grid in the grid diagram indicates a life cycle of a product of a corresponding first bit and a second bit in the multi-stage butterfly operation.

2. The method of claim 1 , wherein generating a trellis diagram associated with a first bit position in the first bit sequence and a second bit position in the second bit sequence comprises: Obtaining a first sequence number of the first bit in the first bit sequence, and a second sequence number of the second bit in the second bit sequence; When the sum of the first sequence number and the second sequence number is the maximum sequence number of the first bit sequence, determining a first stage number of a corresponding butterfly operation in the multi-stage butterfly operation, the first stage number being related to a life cycle of a product of the first bit position and the second bit position; as well as Based on the first level, a first attribute of a grid corresponding to the first bit and the second bit is determined.

3. The method according to claim 2, wherein the butterfly operation includes indicating a multiplication operation related to a rotation factor, and indicating an addition and subtraction operation between a plurality of input data of the butterfly operation, a life cycle of a product of the first bit and the second bit is related to the addition and subtraction operation in the butterfly operation, and the first stage number indicates the addition and subtraction operation in the butterfly operation.

4. The method of claim 1 , wherein generating a trellis diagram associated with a first bit position in the first bit sequence and a second bit position in the second bit sequence comprises: Obtaining a first sequence number of the first bit in the first bit sequence, and a second sequence number of the second bit in the second bit sequence; When the sum of the first sequence number and the second sequence number is less than the maximum sequence number of the first bit sequence, determining a second stage number of the corresponding butterfly operation in the multi-stage butterfly operation, where the second stage number is related to a life cycle of a product of the first bit position and the second bit position; as well as Based on the second level, a second attribute of the grid corresponding to the first bit and the second bit is determined.

5. The method according to claim 4, wherein the butterfly operation includes indicating a multiplication operation related to a rotation factor, and indicating an addition and subtraction operation between a plurality of input data of the butterfly operation, the multiplication operation in the butterfly operation is related to a life cycle of a product of the first bit and the second bit, and the second stage number indicates the multiplication operation in the butterfly operation.

6. The method according to claim 5, wherein when the sum of the first sequence number and the second sequence number is less than the maximum sequence number of the first bit sequence, determining the second stage number of the corresponding butterfly operation in the multi-stage butterfly operation comprises: In a case where the sum of the first sequence number and the second sequence number is less than the maximum sequence number of the first bit sequence, determining whether both the first bit position and the second bit position exist in the multiplication operation; In the case that both the first bit and the second bit exist in the multiplication operation, the second level number of the corresponding multiplication operation is determined in the multi-stage butterfly operation.

7. The method according to claim 1, wherein a first dimension of the grid diagram is determined based on the first bit sequence, a second dimension is determined based on the second bit sequence, a sum of a first sequence number of a first bit position and a second sequence number of a second bit position corresponding to a diagonal grid is a maximum sequence number of the first bit sequence, and generating a grid diagram associated with a first bit position in the first bit sequence and a second bit position in the second bit sequence comprises: Determining a first attribute of the diagonal grid, wherein a life cycle of a product result of the first bit and the second bit corresponding to the diagonal grid is related to an addition or subtraction operation of one stage in the multi-stage butterfly operation, and the first attribute indicates a first stage number of the addition or subtraction operation; and Determine a second attribute of a non-diagonal grid, wherein a life cycle of a product result of the first bit and the second bit corresponding to the non-diagonal grid is related to a multiplication operation of at least one stage in the multi-stage butterfly operation, and the second attribute indicates a second level number of a highest level of multiplication operation in the at least one level of multiplication operation.

8. The method according to claim 7, further comprising: In the grid graph, determining a second attribute corresponding to the off-diagonal grid; Determine a first bit position and a second bit position corresponding to the off-diagonal grid; as well as Based on the second attribute, the first bit, and the second bit corresponding to the non-diagonal grid, an exponent of a rotation factor corresponding to the non-diagonal grid is determined.

9. The method according to any one of claims 1 to 8, wherein the multi-stage butterfly operation is used in a communication device to convert the digital signal into the frequency domain through a fast Fourier transform, or is used in a chip to encrypt the digital signal through a fast number theory transform.

10. A device for generating a grid diagram of a multi-stage butterfly operation, comprising: A first bit sequence acquisition module is configured to acquire a first bit sequence of first data used for the multi-stage butterfly operation from a digital signal, wherein the first bit sequence indicates a sequence number of the first data among a plurality of first data used for the multi-stage butterfly operation; as well as A grid diagram generation module is configured to generate a grid diagram associated with a first bit in the first bit sequence and a second bit in the second bit sequence, wherein the second bit sequence indicates a sequence number of the second data in a plurality of second data after the multi-stage butterfly operation, and a grid in the grid diagram indicates a life cycle of the product of the corresponding first bit and the second bit in the multi-stage butterfly operation.

11. A processor, configured to execute the method according to any one of claims 1 to 9.

12. A computing device comprising: Memory; as well as A processor according to claim 11.

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