A Brain-Computer Interface Signal Recognition Circuit Based on Memristive Neural Network

Abstract

The present invention discloses a brain-computer interface signal recognition circuit based on a memristive neural network, which is composed of three neuron circuits. Each neuron circuit consists of nine parallel branches and includes a signal input module, a weight adjustment module, a summation module ①, a memristor, a summation module ②, a sampling module, and a comparison module. In a single neuron circuit, when the nine input signals V in1 ~V in9 are processed by the signal input module, the weight adjustment module, the summation module ①, and the memristor of the nine parallel branches respectively, and then the nine signals are combined together and passed through a single summation module ②, a sampling module, and a comparison module, and the recognition signal of the single neuron circuit is output. The designed circuit uses the resistance plasticity and threshold characteristics of the memristor to build a memristive neural network circuit, and can initially recognize the meaning of the brain-computer interface signal through its self-learning mechanism, and it can significantly enhance the recognition accuracy of the brain-computer interface signal.

Description

Technical Field

[0001] The present invention relates to the field of memristive neural network circuit design, and particularly to a brain-computer interface signal recognition circuit based on a memristive neural network. Background Art

[0002] The concept of memristor was first proposed by Chinese-American scientist Chua Shao-Tang in 1971. When studying the relationship among current, voltage, charge, and magnetic flux, he inferred that in addition to resistors, capacitors, and inductors, there should be another device representing the relationship between charge and magnetic flux, which is called a memristor.

[0003] The remarkable characteristic of a memristor lies in the plasticity of its resistance value. That is, under the excitation of an external electric field, the resistance value of the memristor can change significantly, and the change in the direction of the electric field will directly cause the resistance value to change in the opposite direction.

[0004] A memristor also has a threshold characteristic. The threshold characteristic of a memristor refers to the fact that in the resistive switching phenomenon of the memristor, there is a specific voltage or current threshold. When the applied voltage or current exceeds this threshold, the resistance state of the memristor will undergo a sudden change.

[0005] With the rapid development of artificial intelligence technology, the limitations of traditional computer architectures have gradually emerged when dealing with complex and variable intelligent tasks. Currently, the emergence of memristors makes it possible to have a memory-computation integrated architecture and a brain-inspired computing hardware circuit, and enables computers to break through the von Neumann architecture, bringing faster information processing speed for artificial intelligence computing.

[0006] The memory-computation integrated hardware circuit of a neural network based on memristors can almost complete a matrix multiply-accumulate calculation (MAC) within the delay of one read operation, which is crucial for reducing energy consumption and improving speed in neural network computing.

[0007] Currently, the brain-computer interface (BCI) technology is a revolutionary information communication method. By directly establishing a connection between the human brain and external devices, it realizes the real-time acquisition, decoding, and application of brain activity signals. This technology shows great potential and development prospects in many research fields such as medical rehabilitation, intelligent device control, and cognitive science.

[0008] The complexity and individual differences of brain-computer interface signals pose challenges to signal processing. Neural networks, especially deep learning models, can capture and learn the complex patterns and features in brain-computer interface signals through their multi-layer structures.

[0009] Traditional brain-computer interfaces usually rely on CMOS chips, which leads to challenges in power consumption and latency when the number of signal acquisition channels increases; while the in-memory computing characteristic of memristors can effectively solve these problems, providing higher computing efficiency and lower energy consumption.

[0010] The acquisition and processing technology of brain-computer interface signals, combined with the adaptability and learning ability of neural networks, provides a powerful tool for decoding brain activities.

[0011] Memristive neural networks have broad application prospects in hardware-accelerating brain-computer interface signal processing. Their in-memory computing characteristic and processing method imitating the biological brain provide technical support for improving the real-time performance and accuracy of brain-computer interface systems.

[0012] The processing method of brain-computer interface signals poses higher demands on computing resources due to its inherent high dimension and complexity, while memristive neural networks have significant advantages in reducing the training duration of neural networks and improving the signal recognition accuracy. In view of this, the present invention proposes a brain-computer interface signal recognition circuit based on a memristive neural network, which is used in the initial processing stage of brain-computer interface signals, and this circuit can significantly enhance the recognition accuracy of brain-computer interface signals. Summary of the Invention

[0013] The present invention proposes a brain-computer interface signal recognition circuit based on a memristive neural network, which uses the resistance plasticity and threshold characteristic of the novel two-port device memristor to build a memristive neural network circuit, and can initially recognize the meaning of brain-computer interface signals through the self-learning mechanism of the memristive neural network circuit.

[0014] The present invention is realized through the following technical solutions: A brain-computer interface signal recognition circuit based on a memristive neural network is composed of three neuron circuits connected in the Figure 1 shown connection manner; each neuron circuit is composed of nine parallel branches, and it includes a signal input module, a weight adjustment module, a summing module ①, a memristor, a summing module ②, a sampling module, and a comparison module.

[0015] In a single neuron circuit, when the nine input voltage signals V in1 ~V in9 each pass through the signal input module, weight adjustment module, summing module ①, and memristor of the nine parallel branches for processing, and then the nine signals are combined together and passed through a single summing module ②, sampling module, and comparison module, and the recognition signal of the single neuron circuit is output.

[0016] Taking the connection relationship of the first neuron circuit as shown in Figure 2 as an example, in the nine parallel input branches, the signal input module consists of an operational amplifier A 1n1 , NMOS transistor M 1n1and resistor R 1n1 Here, the first 1 in the subscript of the operational amplifier, NMOS tube and resistor indicates that the neuron is numbered as the first neuron, the second n indicates that the connected input signal is numbered as n, the third 1 indicates that the operational amplifier, NMOS tube and resistor are numbered as 1, and the subsequent numbers are deduced in the same way. Input voltage signal V inn With operational amplifier A 1n1 The inverting input terminal is connected to transmit the input voltage signal V inn ; Among them, V inn The subscript n represents the number of the input voltage signal, n = 1, 2, 3, ... 9; and the input voltage signal V inn is lower than the threshold voltage of the memristor, so it will not cause the resistance of the memristor to change; operational amplifier A 1n1 The output end is connected to the non-inverting input end and connected to the NMOS tube M 1n1 The source of NMOS tube M 1n1 The gate and control voltage signal V ctrl1 Connected, NMOS tube M 1n1 The drain and resistor R 1n1 One end of the NMOS tube M is connected 1n1 The substrate is grounded, M 1n1 Its function is to control the input voltage signal V inn The on-off resistance R 1n1 The other end of M is grounded. 1n1 The drain is also connected to the resistor R 1n3 The voltage at the junction is denoted as V' inn , and serves as one of the input signals of the next level summation module ①.

[0017] The working principle of the signal input module is as follows. Assume that a complete working cycle of the proposed circuit is 20 milliseconds. The first 10 milliseconds is the signal input period. During this stage, the control voltage V ctrl1 is high level, NMOS tube M 1n1 On, input voltage signal V inn Connect to operational amplifier A 1n1 The inverting input of the operational amplifier A 1n1 The output terminal is then output through the NMOS tube M 1n1 The next level summation module ① is input. The next 10 milliseconds is the weight adjustment period. During this stage, the control voltage V ctrl1 is low level, the control voltage V ctrl2 is high level, at this time NMOS tube M 1n1 is disconnected.

[0018] As Figure 2Taking the connection relationship of the first neuron circuit shown as an example, in the nine-way parallel input branch, the weight adjustment module consists of PMOS transistors M 1n2 and M 1n3 , NMOS transistors M 1n4 -M 1n6 , adjustment voltage sources V adj+ and V adj- , and resistor R 1n2 to form an analog circuit NAND gate, where n = 1, 2, 3,... 9. Here, the sources of M 1n2 and M 1n3 are connected together and connected to the adjustment voltage V adj+ , the drains of M 1n2 and M 1n3 are connected together and connected to the drain of M 1n4 , the substrates of M 1n2 and M 1n3 are connected to the +5V voltage source, the gate of M 1n2 is connected to the input voltage signal V inn , and the gate of M 1n3 is connected to the feedback adjustment voltage signal V cp1 output by the comparison module. The drain of NMOS transistor M 1n4 is connected to the source of M 1n6 , and the voltage at the connection point is denoted as V adjn , the gate of M 1n4 is connected to the input voltage signal V inn , the source of M 1n4 is connected to the drain of M 1n5 , and the substrate of M 1n4 is connected to the -5V DC voltage source. The gate of NMOS transistor M 1n5 is connected to the feedback adjustment voltage signal V cp1 output by the comparison module, the source is connected to the adjustment voltage V adj- , and the substrate is connected to the -5V DC voltage source. The gate of NMOS transistor M 1n6 is connected to the control clock voltage signal V ctrl2 ; the drain of M 1n6 is connected to resistor R 1n2 , and its output voltage is used as one of the input voltages of the summing module ①, denoted as V' adjn . Among them, V adj+ is an adjustment voltage slightly higher than the positive threshold voltage of the memristor, which is set to 1.1V in the present invention, and V adj- is an adjustment voltage slightly lower than the negative threshold voltage of the memristor, which is set to -1.1V in the present invention.

[0019] The working principle of the weight adjustment module is as follows. For the input voltage signal V inn and the feedback adjustment voltage signal V output by the comparison modulecp1 , when the polarities of their voltages are different, it can be divided into the following four cases. If the input voltage signal V inn is a positive voltage and V cp1 is a positive voltage, the MOS transistor M 1n2 is turned off, M 1n3 is turned on, M 1n4 is turned on, M 1n5 is turned on. At this time, the negative adjustment voltage V adj- can pass through the MOS transistor as the adjustment voltage V adjn ; if the input voltage signal V inn is a positive voltage and V cp1 is a negative voltage, the MOS transistor M 1n2 is turned off, M 1n3 is turned on, M 1n4 is turned off, M 1n5 is turned off. At this time, the positive adjustment voltage V adj+ can pass through the MOS transistor as the adjustment voltage V adjn ; if the input voltage signal V inn is a negative voltage and V cp1 is a positive voltage, the MOS transistor M 1n2 is turned on, M 1n3 is turned on, M 1n4 is turned off, M 1n5 is turned off. At this time, the positive adjustment voltage V adj+ can pass through the MOS transistor as the adjustment voltage V adjn ; if the input voltage signal V in1 is a negative voltage and V cp1 is a negative voltage, the MOS transistor M 1n2 is turned on, M 1n3 is turned off, M 1n4 is turned off, M 1n5 is turned on. At this time, the positive adjustment voltage V adj+ can pass through the MOS transistor as the positive adjustment voltage V adjn ; when the control voltage V ctrl2 is a positive voltage, V adjn can flow into the summing module ① through the MOS transistor M 1n6 as the adjustment signal for the memristor. At this time, the signal is denoted as V' adjn .

[0020] Taking the connection relationship of the first neuron circuit shown in Figure 2 as an example, in the nine-way parallel input branch, the summing module ① is composed of resistors R 1n3 -R 1n8 and operational amplifiers A 1n2 , A 1n3 , where n = 1, 2, 3,... 9. The voltage signal V' from the signal input moduleinn is connected to one end of resistor R 1n3 , and the adjusted voltage signal V' from the weight adjustment module adjn is connected to one end of resistor R 1n4 ; the other end of resistor R 113 is connected to the other end of resistor R 1n4 and is connected to the inverting input terminal of operational amplifier A 1n2 ; one end of resistor R 1n5 is connected to the non-inverting input terminal of operational amplifier A 1n2 , and the other end of resistor R 1n5 is grounded; resistor R 1n6 is connected across the output terminal and the inverting input terminal of operational amplifier A 1n2 . Resistors R 1n7 , R 1n8 and operational amplifier A 1n3 together form an inverter. One end of resistor R 1n7 is connected to the output terminal of operational amplifier A 1n2 , and the other end of R 1n7 is connected to the non-inverting input terminal of A 1n3 ; R 1n8 is connected across the inverting input terminal and the output terminal of operational amplifier A 1n3 , and the output terminal voltage signal of operational amplifier A 1n3 is used as the input signal at one end of memristor MR 1n and is denoted as V sum_1n ; the other end of memristor MR 1n is connected to resistor R 1n9 of the next summing module ②; here, the first 1 in the subscript of memristor MR 1n represents the first neuron, and the latter n represents the serial number of the connected input voltage signal.

[0021] The working principle of summing module ① is as follows. Resistors R 1n3 -R 1n6 and operational amplifier A 1n2 together form an inverting adder. After V' inn and V' adjn are proportionally added through the inverting adder, it is then inverted through the inverter composed of resistors R 1n7 , R 1n8 and operational amplifier A 1n3 , and the obtained voltage is denoted as V sum_1n ; for a complete 20-millisecond working cycle, the first 10 milliseconds is the signal input period, at this time V ctrl1 is a positive voltage, V ctrl2 is a negative voltage, V sum_1nis the result obtained after the input voltage signal undergoes front-end calculation through the signal input module and summation module ①, and then passes through the memristor, summation module ② and sampling module for sampling, which is the desired output signal V of the first neuron out1 . In the subsequent 10 milliseconds is the weight adjustment period, at this time the output voltage V out1 is the voltage signal obtained by calculating the weight adjustment voltage through the inverting adder and the memristor. It is not the target signal and is not sampled in the sampling module, so it will not be output as the target voltage signal either

[0022] Take the connection relationship of the first neuron circuit shown in Figure 2 as an example. The summation module ② consists of resistors R 119 -R 199 , resistors R 11 -R 14 and operational amplifiers A 14 , A 15 . Resistors R 119 to resistor R 199 are connected to the inverting input terminal of operational amplifier A 14 ; here, the first digit 1 of the subscript of operational amplifier A 14 represents the number of the neuron circuit, and the latter digit 4 represents the number of the operational amplifier in the circuit; resistor R 11 is connected across the output terminal and the inverting input terminal of operational amplifier A 14 , one end of resistor R 12 is connected to the non-inverting input terminal of operational amplifier A 14 , and the other end is grounded; one end of resistor R 13 is connected to the output terminal of operational amplifier A 14 , and the other end is connected to the non-inverting input terminal of operational amplifier A 15 ; resistor R 14 is connected across the inverting input terminal and the output terminal of operational amplifier A 15 ; the output signal of the output terminal of A 15 is used as the input signal of the next-stage sampling module, denoted as V sum_1 .

[0023] The working principle of the summation module ② is as follows. Resistors R 119 -R 199 , R 11 , R 12 and operational amplifier A 14 together form an inverting adder to perform inverting proportional addition operation on the voltage signal output from the memristor; resistors R 13 , R 14 and operational amplifier A 15 together form an inverter to invert the voltage signal V' from the inverting addersum_1 Invert it and input V sum_1 into the next-stage sampling module.

[0024] Take, for example, the connection relationship of the first neuron circuit as shown Figure 2 below. The sampling module consists of a sample-and-hold circuit Q1, a capacitor C1, and positive and negative voltage sources. The capacitor C1 is used to store the sampled voltage signal, and the positive and negative voltage sources with voltage values of +15V and -15V respectively serve as the power supply for the sample-and-hold circuit Q1. The control voltage V ctrl1 is used to control the sampling period of the sample-and-hold circuit Q1, and the output voltage of the sample-and-hold circuit Q1 is the output voltage signal V out1 of the first neuron. At the same time, this output voltage signal V out1 serves as the input voltage for the next-stage comparison module.

[0025] The working principle of the sampling module is as follows. The positive and negative voltage sources are respectively connected to the positive and negative power supply terminals of the sample-and-hold circuit Q n to provide power for the operation of the sample-and-hold circuit; the capacitor C1 is used to store the acquired voltage signal; the control voltage source V ctrl1 is used to control the sampling operation of the sample-and-hold circuit. When the control voltage source V ctrl1 is at a high voltage, the sample-and-hold circuit samples the output voltage V sum_1 from the previous-stage summing module ② and outputs it to the output terminal of the sample-and-hold circuit, serving as the output voltage signal V out1 of the entire neuron unit.

[0026] Take, for example, the connection relationship of the first neuron circuit as shown Figure 2 below. The comparison module consists of resistors R 15 -R 18 , a reference voltage source V1, and an operational amplifier A 16 . The output signal V out1 of the neuron is connected to one end of the resistor R 15 , and the other end of the resistor R 15 is connected to the inverting input terminal of the operational amplifier A 16 ; one end of the resistor R 17 is connected to the reference voltage source V1, and the other end of the resistor R 17 is connected to the non-inverting input terminal of the operational amplifier A 16 . One end of the resistor R 18 is also connected to the non-inverting input terminal, and the other end of the resistor R 16 is grounded; the resistor R 18 is connected across the output terminal and the inverting input terminal of the operational amplifier A 16 ; the signal V at the output terminal of the operational amplifier A 16 ... 16 at the output terminal...cp1 As a feedback adjustment voltage signal, it is input into the weight adjustment module. For the complete circuit composed of three neurons in parallel in the present invention, different reference voltage sources V n represent the corresponding brain-computer interface signal meanings, where n = 1, 2, 3.

[0027] The working principle of the comparison module is as follows. The resistors R 15 -R 18 and the operational amplifier A 16 together constitute a proportional subtractor. V1 serves as the reference voltage and is compared with the neuron output voltage signal V out1 from the sampling module. The value obtained by subtracting V1 from V out1 is used as the feedback adjustment voltage signal V cp1 and is input into the weight adjustment module, jointly determining the weight adjustment direction of the memristor with the input voltage signal V inn . Description of the Drawings

[0028] Figure 1 is a brain-computer interface signal recognition circuit based on a memristive neural network.

[0029] Figure 2 is the circuit schematic diagram of the first neuron in the present invention.

[0030] Figure 3 is the circuit diagram of the signal input module of the first neuron in the present invention.

[0031] Figure 4 is the circuit diagram of the weight adjustment module of the first neuron in the present invention.

[0032] Figure 5 is the circuit diagram of the summation module ① of the first neuron in the present invention.

[0033] Figure 6 is the circuit diagram of the memristor and the summation module ② of the first neuron in the present invention.

[0034] Figure 7 is the circuit diagram of the sampling module of the first neuron in the present invention.

[0035] Figure 8 is the circuit diagram of the comparison module of the first neuron in the present invention.

[0036] Figure 9 is the schematic diagram of the respective input reference voltages among the three neurons.

[0037] Figure 10 is the corresponding relationship diagram between the nine-channel input voltage signals and the reference voltage.

[0038] Figure 11Schematic diagram of adjusting the output voltage signal of the first neuron.

[0039] Figure 12 Schematic diagram of adjusting the output voltage signal of the second neuron.

[0040] Figure 13 Schematic diagram of adjusting the output voltage signal of the third neuron.

[0041] Figure 14 Output changes of voltage signals adjusted for feedback of three neurons. DETAILED DESCRIPTION

[0042] In order to make the technical solutions, objectives and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0043] like Figure 1 and Figure 2 As shown, the present invention proposes a brain-computer interface signal recognition circuit based on a memristor neural network. It consists of three neuron circuits through Figure 1 The connection method shown is shown; each neuron circuit is composed of nine parallel branches, which includes a signal input module, a weight adjustment module, a summation module①, a memristor, a summation module②, a sampling module and a comparison module.

[0044] As Figure 2 As an example of the connection relationship of the first neuron circuit shown in the figure, when the nine-way input voltage signal V in1 ~V in9 After being processed by the signal input module, weight adjustment module, summing module① and memristor of the nine parallel branches, the nine signals are merged together and passed through a single summing module②, sampling module and comparison module, and a single recognition signal of the neuron circuit is output.

[0045] Signal input module, such as Figure 3 As shown, it consists of an operational amplifier A 1n1 、NMOS tube M 1n1 and resistor R 1n1 Here, the first 1 in the subscript of the operational amplifier, NMOS tube and resistor indicates that the neuron is numbered as the first neuron, the second n indicates that the connected input signal is numbered as n, the third 1 indicates that the operational amplifier, NMOS tube and resistor are numbered as 1, and the subsequent numbers are deduced in the same way. Input voltage signal V inn With operational amplifier A 1n1 The inverting input is connected to inn The subscript n represents the number of the input voltage signal, n = 1, 2, 3, ... 9; operational amplifier A 1n1 The output end is connected to the non-inverting input end and connected to the NMOS tube M1n1 The source of NMOS transistor M 1n1 The gate is connected to the control voltage signal V ctrl1 ; the drain of NMOS transistor M 1n1 is connected to one end of resistor R 1n1 ; the substrate of NMOS transistor M 1n1 is grounded; the other end of resistor R 1n1 is grounded. Among them, the drain of M 1n1 is also connected to one end of resistor R 1n3 , and the voltage at the connection point is denoted as V' inn , and is used as one of the input signals of the next-stage summing module ①.

[0046] The weight adjustment module, as shown in Figure 4 , consists of PMOS transistors M 1n2 and M 1n3 , NMOS transistors M 1n4 -M 1n6 , adjustment voltage sources V adj+ and V adj- , and resistor R 1n2 to form an analog circuit NAND gate, where n = 1, 2, 3,... 9. Here, the sources of M 1n2 and M 1n3 are connected together and connected to the adjustment voltage V adj+ , the drains of M 1n2 and M 1n3 are connected together and connected to the drain of M 1n4 , the substrates of M 1n2 and M 1n3 are connected to the +5V voltage source, the gate of M 1n2 is connected to the input voltage signal V inn , the gate of M 1n3 is connected to the feedback adjustment voltage signal V cp1 output by the comparison module. The drain of NMOS transistor M 1n4 is connected to the source of M 1n6 , and the voltage at the connection point is denoted as V adjn ; the gate of M 1n4 is connected to the input voltage signal V inn , the source of M 1n4 is connected to the drain of M 1n5 , the substrate of M 1n4 is connected to the -5V DC voltage source. The gate of NMOS transistor M 1n5 is connected to the feedback adjustment voltage signal V cp1 output by the comparison module, the source is connected to the adjustment voltage V adj- , and the substrate is connected to the -5V DC voltage source. The gate of NMOS transistor M 1n6 is connected to the control clock voltage signal V ctrl2Connected; M 1n6 The drain is connected to one end of resistor R 1n2 and its output voltage is used as one of the input voltages of summing module ①, denoted as V' adjn ; The other end of resistor R 1n2 is grounded.

[0047] Summing module ①, as Figure 5 shown, it consists of resistor R 1n3 -R 1n8 and operational amplifier A 1n2 、A 1n3 where n = 1, 2, 3,...9. The voltage signal V' inn from the signal input module is connected to one end of resistor R 1n3 , and the adjustment voltage signal V' adjn from the weight adjustment module is connected to one end of resistor R 1n4 ; The other end of resistor R 113 is connected to the other end of resistor R 1n4 and is connected to the inverting input terminal of operational amplifier A 1n2 ; One end of resistor R 1n5 is connected to the non-inverting input terminal of operational amplifier A 1n2 , and the other end of resistor R 1n5 is grounded; Resistor R 1n6 is connected across the output terminal and the inverting input terminal of operational amplifier A 1n2 . Resistor R 1n7 、R 1n8 and operational amplifier A 1n3 together form an inverter. One end of resistor R 1n7 is connected to the output terminal of operational amplifier A 1n2 , and the other end of R 1n7 is connected to the non-inverting input terminal of A 1n3 ; R 1n8 is connected across the inverting input terminal and the output terminal of operational amplifier A 1n3 , and the output voltage signal of operational amplifier A 1n3 is used as the input signal at one end of memristor MR 1n and is denoted as V sum_1n ; The other end of memristor MR 1n is connected to resistor R 1n9 of the next summing module ②; Here, the first 1 in the subscript of memristor MR 1n represents the first neuron, and the latter n represents the serial number of the connected input voltage signal.

[0048] Summing module ② and memristor, as Figure 6 shown; Summing module ② consists of resistor R 119 -R199 , resistor R 11 -R 14 and operational amplifier A 14 , A 15 are composed. V sum_1n is connected to one end of the memristor MR 1n , and the other end of the memristor MR 1n is connected to the resistor R 1n9 , where n = 1, 2, 3,... 9. The resistor R 119 to the resistor R 199 are connected to the inverting input terminal of the operational amplifier A 14 ; here, the first digit 1 of the subscript of the operational amplifier A 14 represents the number of the neuron circuit, and the latter digit 4 represents the number of the operational amplifier in the circuit; the resistor R 11 is connected across the output terminal and the inverting input terminal of the operational amplifier A 14 , one end of the resistor R 12 is connected to the non-inverting input terminal of the operational amplifier A 14 , and the other end is grounded; one end of the resistor R 13 is connected to the output terminal of the operational amplifier A 14 , and the other end is connected to the non-inverting input terminal of the operational amplifier A 15 ; the resistor R 14 is connected across the inverting input terminal and the output terminal of the operational amplifier A 15 ; the output signal of the output terminal of A 15 is used as the input signal of the next-stage sampling module, denoted as V sum_1 .

[0049] Sampling module, as Figure 7 shown, it consists of a sample-and-hold circuit Q1, a capacitor C1, and positive and negative voltage sources. The capacitor C1 is used to store the sampled voltage signal, and the positive and negative voltage sources with voltage values of +15V and -15V respectively are used as the power supply for the sample-and-hold circuit Q1. The control voltage V ctrl1 is used to control the sampling period of the sample-and-hold circuit Q1, and the output voltage of the sample-and-hold circuit Q1 is the output voltage signal V out1 of the first neuron. At the same time, this output voltage signal V out1 is used as the input voltage of the next-stage comparison module.

[0050] Comparison module, as Figure 8 shown, it consists of a resistor R 15 -R 18 , a reference voltage source V1, and an operational amplifier A 16 . The output voltage signal V out1 of the neuron is connected to one end of the resistor R 15 , and one end of the resistor R 15The other end is connected to the inverting input terminal of operational amplifier A 16 ; one end of resistor R 17 is connected to reference voltage source V1, and the other end is connected to the non-inverting input terminal of operational amplifier A 16 ; at the same time, one end of resistor R 18 is also connected to the non-inverting input terminal, and the other end of resistor R 16 is grounded; resistor R 18 is connected across the output terminal and the inverting input terminal of operational amplifier A 16 ; the signal V 16 at the output terminal of operational amplifier A 16 serves as a feedback adjustment voltage signal and is input into the weight adjustment module. cp1

[0051] In the simulation example of a brain-computer interface signal recognition circuit based on a memristive neural network, Figure 9 it is a schematic diagram of the respective input reference voltages in three neurons. Let V1 be 1V, V2 be 2V, and V3 be 3V.

[0052] Figure 10 It is a corresponding relationship diagram of nine-channel input voltage signals and reference voltages. Figure 10 (a) shows the corresponding positions of the nine-channel input voltage signals. Figure 10 (b) is the brain-computer interface signal image corresponding to V1. Figure 10 (c) is the brain-computer interface signal image corresponding to V2. Figure 10 (d) is the brain-computer interface signal image corresponding to V3, where the black blocks correspond to 0.5V and the white blocks correspond to 0V.

[0053] Figure 11 It is a schematic diagram of the output voltage signal adjustment of the first neuron. For the first neuron, its reference voltage V1 is set to 1V, and this schematic diagram is the result obtained after the sampling module of the first neuron samples the output voltage signal; it can be seen from the figure that after two cycles of learning, the output voltage signal of the first neuron is very close to the reference voltage, and at this time the neuron stops learning and the training is completed.

[0054] Figure 12 It is a schematic diagram of the output voltage signal adjustment of the second neuron. For the second neuron, its reference voltage V2 is set to 2V, and this schematic diagram is the result obtained after the sampling module of the second neuron samples the output voltage signal; it can be seen from the figure that after several cycles of learning, the output voltage signal of the second neuron is slightly higher than the reference voltage, and after further adjustment, the neuron output decreases and is consistent with the reference voltage after further adjustment, which reflects the robustness in the neuron adjustment process.

[0055] Figure 13 ​Schematic diagram for adjusting the output voltage signal of the third neuron. For the third neuron, its reference voltage V3 is set to 3V, and this schematic diagram is the result obtained after the sampling module of the third neuron samples the output voltage signal. As can be seen from the figure, after several cycles of learning, the output voltage signal of the third neuron approaches the reference voltage, and the output voltage signal fluctuates near the reference voltage with a small fluctuation value, within the acceptable error range.

[0056] Figure 14 Output variation diagram of the feedback adjustment voltage signals for three neurons. As can be seen from the figure, the difference between the output voltage signals of the three neuron circuits and the reference voltage gradually approaches 0 during the self-learning process, which verifies that the circuit proposed in the present invention can enhance the recognition accuracy of the brain-computer interface signal.

Claims

1. A brain-computer interface signal recognition circuit based on a memristive neural network, characterized in that, It consists of three neuron circuits; each neuron circuit is composed of nine parallel branches and includes a signal input module, a weight adjustment module, a summation module ①, a memristor, a summation module ②, a sampling module, and a comparison module; In a single neuron circuit, when the nine-channel input voltage signals V in1 ~V in9 each pass through the signal input module, weight adjustment module, summation module ① and memristor processing of nine parallel branches, and then the nine-channel signals are merged together and passed through a single summation module ②, sampling module and comparison module, and the recognition signal of the single neuron circuit is output; the designed circuit uses the resistance plasticity and threshold characteristics of the memristor to build a memristive neural network circuit, and can initially recognize the meaning of the brain-computer interface signal through its self-learning mechanism; The nine input voltage signals V in1 ~V in9 are respectively connected to the input ends of the signal input module and the input ends of the weight adjustment module in nine parallel branches. The output ends of the signal input module and the weight adjustment module are respectively connected to the input end of the summing module ①. The output end of the summing module ① is connected to one end of the memristor. The other end of the memristor combines the nine signals together and is connected to the input end of a single summing module ②. The output end of the summing module ② is connected to the input end of the sampling module. The output end of the sampling module is the output voltage signal and is connected to the input end of the comparison module. The output end of the comparison module is the feedback adjustment voltage signal and is connected to the other input end of the weight adjustment module.

2. The brain-computer interface signal recognition circuit based on a memristive neural network according to claim 1, wherein The signal input module consists of operational amplifier A 1n1 , NMOS transistor M 1n1 and resistor R 1n1 , where n = 1, 2, 3,... 9; here, the first 1 in the subscript of the operational amplifier, NMOS transistor, and resistor indicates that the neuron number where they are located is the first neuron, the second n indicates that the input signal number they are connected to is n, and the third 1 indicates that the numbers of the operational amplifier, NMOS transistor, and resistor are 1, and subsequent numbers follow this pattern; the input signal V inn is connected to the inverting input terminal of operational amplifier A 1n1 , where the n in the subscript of V inn represents the number of the input voltage signal, n = 1, 2, 3,... 9; the output terminal of operational amplifier A 1n1 is connected to the non-inverting input terminal and then connected to the source of NMOS transistor M 1n1 , the gate of NMOS transistor M 1n1 is connected to the control voltage signal V ctrl1 , the drain of NMOS transistor M 1n1 is connected to one end of resistor R 1n1 , and the substrate of NMOS transistor M 1n1 is grounded; the other end of resistor R 1n1 is grounded; among them, the drain of M 1n1 is also connected to one end of resistor R 1n3 , and the voltage at the connection point is denoted as V' inn , and is used as one of the input signals of the next-level summation module ①.

3. The brain-computer interface signal recognition circuit based on a memristive neural network according to claim 1, wherein The weight adjustment module consists of PMOS transistors M 1n2 and M 1n3 , NMOS transistors M 1n4 -M 1n6 , adjustment voltage sources V adj+ and V adj- , and a resistor R 1n2 to form an analog circuit NAND gate, where n = 1, 2, 3,... 9; here, the sources of M 1n2 and M 1n3 are connected together and connected to the adjustment voltage V adj+ , the drains of M 1n2 and M 1n3 are connected together and connected to the drain of M 1n4 , the substrates of M 1n2 and M 1n3 are connected to the +5V voltage source, the gate of M 1n2 is connected to the input voltage signal V inn , the gate of M 1n3 is connected to the feedback adjustment voltage signal V cp1 output by the comparison module; the drain of the NMOS transistor M 1n4 is connected to the source of M 1n6 , and the voltage at the connection point is denoted as V adjn ; the gate of M 1n4 is connected to the input voltage signal V inn , the source of M 1n4 is connected to the drain of M 1n5 , the substrate of M 1n4 is connected to the -5V DC voltage source; the gate of the NMOS transistor M 1n5 is connected to the feedback adjustment voltage signal V cp1 output by the comparison module, the source is connected to the adjustment voltage V adj- , and the substrate is connected to the -5V DC voltage source; the gate of the NMOS transistor M 1n6 is connected to the control clock voltage signal V ctrl2 ; the drain of M 1n6 is connected to one end of R 1n2 , and its output voltage is used as one of the input voltages of the summing module ①, denoted as V' adjn ; the other end of the resistor R 1n2 is grounded.

4. The brain-computer interface signal recognition circuit based on a memristive neural network according to claim 1, characterized in that The summation module ① consists of resistors R 1n3 -R 1n8 and operational amplifiers A 1n2 、A 1n3 where n = 1, 2, 3,... 9; the voltage signal V' inn from the signal input module is connected to one end of the resistor R 1n3 , and the adjusted voltage signal V' adjn from the weight adjustment module is connected to one end of the resistor R 1n4 ; the other end of the resistor R 113 is connected to the other end of the resistor R 1n4 and is connected to the inverting input terminal of the operational amplifier A 1n2 ; one end of the resistor R 1n5 is connected to the non-inverting input terminal of the operational amplifier A 1n2 , and the other end of the resistor R 1n5 is grounded; the resistor R 1n6 is connected across the output terminal and the inverting input terminal of the operational amplifier A 1n2 ; the resistors R 1n7 , R 1n8 and the operational amplifier A 1n3 together form an inverter; one end of the resistor R 1n7 is connected to the output terminal of the operational amplifier A 1n2 , and the other end of R 1n7 is connected to the non-inverting input terminal of A 1n3 ; R 1n8 is connected across the inverting input terminal and the output terminal of the operational amplifier A 1n3 , and the voltage signal at the output terminal of the operational amplifier A 1n3 is used as the input signal at one end of the memristor MR 1n and is denoted as V sum_1n ; the other end of the memristor MR 1n is connected to the resistor R 1n9 of the next summation module ②; here, the first 1 in the subscript of the memristor MR 1n represents the first neuron, and the latter n represents the serial number of the connected input voltage signal.

5. The brain-computer interface signal recognition circuit based on a memristive neural network according to claim 1, characterized in that The summation module ② and the memristor consist of a resistor R 119 -R 199 a resistor R 11 -R 14 an operational amplifier A 14 A 15 and a memristor MR 1n ; V sum_1n is connected to one end of the memristor MR 1n and the other end of the memristor MR 1n is connected to the resistor R 1n9 where n = 1, 2, 3,... 9; the resistor R 119 to the resistor R 199 are connected to the inverting input terminal of the operational amplifier A 14 ; here, the first digit 1 of the subscript of the operational amplifier A 14 represents the number of the neuron circuit, and the latter digit 4 represents the number of the operational amplifier in the circuit; the resistor R 11 is connected across the output terminal and the inverting input terminal of the operational amplifier A 14 , one end of the resistor R 12 is connected to the non-inverting input terminal of the operational amplifier A 14 and the other end is grounded; one end of the resistor R 13 is connected to the output terminal of the operational amplifier A 14 and the other end is connected to the non-inverting input terminal of the operational amplifier A 15 ; the resistor R 14 is connected across the inverting input terminal and the output terminal of the operational amplifier A 15 ; the output signal of the output terminal of A 15 is used as the input signal of the next-stage sampling module, denoted as V sum_1 .

6. The brain-computer interface signal recognition circuit based on a memristive neural network according to claim 1, wherein The sampling module consists of a sample and hold circuit Q1, a capacitor C1, and positive and negative voltage sources; the capacitor C1 is used to store the sampled voltage signal, and the positive and negative voltage sources with voltage values of +15V and -15V respectively serve as the power supply for the sample and hold circuit Q1 to control the voltage V ctrl1 for controlling the sampling period of the sample and hold circuit Q1, and the output voltage of the sample and hold circuit Q1 is the output voltage signal V of the first neuron out1 , and at the same time, this output voltage signal V out1 serves as the input voltage of the next-level comparison module.

7. A brain-computer interface signal recognition circuit based on a memristive neural network according to claim 1, characterized in that The comparison module consists of a resistor R 15 -R 18 , reference voltage source V1 and operational amplifier A 16 Composition: The output voltage signal V of the neuron out1 With resistor R 15 One end of the resistor R 15 The other end is connected to the operational amplifier A 16 The inverting input terminal is connected to the resistor R 17 One end is connected to the reference voltage source V1, and the other end is connected to the operational amplifier A 16 At the same time, the resistor R 18 One end of the operational amplifier A 16 Also connected to the non-inverting input terminal, resistor R 18 The other end of the resistor R 16 Across operational amplifier A 16 Between the output and the inverting input; Operational amplifier A 16 Output signal V cp1 As a feedback adjustment voltage signal, it is input into the weight adjustment module.

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