Memory and operating method thereof, memory system, and electronic device

Abstract

Embodiments of the present disclosure disclose a memory and an operating method thereof, a memory system and an electronic device. The memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the peripheral circuit comprises: a temperature sensing circuit configured to sense a temperature of the memory and generate a temperature signal based on the sensed temperature; a control logic circuit configured to determine a target refresh period based on the temperature signal and a mapping table; wherein the mapping table comprises a plurality of preset temperature signals and a plurality of preset refresh periods, and the plurality of preset temperature signals and the plurality of preset refresh periods correspond one by one; and a refresh control circuit configured to adjust a refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to instruct to perform a refresh operation on the memory cell array.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and includes, but is not limited to, a memory and its operation method, a memory system, and an electronic device. Background Technology

[0002] Semiconductor memories are classified into volatile memories and non-volatile memories based on whether they retain stored data when power is off. Volatile memories, which lose data when power is off, can include Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM).

[0003] Volatile memory maintains the data stored in its cells through periodic refreshes. As temperature increases, the data retention characteristics of the cells deteriorate, therefore, refresh operations need to be performed with shorter refresh cycles (i.e., more frequent refreshes) to ensure data reliability. However, frequent refreshes lead to increased power consumption. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory, an operation method thereof, a memory system, and an electronic device.

[0005] In a first aspect, embodiments of this disclosure provide a memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array; the peripheral circuitry includes:

[0006] A temperature sensing circuit, configured to: sense the temperature of the memory and generate a temperature signal based on the sensed temperature;

[0007] A control logic circuit is configured to determine a target refresh period based on the temperature signal and a mapping table; wherein the mapping table includes multiple preset temperature signals and multiple preset refresh periods, and the multiple preset temperature signals and the multiple preset refresh periods correspond one-to-one.

[0008] A refresh control circuit is configured to adjust the refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to indicate that a refresh operation is performed on the memory cell array.

[0009] Secondly, embodiments of this disclosure also provide a method for operating a memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array; the method includes:

[0010] The temperature of the memory is sensed, and a temperature signal is generated based on the sensed temperature;

[0011] The target refresh period is determined based on the temperature signal and the mapping table; wherein, the mapping table includes multiple preset temperature signals and multiple preset refresh periods, and the multiple preset temperature signals and the multiple preset refresh periods correspond one-to-one;

[0012] The refresh period of the refresh signal is adjusted to the target refresh period; wherein the refresh signal is used to indicate that a refresh operation is performed on the storage cell array.

[0013] Thirdly, embodiments of this disclosure also provide a memory system, the memory system comprising:

[0014] One or more memories as described in any of the above embodiments;

[0015] A memory controller is coupled to the memory and configured to control the memory.

[0016] Fourthly, embodiments of this disclosure also provide an electronic device, including a memory system as described in the above embodiments.

[0017] In this embodiment, a temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature. A control logic circuit determines the target refresh period based on the temperature signal and a mapping table. The refresh control circuit adjusts the refresh period of the refresh signal to the target refresh period. Thus, firstly, the refresh period can be adjusted based on temperature changes, avoiding data loss and ensuring data reliability; secondly, the refresh period can be flexibly adjusted based on temperature changes, avoiding frequent refresh operations, thereby reducing power consumption and increasing the lifespan of the memory; and thirdly, without changing the circuit design, different mapping tables can be customized for different memories, increasing the flexibility of refresh period adjustment. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a system according to an embodiment of the present disclosure;

[0019] Figure 2a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0020] Figure 2b This is a schematic diagram of a solid-state drive according to an embodiment of the present disclosure;

[0021] Figure 3 This is a schematic diagram illustrating the change of leakage current with temperature according to an embodiment of the present disclosure;

[0022] Figure 4 This is a schematic diagram illustrating the change of data retention time with temperature according to embodiments of the present disclosure;

[0023] Figure 5 These are refresh cycles at different temperatures as shown in embodiments of this disclosure;

[0024] Figure 6 This is a schematic diagram illustrating the change in power consumption with the self-refresh cycle according to an embodiment of this disclosure;

[0025] Figure 7a and Figure 7b This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0026] Figure 8 This is a schematic diagram illustrating the refresh cycle as a function of temperature according to an embodiment of the present disclosure;

[0027] Figure 9 This is a schematic diagram illustrating another refresh cycle as a function of temperature according to an embodiment of the present disclosure;

[0028] Figure 10 This is a schematic diagram of another memory according to an embodiment of the present disclosure;

[0029] Figure 11 This is a flowchart illustrating a method of operating a memory according to an embodiment of the present disclosure;

[0030] Figure 12 This is a schematic diagram illustrating an adjustment of the refresh cycle according to an embodiment of the present disclosure;

[0031] Figure 13 This is a schematic diagram illustrating a process for generating a mapping table using an algorithm according to an embodiment of this disclosure;

[0032] Figure 14 This is a schematic diagram illustrating a process for adjusting a temperature window according to an embodiment of the present disclosure. Detailed Implementation

[0033] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0035] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0036] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0038] Figure 1 This is a schematic diagram illustrating a system 100 according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0039] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0040] Memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital Memory Card (SD Card), Compact Flash Card (CF Card), Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state disks (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0041] The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and write operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with a host (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIE), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced System Device Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0042] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a general-purpose flash memory package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Reduced-Size MMC (RS-MMC), a Multimedia Card Micro (MMCmicro), an SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. The memory 104 may include volatile and non-volatile memory, such as NAND flash memory, dynamic random access memory, ferroelectric random access memory, magnetic random access memory, phase-change random access memory, resistive random access memory, nano-random access memory, etc.

[0043] The leakage current of volatile memory cells is directly proportional to temperature; that is, the leakage current increases as the temperature rises. Figure 3 As shown. Because the charge stored in a memory cell is limited, the data retention time of the memory cell is inversely proportional to temperature. For example, the data retention time at 40℃ is t1, and at 80℃ it is t2, where t2 is less than t1. Figure 4 As shown. To ensure data reliability, volatile memory requires periodic refresh operations to maintain the data stored in the memory cells.

[0044] There are two methods for periodic refresh operations: one is where the memory controller issues a periodic refresh command, and the memory controller is responsible for maintaining the data; the other is where the memory internally generates a refresh signal (also known as self-refresh). Self-refresh is a method used to maintain data without external refresh commands. The memory has an internal timer that can trigger periodic refresh operations internally. When the user issues a self-refresh enter command, the memory enters self-refresh mode, and automatically performs refresh operations until a self-refresh exit command is issued.

[0045] Self-refresh operations typically employ a fixed refresh cycle, which should be short enough to ensure data integrity at high temperatures. For example, to ensure proper operation of the memory at temperatures below 80°C, the refresh cycle should be less than t2. However, this would result in excessively frequent self-refresh operations at temperatures below 80°C, leading to additional power consumption without any benefit and reducing the memory's lifespan.

[0046] It should be noted that since leakage current increases with increasing temperature, the refresh cycle of the self-refresh operation must decrease as temperature rises. For example, the refresh cycle at low temperatures is t... low At high temperatures, the value is t. high , t high Less than t low ,like Figure 5 As shown. However, a shorter refresh cycle means a higher refresh rate, which will result in higher power consumption. For example, a refresh cycle of t... low At that time, the power consumption is P low The refresh cycle is t high At that time, the power consumption is P high P high Greater than P low ,like Figure 6 As shown.

[0047] In view of this, in order to solve one or more of the above-mentioned technical problems, this disclosure provides a memory.

[0048] Figure 7a and Figure 7b This is a schematic diagram illustrating a memory 300 according to an embodiment of the present disclosure. (Refer to...) Figure 7a and Figure 7b As shown, the memory 300 includes a memory cell array 320 and peripheral circuitry 310 coupled to the memory cell array 320; the peripheral circuitry 310 includes:

[0049] Temperature sensing circuit 330 is configured to: sense the temperature of memory 300 and generate a temperature signal based on the sensed temperature;

[0050] The control logic circuit 340 is configured to determine the target refresh period based on the temperature signal and the mapping table; wherein the mapping table includes multiple preset temperature signals and multiple preset refresh periods, and the multiple preset temperature signals and multiple preset refresh periods correspond one-to-one.

[0051] The refresh control circuit 350 is configured to adjust the refresh period of the refresh signal to a target refresh period; wherein the refresh signal is used to indicate that a refresh operation is performed on the memory cell array 320.

[0052] In this embodiment of the disclosure, the memory 300 includes, but is not limited to, DRAM, Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), and High Bandwidth Memory (HBM).

[0053] Reference Figure 7b As shown, the memory 300 includes multiple word lines 322 and multiple bit lines 323. The peripheral circuitry 310 is coupled to the memory cell array 320 via the word lines 322 and bit lines 323. The memory cell array 320 includes multiple memory cells 321 arranged in an array. Each memory cell 321 includes a transistor 324 and an energy storage element 325 coupled to the transistor 324. The transistor 324 includes a semiconductor pillar 326, a gate dielectric layer 327, and a gate 328. The semiconductor pillar includes a source, a drain, and a channel between the source and drain. The gate dielectric layer 327 covers the sidewalls of the channel. The gate 328 is in contact with at least one sidewall of the gate dielectric layer 327. Word lines 322 are coupled to the gates of memory cells 321 located in the same row, and bit lines 323 are coupled to the semiconductor pillars (e.g., the drains of the semiconductor pillars) of memory cells 321 located in the same column.

[0054] In one specific embodiment, the storage cell 321 can be a volatile storage cell, such as a DRAM storage cell, and the energy storage element 325 can be a capacitor. Of course, in other embodiments, the storage cell 321 can be a phase-change storage cell, and the energy storage element 325 can be a phase-change storage layer; or, the storage cell 321 can also be a ferroelectric storage cell, and the energy storage element 325 can be a ferroelectric storage layer; this disclosure does not limit this.

[0055] The temperature sensing circuit 330 can sense the temperature of the memory 300 and output a temperature signal based on the sensed temperature. In one embodiment, the temperature sensing circuit 330 includes a temperature sensor that can convert an analog temperature signal into a digital temperature signal and send the digital temperature signal to the control logic circuit 340. The temperature signal output by the temperature sensor can be a voltage signal corresponding to the sensed temperature, and there can be one or more temperature sensors. Although this embodiment describes the case where the temperature sensing circuit 330 is located inside the memory 300, the temperature sensing circuit 330 can also be located outside the memory 300 and sense the temperature of the memory 300.

[0056] It should be noted that the operating temperature range of the memory 300 can be divided into multiple temperature segments, and the temperature signals corresponding to different temperatures can be the same or different. For example, if the first temperature and the second temperature belong to the same temperature segment, then the temperature signals corresponding to the first temperature and the second temperature can be the same; or, for another example, if the first temperature and the second temperature belong to different temperature segments, then the temperature signals corresponding to the first temperature and the second temperature can be different.

[0057] For example, refer to Figure 8 As shown, seven key temperatures are selected within the operating temperature range of memory 300, for example, key temperature T. e1 T e2 T e3 T e4 T e5 T e6 and T e7 The temperature can be divided into 7 temperature zones, each corresponding to a preset temperature signal. For example, the preset temperature signal T in Table 1... code1 T code2 T code3 T code4 T code5 T code6 and T code7 .

[0058] In a specific example, the operating temperature range of the memory 300 is 20℃ ≤ T ≤ 80℃, with seven key temperatures of 25℃, 35℃, 45℃, 50℃, 60℃, 70℃, and 80℃. When the temperature sensing circuit 330 senses a temperature of 40℃ in the memory 300, corresponding to the third temperature range, the temperature sensor outputs a temperature signal T. code3 .

[0059] It should be noted that the critical temperature and / or the number of critical temperatures can be determined based on the temperature-dependent characteristics of the leakage current of the memory 300. For example, if the leakage current of the memory 300 changes drastically at at least one temperature, that temperature can be determined as a critical temperature. Alternatively, if the leakage current of the memory 300 is highly sensitive to temperature changes, more critical temperatures can be selected, thereby dividing the memory into more temperature ranges to achieve finer adjustments to the refresh cycle. The above values ​​are merely examples to convey this disclosure to those skilled in the art, and the number of critical temperatures and / or critical temperatures is not limited thereto.

[0060] The control logic circuit 340 can receive temperature signals and determine the target refresh period based on the received temperature signals and a mapping table. For example, referring to Table 1, the mapping table includes seven preset temperature signals T. code1 T code2 T code3 T code4 T code5 T code6 and T code7 The seven preset temperature signals correspond to seven preset refresh cycles R1, R2, R3, R4, R5, R6, and R7, respectively. When the control logic circuit 340 receives the temperature signal T... code3 When the target refresh period is determined to be R3, the refresh control circuit 350 adjusts the refresh period of the refresh signal to the target refresh period R3, and performs a refresh operation on the memory cell array 320 with the target refresh period R3 as the refresh period.

[0061] Table 1 Mapping Table

[0062]

[0063] For example, at the first moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 is 75°C and outputs a temperature signal T. code7 The control logic circuit 340 is based on the temperature signal T. code7 The target refresh period is determined by looking up the mapping table as R7. The refresh control circuit 350 adjusts the refresh period of the refresh signal to the target refresh period R7 to avoid data loss. At the second moment, the temperature sensing circuit 330 senses that the temperature of the memory 300 has dropped to 40°C and outputs a temperature signal T. code3 The control logic circuit 340 is based on the temperature signal T. code3The target refresh period is determined by looking up the mapping table as R3, and the refresh control circuit 350 adjusts the refresh signal's refresh period to the target refresh period R3. It is understood that when the temperature drops to 40℃, the leakage current of the memory cell will decrease, and adjusting the refresh period to the target refresh period R3 is sufficient to retain data, thus avoiding frequent refreshes. In this way, the refresh period can be adjusted based on temperature changes to avoid data loss and ensure data reliability; at the same time, flexibly adjusting the refresh period based on temperature changes avoids frequent refresh operations, thereby reducing power consumption.

[0064] In practical applications, different mapping tables can be customized for different types of memory, increasing the flexibility of refresh cycle adjustment. For example, before the memory leaves the factory, R&D personnel develop and design different mapping tables for different types of memory and write (also known as programming) these mapping tables into the memory.

[0065] In this embodiment, a temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature. A control logic circuit determines the target refresh period based on the temperature signal and a mapping table. The refresh control circuit adjusts the refresh period of the refresh signal to the target refresh period. Thus, firstly, the refresh period can be adjusted based on temperature changes, avoiding data loss and ensuring data reliability; secondly, the refresh period can be flexibly adjusted based on temperature changes, avoiding frequent refresh operations, thereby reducing power consumption and increasing the lifespan of the memory; and thirdly, without changing the circuit design, different mapping tables can be customized for different memories, increasing the flexibility of refresh period adjustment.

[0066] In some embodiments, the peripheral circuit 310 further includes:

[0067] The register circuit 360 is configured to store a mapping table; wherein the mapping table includes multiple sub-mapping tables, which are used to record the correspondence between preset temperature signals and preset refresh cycles.

[0068] Address decoding circuit 370 is configured to: decode and generate a first target address based on a temperature signal; wherein the first target address is used to indicate the physical address of a first sub-mapping table in a plurality of sub-mapping tables;

[0069] The control logic circuit 340 is specifically configured to: obtain the first sub-mapping table based on the first target address and determine the target refresh cycle.

[0070] In this embodiment, the mapping table can be stored in the register circuit 360. The mapping table includes multiple sub-mapping tables, and different sub-mapping tables record the correspondence between different preset temperature signals and preset refresh periods. For example, referring to Table 1, the mapping table includes 7 sub-mapping tables, and the first sub-mapping table records the preset temperature signal T. code1 The mapping relationship between the preset refresh period R1 and the second sub-mapping table records the preset temperature signal T. code2 The mapping relationship between the preset refresh cycle R2, ..., the 7th sub-mapping table records the preset temperature signal T. code7 The mapping relationship between the preset refresh cycle R7 and the mapping table has a number of sub-mapping tables that are not limited to 7. The number of sub-mapping tables can be less than or greater than 7.

[0071] For example, the address decoding circuit 370 receives the temperature signal T. code3 The temperature signal is decoded to generate a first target address, which is then sent to the control logic circuit 340. The control logic circuit 340 reads the third sub-mapping table in the register circuit 360 based on the first target address to determine the target refresh period R3. It is understood that multiple sub-mapping tables are stored in different locations within the register circuit 360, corresponding to multiple different physical addresses. The first sub-mapping table is one of these multiple sub-mapping tables, and the first target address is the physical address corresponding to that sub-mapping table. In this example, the first sub-mapping table is the third sub-mapping table, and the first target address is the physical address of the third sub-mapping table.

[0072] The register circuit 360 includes, but is not limited to, a mode register. The mode register can store various operating parameters and control parameters of the operating memory 300. The mode register can be programmed to set multiple operating parameters and control parameters, and it can store parameter codes. For example, the mode register can store parameter codes (i.e., a mapping table) for multiple refresh cycles related to the temperature signal. The mode register can be read to determine the target refresh cycle. In one specific embodiment, the mode register can store data temporarily or permanently.

[0073] In some embodiments, the memory cell array 320 includes a first memory cell and a second memory cell, wherein the data retention time of the second memory cell is shorter than the data retention time of the first memory cell; the control logic circuit 340 is specifically configured to:

[0074] Based on the first target address, obtain the first sub-mapping table and determine the first target refresh cycle of the first storage unit;

[0075] Based on the first target address with offset, the second sub-mapping table of multiple sub-mapping tables is obtained to determine the second target refresh period of the second storage unit; wherein, the second sub-mapping table is different from the first sub-mapping table; the second target refresh period is less than the first target refresh period.

[0076] The storage cell array 320 includes multiple storage cells 321. The data retention characteristics of any two storage cells 321 at the same temperature may be the same or different, depending on the characteristics of the storage cell 321. For example, if the storage cell array 320 includes a first storage cell and a second storage cell, at the same temperature, the data retention time of the second storage cell is shorter than that of the first storage cell, meaning the data retention characteristic of the second storage cell is worse. To avoid data loss, different refresh cycles can be set for storage cells with different data retention characteristics. The following will refer to Table 1... Figure 8 and Figure 9 Please provide an explanation.

[0077] For example, combining Table 1 and Figure 8 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40°C, it outputs a temperature signal T. code3 Address decoding circuit 370 is based on temperature signal T code3 The first target address is generated by decoding; the control logic circuit 340 reads the third sub-mapping table based on the first target address to determine the target refresh period R3 of the first memory cell. Here, the first sub-mapping table is the third sub-mapping table, the first target address is the physical address of the third sub-mapping table, and the first target refresh period is the target refresh period R3.

[0078] For example, combining Table 1 and Figure 9 As shown, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40°C, it outputs a temperature signal T. code3 Address decoding circuit 370 is based on temperature signal T code3 The first target address is generated by decoding; the control logic circuit 340 reads the fourth sub-mapping table based on the offset first target address to determine the target refresh period R4 of the second memory unit, where R4 < R3. Here, the second sub-mapping table is the fourth sub-mapping table, the offset first target address is the physical address of the fourth sub-mapping table, and the second target refresh period is the target refresh period R4.

[0079] It should be noted that in this embodiment, the second sub-mapping table can be obtained by offsetting the target address. In other embodiments, the second sub-mapping table can be obtained by offsetting the temperature signal. For example, a second target address different from the first target address is generated based on the offset temperature signal, and the second target address is used to indicate the physical address of the second sub-mapping table.

[0080] In this embodiment of the disclosure, a second sub-mapping table different from the first sub-mapping table can be obtained by offsetting the first target address. The second target refresh cycle is determined based on the second sub-mapping table. In this way, different refresh cycles can be set for storage units with different data retention characteristics, avoiding data loss in the second storage unit with poor data retention characteristics due to temperature rise, which is conducive to further ensuring data reliability.

[0081] In some embodiments, the first storage cell and the second storage cell are located in the same storage cell row; the refresh control circuit 350 is specifically configured to adjust the refresh period of the storage cell row to a second target refresh period.

[0082] The memory cell array 320 includes multiple rows of memory cells, each row of memory cells includes multiple memory cells 321, and each row of memory cells is coupled to a word line 322. Since the refresh operation of the memory 300 is usually performed row by row, when the first memory cell and the second memory cell are located in the same row of memory cells, the refresh period can be adjusted to the second target refresh period, thereby avoiding the loss of data in the first memory cell and the second memory cell.

[0083] In some embodiments, the first storage cell and the second storage cell are located in different rows of storage cells; the refresh control circuit 350 is specifically configured to: adjust the refresh period of the row of storage cells corresponding to the first storage cell to a first target refresh period; and adjust the refresh period of the row of storage cells corresponding to the second storage cell to a second target refresh period.

[0084] It is understood that in this embodiment of the present disclosure, when the first storage unit and the second storage unit are located in different rows of storage units, the refresh period can be adjusted for each row of storage units. That is, the refresh period of the row of storage units corresponding to the first storage unit is adjusted to the first target refresh period, and the refresh period of the row of storage units corresponding to the second storage unit is adjusted to the second target refresh period. While ensuring that the data of the first storage unit and the second storage unit is not lost, power consumption can be reduced and the service life of the memory can be increased.

[0085] In some embodiments, the peripheral circuit 310 further includes:

[0086] Address offset circuit 380 is configured to: generate a second target address based on a first target address, the second target address being used to indicate the physical address of a second sub-mapping table in a plurality of sub-mapping tables;

[0087] The control logic circuit 340 is specifically configured to: obtain the second sub-mapping table based on the second target address, and determine the second target refresh cycle.

[0088] For example, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40°C, it outputs a temperature signal T. code3 Address decoding circuit 370 is based on temperature signal T code3 Decode to generate the first target address; address offset circuit 380 generates the second target address based on the first target address; control logic circuit 340 reads the fourth sub-mapping table based on the second target address to determine the target refresh period R4 of the second storage unit, where R4 < R3.

[0089] In some embodiments, address offset operations can be performed for a specific temperature window. For example, temperature window T e2 To T e6 .

[0090] For example, refer to Figure 8 As shown, when the temperature is less than or equal to T e2 When the temperature is greater than T, the preset refresh cycle can be set to a fixed value R2 to avoid data loss while minimizing power consumption; e2 And less than or equal to T e6 At that time, four preset refresh cycles R3, R4, R5, and R6 can be set for the four temperature segments respectively; when the temperature is greater than T e6 And less than or equal to T e7 At this time, the preset refresh cycle can be set to a fixed value R7 to avoid data loss due to excessive temperature. It can be seen that within the temperature window T... e2 To T e6 Internally, the data retention characteristics of the storage unit change significantly with temperature; therefore, specific temperature windows T can be targeted. e2 To T e6 Perform an address offset operation.

[0091] For example, when the temperature sensed by the temperature sensor is greater than T e2 And less than or equal to T e6 At that time, the address offset circuit 380 can generate a second target address based on the first target address offset, and the control logic circuit 340 determines the first target refresh period and the second target refresh period based on the first target address and the second target address respectively, so as to adapt to the data retention characteristics of different memory units.

[0092] For example, when the temperature sensed by the temperature sensor is less than or equal to T e2 Or greater than T e6 At that time, the control logic circuit 340 determines the first target refresh cycle based on the first target address.

[0093] In this embodiment, by setting the address offset circuit 380, the first target address generated by decoding the temperature signal can be offset to generate a second target address, and the second target refresh cycle can be determined based on the second target address. Thus, for memory cells with different data retention characteristics, there is no need to change the mapping table or add other mapping tables (e.g., designing different mapping tables for memory cells with different data retention characteristics); the refresh cycle can be adjusted through simple circuit design.

[0094] In some embodiments, at a first temperature, there is a first difference between a first target refresh cycle and a second target refresh cycle; at a second temperature, there is a second difference between the first target refresh cycle and the second target refresh cycle; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

[0095] The difference between the data retention times of the first and second storage cells may vary at different temperatures. For example, at low temperatures, the difference is smaller; at high temperatures, the difference is larger. Therefore, different refresh cycle offsets can be set based on different temperatures.

[0096] For example, when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 40°C, it determines that the first target refresh period is R3 and the second target refresh period is R4, and there is a first difference between the first target refresh period R3 and the second target refresh period R4; when the temperature sensing circuit 330 senses that the temperature of the memory 300 is 60°C, it determines that the first target refresh period is R5 and the second target refresh period is R6, and there is a second difference between the first target refresh period R5 and the second target refresh period R6; wherein, the second difference is greater than the first difference.

[0097] In this embodiment of the disclosure, different refresh cycle offsets are set for different temperatures. Based on the differences in data retention characteristics of different storage units at different temperatures, the refresh cycle can be reasonably set, which is beneficial to further reduce power consumption and increase the lifespan of the memory 300.

[0098] Figure 10 This is a schematic diagram of another memory 300 according to an embodiment of the present disclosure. Figure 10 The memory cell array 320, temperature sensing circuit 330, control logic circuit 340, refresh control circuit 350, register circuit 360, address decoding circuit 370, and address offset circuit 380 are similar to those in the above embodiments and will not be described again. The difference from the above embodiments is that... Figure 10The peripheral circuit 310 also includes an electric fuse circuit 390, which is configured to store a mapping table. The control logic circuit 340 is specifically configured to read the mapping table in the electric fuse circuit 390 and save the read mapping table to the register circuit 360.

[0099] The electrical fuse circuit 390 is used to store the mapping table. The electrical fuse circuit 390 includes programmable logic devices, such as one-time programmable (OTP) registers, several-time programmable (FTP) registers, or multi-time programmable (MTP) registers. OTPs include fuse-based OTPs or anti-fuse OTPs. The mapping table can be written into the electrical fuse circuit 390 before the memory 300 leaves the factory. Because OTPs, FTPs, and MTPs are non-volatile, the mapping table can still be saved when the memory 300 is powered off, preventing the loss of the mapping table.

[0100] The control logic circuit 340 can first read the mapping table in the fuse circuit 390 and cache the read mapping table in the register circuit 360. Then, when the temperature changes (e.g., rises or falls), the target refresh period is determined based on the temperature signal output by the temperature sensing circuit 330 and the mapping table cached in the register circuit 360, and the refresh period of the refresh signal is adjusted to the target refresh period in a timely manner.

[0101] In this embodiment of the disclosure, by setting an electric fuse circuit to store the mapping table, due to the non-volatility of the electric fuse circuit, the mapping table can still be saved when the memory is powered off, thus avoiding the loss of the mapping table.

[0102] In some embodiments, the memory 300 is further configured to: after the usage time of the memory 300 is greater than or equal to a preset duration, update the preset refresh period corresponding to at least one preset temperature signal in the mapping table; wherein the updated preset refresh period is less than the preset refresh period corresponding to at least one preset temperature signal before the update.

[0103] Compared to when it was first manufactured, the performance of the memory 300 may degrade after a period of use; for example, the data retention time of the memory cells may decrease at at least one temperature. Therefore, after the memory 300 has been used for a period greater than or equal to a preset duration, the preset refresh period corresponding to at least one preset temperature signal can be adjusted to a smaller value. For example, the preset temperature signal T in the third sub-mapping table... code3 The corresponding preset refresh cycle is R3. After a period of use, the preset temperature signal T in the third sub-mapping table can be refreshed. code3The corresponding preset refresh period is R3', where R3' is less than R3. The preset duration includes one month, six months, one year, or other longer periods. It should be noted that after the usage time of the memory 300 is greater than or equal to the preset duration, the preset refresh period corresponding to one or more preset temperature signals in the mapping table can be updated, and this disclosure does not impose any special restrictions on this.

[0104] In this embodiment, after the memory usage time is greater than or equal to a preset duration, the preset refresh period corresponding to at least one preset temperature signal in the mapping table is updated, and the updated preset refresh period is less than the preset refresh period corresponding to the at least one preset temperature signal before the update. In this way, the preset refresh period corresponding to the preset temperature signal can be adjusted in a timely manner according to the memory usage time, further preventing data loss and increasing the memory's lifespan.

[0105] Based on the above-described memory, this disclosure also provides a method for operating the memory.

[0106] Figure 11 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. (Refer to...) Figure 11 As shown, this operation method includes at least the following steps:

[0107] Step S410: Sensing the temperature of the memory and generating a temperature signal based on the sensed temperature;

[0108] Step S420: Determine the target refresh period based on the temperature signal and the mapping table; wherein, the mapping table includes multiple preset temperature signals and multiple preset refresh periods, and the multiple preset temperature signals and multiple preset refresh periods correspond one-to-one;

[0109] Step S430: Adjust the refresh period of the refresh signal to the target refresh period; wherein, the refresh signal is used to indicate that a refresh operation is performed on the memory cell array.

[0110] In some embodiments, the mapping table includes multiple sub-mapping tables, which are used to record the correspondence between preset temperature signals and preset refresh cycles; step S420 above includes:

[0111] Based on the temperature signal, a first target address is generated by decoding; wherein, the first target address is used to indicate the physical address of the first sub-mapping table in multiple sub-mapping tables;

[0112] Based on the first target address, obtain the first sub-mapping table and determine the target refresh cycle.

[0113] In some embodiments, the storage cell array includes a first storage cell and a second storage cell, wherein the data retention time of the second storage cell is shorter than the data retention time of the first storage cell;

[0114] The above-mentioned process of obtaining the first sub-mapping table based on the first target address and determining the target refresh cycle includes:

[0115] Based on the first target address, obtain the first sub-mapping table and determine the first target refresh cycle of the first storage unit;

[0116] The above operating methods also include:

[0117] Based on the first target address with offset, the second sub-mapping table of multiple sub-mapping tables is obtained to determine the second target refresh period of the second storage unit; wherein, the second sub-mapping table is different from the first sub-mapping table; the second target refresh period is less than the first target refresh period.

[0118] In some embodiments, obtaining the second sub-mapping table from multiple sub-mapping tables based on the first target address with an offset, and determining the second target refresh period of the second storage unit, includes:

[0119] Based on the first target address, an offset is generated to generate a second target address, which is used to indicate the physical address of the second sub-mapped table in multiple sub-mapped tables;

[0120] Based on the second target address, obtain the second sub-mapping table and determine the second target refresh cycle.

[0121] In some embodiments, at a first temperature, there is a first difference between a first target refresh cycle and a second target refresh cycle; at a second temperature, there is a second difference between the first target refresh cycle and the second target refresh cycle; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

[0122] In some embodiments, the first storage unit and the second storage unit are located in the same storage unit row; adjusting the refresh period of the refresh signal to the target refresh period includes:

[0123] Adjust the refresh cycle of the storage cell row to the second target refresh cycle.

[0124] In some embodiments, the first storage unit and the second storage unit are located in different rows of storage units; adjusting the refresh period of the refresh signal to the target refresh period includes:

[0125] Adjust the refresh cycle of the storage cell row corresponding to the first storage cell to the first target refresh cycle;

[0126] The refresh cycle of the storage cell row corresponding to the second storage cell is adjusted to the second target refresh cycle.

[0127] In some embodiments, the peripheral circuitry includes an electric fuse circuit and a register circuit, wherein the electric fuse circuitry is configured to store a mapping table; the above-described operation method further includes:

[0128] Read the mapping table in the electric fuse circuit and save the read mapping table to the register circuit.

[0129] In some embodiments, the above-described operation method further includes:

[0130] After the memory usage time is greater than or equal to a preset duration, the preset refresh period corresponding to at least one preset temperature signal in the mapping table is updated; wherein the updated preset refresh period is less than the preset refresh period corresponding to at least one preset temperature signal before the update.

[0131] The above operation method has been described in detail on the memory side, and will not be repeated here for the sake of brevity.

[0132] Figure 12 This is a schematic diagram illustrating an embodiment of the present disclosure of adjusting the refresh cycle. (Refer to...) Figure 12 As shown, the temperature sensing circuit senses the temperature of the memory and generates a temperature signal based on the sensed temperature; the control logic circuit receives the temperature signal and determines the target refresh cycle based on the temperature signal and a mapping table; the refresh control circuit adjusts the refresh cycle of the refresh signal to the target refresh cycle. Here, the mapping table is used to store the results of the computer algorithm, which can be developed in parallel with the memory circuit design; it is written after chip testing. Of course, during other circuit design and chip testing processes, the algorithm can be optimized based on the circuit design and test results.

[0133] In one specific embodiment, reference is made to Figure 12 As shown, the address decoding circuit receives the temperature signal, decodes the temperature signal to generate the target address; the control logic circuit reads the first sub-mapping table in the register circuit based on the target address and outputs the result, which is used to indicate the target refresh cycle.

[0134] Figure 13 This is a schematic diagram illustrating a process for generating a mapping table using an algorithm, according to an embodiment of this disclosure. The following will be combined with... Figure 13 The process of generating a mapping table according to the embodiments of this disclosure will be described in the above embodiments.

[0135] Perform step S510: Select critical temperatures. Select at least one critical temperature within the operating temperature range of the memory. For example, if the operating temperature range of the memory is 20℃≤T≤80℃, seven critical temperatures can be selected: 25℃, 35℃, 45℃, 50℃, 60℃, 70℃, and 80℃.

[0136] Step S520: Calculate the configuration values. Calculate the refresh cycles (i.e., configuration values) corresponding to the above 7 key temperatures, and establish the correspondence between the 7 key temperatures and the 7 configuration values, i.e., a mapping table.

[0137] Step S530: Save the mapping table to the fuse circuit. For example, the data in the mapping table can be saved to the fuse circuit by programming.

[0138] Perform step S540: Test configuration values. For example, provide a test temperature to test the memory.

[0139] Step S550: Based on the test results, determine whether the configuration value meets the requirements; if yes, complete; if no, return to step S520, recalculate the configuration value by adjusting the algorithm, and write the newly calculated configuration value into the capacitor wire circuit until the requirements are met. Here, at the test temperature, when the configuration value corresponding to the test temperature is used as the refresh cycle, the memory is sufficient to retain the data, and it can be determined that the configuration value meets the requirements.

[0140] Figure 14 This is a schematic flowchart illustrating an adjustment of a temperature window according to an embodiment of this disclosure. The following will be combined with... Figure 14 The process of adjusting the temperature window in the embodiments of this disclosure will be described in conjunction with the above embodiments.

[0141] Execute step S610: Select critical temperatures. Select at least one critical temperature within the operating temperature range of the memory. For example, if the operating temperature range of the memory is 20℃≤T≤80℃, seven critical temperatures can be selected: 25℃, 35℃, 45℃, 50℃, 60℃, 70℃, and 80℃.

[0142] Step S620: Determine the temperature window. For example, when the temperature is greater than 40°C and less than or equal to 70°C, the refresh cycle changes with the temperature, and 40°C to 70°C can be used as the temperature window.

[0143] Execute step S630: Offset the temperature signal. For example, if the above temperature window cannot meet the requirements, the minimum threshold of the temperature window needs to be switched from 40℃ to 35℃. Simply offset the temperature by -5℃ so that the actual temperature is 40℃, while the temperature signal is the temperature signal corresponding to 35℃. Then, read the configuration value according to the offset temperature signal.

[0144] Perform step S640: Test configuration values. For example, provide a test temperature to test the memory.

[0145] Step S650: Determine whether the requirements are met based on the test results; if yes, complete; if no, return to step S630, adjust the algorithm to re-offset the temperature signal, and write the configuration value corresponding to the new temperature window into the capacitor wire circuit until the requirements are met. Here, at the test temperature, when the configuration value corresponding to the test temperature is used as the refresh cycle, the memory is sufficient to hold the data, and it can be determined that the temperature window meets the requirements.

[0146] This disclosure also provides a memory system, such as... Figure 1 As shown, the memory system 102 includes:

[0147] One or more memory 300 as described in any of the above embodiments;

[0148] The memory controller 106 is coupled to the memory 300 and configured to control the memory 300.

[0149] Memory 300 can be referenced accordingly Figure 1 The memory 104 in the illustrated embodiment will not be described in detail here, nor will the functions, applications, and interactions between the memory 300 and the memory controller 106 be repeated.

[0150] This disclosure also provides an electronic device, including a memory system as described in the above embodiments.

[0151] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0152] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0153] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a first memory cell and a second memory cell, wherein the data retention time of the second memory cell is shorter than the data retention time of the first memory cell; The peripheral circuit includes: A temperature sensing circuit, configured to: sense the temperature of the memory and generate a temperature signal based on the sensed temperature; A control logic circuit is configured to: determine a target refresh period based on the temperature signal and a mapping table; wherein the mapping table includes multiple preset temperature signals and multiple preset refresh periods, and the multiple preset temperature signals and multiple preset refresh periods correspond one-to-one; the mapping table includes multiple sub-mapping tables, and the sub-mapping tables are used to record the correspondence between the preset temperature signals and the preset refresh periods; A refresh control circuit is configured to adjust the refresh period of a refresh signal to the target refresh period; wherein the refresh signal is used to indicate that a refresh operation is performed on the memory cell array. An address decoding circuit is configured to: decode and generate a first target address based on the temperature signal; wherein the first target address is used to indicate the physical address of a first sub-mapping table in the plurality of sub-mapping tables; Specifically, the control logic circuit is configured as follows: Based on the first target address, obtain the first sub-mapping table and determine the first target refresh period of the first storage unit; Based on the offset of the first target address, the second sub-mapping table of the plurality of sub-mapping tables is obtained, and the second target refresh period of the second storage unit is determined; wherein, the second sub-mapping table is different from the first sub-mapping table; the second target refresh period is less than the first target refresh period.

2. The memory according to claim 1, characterized in that, The peripheral circuit also includes: A register circuit configured to store the mapping table.

3. The memory according to claim 1, characterized in that, The peripheral circuit also includes: An address offset circuit is configured to: generate a second target address based on the first target address, the second target address being used to indicate the physical address of the second sub-mapping table; The control logic circuit is specifically configured to: obtain the second sub-mapping table based on the second target address, and determine the second target refresh period.

4. The memory according to claim 1, characterized in that, At the first temperature, there is a first difference between the first target refresh cycle and the second target refresh cycle; At the second temperature, there is a second difference between the first target refresh cycle and the second target refresh cycle; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

5. The memory according to claim 1, characterized in that, The first storage unit and the second storage unit are located in the same storage unit row; the refresh control circuit is specifically configured as follows: The refresh cycle of the storage cell row is adjusted to the second target refresh cycle.

6. The memory according to claim 1, characterized in that, The first storage unit and the second storage unit are located in different rows of storage units; the refresh control circuit is specifically configured as follows: Adjust the refresh period of the storage cell row corresponding to the first storage cell to the first target refresh period; The refresh period of the storage cell row corresponding to the second storage cell is adjusted to the second target refresh period.

7. The memory according to claim 1, characterized in that, The peripheral circuit also includes: An electric fuse circuit, the electric fuse circuit being configured to store the mapping table; The control logic circuit is specifically configured to: read the mapping table in the electric fuse circuit and save the read mapping table to the register circuit.

8. The memory according to claim 1, characterized in that, The memory is also configured to: After the memory usage time is greater than or equal to a preset duration, the preset refresh period corresponding to at least one preset temperature signal in the mapping table is updated; wherein, the updated preset refresh period is less than the preset refresh period corresponding to the at least one preset temperature signal before the update.

9. A method for operating a memory, characterized in that, The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a first memory cell and a second memory cell, wherein the data retention time of the second memory cell is shorter than the data retention time of the first memory cell; the operation method includes: The temperature of the memory is sensed, and a temperature signal is generated based on the sensed temperature; The target refresh period is determined based on the temperature signal and the mapping table; wherein, the mapping table includes multiple preset temperature signals and multiple preset refresh periods, and the multiple preset temperature signals and multiple preset refresh periods correspond one-to-one; the mapping table includes multiple sub-mapping tables, and the sub-mapping tables are used to record the correspondence between the preset temperature signals and the preset refresh periods; The refresh period of the refresh signal is adjusted to the target refresh period; wherein the refresh signal is used to indicate that a refresh operation is performed on the memory cell array; The step of determining the target refresh cycle based on the temperature signal and the mapping table includes: Based on the temperature signal, a first target address is generated by decoding; wherein, the first target address is used to indicate the physical address of the first sub-mapping table in the plurality of sub-mapping tables; Based on the first target address, obtain the first sub-mapping table and determine the first target refresh period of the first storage unit; Based on the offset of the first target address, the second sub-mapping table of the plurality of sub-mapping tables is obtained, and the second target refresh period of the second storage unit is determined; wherein, the second sub-mapping table is different from the first sub-mapping table; the second target refresh period is less than the first target refresh period.

10. The operating method according to claim 9, characterized in that, The process of obtaining the second sub-mapping table from the plurality of sub-mapping tables based on the first target address with offset, and determining the second target refresh period of the second storage unit, includes: Based on the first target address, an offset is generated to generate a second target address, which is used to indicate the physical address of the second sub-mapping table; Based on the second target address, obtain the second sub-mapping table and determine the second target refresh cycle.

11. The operating method according to claim 9, characterized in that, At the first temperature, there is a first difference between the first target refresh cycle and the second target refresh cycle; At the second temperature, there is a second difference between the first target refresh cycle and the second target refresh cycle; wherein the second temperature is different from the first temperature, and the second difference is different from the first difference.

12. The operating method according to claim 9, characterized in that, The first storage unit and the second storage unit are located in the same storage unit row; adjusting the refresh period of the refresh signal to the target refresh period includes: The refresh cycle of the storage cell row is adjusted to the second target refresh cycle.

13. The operating method according to claim 9, characterized in that, The first storage unit and the second storage unit are located in different rows of storage units; adjusting the refresh period of the refresh signal to the target refresh period includes: Adjust the refresh period of the storage cell row corresponding to the first storage cell to the first target refresh period; The refresh period of the storage cell row corresponding to the second storage cell is adjusted to the second target refresh period.

14. The operating method according to claim 9, characterized in that, The peripheral circuitry includes an electric fuse circuit and a register circuit, wherein the electric fuse circuit is configured to store the mapping table; the operation method further includes: The mapping table in the electric fuse circuit is read, and the read mapping table is saved to the register circuit.

15. The operating method according to claim 9, characterized in that, The operation method further includes: After the memory usage time is greater than or equal to a preset duration, the preset refresh period corresponding to at least one preset temperature signal in the mapping table is updated; wherein, the updated preset refresh period is less than the preset refresh period corresponding to the at least one preset temperature signal before the update.

16. A memory system, characterized in that, include: One or more memories as described in any one of claims 1 to 8; A memory controller, coupled to the memory and configured to control the memory.

17. An electronic device, characterized in that, include: The memory system as described in claim 16.

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