Static memory

Abstract

The invention provides a static memory. The static memory comprises a plurality of memory elements arranged in an array; a word line; a first transmission line and a second transmission line connected to the plurality of memory cells located in the same column; the memory cell includes: a first transistor coupled to a first node, a first power line, and a second node, respectively; a second transistor coupled to the second node, the first power line, and the first node, respectively; a third transistor coupled to the first node, the second node, and a second power line, respectively; a fourth transistor coupled to the second node, the first node, and a second power line, respectively; the fifth transistor is respectively coupled with the word line, the second node and the first transmission line, and the fifth transistor is a PMOS (P-channel Metal Oxide Semiconductor); and the sixth transistor is respectively coupled with the word line, the first node and the second transmission line, and the sixth transistor is a PMOS (P-channel Metal Oxide Semiconductor). According to the SRAM disclosed by the invention, a read-write path is changed, and a pull-down tube can be prepared by adopting an oxide transistor.

Description

Technical Field

[0001] The present disclosure relates to the technical field of static random access memory, and in particular to a static random access memory. Background Art

[0002] With the continuous advancement of SRAM (static random access memory, or SRAM, or static memory) technology, its application in computer systems and related electronic devices has become increasingly widespread, gradually establishing its position as the main storage medium. SRAM plays a key role in the field of microelectronics and has become an indispensable component in integrated circuit design.

[0003] The architecture of traditional 6T SRAM consists of a pair of mutually coupled inverters, each of which is assisted by two N-type pass transistors. Under the premise of the same storage capacity, the area occupied by SRAM is about six times that of DRAM. Therefore, optimizing the area of ​​SRAM standard cells to reduce their area requirements in integrated circuits is an important challenge for the development of SRAM.

[0004] In addition, in the circuit design of a standard 6T SRAM cell, each transistor will generate inevitable leakage current. As the technology node evolves to the deep submicron scale, this leakage current phenomenon becomes more and more significant, which has a significant impact on the static power consumption of the SRAM cell. Therefore, in-depth research on the static leakage power consumption of SRAM cells is crucial to achieve its low power optimization.

[0005] In the related art, oxide transistors (such as IGZO TFT) have been applied to SRAM. Oxide transistors have the advantages of extremely low leakage, low temperature and large area preparation, and low cost, making them the preferred choice for SRAM. However, in traditional 6T SRAM, in order to resolve the conflict between read and write stability, it is usually necessary to meet the following conditions: pull-down tube drive current> transmission tube drive current> pull-up tube drive current. Since IGZO TFT can only prepare N-type devices, it can only play the role of pull-down tube and transmission tube in traditional 6T SRAM circuits. In addition, at the same size, the driving current of IGZO TFT is much smaller than that of the surround gate transistor (GAAFET). Therefore, in the traditional hybrid 6T SRAM, the size of the IGZO TFT device needs to be very large to maintain read and write stability, which is not conducive to further improving the SRAM integration density. Summary of the invention

[0006] The embodiments of the present disclosure provide a static memory to solve or alleviate one or more technical problems in the prior art.

[0007] The present disclosure provides a static memory, including:

[0008] A plurality of storage elements arranged in an array;

[0009] A word line connected to a plurality of memory cells in the same row;

[0010] A first transmission line and a second transmission line are connected to a plurality of storage cells located in the same column, and the first transmission line and the second transmission line are respectively used for transmitting data;

[0011] The storage element includes:

[0012] A first transistor, wherein a gate of the first transistor is coupled to the first node, and a first electrode and a second electrode of the first transistor are coupled to the first power line and the second node respectively;

[0013] A second transistor, wherein a gate of the second transistor is coupled to the second node, and a first electrode and a second electrode of the second transistor are coupled to the first power line and the first node respectively;

[0014] a third transistor, wherein a gate of the third transistor is coupled to the first node, and a first electrode and a second electrode of the third transistor are coupled to the second node and the second power line respectively;

[0015] a fourth transistor, wherein a gate of the fourth transistor is coupled to the second node, and a first electrode and a second electrode of the fourth transistor are coupled to the first node and the second power line respectively;

[0016] a fifth transistor, wherein a gate of the fifth transistor is coupled to the word line, a first electrode and a second electrode of the fifth transistor are coupled to the second node and the first transmission line respectively, and the fifth transistor is a PMOS;

[0017] A sixth transistor, a gate of the sixth transistor is coupled to the word line, a first electrode and a second electrode of the sixth transistor are respectively coupled to the first node and the second transmission line, and the sixth transistor is a PMOS.

[0018] In some embodiments,

[0019] The third transistor is an oxide transistor; and the fourth transistor is an oxide transistor.

[0020] In some embodiments,

[0021] The first transistor is a PMOS; the second transistor is a PMOS; the third transistor is an NMOS; and the fourth transistor is an NMOS.

[0022] In some embodiments,

[0023] The first transistor is a surround gate transistor; the second transistor is a surround gate transistor; the fifth transistor is a surround gate transistor; and the sixth transistor is a surround gate transistor.

[0024] In some embodiments, the first transmission line and the second transmission line are configured to be pre-charged with data 0 in a read operation.

[0025] In some embodiments, including:

[0026] substrate;

[0027] A first structure layer, located on one side of the substrate, the first structure layer comprising a first transistor, a second transistor, a fifth transistor and a sixth transistor;

[0028] The second structure layer is located on a side of the first structure layer away from the substrate, and the second structure layer includes a third transistor and a fourth transistor.

[0029] In some embodiments,

[0030] The first transistor, the second transistor, the fifth transistor and the sixth transistor are all surround gate transistors; the third transistor and the fourth transistor are all oxide transistors;

[0031] For the storage element, the orthographic projection of the second region in the second structure layer on the substrate at least partially overlaps with the orthographic projection of the first region in the first structure layer on the substrate, the first region includes at least the region occupied by the first transistor and the second transistor, and the second region includes at least the region occupied by the third transistor and the fourth transistor.

[0032] In some embodiments, for a memory cell, the first power line and the second power line are located on the same side of an orthographic projection of the first region and the second region on the substrate.

[0033] In some embodiments, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are all surround gate transistors; the third transistor and the fourth transistor are all oxide transistors;

[0034] For the memory cell, an orthographic projection of the oxide transistor in the second structure layer on the substrate at least partially overlaps with an orthographic projection of the surround gate transistor in the first structure layer on the substrate.

[0035] In some embodiments, for the memory cell, an orthographic projection of the third transistor on the substrate at least partially overlaps with an orthographic projection of the first transistor on the substrate, and an orthographic projection of the fourth transistor on the substrate at least partially overlaps with an orthographic projection of the second transistor on the substrate.

[0036] The technical solution of the embodiment of the present disclosure changes the read and write paths compared to the traditional 6T SRAM by setting the transmission tube (i.e., the fifth transistor and the sixth transistor) as PMOS, so that the driving current of the pull-down tube is minimized, which is conducive to using oxide transistors to prepare the pull-down tube (i.e., the third transistor T3 and the fourth transistor T4) and will not increase the size of the pull-down tube.

[0037] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0039] Figure 1 It is a partial circuit diagram of a static memory in one embodiment of the present disclosure;

[0040] Figure 2 It is a schematic diagram of the local structure in the traditional 6T SRAM;

[0041] Figure 3A It is a schematic diagram of the architecture of SRAM according to an embodiment of the present disclosure;

[0042] Figure 3B It is a structural diagram of an SRAM according to an embodiment of the present disclosure;

[0043] Figure 4 It is a schematic diagram of the structure of a surround gate transistor in one embodiment of the present disclosure;

[0044] Figure 5A-Figure 23A as well as Figure 5B-Figure 23B They are cross-sectional views along the XX axis and YY axis directions of the center of the full-ring gate transistor during the manufacturing process;

[0045] Fig.24 It is a schematic diagram after forming the first connecting part, the second connecting part and the third connecting part;

[0046] Figure 25A-25G It is a cross-sectional schematic diagram of forming the second structural layer.

[0047] Description of reference numerals:

[0048] 401 - semiconductor substrate; 402 - first semiconductor layer; 403 - second semiconductor layer; 404 - first sidewall; 405 - sacrificial layer; 406 - fin; 406 - 1 - lower fin; 406 - 2 - first semiconductor fin; 406 - 3 - second semiconductor fin; 407 - silicon germanium layer;

[0049] 408-nanosheet; 409-shallow trench isolation; 410-dummy gate stack; 411-gate oxide layer; 412-silicon layer; 413-mask layer; 414-gate stack sidewall; 415-embedded cavity structure; 416-inner sidewall insulating dielectric layer; 417-inner sidewall; 420-drain-source layer; 421-1-source region; 421-2-drain region; 422-first interlayer dielectric layer;

[0050] 423 - first opening; 424 - second opening; 425 - diffusion barrier layer; 426 - work function layer; 427 - conductive filling layer; 428 - gate insulating dielectric layer; 429 - metal gate material layer; 430 - second interlayer dielectric layer; 431 - third opening; 432 - fourth opening; 433 - metal gate stack;

[0051] 52 - isolation dielectric layer; 531 - gate electrode; 54 - gate dielectric layer; 551 - oxide semiconductor layer; 561 - source electrode; 562 - drain electrode; 57 - passivation layer. DETAILED DESCRIPTION

[0052] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0053] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is called the first electrode, the drain (drain electrode) is called the second electrode, or the drain can be called the first electrode and the source is called the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain. The switching transistor used in the embodiment of the present invention can be a P-type transistor (PMOS) or an N-type transistor (PMOS). The P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in each embodiment of the present invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential state quantities of the signal, and do not represent that the first potential or the second potential in the full text has a specific value. In the embodiment of the present invention, the first potential is taken as an effective potential for description.

[0054] The coupling may include: direct physical contact between the two ends or indirect connection between the two ends (eg, connection between the two ends via a signal line). The embodiment of the present invention does not limit the coupling method between the two ends.

[0055] Figure 1 1 is a partial circuit diagram of a static memory in an embodiment of the present disclosure, wherein the static memory includes a plurality of memory cells arranged in an array, a word line WL, a first transmission line BL, and a second transmission line BLB. The plurality of memory cells may be arranged in a matrix array. The word line WL is connected to a plurality of memory cells in the same row. The word line WL may provide a word selection signal to the memory cell.

[0056] The first transmission line BL and the second transmission line BLB are connected to a plurality of memory cells located in the same column, and the first transmission line BL and the second transmission line BLB are respectively used for transmitting data.

[0057] like Figure 1 As shown, the memory cell may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6.

[0058] A gate of the first transistor T1 is coupled to the first node QB, and a first electrode and a second electrode of the first transistor T1 are coupled to the first power line VDD and the second node Q, respectively.

[0059] A gate of the second transistor T2 is coupled to the second node Q, and a first electrode and a second electrode of the second transistor T2 are coupled to the first power line VDD and the first node QB, respectively.

[0060] A gate of the third transistor T3 is coupled to the first node QB, and a first electrode and a second electrode of the third transistor T3 are coupled to the second node Q and the second power line VSS, respectively.

[0061] A gate of the fourth transistor T4 is coupled to the second node Q, and a first electrode and a second electrode of the fourth transistor T4 are coupled to the first node QB and the second power line VSS, respectively.

[0062] A gate of the fifth transistor T5 is coupled to the word line WL, a first electrode and a second electrode of the fifth transistor T5 are coupled to the second node Q and the first transmission line BL respectively, and the fifth transistor T5 is a PMOS.

[0063] A gate of the sixth transistor T6 is coupled to the word line WL, a first electrode and a second electrode of the sixth transistor T6 are coupled to the first node QB and the second transmission line BLB respectively, and the sixth transistor T6 is a PMOS.

[0064] In the conventional 6T SRAM, the fifth transistor T5 and the sixth transistor T6 used as transmission transistors are both NMOS, which is not conducive to reducing the occupied area of ​​the memory cell.

[0065] In the technical solution disclosed in the present invention, the fifth transistor T5 and the sixth transistor T6 used as transmission pipes in the storage element of the static memory are both PMOS, which is beneficial to reducing the occupied area of ​​the storage element and improving the integration density of the SRAM.

[0066] It should be noted that, in the 6T SRAM, the first transistor T1 and the second transistor T2 are called pull-up transistors; the third transistor T3 and the fourth transistor T4 are called pull-down transistors; and the fifth transistor T5 and the sixth transistor T6 are called transmission transistors.

[0067] In one embodiment, Figure 1 As shown, the first transistor T1 is a PMOS; the second transistor T2 is a PMOS; the third transistor T3 is an NMOS; and the fourth transistor T4 is an NMOS.

[0068] Figure 2 Figure 1 is a schematic diagram of the local structure in a traditional 6T SRAM. In a traditional 6T SRAM, in order to resolve the conflict between read and write stability, it is usually necessary to satisfy the following conditions: pull-down tube (T3, T4) drive current > transmission tube (T5, T6) drive current > pull-up tube (T1, T2) drive current. Since oxide transistors can only be prepared as N-type devices, they can only act as pull-down tubes and transmission tubes in traditional 6T SRAM circuits. In addition, at the same size, the driving current of IGZO TFT is much smaller than that of the surrounding gate transistor (GAAFET). Therefore, if IGZO TFT devices are used as pull-down frames or transmission tubes in traditional 6T SRAM, the required size needs to be very large to maintain read and write stability, which is not conducive to further improving the SRAM integration density.

[0069] The working principle of the 6T SRAM in the embodiment of the present disclosure is as follows:

[0070] In the write operation: in the initial state, the second node Q is data 0 and the first node QB is data 1. Assuming that data 1 is to be written, the first transmission line BL is data 1 and the second transmission line BLB is data 0. In order to achieve data writing, the transmission tube (for example, T5 and T3) need to be opposed. Therefore, the write path includes the transmission tube and the pull-down box. In order to achieve data writing, it is necessary to meet: the transmission tube drive current> the pull-down tube drive current.

[0071] In the read operation: in the initial state, the second node Q is data 1, and the first node QB is data 0. The first transmission line BL and the second transmission line BLB are pre-charged with data 0. In order to read the data, the pull-up tube and the transmission tube (for example, T1 and T5) need to be opposed. Therefore, the read path includes the pull-up tube and the transmission tube. In order to read the data, it is necessary to meet the following conditions: the pull-up tube driving current> the transmission tube driving current.

[0072] Therefore, for the stability of reading and writing, the 6T SRAM disclosed in the present invention needs to satisfy the following conditions: pull-up tube driving current>transmission tube driving current>pull-down tube driving current. In other words, the pull-down tube driving current is the smallest.

[0073] The 6T SRAM of the disclosed embodiment changes the read-write path compared to the conventional 6T SRAM by setting the transmission tube (i.e., the fifth transistor T5 and the sixth transistor T6) as PMOS, so that the driving current of the pull-down tube (NMOS) is minimized, which is conducive to using oxide transistors to prepare the pull-down tube (i.e., the third transistor T3 and the fourth transistor T4) without increasing the size of the pull-down tube.

[0074] In one embodiment, the first transistor T1 is a surround gate transistor; the second transistor T2 is a surround gate transistor; the fifth transistor T5 is a surround gate transistor; and the sixth transistor T6 is a surround gate transistor.

[0075] Exemplarily, the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 are all gate-all-around transistors (GAA), for example, the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 are all gate-all-around field effect transistors (GAA FET).

[0076] In this embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 are all configured to use gate-all-around transistors (GAA). GAA transistors can provide a larger driving current, and compared with fin field effect transistors (FinFETs), the parasitic resistance and parasitic capacitance of GAA transistors are significantly optimized, which can further improve the performance of SRAM.

[0077] In one embodiment, the third transistor T3 is an oxide transistor; the fourth transistor T4 is an oxide transistor. For example, the third transistor T3 and the fourth transistor T4 are both oxide transistors. That is, the channel material of the third transistor T3 is an oxide semiconductor, and the channel material of the third transistor T4 is an oxide semiconductor.

[0078] Exemplarily, the oxide may include amorphous and polycrystalline semiconductor materials such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO), zinc oxide (ZnO), and titanium oxide (TiO).

[0079] Through the above analysis, in the SRAM of the embodiment of the present disclosure, the driving current of the pull-down tube is the smallest. Therefore, when the third transistor T3 and the fourth transistor T4 of the pull-down tube are oxide transistors, the sizes of the third transistor T3 and the fourth transistor T4 will not be increased. In addition, oxide transistors have the characteristics of extremely low leakage, low temperature and large area preparation, and low cost, which can improve the integration density of SRAM, reduce static power consumption, and reduce costs.

[0080] In one embodiment, in order to implement a data read operation, the first transmission line BL and the second transmission line BLB are configured to be pre-charged with data 0 in a read operation, so as to implement the reading of the shift register data.

[0081] Figure 3A Schematic diagram of the architecture of SRAM according to an embodiment of the present disclosure. Figure 3B Schematic diagram of the structure of SRAM according to an embodiment of the present disclosure. Figure 3B A wrap-around gate transistor in the first structure layer and an oxide transistor in the second structure layer are shown. Figure 3A and Figure 3B As shown, the SRAM may include a substrate 401, a first structure layer 400, and a second structure layer 500. The first structure layer 400 is located on one side of the substrate 401, and the first structure layer 400 includes a first transistor T1, a second transistor T2, a fifth transistor T5, and a sixth transistor T6. The second structure layer 500 is located on the side of the first structure layer 400 away from the substrate 401, and the second structure layer 500 includes a third transistor T3 and a fourth transistor T4.

[0082] The SRAM in this embodiment can reduce the occupied area of ​​the memory cell and improve the integration density by setting the SRAM as a stacked structure of two structural layers.

[0083] Exemplarily, the first transistor T1 , the second transistor T2 , the fifth transistor T5 and the sixth transistor T6 are all surround-gate transistors (also called full-ring-gate transistors); the third transistor T3 and the fourth transistor T4 are all oxide transistors.

[0084] For the storage element, the orthographic projection of the second region in the second structure layer 500 on the substrate 401 at least partially overlaps with the orthographic projection of the first region in the first structure layer 400 on the substrate 401. The first region at least includes the region occupied by the first transistor T1 and the second transistor T2, and the second region at least includes the region occupied by the third transistor T3 and the fourth transistor T4. This arrangement can further reduce the occupied area of ​​the storage element.

[0085] For the memory cell, the first power line VDD and the second power line VSS are located on the same side of the positive projection of the first region and the second region on the substrate. Figure 3A In the embodiment, the first power line VDD is located at the first side of the first region, and the second power line VSS is located at the first side of the second region. In this arrangement, the signal lines are concentrated on the same side of the storage cell, which can further reduce the occupied area of ​​the storage cell.

[0086] In one embodiment, for a memory cell, an orthographic projection of an oxide transistor in the second structure layer 500 on the substrate 401 at least partially overlaps with an orthographic projection of a gate-all-around transistor in the first structure layer 400 on the substrate 401 .

[0087] For the storage element, the orthographic projection of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the first transistor T1 on the substrate, and the orthographic projection of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the second transistor T2 on the substrate. Figure 1 and Figure 3A It can be seen that the gate of the third transistor T3 is coupled to the gate of the first transistor T1, and by at least partially overlapping the orthographic projection of the third transistor T3 on the substrate with the orthographic projection of the first transistor T1 on the substrate, it is beneficial to achieve the coupling of the gate of the third transistor T3 with the gate of the first transistor T1; the gate of the fourth transistor T4 is coupled to the gate of the second transistor T2, and by at least partially overlapping the orthographic projection of the fourth transistor T4 on the substrate with the orthographic projection of the second transistor T2 on the substrate, it is beneficial to achieve the coupling of the gate of the fourth transistor T4 with the gate of the second transistor T2, thereby reducing the coupling resistance, further reducing the occupied area of ​​the storage element, and improving the integration density of the SRAM.

[0088] Figure 4 Schematic diagram of the structure of a surround gate transistor in an embodiment of the present disclosure. The following uses a surround gate transistor in the first structure layer and an oxide transistor in the second structure layer as examples to illustrate the preparation process of an SRAM in an embodiment of the present disclosure. In the following, the substrate adopts a semiconductor substrate. Among them, Figure 5A-Figure 23A as well as Figure 5B-Figure 23B They are cross-sectional views along the XX axis and YY axis directions of the center of the full-ring gate transistor during the manufacturing process, respectively, and the XX axis and the YY axis are perpendicular to each other.

[0089] In step S201, refer to Fig. 7A and Figure 7B , a fin 406 is formed above the semiconductor substrate 401, wherein the fin 406 includes a lower fin 406-1 and an upper stacked structure located above the lower fin 406-1 to form a channel region, and the upper stacked structure includes a plurality of alternating stacks of a first semiconductor layer (i.e., the first semiconductor layer after etching) and a second semiconductor layer (i.e., the second semiconductor layer after etching).

[0090] Forming a fin 406 on the semiconductor substrate 401 may include: Figure 5A and Figure 5B , a first semiconductor layer 402 and a second semiconductor layer 403 are periodically epitaxially grown on a semiconductor substrate 401 using a superlattice epitaxial growth process to form a plurality of epitaxial stacks; Fig. 6A and Figure 6B , forming a sacrificial layer on the plurality of epitaxial stacks by a self-aligned spacer transfer process and etching the sacrificial layer to form a first spacer 404; and referring to Fig. 7A and Figure 7B , using the first sidewall 404 as a hard mask, the multiple epitaxial stacks and a portion of the semiconductor substrate 401 are etched to form a recessed portion and a fin 406 protruding above the recessed portion, wherein the portion of the semiconductor substrate is etched into a lower fin 406-1, and the first semiconductor layer 402 and the second semiconductor layer 403 in the multiple epitaxial stacks are respectively etched into a first semiconductor fin 406-2 and a second semiconductor fin 406-3, so that the lower fin 406-1 is aligned with the upper stack structure in a vertical direction, the material of the first semiconductor layer 402 includes silicon germanium (SiGe), and the material of the second semiconductor layer 403 includes silicon (Si).

[0091] For example, the semiconductor substrate 401 may be a bulk silicon substrate, and the semiconductor substrate 401 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.

[0092] For example, impurities may be injected into the bulk silicon substrate, and a highly doped well region may be formed after annealing to achieve the desired well depth. The doping type of the semiconductor substrate 401 is different for different device types, wherein for a P-type semiconductor device, the highly doped well region is an N-well, and the injected impurities are n-type impurity ions, such as phosphorus (P) ions, wherein for an N-type semiconductor device, the highly doped well region is a p-well, and the injected impurities are p-type impurity ions, such as boron (B) ions.

[0093] In an embodiment of the present application, the first semiconductor layer 402 and the second semiconductor layer 403 can be formed by an epitaxial growth process. Specifically, for different device types, the materials of the first semiconductor layer 402 and the second semiconductor layer 403 can be the same, for example, the material of the first semiconductor layer 402 can be silicon germanium, and the material of the second semiconductor layer 403 can be silicon or germanium. For different device types, the materials of the first semiconductor layer 402 and the second semiconductor layer 403 can be different, for example, for a P-type semiconductor device, the material of the first semiconductor layer 402 can be silicon, and the material of the second semiconductor layer 403 can be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 402 can be silicon germanium, and the material of the second semiconductor layer 403 can be silicon. In the present disclosure, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 located in the first structural layer are all PMOS, and are all surrounding gate transistors. Therefore, these four transistors can be formed at the same time, which improves the preparation efficiency of SRAM.

[0094] In practical applications, silicon oxide may be formed on the semiconductor substrate 401 . The stacked structure may be formed after the silicon oxide on the semiconductor substrate 401 is removed and the semiconductor substrate 401 is cleaned.

[0095] In an embodiment of the present application, a self-aligned sidewall transfer process is used to form a first sidewall 404. The material of the first sidewall 404 is silicon nitride. The specific formation process is: a sacrificial layer is covered on the stacked structure. The material of the sacrificial layer can be polysilicon or amorphous silicon. Part of the sacrificial layer is patterned and etched away by photolithography, and silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 405, so that only the silicon nitride material on the stacked structure is retained to form the first sidewall 404. The first sidewall 404 acts as a hard mask in the subsequent photolithography for forming the fin.

[0096] In the embodiment of the present application, multiple epitaxial stacks can be etched by an etching process to form multiple periodically distributed fins (also referred to as fins), see Fig. 7A and Figure 7B The first sidewall 404 is used as a hard mask for etching to form a fin 406 with a stacked structure. The upper part of the fin is a channel region formed by the stacked structure, and the lower part of the fin (referred to as the lower fin 406-1) is a semiconductor substrate 401, forming a Figure 7B The fin shown in FIG. The fin includes not only a stacked structure but also a single crystal silicon structure that penetrates into the semiconductor substrate 401. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin will be used to form a nanosheet of a semiconductor device. Although Figure 7BWhile one fin is shown, it should be understood that any suitable number and configuration of fins may be used in practical applications.

[0097] In step S202, refer to Figures 8A to 9B A shallow trench isolation (STI) 409 is formed on both sides of the lower fin 406 - 1 , and a dummy gate stack 410 is formed above the shallow trench isolation 409 to cross the upper stack structure and form a gate stack spacer 414 sandwiching the dummy gate stack 410 .

[0098] Forming a dummy gate stack 410 across the upper stack structure and a gate stack spacer 414 sandwiching the dummy gate stack 410 above the shallow trench isolation 409 may include: Fig. 8A and Figure 8B , a shallow trench isolation member 409 is formed at the recessed portion (i.e., the recessed portion formed by etching the plurality of epitaxial stacks and a portion of the semiconductor substrate), wherein the top surface of the shallow trench isolation member 409 is flush with the top surface of the lower fin 406-1; Fig. 9A and Fig. 9B , a gate oxide layer 411, a silicon layer 412 and a mask layer 413 are conformally deposited above the shallow trench isolation member 409 and the upper stacked structure, wherein the silicon layer 412 is an amorphous silicon layer or a polycrystalline silicon layer; the mask layer 413 is etched to form a gate mask 413, wherein the gate mask 413 is located above the central region and the sidewall of the upper stacked structure; the silicon layer 412 and the gate oxide layer 411 are etched respectively by using the gate mask 413 to form a dummy gate stack 410 spanning the upper stacked structure; refer to Fig. 10A and Fig. 10B , forming a spacer isolation dielectric layer on the opposite sidewalls of the dummy gate stack 410 ; and etching the spacer isolation dielectric layer to form a gate stack spacer 414 .

[0099] In an embodiment of the present application, a shallow trench isolation 409 can be formed between different fins. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as a CMP process, and then a selective etching back process of the dielectric insulating material can be performed to expose the three-dimensional fins, thereby forming a shallow trench isolation 409 adjacent to the fin. The surface of the side of the shallow trench isolation 409 away from the semiconductor substrate 401 can be flush with the surface of the side of the stacked structure in the fin close to the semiconductor substrate 401, or it can be higher or lower than the surface. The shallow trench isolation 409 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 409 is to separate the channels on adjacent fins.

[0100] In an embodiment of the present application, a dummy gate stack (also called a replacement gate stack, dummy gate) 410 is formed on the exposed fin and in a direction perpendicular to the fin line, that is, in the YY direction. The dummy gate stack 410 is a multi-layer structure, including a gate oxide layer 411, a silicon layer 412 and a mask layer 413. The dummy gate stack 410 can be formed by processes such as thermal oxidation, chemical vapor deposition, and sputtering. The dummy gate stack 410 spans the stacked structure on the upper part of the fin, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 412 can be polycrystalline silicon or amorphous silicon. The mask layer 413 is a hard mask layer, and the material of the hard mask layer 413 can be oxide, carbide, organic matter, etc.

[0101] In the embodiment of the present application, gate stack spacers 414 may be provided on both sides of the dummy gate stack along the fin line direction, i.e., the XX direction, and the gate stack spacers 414 on both sides have the same thickness. The gate stack spacers 414 may be made of a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0102] In step S203, refer to Fig. 12A , 12A and Fig.14A , the exposed first end and the second end in the first semiconductor layer are replaced with an insulating dielectric (eg, silicon nitride) material to form an inner sidewall 417 , wherein the width of the inner sidewall 417 is the same as the width of the gate stack sidewall 414 .

[0103] Replacing the exposed first end and the second end of the first semiconductor layer with an insulating dielectric material to form an inner sidewall 417 may include: Fig. 10A , Fig. 10B , Fig.11A and Fig. 11B , the upper stack structure is etched using the dummy gate stack 410 and the gate stack spacer 414 as masks to form the first semiconductor layer into a SiGe layer 407 exposing the first end and the second end (i.e., the first semiconductor fin 406-2 described above is further etched) and the second semiconductor layer is formed into a nanosheet 408 (i.e., the second semiconductor fin 406-3 described above is further etched), i.e., a nanosheet 408 exposing the end of the nanosheet is formed; refer to Fig. 12A and Fig. 12B , the first end and the second end of the SiGe layer 407 are selectively etched back to form a plurality of embedded cavity structures 415 at the first end and the second end in situ, so that the opposite side walls of the upper stacked structure after the back etching have a plurality of teeth (e.g., rectangular teeth or square teeth) of the nanosheet, wherein the depth of the plurality of embedded cavity structures 415 is the same as the thickness of the gate stack spacer 414; Fig.13A and Fig. 13B, an inner sidewall insulating dielectric layer (also referred to as a dielectric layer) 416 is conformally deposited on the top surface and a portion of the sidewalls of the dummy gate stack 410, on the gate stack sidewall 414, in the embedded cavity structure, and on a plurality of teeth; and the inner sidewall insulating dielectric layer 416 is etched to remove the inner sidewall insulating dielectric layer on the top surface and a portion of the sidewalls of the dummy gate stack 410, and to remove the inner sidewall insulating dielectric layer on the gate stack sidewall and a plurality of teeth, while retaining the first end and the second end of the inner sidewall insulating dielectric layer in the plurality of embedded cavity structures to form an inner sidewall 417.

[0104] In the embodiment of the present application, after etching the SiGe layer 407, a dielectric material is deposited on the stacked structure located in the channel region, i.e., the periphery of the fin, and the dielectric material is etched to form an inner sidewall 417, and the inner sidewall 417 is flush with the nanosheet 408 in a direction perpendicular to the plane where the semiconductor substrate 401 is located. In other words, the embedded cavity structure 415 formed by etching back the SiGe layer 407 is filled with the inner sidewall 417, and the material of the inner sidewall 417 can be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, low-k material and air, wherein the material of the inner sidewall 417 is air, which means that an air cavity can be formed at the location of the inner sidewall 417, and the function of the inner sidewall 417 is achieved by utilizing the air cavity.

[0105] In step 205, refer to Fig. 20A and Fig. 20B , a source region 421 - 1 and a drain region 421 - 2 are formed on the outer surface of the inner sidewall 417 , and then the dummy gate stack and the first semiconductor layer in the upper stack structure are replaced with a metal gate material layer.

[0106] refer to Fig.15A and Fig.16A , forming a drain region and a source region on the outer surface of the outer sidewall 419, which may include: Fig.15A and Fig. 15B , epitaxially growing a drain source layer 420 on the outer surface of the outer sidewall 419 and above the shallow trench isolation member 409 without changing the epitaxial growth crystal direction of the drain source layer, wherein the material of the drain source layer includes SiGe, Si or SiC; and reference Fig.16A and Fig. 16B The drain-source layer is doped with a drain-source dopant to form a source region 421 - 1 and a drain region 421 - 2 .

[0107] Replacing the SiGe layer in the dummy gate stack and the plurality of epitaxial stacks with a metal gate material layer may include: referring to Fig.17A and Fig. 17B , depositing a first interlayer dielectric layer 422 above the dummy gate stack, the source region, and the drain region; Fig.17A and Fig. 17B, the first interlayer dielectric layer is planarized by chemical mechanical polishing process; reference Fig.18A and Fig.18B , removing the dummy gate stack by a dummy gate removal process to form a first opening 423, and then removing the SiGe layer by a nanosheet release process while retaining the first end and the second end of the insulating dielectric material to form a plurality of second openings 424 between adjacent nanosheets in the released nanosheets; and referring to Fig.19A and Fig.19B A metal gate stack 433 and a metal gate material layer 429 are respectively formed in the first opening 423 and the plurality of second openings 424, wherein the metal gate stack 433 and the metal gate material layer 429 include a gate insulating dielectric layer 428, a diffusion barrier layer 425 located above the gate insulating dielectric layer 428, a work function layer 426 located above the diffusion barrier layer 425, and a conductive filling layer 427 located above the work function layer 426.

[0108] After replacing the dummy gate stack with the metal gate material layer, a contact hole of the full-all-around gate transistor is formed. Specifically, forming the contact hole of the full-all-around gate transistor includes referring to Fig.21A and Fig.21B , chemically mechanically polishing the metal gate stack to expose the top surface of the metal gate stack; referring to Fig.22A and Fig. 22B , a second interlayer dielectric layer 430 is formed above the metal gate stack; the second interlayer dielectric layer 430 is etched to form a third opening 431, a fourth opening 432 and a fifth opening (not shown) in the second interlayer dielectric layer 430 to expose the source region, the drain region and the top surface of the metal gate stack; and tungsten contact holes are formed in the third opening 431, the fourth opening 432 and the fifth opening as source contact holes, drain contact holes and gate contact holes.

[0109] In the examples of this application, reference is made to Fig.17A and Fig. 17B , a first interlayer dielectric layer 422 may be deposited on the surface of the dummy gate stack 410, the source region 421-1 and the drain region 421-2 to prevent the interconnection short circuit between the dummy gate stack 410 and the source or drain 421 in the subsequent steps, and the first interlayer dielectric layer 422 may be subjected to a chemical mechanical polishing process to make it flat. Then, as Fig.18A and Fig.18B As shown, the dummy gate stack 410 formed of the polysilicon or amorphous silicon is etched or corroded by a selective etching or corrosion process, that is, the dummy gate stack 410 is removed.

[0110] In the embodiment of the present application, the first semiconductor layer silicon germanium layer 407 in the channel region can be removed, that is, a nanosheet channel release process is performed, so as to form a plurality of gaps to be filled between the nanosheets, that is, a plurality of second openings 424, as shown in FIG. Fig.19Aand Fig.19B shown.

[0111] Specifically, the silicon germanium layer 407 in the stacked structure in the channel region can be selectively etched to release the nanosheet channel. In other words, the stacked structure exposed by the fin is processed to remove each layer of the silicon germanium layer 407, which is a sacrificial layer, and release the nanosheet 408 formed by the second semiconductor layer.

[0112] In the embodiment of the present application, after the nanosheet channel is released, there are multiple gaps to be filled between the multiple nanosheets 408, and a metal gate material layer (referred to as a gate) 429 can be filled in the multiple gaps to be filled. The metal gate material layer 429 surrounds the nanosheet 408 to form a ring gate structure. The stack composed of multiple nanosheets 408 forms a channel structure, that is, a nanosheet channel of a semiconductor device is formed. Fig.21A and Fig.21B shown.

[0113] In the embodiment of the present application, the metal gate material layer 429 may further include a multi-layer structure (not shown) such as a gate insulating dielectric layer, a diffusion barrier layer, a work function layer, and a conductive filling layer.

[0114] In actual applications, in addition to forming a metal gate material layer 429 in the gap to be filled, the gate (metal gate stack) 433 covers the first interlayer dielectric layer (also called isolation layer) 422 and the space after the dummy gate stack 410 is removed. The metal gate stack 433 covering the first interlayer dielectric layer 422 can be chemically mechanically polished and planarized.

[0115] In the embodiment of the present application, after forming the metal gate material layer 429, a dielectric deposition may be performed on the top of the semiconductor device away from the semiconductor substrate 401 to form a second interlayer dielectric layer (also referred to as a top dielectric layer) 430, as shown in FIG. Fig.22A and Fig. 22B shown.

[0116] In the embodiment of the present application, contact holes are etched in the second interlayer dielectric layer 430 to the top surface of the source region, the drain region or the gate, and metal materials are deposited in the contact holes to form source contact holes, drain contact holes and gate contact holes. Fig.23A and Fig. 23B shown.

[0117] refer to Fig.24A metal layer is deposited on the upper side of the second interlayer dielectric layer 430, and the metal layer is patterned to form a first connection portion 451, a second connection portion 452, and a third connection portion 453. The first connection portion 451, the second connection portion 452, and the third connection portion 453 are respectively connected to the source region, the drain region, or the gate of the full-all-around gate transistor. The materials of the first connection portion 451, the second connection portion 452, and the third connection portion 453 can be conductive metals.

[0118] refer to Fig.25A An isolation dielectric layer 52 is deposited on the upper side of the second interlayer dielectric layer 430 formed with the first connection portion 451, the second connection portion 452 and the third connection portion 453. The isolation dielectric layer 52 may be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The isolation dielectric layer 52 is patterned to form a via hole exposing the third connection portion.

[0119] refer to Fig.25B A gate metal layer is deposited on the upper side of the isolation dielectric layer 52 , and the gate metal layer is patterned to form a gate 531 . The gate 531 is connected to the third connection portion 453 (not shown) through a via hole in the isolation dielectric layer 52 .

[0120] refer to Fig.25C A gate dielectric layer 54 is formed on the upper side of the gate. The gate dielectric layer 54 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0121] refer to Fig.25D An oxide semiconductor film is deposited on the upper side of the gate dielectric layer 54 by a sputtering process, and the oxide semiconductor film is patterned by a wet etching process to form an oxide semiconductor layer 551 of the oxide transistor. The oxide semiconductor layer 551 can be conductorized by a conductorization process to form a first conductorization region, a second conductorization region and a channel, respectively, and the channel is located between the first conductorization region and the second conductorization region.

[0122] refer to Fig.25E A source-drain metal layer is deposited on the upper side of the oxide semiconductor layer 551, and the source-drain metal layer is patterned to form a source electrode 561 and a drain electrode 562. The source electrode 561 and the drain electrode 562 are connected to the first conductive region and the second conductive region, respectively.

[0123] refer to Fig.25F A passivation layer 57 is deposited on the upper side of the source 561 and the drain 562. The material of the passivation layer can be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0124] refer to Figure 25G, the passivation layer is etched to form vias exposing the source 561 and the drain 562; then a metal layer is deposited on the upper side of the passivation layer, and the metal layer is patterned to form a fourth connection portion 581 and a fifth connection portion 582, and the fourth connection portion 581 and the fifth connection portion 582 are used to realize the connection in the SRAM.

[0125] Figure 25A-25G Only one oxide transistor in the second structure layer is described. It can be understood that a plurality of oxide transistors in the second structure layer can be formed simultaneously.

[0126] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0127] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0128] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0129] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0130] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0131] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A static memory, characterized in that: include: A plurality of storage elements arranged in an array; A word line connected to a plurality of the memory cells located in the same row; A first transmission line and a second transmission line are connected to the plurality of storage cells located in the same column, and the first transmission line and the second transmission line are respectively used for transmitting data; Wherein, the storage element comprises: A first transistor, wherein a gate of the first transistor is coupled to a first node, and a first electrode and a second electrode of the first transistor are coupled to a first power line and a second node respectively; a second transistor, wherein a gate of the second transistor is coupled to the second node, and a first electrode and a second electrode of the second transistor are coupled to the first power line and the first node respectively; a third transistor, wherein a gate of the third transistor is coupled to the first node, and a first electrode and a second electrode of the third transistor are coupled to the second node and a second power line, respectively; a fourth transistor, wherein a gate of the fourth transistor is coupled to the second node, and a first electrode and a second electrode of the fourth transistor are coupled to the first node and the second power line respectively; a fifth transistor, wherein a gate of the fifth transistor is coupled to the word line, a first electrode and a second electrode of the fifth transistor are respectively coupled to the second node and the first transmission line, and the fifth transistor is a PMOS; A sixth transistor, wherein a gate of the sixth transistor is coupled to the word line, a first electrode and a second electrode of the sixth transistor are respectively coupled to the first node and the second transmission line, and the sixth transistor is a PMOS.

2. The static memory according to claim 1, characterized in that: The third transistor is an oxide transistor; and the fourth transistor is an oxide transistor.

3. The static memory according to claim 1, characterized in that: The first transistor is a PMOS transistor; the second transistor is a PMOS transistor; the third transistor is an NMOS transistor; and the fourth transistor is an NMOS transistor.

4. The static memory according to claim 1, characterized in that: The first transistor is a surround gate transistor; the second transistor is a surround gate transistor; the fifth transistor is a surround gate transistor; and the sixth transistor is a surround gate transistor.

5. The static memory according to claim 1, characterized in that: The first transmission line and the second transmission line are configured to be pre-charged with data 0 in a read operation.

6. The static memory according to any one of claims 1 to 5, characterized in that: include: substrate; a first structure layer, located at one side of the substrate, the first structure layer comprising the first transistor, the second transistor, the fifth transistor and the sixth transistor; The second structure layer is located on a side of the first structure layer away from the substrate, and the second structure layer includes the third transistor and the fourth transistor.

7. The static memory according to claim 6, characterized in that: The first transistor, the second transistor, the fifth transistor and the sixth transistor are all surround gate transistors; the third transistor and the fourth transistor are all oxide transistors; For the storage element, the orthographic projection of the second region in the second structure layer on the substrate at least partially overlaps with the orthographic projection of the first region in the first structure layer on the substrate, the first region includes at least the region occupied by the first transistor and the second transistor, and the second region includes at least the region occupied by the third transistor and the fourth transistor.

8. The static memory according to claim 7, characterized in that: For the memory cell, the first power line and the second power line are located on the same side of the orthographic projections of the first region and the second region on the substrate.

9. The static memory according to claim 6, characterized in that: The first transistor, the second transistor, the fifth transistor and the sixth transistor are all surround gate transistors; the third transistor and the fourth transistor are all oxide transistors; For the memory cell, an orthographic projection of the oxide transistor in the second structure layer on the substrate at least partially overlaps with an orthographic projection of the surrounding gate transistor in the first structure layer on the substrate.

10. The static memory according to claim 9, characterized in that: For the storage cell, an orthographic projection of the third transistor on the substrate at least partially overlaps with an orthographic projection of the first transistor on the substrate, and an orthographic projection of the fourth transistor on the substrate at least partially overlaps with an orthographic projection of the second transistor on the substrate.

Images