Multi-chip package for dies of different sizes

Abstract

Apparatuses, methods, and storage media associated with an integrated package for a stack of semiconductor dies of different sizes are disclosed. In an embodiment, an apparatus including dies of different sizes may include a first die having a first side and a second side opposite the first side, and a second smaller die having a first side and a second side opposite the first side. The second side of the first die may be smaller than the first side of the second die and may be coupled with the first side of the second die such that a portion of the first side of the second die is exposed. The device may include a lead coupled with the portion of the first side of the second die and extending from the portion through the housing to a redistribution layer coupled with one side of the housing to electrically couple the die. Other embodiments may be disclosed and / or claimed.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201780033272.3, application date May 26, 2017, and invention name “Multi-chip package for dies of different sizes”.

[0002] Related Applications

[0003] This application claims priority to U.S. Application No. 15 / 197,494, filed on June 29, 2016, entitled “MULTICHIP PACKAGING FOR DICE OF DIFFERENT SIZES.” Technical Field

[0004] The present disclosure relates to techniques for multi-chip packaging for dies of different sizes. Background Art

[0005] The purpose of the background information provided herein is to generally give the context of the present disclosure.Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.

[0006] Flip chip and / or TSV (Through Silicon Via) technology can be used for multi-chip package (MCP). However, in order to avoid design complexity and / or the cost associated with flip chip and / or TSV technology, or for other reasons, wire bonding may be preferred. In a typical wire bonding example, multi-chip package (MCP) can utilize a printed circuit board (PCB). The bonding finger on the PCB can be arranged around one or more chips on the PCB to provide contact points corresponding to external devices. The lead can be suspended downward toward the bonding finger from the surface raised relative to the surface of the PCB of the chip.

[0007] As the bonding density (number of bonded leads) increases, the amount of clearance required between hanging leads (to avoid shorts) may become impractical and / or the size of the bond fingers of the PCB may need to be large to enable the necessary leads to connect to the substrate, which may affect the xy dimensions of the package. Also, in a multi-level scenario (i.e., a stack of dies), the pads on the level farthest from the PCB may not be bonded before all pads on the levels close to the PCB are bonded. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments will be easily understood according to the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals indicate similar structural elements. The embodiments are shown in the figures of the accompanying drawings by way of example and not limitation.

[0009] Figure 1Dies of a multi-chip package for dies of different sizes are shown according to various embodiments.

[0010] Figure 2 It shows the various embodiments Figure 1 A cross-sectional view of an example of a multi-chip package, Figure 1 The multi-chip package includes a housing surrounding leads extending from a surface of a chip.

[0011] Figure 3 It shows the various embodiments Figure 2 An isometric view of an example of , showing the ends of the leads exposed by the housing.

[0012] Figure 4 It shows the various embodiments Figure 3 A cross-sectional view of an example of a device that includes a redistribution layer (RDL) coupled to ends of leads.

[0013] Figure 5 A process for forming an integrated circuit package for stacks of semiconductor dies of different sizes is shown.

[0014] Figure 6 An exemplary computing device is shown in which the apparatus and / or methods described herein may be employed in accordance with various embodiments. DETAILED DESCRIPTION

[0015] Disclosed herein are devices, methods, and storage media associated with integrated packaging for stacks of semiconductor dies of different sizes. In an embodiment, a device including dies of different sizes may include a first die having a first side and a second side opposite to the first side and a second smaller die having a first side and a second side opposite to the first side. The second side of the first die may be smaller than the first side of the second die and may be coupled thereto so that a portion of the first side of the second die is exposed. The device may include leads coupled to the portion of the first side of the second die and extending from the portion through a housing to a redistribution layer (RDL) coupled to one side of the housing to electrically couple the die. In some embodiments, the device may include leads coupled to the first side of the first die and extending from it through the housing to the RDL. Other embodiments may be disclosed and / or claimed.

[0016] In the following detailed description, reference will be made to the accompanying drawings forming a part thereof, in which like reference numerals indicate like parts throughout the drawings, and in which embodiments that can be practiced are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the embodiments is defined solely by the appended claims and their equivalents.

[0017] Various aspects of the present disclosure are disclosed in the accompanying description. Alternative embodiments of the present disclosure and their equivalents may be designed without departing from the spirit or scope of the present disclosure. It should be noted that similar elements disclosed below are indicated by similar reference numerals in the accompanying drawings.

[0018] Various operations may be described as multiple discrete actions or operations in sequence in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must rely on the order. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0019] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0020] The specification may use the phrase "in an embodiment," which may refer to one or more of the same or different embodiments. In addition, the terms "including," "having," etc. used with respect to the embodiments of the present disclosure are synonymous.

[0021] As used herein, the term "circuitry" may refer to or include or be part of an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, combinational logic circuits, and / or other appropriate components that provide the described functionality.

[0022] Figure 1 Dies 110 and 120 of the multi-chip package 100 for dies of different sizes are shown according to various embodiments. A side of the first die 110 may be coupled to a larger side of the second die 120 such that a portion 126 of a side of the second die 120 may be exposed.

[0023] The lead 125 may be coupled to and extend from the exposed portion 126 on one side of the second die 120, for example, the lead 125 may be bonded to the pad 121 on the exposed portion 126 on one side of the second die 120. The shorter lead 115 may extend from the side of the first die 110 opposite to the coupled side, for example, the lead 115 may be bonded to the pad 111 of the first die 110. For simplicity, only some of the leads 115 and 125 are shown; however, it should be understood that the leads 115 and 125 may be formed on some (e.g., all) of the pads 111 and 121.

[0024] Reference now Figure 2 , showing Figure 1 1 is a cross-sectional view of an example of a multi-chip package 100 . The housing 130 surrounds the leads 115 and 125 and may cover an exposed portion of one side of the second die 120 and a side of the first die 110 extending from the leads 115 .

[0025] In the illustrated embodiment, the case 130 does not cover a side of the second die 120 opposite to a side of the exposed portion of the second die 120. However, in other embodiments, the case may cover side surfaces corresponding to both ends of the stack.

[0026] Reference now Figure 3 , showing Figure 2 An isometric view of an example of a housing 130 is shown, which shows the ends of leads 115 and 125 exposed by housing 130. In some embodiments, a portion of housing 130 can be removed to expose the ends of leads 115 and 125. Figure 1 As such, where only some of the leads 115 and 125 are shown for the sake of brevity, only some of the exposed ends of the leads 115 and 125 are shown for the sake of brevity.

[0027] In some embodiments, a grinding process may be applied to housing 130 to make the housing coplanar with the ends of leads 115 and 125. However, in other embodiments, portions of housing 130 may be removed using any removal process such as chemical etching, plasma etching, grinding, etc. or a combination thereof.

[0028] Reference now Figure 4 , showing Figure 3 , which includes a redistribution layer (RDL) 150 coupled to the ends of leads 115 and 125. In redistribution layer technology, additional circuits can be formed on the wafer after wafer manufacturing, which can enable electrical signals to be routed from one location on the top of the wafer to another location. In some examples, the redistribution layer technology can utilize additional metal layers (typically one to two layers) in combination with dielectric layers. The metal and dielectric layers can be interwoven to maintain circuits on a top metal layer that is electrically isolated from the bottom metal layer. Some redistribution layers include additional metal layers on the integrated circuit that contact the integrated circuit, for example, I / O (input / output) pads of the integrated circuit that are available in other locations.

[0029] The RDL 150 may be formed using any redistribution layer technology (e.g., currently available or later developed). The RDL 150 may provide chip-to-chip interconnects to couple selected connections of the first die 110 to selected connections of the second die 120. The RDL 150 may provide device-to-device interconnects via an external interface of a multi-chip package. For example, a first device having a multi-chip package may be coupled to an external second device via an external interface of the first device. The external interface of the first device may be an RDL 150 and / or a structure formed on the RDL 150, such as a solder ball 155 or some other structure for bringing out a connection of the RDL 150 from the multi-chip package for an interface to an external device. In some embodiments, the RDL 150 may include conductive regions 152 coplanar with the dielectric layer 151, and the solder balls 155 may be on these conductive regions 152.

[0030] Figure 5 4 shows a process 400 for forming an integrated circuit package for a stack of semiconductor dies of different sizes. In some embodiments, one of the dies may be similar to die 110 ( Figure 1 ), and another of the dies may be similar to die 120 ( Figure 1 ).

[0031] Block 401 of process 400 may include coupling a first die having a first side and a second side opposite the first side to a second die having a first side and a second side opposite the first side. The second side of the first die is smaller than the first side of the second die and is coupled to the first side of the second die such that a portion of the first side of the second die is exposed. Block 402 may include bonding a wire to a pad on the portion of the first side of the second die, and bonding a wire to a pad on the first side of the first die.

[0032] In block 403, process 400 may include covering the first side of the first die and the portion of the first side of the second die with a dielectric material. In block 404, a portion of the dielectric material may be removed to expose the ends of the leads. In some embodiments, the removal may include grinding the surface of the dielectric material to remove portions of the dielectric material to expose the ends of the leads at a first side of the housing opposite to a second side directly adjacent to the first die and the second die. The grinding may reach down to the ends of the leads. For example, the ends of the leads may be polished and / or scored, for example, partially polished or scored, by grinding.

[0033] In block 405, a conductive layer, such as a redistribution layer (RDL), may be formed over the remainder of the dielectric and the ends of the leads. The RDL may couple selected connections of the first die to selected connections of the second die. A first side of the RDL may be directly adjacent to the ends of the leads, and a second side opposite the first side may include conductive regions. These conductive regions may be referred to herein as "pads" on the second side of the RDL. In some examples, these pads may be coplanar with the dielectric regions on the second side of the RDL.

[0034] In block 406, process 400 may include forming conductive structures (e.g., solder balls or other portions of an external interface) on the RDL (e.g., on pads of the RDL) to provide interconnections between at least one of the dies and the external device. In some embodiments, solder balls may be formed on the pads on the second side of the RDL to couple the multi-chip package to a circuit board such as a printed circuit board (PCB) of the external device.

[0035] In contrast to wire bonding methods using a PCB with bonding fingers surrounding a stack of chips and leads hanging downward from the chips toward the bonding fingers, a multi-chip package formed using process 400 can have an xy dimension, which is a lateral dimension measured in a plane parallel to the first or second side of one of the above-mentioned tube cores, which can correspond to the surface area of ​​the side of the tube core that is farthest from the RDL. In some examples, the xy dimension of the package can be the same as the surface area of ​​the side of the tube core that is farthest from the RDL. Moreover, in contrast to wire bonding methods using a PCB with bonding fingers, a multi-chip package formed using process 400 can not require a substrate such as a PCB.

[0036] Reference again Figure 1 In some embodiments, at least one of the first die 110 or the second die 120 is a field programmable gate array (FPGA) including logic silicon, which may include a different bonding density (e.g., a greater bonding density) than other examples (e.g., a memory die stack of the same memory die). Utilizing the bonding density associated with logic silicon, the bonding pads 111 and 121 can be arranged on more than one side of the first die 110 and the second die 120. In this particular example, a 4-side bonding pad arrangement is shown for each of the first die 110 and the second die 120. In some embodiments, one of the dies of the multi-chip package can include an N-side bonding pad arrangement, and another die in the multi-chip package can include an X-side bonding pad arrangement, where X and N can be different values, and at least one of X or N can be greater than one.

[0037] In the illustrated example, the first die 110 and the second die 120 have the same geometry, but have different dimensions (e.g., different areas of the coupled sides). In some embodiments, the different sized dies in the stack can have different geometries, for example, the square side of one die can be coupled to the rectangular side of another die. In some embodiments, a rectangular side die having a long side equal in length to the edge of the square side die can be coupled to one side of the square side die to expose a portion of that side of the square side die. The rectangular side die can be centered on the square side die to expose two separate portions of the square side. In any embodiment, the thickness of one die of the stack can be different from the thickness of another die of the stack.

[0038] In the illustrated example, the stack includes two dies. However, in other examples, the stack may include any number of dies, such as 2-4 or more dies. The die sizing in the stack may be fully heterogeneous (in a stack of square side dies with fully heterogeneous sizing, the largest die may be on one end of a diamond-shaped stack, followed by smaller dies in sequence, until the smallest die on the other end of the diamond-shaped stack) or partially heterogeneous (a subset of two or more dies in the stack have the same size). Moreover, the functionality of the dies in the stack may be fully heterogeneous (e.g., a unique function for each die in the stack), or partially heterogeneous (wherein a subset of two or more dies have the same non-unique function, such as memory).

[0039] In a stack with partially heterogeneous size settings, one or more dies at one end of the stack may be logic silicon (if more than one, they may have different sizes), and the dies at the other end of the stack may include two or more memory dies of the same type in memory dies of the same size, each memory die having bonding pads only on one or two sides. Two or more memory dies each having bonding pads only on one or two sides may be arranged as a tile (with overhangs) to expose the bonding pads so that leads can be attached thereto. Two or more memory dies may have non-unique functions, for example, they may all be memories. The stack may include any combination of logic / memory dies, such as NAND (non-logical AND), DRAM (dynamic random access memory), 3D XPoint (three-dimensional crosspoint), SoC (system on chip), FPGA (i.e., multi-chip), etc., and combinations thereof.

[0040] Although the examples described herein utilize leads, other examples may utilize any elongated conductive structure that can remain vertical (e.g., completely vertical) for a period of time after being formed or attached, where the period of time is a period of time sufficient to apply molding to fix the position of the conductive structure relative to the die surface. Such elongated conductive structures may include conductive pillars, conductive rods, etc., or combinations thereof, that are located on (e.g., attached or formed on) the surface.

[0041] According to process 400 ( Figure 5 ) can be about 500 μm long, compared to about 2-3 mm long for the leads used in the suspension. The reduced length can improve signal integrity compared to the suspension lead approach.

[0042] In some examples, the leads may extend from an exposed portion of the larger die to the RDL, and other conductive structures (e.g., pads, etc., which are not necessarily elongated) may be located between one side of the smaller die and the RDL. Referring again to the leads, the length of the leads in a dual die stack may be the thickness of the smaller die (which thickness refers to the measurement of the distance between the aforementioned sides of such a die) plus an additional length corresponding to the thickness of the thin portion of the molding between the RDL and one side of the smaller die (which thickness here refers to the measurement of the distance between the side of the housing directly adjacent to the smaller die and the opposite side of the housing). The length of the conductive structures located between one side of the smaller die and the RDL may be equal to the additional length. In some embodiments, these conductive structures may be part of the RDL. For example, the RDL may include dielectric 151 ( Figure 5 ) between the pads. The pads on the side of the RDL closest to the smaller die can directly contact the selected pads of the smaller die.

[0043] In some examples, the count of interconnects (including chip-to-chip and / or device-to-device interconnects) provided by the RDL can be on the order of at least a few hundred or a few thousand, and the count of leads extending from the surface of the die can be on the order of at least a few hundred or a few thousand. The RDL and leads can route signals as follows: 1) from chip to chip; 2) from chip to an external interface on the side of the RDL opposite the stack; and / or 3) from chip to an external interface on the same side of the RDL as the stack (in which case there can be more than one multi-chip stack connected to the same RDL).

[0044] Figure 6 An exemplary computing device 500 is shown in which the apparatus and / or methods described herein may be employed according to various embodiments. In various embodiments, any component such as storage 520 (e.g., non-volatile storage (e.g., solid-state drive) having a two or more chip field programmable gate array architecture) may be previously referenced. Figure 1-Figure 5 The first device of the multi-chip packaging technology described. The first device may have a single semiconductor package with a stack of semiconductor dies of different sizes for the first device. In various embodiments, the computing device 500 may include a printed circuit board (PCB) 502; however, in alternative embodiments, various components may be coupled without the need for a PCB 502. In various embodiments, any component such as storage 520 may be physically and electrically coupled to a printed circuit board (PCB) 502 and electrically coupled to some other device through the PCB 502, or in embodiments without a PCB 502 may be directly physically and electrically coupled to other devices via an external interface of the first device.

[0045] Depending on its application, computing device 500 may include other components that may or may not be physically and electrically coupled to PCB 502. These other components may include one or more processors 504 (one is shown), at least one communication chip 506. In other implementations, communication chip 506 may be part of one or more processors 504. For these embodiments, one or more processors 504 and communication chip 506 may be disposed thereon. These components include, but are not limited to, a memory controller (not shown), a volatile memory (e.g., a dynamic random access memory (DRAM) not shown), an additional non-volatile memory such as a read-only memory (ROM) (not shown), a flash memory (not shown), an I / O controller (not shown), a digital signal processor (not shown), a cryptographic processor (not shown), a graphics processor 530, one or more antennas 528, a display (not shown), a touch screen display 532, a touch screen controller 546, a battery 536, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device 540, a compass 542, an accelerometer (not shown), a gyroscope (not shown), a speaker 550, a camera 552, and a mass storage device (e.g., a hard drive, a solid state drive, a compact disk (CD), a digital versatile disk (DVD) (not shown), etc. As previously described, any of these components may be previously referenced. Figure 1-Figure 5 The first device of the multi-chip packaging technology.

[0046] The communication chip 506 can implement wired and / or wireless communication for transmitting data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 506 may implement any of a number of wireless standards or protocols, including but not limited to IEEE 702.20, Long Term Evolution (LTE), Advanced LTE (LTE-A), General Packet Radio Service (GPRS), Evolution Data Optimized (Ev-DO), Evolved High Speed ​​Packet Access (HSPA+), Evolved High Speed ​​Downlink Packet Access (HSDPA+), Evolved High Speed ​​Uplink Packet Access (HSUPA+), Global Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Worldwide Interoperability for Microwave Access (WiMAX), Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. The computing device 500 may include multiple communication chips 506. For example, the first communication chip 506 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 506 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0047] In various embodiments, computing device 500 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit (e.g., game console or car entertainment unit), digital camera, home appliance, portable music player, or digital video recorder. In other embodiments, computing device 500 may be any other electronic device that processes data.

[0048] Any combination of one or more computer-usable or computer-readable media can be utilized. Computer-usable or computer-readable media can be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices, apparatuses or propagation media. More specific examples (non-exhaustive list) of computer-readable media will include the following: electrical connections with one or more leads, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, such as transmission media supporting the Internet or intranet, or magnetic storage media. It should be noted that a computer-usable or computer-readable medium can even be paper or another suitable medium on which a program can be printed, because the program can be captured electronically, for example, by optically scanning paper or other media, and then, if necessary, compiled, interpreted or otherwise processed by appropriate means, and then the program is stored in a computer memory. In the context of this article, a computer-usable or computer-readable medium can be any medium capable of containing, storing, transmitting, propagating or transmitting a program for use by or in conjunction with an instruction execution system, apparatus or device. The computer usable medium may include a propagated data signal containing the computer usable program code therein, either in baseband or as part of a carrier wave. The computer usable program code may be transmitted using any appropriate medium including but not limited to wireless, wired, optical cable, RF, etc.

[0049] Computer program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or a connection to an external computer may be formed (e.g., over the Internet using an Internet service provider).

[0050] Example

[0051] Example 1 is a device including a multi-chip package, the device comprising: a first tube core having a first side and a second side opposite to the first side; a second tube core having a first side and a second side opposite to the first side, the second side of the first tube core being smaller than the first side of the second tube core and coupled to the first side of the second tube core so that a portion of the first side of the second tube core is exposed; a first plurality of leads coupled to a portion of the first side of the second tube core and extending from the portion; a second plurality of leads coupled to the first side of the first tube core and extending from the first side of the first tube core; a housing surrounding the first and second plurality of leads and covering the first side of the first tube core and the portion of the first side of the second die, wherein ends of the first and second plurality of leads are exposed on a first side of the housing opposite to a second side directly adjacent to the first and second tube cores; and a redistribution layer (RDL) coupled to the first side of the housing and electrically coupled to the first and second plurality of leads.

[0052] Example 2 includes the subject matter of Example 1, and the RDL electrically connects at least one lead of the first plurality of leads and at least one lead of the second plurality of leads.

[0053] Example 3 includes the subject matter of any of Examples 1-2, and the external interface is electrically connected to the RDL.

[0054] Example 4 includes the subject matter of any of Examples 1-3, and the first side of the housing is smooth, and the exposed ends of the first and second leads are scored or polished.

[0055] Example 5 includes the subject matter of any of Examples 1-4, and the first plurality of leads are bonded to pads on the portion of the first side of the second die.

[0056] Example 6 includes the subject matter of any of Examples 1-5, and the second plurality of wires are bonded to pads on the first side of the first die.

[0057] Example 7 includes the subject matter of any of Examples 1-6, and the first plurality of leads are longer than the second plurality of leads.

[0058] Example 8 includes the subject matter of any of Examples 1-7, and end portions of the first plurality of leads and the second plurality of leads including the ends of the first and second pluralities of leads are perpendicular to the RDL.

[0059] Example 9 includes the subject matter of any of Examples 1-8, and end portions of other ends of the first and second pluralities of leads are perpendicular to the first side of the first die and the first side of the second die, respectively.

[0060] Example 10 includes the subject matter of any of Examples 1-9, and ends of the first and second pluralities of leads are coplanar with the first side of the housing.

[0061] Example 11 includes a method for multi-chip packaging, the method comprising: coupling a first die having a first side and a second side opposite to the first side and a second die having a first side and a second side opposite to the first side, wherein the second side of the first die is smaller than the first side of the second die and is coupled to the first side of the second die so that a portion of the first side of the second die is exposed; forming a housing that surrounds a first lead extending from a portion of the first side of the second die and a second lead extending from the first side of the first die and covers the first side of the first die and the portion of the first side of the second die, wherein ends of the first and second plurality of leads are exposed on a first side of the housing opposite to a second side directly adjacent to the first and second dies; and forming a redistribution layer (RDL) coupled to the first side of the housing and electrically coupled to the first and second plurality of leads.

[0062] Example 12 includes the subject matter of Example 11, and bonding the first plurality of wires to pads on the portion of the first side of the second die; and bonding the second plurality of wires to pads on the first side of the first die.

[0063] Example 13 includes the subject matter of any of Examples 11-12, and forming the housing further comprises: covering the first side of the first die and the portion of the first side of the second die with a dielectric material; and removing portions of the dielectric material to expose ends of the first and second pluralities of leads.

[0064] Example 14 includes the subject matter of any of Examples 11-13, and grinding the surface of the dielectric material to remove portions of the dielectric material.

[0065] Example 15 includes the subject matter of any of Examples 11-14, and forming solder balls on pads of the RDL.

[0066] Example 16 is a system including a multi-chip package, the system comprising: a first device having a single semiconductor package for a stack of semiconductor dies of different sizes for the first device, wherein a dimension of the first semiconductor die of the stack is larger than a dimension of a second semiconductor die of the stack adjacent to the first semiconductor die in the stack so that the second semiconductor die exposes a surface of the first semiconductor die, wherein the single semiconductor package includes a housing surrounding leads extending from the exposed surface of the first semiconductor die at least to a plane coplanar with an end of the stack; and a second device coupled to at least one of the leads via an external interface of the semiconductor package.

[0067] Example 17 includes the subject matter of Example 16, and the external interface secures the first device to a circuit board of the second device.

[0068] Example 18 includes the subject matter of any of Examples 16-17, and at least one of the leads provides an electrical connection between the first semiconductor die and the second semiconductor die.

[0069] Example 19 includes the subject matter of any of Examples 16-18, and at least one of the leads provides an electrical connection between the external interface and at least one of the first semiconductor die or the second semiconductor die.

[0070] Example 20 includes the subject matter of any of Examples 16-19, and the housing surrounds the leads extending from the surface of the second semiconductor die.

[0071] Example 21 is a device including a multi-chip package, the device comprising: a module for encapsulating the sides of leads extending from the surface of a first semiconductor die of a stack of semiconductor die of different sizes; wherein the surface is exposed by a second semiconductor die, which is smaller than the first semiconductor die and is adjacent to the first semiconductor die in the stack; and a module for connecting the exposed ends of at least one of the leads to the exposed ends of at least one of the leads extending from the exposed surface of the second semiconductor die.

[0072] Example 22 includes the subject matter of Example 21, and a module for attaching an external electrical interface of a device to a circuit board.

[0073] Example 23 includes the subject matter of any of Examples 21-22, and the encapsulated module exposes ends of the leads.

[0074] Example 24 includes the subject matter of any of Examples 21-23, and the ends of the leads and the encapsulation module are coplanar.

[0075] Example 25 includes the subject matter of any of Examples 21-24, and a module for attaching leads to exposed surfaces of first and second semiconductor dies.

Claims

1. A device comprising: a first die having a first side and a second side opposite the first side, wherein the first die includes a first plurality of pads on N sides on the first side of the first die; a second die having a first side and a second side opposite the first side, the second side of the first die being smaller than the first side of the second die and coupled to the first side of the second die such that a portion of the first side of the second die is exposed, wherein the second die includes a second plurality of pads on X sides on the portion of the first side of the second die, and wherein X and N are different values; a first plurality of leads coupled to and extending from the portion of the first side of the second die, wherein the first plurality of leads are vertically bonded to the second plurality of pads located on the X sides; a second plurality of leads coupled to and extending from the first side of the first die, wherein the second plurality of leads are vertically bonded to the first plurality of pads located on the N sides; a housing surrounding the first and second pluralities of leads and covering the portions of the first and second sides of the first and second dies, wherein ends of the first and second pluralities of leads are exposed at a first side of the housing opposite to a second side directly adjacent to the first and second dies; and a redistribution layer (RDL) coupled to the first side of the housing and electrically coupled to the first plurality of leads and the second plurality of leads, wherein the first plurality of pads of the first die are located between the second plurality of pads of the second die and the redistribution layer, wherein the first die is a memory die, the second die is a field programmable gate array including logic silicon, and the first die and the second die have different geometries; wherein the size setting of the first tube die and the size setting of the second tube die are completely heterogeneous, and the function of the first tube die and the function of the second tube die are completely heterogeneous; wherein the first tube die and the second tube die have different bonding densities; Each second lead in the second plurality of leads is located between two adjacent first leads in the first plurality of leads.

2. The device according to claim 1, wherein: The RDL electrically connects at least one lead of the first plurality of leads and at least one lead of the second plurality of leads. 3 . The device of claim 1 , further comprising an external interface electrically connected to the RDL.

4. The device according to claim 1, wherein: The first side of the housing is smooth, and the exposed ends of the first lead and the second lead are scored or polished.

5. The device according to claim 1, wherein: The first plurality of leads is longer than the second plurality of leads.

6. The device according to claim 1, wherein: End portions of the first and second pluralities of leads including the ends of the first and second pluralities of leads are perpendicular to the RDL.

7. The device according to claim 6, wherein: End portions of other ends of the first plurality of leads and the second plurality of leads are perpendicular to the first side of the first die and the first side of the second die, respectively.

8. The device according to any one of claims 1 to 6, wherein: Ends of the first plurality of leads and the second plurality of leads are coplanar with a first side of the housing.

9. A method comprising: coupling a first die having a first side and a second side opposite the first side and a second die having a first side and a second side opposite the first side, wherein the second side of the first die is smaller than the first side of the second die and coupled to the first side of the second die such that a portion of the first side of the second die is exposed, wherein the first die includes a first plurality of pads on N sides on the first side of the first die, and the second die includes a second plurality of pads on X sides on the portion of the first side of the second die, and wherein X and N are different values; forming a housing surrounding first leads extending from the portion of the first side of the second die and second leads extending from the first side of the first die and covering the portion of the first side of the first die and the first side of the second die, wherein ends of the first plurality of leads and the second plurality of leads are exposed at a first side of the housing opposite to a second side directly adjacent to the first die and the second die, wherein the first plurality of leads are vertically bonded to the second plurality of pads located on X sides, and the second plurality of leads are vertically bonded to the first plurality of pads located on N sides; and forming a redistribution layer (RDL) coupled to the first side of the housing and electrically coupled to the first plurality of leads and the second plurality of leads, wherein the first plurality of pads of the first die are located between the second plurality of pads of the second die and the redistribution layer, wherein the first die is a memory die, the second die is a field programmable gate array including logic silicon, and the first die and the second die have different geometries, wherein the size setting of the first die and the size setting of the second die are completely heterogeneous, and the function of the first die and the function of the second die are completely heterogeneous, wherein the first tube die and the second tube die have different bonding densities, Each second lead in the second plurality of leads is located between two adjacent first leads in the first plurality of leads.

10. The method according to claim 9, wherein: Forming the housing further comprises: covering the first side of the first die and the portion of the first side of the second die with a dielectric material; and Portions of the dielectric material are removed to expose the ends of the first and second pluralities of leads.

11. The method of claim 10, further comprising grinding a surface of the dielectric material to remove the portion of the dielectric material.

12. The method according to any one of claims 9-10, further comprising forming solder balls on pads of the RDL.

13. A system comprising: a first device having a single semiconductor package for a stack of semiconductor dies of different sizes for the first device, wherein a first semiconductor die of the stack has a dimension greater than a dimension of a second semiconductor die of the stack adjacent to the first semiconductor die in the stack such that the second semiconductor die exposes a surface of the first semiconductor die, wherein the second semiconductor die includes a first plurality of solder pads on N sides on a first side of the second semiconductor die, and the first semiconductor die includes a second plurality of solder pads on X sides on an exposed surface of the first side of the first semiconductor die, and wherein X and N are different values, wherein the single semiconductor package comprises a housing that encloses a first plurality of leads extending from an exposed surface of the first semiconductor die to at least a plane coplanar with an end of the stack and a second plurality of leads extending from a surface of the second semiconductor die, wherein the first plurality of leads are vertically bonded to the second plurality of pads located on X sides, and the second plurality of leads are vertically bonded to the first plurality of pads located on N sides; wherein the single semiconductor package further comprises a redistribution layer coupled to the first side of the housing and electrically coupled to the first plurality of leads and the second plurality of leads, wherein the first plurality of pads of the second semiconductor die are located between the second plurality of pads of the first semiconductor die and the redistribution layer, and a second device coupled to at least one of the first plurality of leads via an external interface of the semiconductor package, wherein the first semiconductor die is a field programmable gate array including logic silicon, the second semiconductor die is a memory die, and the first semiconductor die and the second semiconductor die have different geometries, wherein the size setting of the first semiconductor die and the size setting of the second semiconductor die are completely heterogeneous, and the function of the first semiconductor die and the function of the second semiconductor die are completely heterogeneous, wherein the first semiconductor die and the second semiconductor die have different bonding densities, Each second lead in the second plurality of leads is located between two adjacent first leads in the first plurality of leads.

14. The system according to claim 13, wherein: The external interface secures the first device to a circuit board of the second device.

15. The system of claim 13, wherein: At least one of the first plurality of leads provides an electrical connection between the first semiconductor die and the second semiconductor die.

16. The system of claim 13, wherein: At least one of the first plurality of leads provides an electrical connection between the external interface and at least one of the first semiconductor die or the second semiconductor die.

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