Semiconductor package and method of manufacturing the same

Abstract

There is provided a semiconductor package including: a lower package substrate including a lower insulating layer; a first semiconductor device mounted on the lower package substrate; a core layer on the lower package substrate to be laterally spaced apart from the first semiconductor device; an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer; an upper package substrate disposed on the encapsulation material, the upper package substrate including a first upper redistribution layer and a second upper redistribution layer; wherein a first line width and a first line pitch of a first fine pattern of the first upper redistribution pattern are greater than or equal to a corresponding second line width and a corresponding second line pitch of a second fine pattern of the second upper redistribution pattern, respectively.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0113970 filed on August 29, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a panel-level semiconductor package and a method of manufacturing the same. Background Art

[0004] In the electronic product market, the demand for portable devices is rapidly increasing. The miniaturization and lightweighting of electronic components mounted on these electronic products are still desired. In order to miniaturize and lightweight electronic components, semiconductor packages mounted on electronic components need to process large-capacity data, while the volume of semiconductor packages is gradually reduced. Recently, a panel-level packaging (PLP) technology has been proposed, which performs a semiconductor packaging process at a panel level and divides the panel-level semiconductor structure on which the semiconductor packaging process is performed into separate packages. Summary of the invention

[0005] The inventive concept provides a semiconductor package in which a line width of a fine pattern included in a redistribution pattern of an upper package substrate is further refined.

[0006] Those skilled in the art will understand that the objectives that can be achieved by using the inventive concept are not limited to the contents specifically described above, and through the following detailed description, the above and other objectives that can be achieved by the inventive concept will be more clearly understood.

[0007] According to an aspect of the inventive concept, a semiconductor package is provided, comprising: a lower package substrate comprising a lower insulating layer; a first semiconductor device mounted on the lower package substrate; a core layer on the lower package substrate, the core layer being laterally spaced apart from the first semiconductor device and comprising: a core substrate, a core via passing through the core substrate, and a core pattern connecting the core vias to each other; an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer; and an upper package substrate disposed on the encapsulation material, the upper package substrate comprising a first upper redistribution layer and a second upper redistribution layer, wherein the first upper redistribution layer comprises a first upper insulating layer and a first upper redistribution pattern on the first upper insulating layer, the second upper redistribution layer comprises a second upper insulating layer on the first upper insulating layer and a second upper redistribution pattern on the second upper insulating layer, a first line width of a first fine pattern of the first upper redistribution pattern being greater than or equal to a corresponding second line width of a second fine pattern of the second upper redistribution pattern, and a first line spacing of the first fine pattern being greater than or equal to a corresponding second line spacing of the second fine pattern.

[0008] According to another aspect of the inventive concept, there is provided a method for manufacturing a semiconductor package, the method comprising: forming a first process structure, the first process structure comprising: a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate, and an encapsulation material surrounding the first semiconductor device on the lower package substrate, and the core layer is laterally spaced apart from the first semiconductor device, and the encapsulation material is on the core layer; forming a first upper redistribution layer, the first upper redistribution layer comprising: a first upper insulating layer on the encapsulation material of the first process structure, and a first upper redistribution pattern on the first upper insulating layer; and forming a second upper redistribution layer, the second upper redistribution layer comprising: a second upper insulating layer on the first upper redistribution layer, and a second upper redistribution pattern on the second upper insulating layer, wherein forming the first upper redistribution layer comprises: forming the first upper insulating layer on the encapsulation material; forming a plurality of first upper through holes by recessing a portion of the encapsulation material, the plurality of first upper through holes passing through the first upper insulating layer, and exposing a portion of the core layer through the plurality of first upper through holes; forming a first seed layer on the first upper insulating layer having the plurality of first upper through holes; and forming a first upper via pattern in the plurality of first upper via holes, the first upper via pattern being electrically connected to the core layer, and forming a first upper line pattern on the first upper via pattern, wherein forming a second upper redistribution layer comprises: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper via holes passing through the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper via holes; forming a resist layer on the second upper insulating layer having the second seed layer formed thereon; and forming a second upper via pattern on the plurality of second upper via holes, and forming a second upper line pattern on the second upper via pattern, wherein the material of the first upper insulating layer and the material of the second upper insulating layer are different from each other, the first upper redistribution pattern and the second upper redistribution pattern are formed so that a first line width of a first fine pattern of the first upper redistribution pattern is greater than or equal to a corresponding second line width of a second fine pattern of the second upper redistribution pattern, the first upper redistribution pattern and the second upper redistribution pattern are formed so that a first line spacing of the first fine pattern is greater than or equal to a corresponding second line spacing of the second fine pattern, and the first seed layer is formed by electroless plating. The first seed layer is formed by a sputtering process, and the second seed layer is formed by a sputtering process.

[0009] According to another aspect of the inventive concept, a method for manufacturing a semiconductor package is provided, the method comprising: forming a first process structure, the first process structure comprising: a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate, and an encapsulation material surrounding the first semiconductor device on the lower package substrate, the core layer being laterally spaced apart from the first semiconductor device, and the encapsulation material being on the core layer; forming a first upper redistribution layer, the first upper redistribution layer comprising: a first upper insulating layer on the encapsulation material of the first process structure, and a first upper redistribution pattern on the first upper insulating layer; and forming a second upper redistribution layer, the second upper redistribution layer comprising: a second upper insulating layer on the first upper redistribution layer, and a second upper redistribution pattern on the second upper insulating layer, wherein forming the first upper redistribution layer comprises: forming the first upper insulating layer on the encapsulation material; forming a plurality of first upper through holes by recessing a portion of the encapsulation material, A plurality of first upper vias pass through the first upper insulating layer, and a portion of the core layer is exposed through the plurality of first upper vias; a first seed layer is formed on the first upper insulating layer having the plurality of first upper vias; and a first upper via pattern is formed in the plurality of first upper vias, the first upper via pattern is electrically connected to the core layer, and a first upper line pattern is formed on the first upper via pattern, and forming a second upper redistribution layer includes: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper vias passing through the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper vias; forming an anti-etching layer on the second upper insulating layer having the second seed layer formed thereon; and forming a second upper via pattern on the plurality of second upper vias, and forming a second upper line pattern on the second upper via pattern, wherein the material of the first upper insulating layer and the material of the second upper insulating layer are the same as each other, and the first seed layer and the second seed layer are each formed using a sputtering process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment;

[0012] Figure 2 is a diagram showing a cross section of a semiconductor package according to an embodiment;

[0013] Figure 3 is a cross-sectional view of a semiconductor package according to an embodiment;

[0014] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment;

[0015] Figure 5 is a flowchart for explaining a method for manufacturing a semiconductor package according to an embodiment;

[0016] Figure 6 is a flowchart for explaining in more detail a method for manufacturing a semiconductor package according to an embodiment;

[0017] 7A to 7F is a cross-sectional view for explaining a method for manufacturing a semiconductor package according to an embodiment;

[0018] FIG. 8A to FIG. 8J is a cross-sectional view for explaining a method for manufacturing a semiconductor package according to an embodiment;

[0019] Fig. 9 is a flowchart for explaining a method for manufacturing a semiconductor package according to an embodiment; and

[0020] FIG. 10A to FIG. 10J is a cross-sectional view for explaining a method for manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and their repeated descriptions are omitted.

[0022] Figure 1 is a cross-sectional view of a semiconductor package 1 according to the embodiment.

[0023] Reference Figure 1 , the semiconductor package 1 includes: a semiconductor chip 200, a lower package substrate 300 disposed below the semiconductor chip 200, a core layer 100 having a through hole CA to mount the semiconductor chip 200 therein, an encapsulation material 130 surrounding the side surface and upper surface of the semiconductor chip 200 and the upper surface and part of the side surface of the core layer 100, and an upper package substrate 400 disposed on the encapsulation material 130. The semiconductor package 1 may be a fan-out type semiconductor package in which the connection pads 220 of the semiconductor chip 200 are redistributed externally. In this specification, the semiconductor chip 200 may be referred to as a first semiconductor device.

[0024] The core layer 100 may include through holes CA passing through the upper and lower surfaces thereof to mount the semiconductor chip 200 therein. Figure 1 As shown, the through hole CA may be formed at the center of the core layer 100, but the number and arrangement of the through holes CA are not limited to this figure. In some embodiments, the through hole CA may have a cavity shape instead of completely passing through the lower surface of the core layer 100. For example, the through hole CA may not completely pass through the lower surface of the core layer 100, and a portion of the core layer 100 may remain below the through hole CA.

[0025] The core layer 100 may include a core insulating layer 110, a core wiring layer 121, and a core via 122. The core wiring layer 121 and the core via 122 may be arranged to electrically connect the upper surface and the lower surface of the core layer 100 to each other. The core wiring layer 121 may be arranged inside the core insulating layer 110, but is not limited thereto. The core wiring layer 121 exposed through the lower surface of the core layer 100 among all the core wiring layers 121 may be embedded and arranged in the core insulating layer 110, which may be a structure based on a manufacturing process. The core insulating layer 110 may be referred to as a base substrate.

[0026] The core insulating layer 110 may be formed of an insulating material (e.g., a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide) or include an insulating material (e.g., a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide), and may also include an inorganic filler. Alternatively, in addition to the inorganic filler, the core insulating layer 110 may include a resin impregnated into a core material (e.g., glass fiber, glass cloth, and glass fabric), such as a prepreg, ajinomoto built-in film (ABF), FR-4, or bismaleimide triazine (BT). The core insulating layer 110 may be a multilayer substrate including a plurality of layers.

[0027] The semiconductor chip 200 may be mounted in the through hole CA of the core layer 100 and may be spaced apart from the inner wall of the through hole CA. The first semiconductor chip 200 may be configured as a single chip or multiple chips. The semiconductor chip 200 may include a semiconductor substrate 210 having an active surface and an inactive surface opposite to each other, and a connection pad 220 disposed on the active surface of the semiconductor chip 200. For example, the semiconductor chip 200 may have a vertical thickness of about 150 μm or more.

[0028] The semiconductor chip 200 may have a face-down arrangement in which an active surface of the semiconductor substrate 210 faces the lower package substrate 300, and may be mounted on an upper surface of the lower package substrate 300. In this case, the inactive surface of the semiconductor chip 200 may be referred to as an upper surface of the semiconductor chip 200, and a surface of the semiconductor substrate 210 opposite to the inactive surface of the semiconductor chip 200 may be referred to as a lower surface of the semiconductor chip 200.

[0029] The semiconductor substrate 210 may be formed of, for example, a semiconductor material such as silicon (Si) or germanium (Ge) or include, for example, a semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the semiconductor substrate 210 may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 210 may include a well doped with impurities as a conductive region. The semiconductor substrate 210 may have various device separation structures such as a shallow trench isolation (STI) structure.

[0030] A semiconductor device including a plurality of individual devices of various types may be formed on an active surface of the semiconductor substrate 210. The plurality of individual devices may be electrically connected to a conductive region of the semiconductor substrate 210. The semiconductor device may further include a conductive wiring or a conductive plug that electrically connects the plurality of individual devices to the conductive region of the semiconductor substrate 210. The plurality of individual devices may be electrically separated from other individual devices adjacent to each other by an insulating film.

[0031] In some embodiments, the semiconductor chip 200 may include a logic device. For example, the semiconductor chip 200 may be a central processing device chip, a graphics processing device chip, or an application processor (AP). In other embodiments, when the semiconductor package 1 includes a plurality of semiconductor chips 200, one of the plurality of semiconductor chips 200 may be a central processing device chip, a graphics processing device chip, or an AP chip, and another may be a memory semiconductor chip including a memory device.

[0032] For example, the memory device may be a non-volatile memory device such as a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some embodiments, the memory device may be a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0033] The semiconductor chip 200 may include a connection pad 220 disposed on the lower surface of the semiconductor chip 200. The connection pad 220 may be provided to electrically connect the semiconductor chip 200 to other components. In some embodiments, a redistribution layer, a bump, etc. connected to the connection pad 220 may be further provided on the lower surface of the semiconductor chip 200. The connection pad 220 may be formed of a conductive material (such as aluminum (Al)) or include a conductive material (such as aluminum (Al)). The semiconductor chip 200 may be electrically connected to the lower redistribution pattern 320 of the lower package substrate 300 through the connection pad 220.

[0034] On the lower package substrate 300, the connection pads 220 may be redistributed in a region outside the semiconductor chip 200 below the semiconductor chip 200. The lower package substrate 300 may include a plurality of lower insulating layers 310, and a lower redistribution pattern 320 including a lower via pattern 321 and a lower line pattern 322. The number and arrangement of the lower insulating layers 310, the lower via pattern 321, and the lower line pattern 322 constituting the lower package substrate 300 are not limited to the drawings, and may be changed in various ways in some embodiments.

[0035] The lower insulating layer 310 may be formed of an insulating material such as a photoimageable dielectric (PID) resin or include an insulating material such as a photoimageable dielectric (PID) resin. In this case, the lower insulating layer 310 may further include an inorganic filler. The lower insulating layer 310 may include the same material or different materials. The lower redistribution pattern 320 including the lower via pattern 321 and the lower line pattern 322 may perform a function of redistributing the connection pad 220.

[0036] The lower line pattern 322 may be disposed on at least one of the upper surface and the lower surface of the lower insulating layer 310. The lower via pattern 321 may be connected to a portion of the lower line pattern 322 through the lower insulating layer 310.

[0037] The lower via pattern 321 may be completely filled with a conductive material, or may have a shape in which a conductive material is formed along the wall of the via. The lower redistribution pattern 320 may be formed of or include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof.

[0038] The lower surface of the semiconductor chip 200 may be in contact with the uppermost lower insulating layer 310 of all the lower insulating layers 310. It should be understood that when an element is referred to as "contacting" another element or "contacting" another element (or any form of the word "contacting"), there is no intermediate element at the contact portion. In the semiconductor package manufacturing method S1 as a manufacturing process of the semiconductor package 1 according to the embodiment described below (see, for example, Figure 5 ), the lower package substrate 300 can be formed on the lower surface of the semiconductor chip 200 by a chip-first process. Figure 7F As described above, according to the order of forming the lower package substrate 300 , in the semiconductor package 1 according to the embodiment, the lower via pattern 321 may have a tapered shape whose horizontal width increases as it goes away from the semiconductor chip 200 .

[0039] The lower passivation layer 350 may be disposed on a lower surface of the lower package substrate 300 and may protect the lower package substrate 300. The lower passivation layer 350 may be formed of or include an insulating material (eg, resin), but is not limited thereto.

[0040] At least a portion of the lower line pattern 322 may be exposed through the opening of the lower passivation layer 350, and the lower pads 330 may be disposed on the exposed lower line pattern 322. The external connection terminals 340 may be electrically connected to the lower pads 330, respectively.

[0041] The external connection terminal 340 can connect the semiconductor package 1 to a main board of a separate electronic device on which the semiconductor package 1 is mounted. The external connection terminal 340 may be formed of or include at least one of a conductive material such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). In addition to a spherical shape, the shape of the external connection terminal 340 may be changed to various forms such as a pad, a bump, a column, or a pin.

[0042] The encapsulation material 130 can prevent the semiconductor chip 200 from being physically and / or chemically damaged from the outside by sealing the semiconductor chip 200. The encapsulation material 130 can fill the space in the through hole CA of the core layer 100 and extend on the upper surface of the core layer 100. In other words, the encapsulation material 130 can fill the space between the inner wall of the through hole CA and the semiconductor chip 200, and cover a part of the upper surface of the semiconductor chip 200 and the upper surface of the core layer 100. In some embodiments, the encapsulation material 130 can fill at least part of the space between the semiconductor chip 200 and the upper package substrate 400. The encapsulation material 130 can be formed by an insulating material (such as epoxy resin or polyimide) or include an insulating material (such as epoxy resin or polyimide). However, the material of the encapsulation material 130 is not limited to the above-mentioned materials.

[0043] The upper package substrate 400 may include a first upper redistribution layer RDL1 and a second upper redistribution layer RDL2. The upper package substrate 400 may be disposed on an upper surface of the encapsulation material 130 and may be electrically connected to the semiconductor chip 200 and the lower package substrate 300 through the core wiring layer 121 and the core via 122 of the core layer 100.

[0044] The first upper redistribution layer RDL1 may include a first upper insulating layer 411A disposed on the encapsulation material 130 and a first redistribution pattern 420. The first redistribution pattern 420 may include a first upper via pattern 421 (e.g., a first upper via), a first upper line pattern 422 (e.g., a first upper line), and a first fine pattern FP1. A first seed layer SD1A serving as a substrate for forming the first redistribution pattern 420 may be disposed on a lower surface of the first redistribution pattern 420. Unless otherwise specified, the term "pattern" may refer to vias and / or lines forming part of a redistribution layer or other layer. The term "pattern" may also refer to a group of patterns. For example, the term "pattern" may collectively refer to one or more via patterns and one or more line patterns.

[0045] The first upper via patterns 421 may each pass through the first upper insulating layer 411A. The first upper via patterns 421 may each be electrically connected to the uppermost core wiring layer 121 of the core layer 100 through a portion of the encapsulation material 130. The first upper line pattern 422 may be disposed on the first upper insulating layer 411A and the first upper via patterns 421. Redistribution of electrical input and output in the first upper redistribution layer RDL1 may be achieved by the first fine pattern FP1.

[0046] Among all side surfaces of the first upper via pattern 421 , portions of the side surfaces of the first upper via pattern 421 may contact the first upper insulating layer 411A, and at least other portions of the side surfaces of the first upper via pattern 421 that are not in contact with the first upper insulating layer 411A may contact the encapsulation material 130 .

[0047] The first seed layer SD1A may be disposed between the first upper via pattern 421 and the first upper insulating layer 411A and between the first upper line pattern 422 and the first upper insulating layer 411A. In the specification, the first upper via pattern 421 and the first upper line pattern 422 are considered to include the first seed layer SD1A until it contacts the lower surface. That is, a portion of the side surface of the first upper via pattern 421 is shown as being in contact with the first seed layer SD1A, and a portion of the side surface of the first seed layer SD1A is shown as being in contact with the first upper insulating layer 411A, but the first seed layer SD1A in contact with the first upper via pattern 421 is included in the first upper via pattern 421 (e.g., is a portion of the first upper via pattern 421), and therefore, a portion of the side surface of the first upper via pattern 421 may be described as being in contact with the first upper insulating layer 411A. Meanwhile, among all side surfaces of the first upper via pattern 421 , at least other portions of the surface of the first upper via pattern 421 that are not in contact with the first upper insulating layer 411A may be described as being in contact with the encapsulation material 130 .

[0048] The first upper via pattern 421 may have a tapered shape whose horizontal width increases as it moves away from the lower package substrate 300 .

[0049] The first upper insulating layer 411A may be processed, and a first through hole 420R (see FIG. 4B ) in which the first redistribution pattern 420 is to be disposed may be formed in the first upper insulating layer 411A. Figure 8C For example, the first upper insulating layer 411A may be laser processed, and a first through hole 420R in which the first redistribution pattern 420 is to be disposed may be formed in the first upper insulating layer 411A (see Figure 8C ).

[0050] The first upper insulating layer 411A may be formed of a build-up material or include a build-up material. According to an embodiment, a build-up film as a build-up material may be a film obtained by adding SiO2 using epoxy resin as a main component. 2 The three-layer structure is obtained by combining a resin structure of a filler material and a flame retardant with a PET film as a base at the bottom. The laminated material may include an Ajinomoto laminated film (ABF) or other laminated materials. For example, ABF may be used as the laminated material included in the first upper insulating layer 411A. Therefore, according to an embodiment, the encapsulation material 130 and the first upper insulating layer 411A may include the same laminated material.

[0051] In order to form the first seed layer SD1A as a base of the first redistribution pattern 420 by electroless plating after forming the encapsulation material 130 including ABF, the first upper insulating layer 411A including ABF may be newly formed on the upper surface of the encapsulation material 130 including the hardened ABF. When the unhardened first upper insulating layer 411A including ABF is formed on the encapsulation material 130 including the hardened ABF, the unhardened ABF may have greater adhesion to the plating layer than the hardened ABF in the electroless plating. Therefore, in order to easily form the electroless plating for forming the first seed layer SD1A, the first upper insulating layer 411A may be formed by applying ABF to form the first upper insulating layer 411A on the encapsulation material 130. In this way, the reliability of the wiring of the semiconductor package 1 according to the embodiment may be improved.

[0052] The first seed layer SD1A formed by electroless plating can be formed of one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti) and gold (Au), or include one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti) and gold (Au).

[0053] The second upper redistribution layer RDL2 may include a second upper insulating layer 412 and a second redistribution pattern 430 disposed on the first upper insulating layer 411A. The second redistribution pattern 430 may include a second upper via pattern 431, a second upper line pattern 432, and a second fine pattern FP2. A second seed layer SD2 used as a substrate for forming the second redistribution pattern 430 may be disposed on a lower surface of the second redistribution pattern 430. The redistribution of electrical inputs and outputs in the second upper redistribution layer RDL2 may be achieved by the second fine pattern FP2. Unlike the accompanying drawings, the semiconductor package 1 according to the embodiment may include three or more redistribution layers by stacking a plurality of second upper redistribution layers RDL2. In this case, the second upper via pattern 431 may be a stacked via or an alternating via, and may be disposed on the second upper redistribution layer RDL2 in the front. Stacked vias refer to a structure in which via patterns are stacked up and down, and alternating vias refer to a structure in which via patterns are stacked up and down and are arranged laterally at a distance offset from each other.

[0054] The second upper insulating layer 412 may be disposed on the first upper insulating layer 411A and the first redistribution pattern 420. The second upper insulating layer 412 may be formed of or include an insulating material such as a PID resin. In this case, the second upper insulating layer 412 may further include an inorganic filler.

[0055] A second redistribution pattern 430 including a second upper via pattern 431 and a second upper line pattern 432 may be formed on the second upper insulating layer 412. The second upper via pattern 431 may be electrically connected to at least a portion of the first upper line pattern 422 of the first upper redistribution layer RDL1 through the second upper insulating layer 412. The second upper line pattern 432 may be disposed on the second upper insulating layer 412, and may be disposed on the second upper via pattern 431. A metal plating layer 433 may be disposed on at least a portion of the second upper line pattern 432. The metal plating layer 433 may be formed of or include a metal, including, for example, gold (Au).

[0056] The upper passivation layer 440 may be disposed on the upper surface of the second upper insulating layer 412 and may protect the upper package substrate 400. The upper passivation layer 440 may include an insulating material, such as a build-up material, but is not limited thereto. The upper passivation layer 440 may include a third hole 440R obtained by recessing a portion of the upper passivation layer 440, through which at least a portion of the second upper via pattern 431 and the metal plating layer 433 are exposed. In a package-on-package type package in which the upper semiconductor device 500 described below is stacked or attached to another package, the upper connection terminal 540 may be located in the third hole 440R.

[0057] According to an embodiment, the second upper insulating layer 412 may include a photo-imageable dielectric (PID) resin, and the second seed layer SD2 as a base of the second redistribution pattern 430 may be formed by a sputtering process. The second seed layer SD2 may be formed to have a smaller line width than the case where the second seed layer SD2 is formed by electroless plating. When the second upper insulating layer 412 includes the PID resin, the second seed layer SD2 is correspondingly formed by a sputtering process, and therefore, the line width of the second seed layer SD2 may be smaller than the line width of the first seed layer SD1A as a base of the first redistribution pattern 420 formed by electroless plating. Therefore, the line width of the second fine pattern FP2 of the second redistribution pattern 430 may be equal to or smaller than the line width of the first fine pattern FP1 of the first redistribution pattern 420. In other words, the line width of the first fine pattern FP1 of the first redistribution pattern 420 may be equal to or larger than the line width of the second fine pattern FP2 of the second redistribution pattern 430.

[0058] For example, the first line width LW1A and the first line spacing LS1A of the first fine pattern FP1 are respectively equal to or greater than the second line width LW2 and the second line spacing LS2 of the second fine pattern FP2. The first line width LW1A of the first fine pattern FP1 may be equal to or less than 10 μm, the first line spacing LS1A may be equal to or less than 13 μm, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the first line width LW1A may be about 5 μm to about 10 μm, the first line spacing LS1 may be about 5 μm to about 13 μm, the second line width LW2 may be about 3 μm to about 9 μm, and the second line spacing LS2 may be about 3 μm to about 12 μm. Alternatively, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 5 μm, and the second line spacing LS2 may be equal to or less than 5 μm.

[0059] In the semiconductor package 1, the line width of the second fine pattern FP2 may be smaller than that of the first fine pattern FP1. Therefore, in the semiconductor package 1 according to the embodiment, the fine pattern of the second package substrate 400 corresponding to the post redistribution layer may be further refined, thereby improving the performance of the semiconductor package 1.

[0060] Figure 2 1A is a diagram showing a cross section of a semiconductor package 1A according to an embodiment. Description of elements similar to those described above may be omitted.

[0061] Reference Figure 2The semiconductor package 1A includes: a semiconductor chip 200, a lower package substrate 300 disposed under the semiconductor chip 200, a core layer 100 having a through hole CA to mount the semiconductor chip 200 therein, an encapsulation material 130 surrounding the side surface and upper surface of the semiconductor chip 200 and the upper surface and part of the side surface of the core layer 100, and an upper package substrate 400 disposed on the encapsulation material 130. Figure 1 to describe the difference Figure 2 .

[0062] The upper package substrate 400 may include a first upper redistribution layer RDL1 and a second upper redistribution layer RDL2 .

[0063] The first upper redistribution layer RDL1 may include a first upper insulating layer 411B disposed on the encapsulation material 130, and a first redistribution pattern 420. The first redistribution pattern 420 may include a first upper via pattern 421, a first upper line pattern 422, and a first fine pattern FP1. The first upper via patterns 421 may each pass through the first upper insulating layer 411B. The first upper via patterns 421 may each be electrically connected to the uppermost core wiring layer 121 of the core layer 100 through a portion of the encapsulation material 130. The first upper line pattern 422 may be disposed on the first upper insulating layer 411B and the first upper via pattern 421.

[0064] According to Figure 1 The semiconductor package 1 of the embodiment is different from that of Figure 2 In another embodiment of the semiconductor package 1A, the first upper insulating layer 411B may include an insulating material other than a build-up material, such as a photo-imageable dielectric (PID) resin. In this case, the first upper insulating layer 411B may further include an inorganic filler.

[0065] According to an embodiment, the first upper insulating layer 411B may include a photo-imageable dielectric (PID) resin, and the first seed layer SD1B as a base of the first redistribution pattern 420 may be formed by a sputtering process. The first seed layer SD1B may be formed to have a smaller line width than the case where the first seed layer SD1B is formed by electroless plating. When the first upper insulating layer 411B includes the PID resin, the first seed layer SD1B is correspondingly formed by a sputtering process, and therefore, the line width of the first seed layer SD1B formed by the sputtering process may be smaller than the line width of the first seed layer SD1B formed by electroless plating. Therefore, the line width of the first fine pattern FP1 of the first redistribution pattern 420 may be further refined.

[0066] The range of the first line width LW1B of the first fine pattern FP1 and the range of the second line width LW2 of the second fine pattern FP2 may be the same. The range of the first line interval LS1B of the first fine pattern FP1 and the range of the second line interval LS2 of the second fine pattern FP2 may be the same.

[0067] For example, the first line width LW1B of the first fine pattern FP1 may be equal to or less than 9 μm, and the first line spacing LS1B may be equal to or less than 12 μm, and similarly, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the first line width LW1B and the second line width LW2 may each be about 3 μm to about 9 μm, and the first line spacing LS1B and the second line spacing LS2 may each be about 3 μm to about 12 μm. Alternatively, the first line width LW1B and the second line width LW2 of the first fine pattern FP1 may be equal to or less than 5 μm, and the first line spacing LS1B and the second line spacing LS2 of the second fine pattern FP2 may each be equal to or less than 5 μm.

[0068] Therefore, in the semiconductor package 1A according to the embodiment, the fine pattern of the second package substrate 400 corresponding to the post-redistribution layer may be further refined, thereby improving the performance of the semiconductor package 1A.

[0069] Figure 3 is a cross-sectional view of a semiconductor package 2 according to the embodiment. Figure 4 2A is a cross-sectional view of a semiconductor package 2A according to an embodiment. Descriptions of elements similar to those described above may be omitted.

[0070] Reference Figure 3 The semiconductor package 2 according to the embodiment may further include a semiconductor package mounted on a reference Figure 1 The upper semiconductor device 500 on the semiconductor package 1 is described. That is, the semiconductor package 2 may be a package-on-package type package in which the upper semiconductor device 500 corresponding to the upper package is stacked or attached to the semiconductor package 1 corresponding to the lower package.

[0071] The upper semiconductor device 500 may be electrically connected to the upper package substrate 400 through the upper connection terminal 540. The upper connection terminal 540 may be formed of or include at least one of a conductive material such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). In addition to a spherical shape, the shape of the upper connection terminal 540 may be changed to various forms such as a pad, a bump, a column, or a pin.

[0072] The upper semiconductor device 500 may be a semiconductor package including at least one semiconductor chip. At least one of the semiconductor chips included in the upper semiconductor device 500 may include a memory chip, a logic chip, a system on chip (SoC), a power management integrated circuit (PMIC) chip, and a radio frequency integrated circuit (RFIC) chip. The memory chip may include a DRAM chip, an SRAM chip, an MRAM chip, a NAND flash memory chip, and / or a high bandwidth memory (HBM) chip. The logic chip may include an application processor (AP), a microprocessor, a central processing unit (CPU), a controller, and / or an application specific integrated circuit (ASIC). For example, the SoC may include at least two of a logic circuit, a memory circuit, a digital integrated circuit (IC), an RFIC, and an input / output circuit.

[0073] Reference Figure 4 The semiconductor package 2A according to the embodiment may further include a semiconductor package mounted on a reference Figure 2 The upper semiconductor device 500 on the semiconductor package 1A is described. That is, the semiconductor package 2A may be a package on package type package in which the upper semiconductor device 500 corresponding to the upper package is stacked or attached to the semiconductor package 1A corresponding to the lower package.

[0074] Figure 5 is a flowchart for explaining a semiconductor package manufacturing method S1 according to an embodiment. Figure 6 is a flowchart for explaining the semiconductor package manufacturing method S1 according to the embodiment in more detail.

[0075] Reference Figure 5 According to the embodiment, the semiconductor package manufacturing method S1 may include: forming a first process structure including a lower package substrate, a first semiconductor device, a core layer and an encapsulation material (S100); forming a first upper redistribution layer including a first upper insulating layer, a first upper via pattern and a first upper line pattern (S200A and S200B); and forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern and a second upper insulating layer (S300). Steps S200A and S200B are respectively Figure 6 and Fig. 9 is shown in more detail in .

[0076] Figure 6 is a flowchart illustrating in more detail operation S200A of forming a first upper redistribution layer including a first upper insulating layer, a first upper via pattern, and a first upper line pattern, and operation S300 of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer.

[0077] Reference Figure 6, operation S200A of forming a first upper redistribution layer may include: forming a first upper insulating layer including a build-up material on the encapsulation material (S210A); forming a plurality of first upper through holes by recessing a portion of the encapsulation material, the plurality of first upper through holes passing through the first upper insulating layer, and exposing a portion of the core layer through the plurality of first upper through holes (S220); forming a first seed layer using an electroless plating process (S230A); and forming a plurality of first upper via patterns and a plurality of first upper line patterns on the plurality of first upper through holes (S240).

[0078] Operation S300 of forming a second upper redistribution layer may include: forming a second upper insulating layer including a PID on the first upper redistribution layer (S310); forming a plurality of second upper through holes passing through the second upper insulating layer (S320); forming a second seed layer using a sputtering process (S330); forming a liquid photoresist layer on the second upper insulating layer (S340); and forming a plurality of second upper via patterns and a plurality of second upper line patterns in the plurality of second upper through holes (S350).

[0079] Will refer to Figure 5 and Figure 6 and the following description 7A to 7F and FIG. 8A to FIG. 8J A semiconductor package manufacturing method S1 according to an embodiment will be described.

[0080] 7A to 7F 1 is a cross-sectional view for explaining a semiconductor package manufacturing method S1 according to an embodiment. 7A to 7F The described operations may correspond to operation S100 of forming a first process structure including a lower package substrate, a first semiconductor device, a core layer, and an encapsulation material.

[0081] Reference Fig. 7A , the core layer 100 having the through hole CA may be disposed on the adhesive tape carrier TC. The core insulating layer 110 may include an insulating material or a resin, and may be a multilayer substrate including a plurality of layers, as described above. The core layer 100 may include a core wiring layer 121 disposed between adjacent layers among the plurality of layers of the core insulating layer 110, and disposed on at least a portion of the upper and lower surfaces of the plurality of layers of the core insulating layer 110.

[0082] Reference Figure 7B The semiconductor chip 200 and the connection pads 220 disposed on the lower surface of the semiconductor chip 200 may face the adhesive tape carrier TC and may be disposed in the through holes CA formed in the core insulating layer 110 so that the active surface of the semiconductor chip 200 faces the adhesive tape carrier TC.

[0083] Reference Figure 7CThe encapsulation material 130 may be formed around the semiconductor chip 200 and around a portion of the side surface and a portion of the upper surface of the core insulating layer 110. The encapsulation material 130 may be formed, and a planarization portion may be separately formed on an upper surface of the encapsulation material 130.

[0084] Reference Fig.7D , the core wiring layer 121, the core insulating layer 110, and the semiconductor chip 200 disposed on the adhesive tape carrier TC may be disposed on the first carrier CR1 so that the upper surface of the semiconductor chip 200 faces the first carrier CR1. A first adhesive layer CF1 for attaching a process product may be disposed between the encapsulation material 130 and the first carrier CR1. The first adhesive layer CF1 may be a copper foil for attachment.

[0085] Reference Fig. 7E and Figure 7F , the adhesive tape carrier TC attached to the lower surface side of the semiconductor chip 200 having the connection pads 220 can be removed, and the lower package substrate 300 can be formed on the surface where the semiconductor chip 200, the encapsulation material 130 and the core insulating layer 110 are provided, which is the surface from which the adhesive tape carrier TC is removed.

[0086] The process of forming the lower package substrate 300 may be implemented by a redistribution process. That is, the lower package substrate 300 may be formed by alternately forming the lower via pattern 321 and the lower line pattern 322 included in the lower insulating layer 310 and the lower redistribution pattern 320. The process result located on the first adhesive layer CF1 may be referred to herein as a first process structure, and the process until the lower via pattern 321 and the lower line pattern 322 are formed on the first adhesive layer CF1. Figure 7F That is, the first process structure may include the semiconductor chip 200 , the core layer 100 , the encapsulation material 130 and the lower package substrate 300 .

[0087] FIG. 8A to FIG. 8J 1 is a cross-sectional view for explaining a semiconductor package manufacturing method S1 according to an embodiment. FIG. 8A to FIG. 8J The described operations may correspond to operation S200A of forming a first upper redistribution layer including a first upper insulating layer, a first upper via pattern, and a first upper line pattern, and operation S300 of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer. Specifically, FIG. 8A to FIG. 8D may correspond to operation S200A of forming a first upper redistribution layer, and FIG. 8E to FIG. 8J This may correspond to operation S300 of forming the second upper redistribution layer.

[0088] Reference Fig. 8A, the first process structure may be removed from the first carrier CR1 using the first adhesive layer CF1, and the first process structure may be disposed on the second carrier CR2. A second adhesive layer CF2 for attaching the lower package substrate 300 to the second carrier CR2 may be disposed between the lower package substrate 300 and the second carrier CR2. Similar to the first adhesive layer CF1, the second adhesive layer CF2 may be a copper foil for attachment.

[0089] Reference Figure 8B , the first adhesive layer CF1 may be removed from the encapsulation material 130, and the first upper insulating layer 411A may be formed on the encapsulation material 130. According to an embodiment, as described above, the encapsulation material 130 may include a build-up material. The first upper insulating layer 411A may also include a build-up material. The encapsulation material 130 and the first upper insulating layer 411A may include the same build-up material, and for example, the encapsulation material 130 and the first upper insulating layer 411A may be configured to include an Ajinomoto build-up film (ABF). Figure 8B This may correspond to operation S210A of forming a first upper insulating layer including a build-up material on the encapsulation material.

[0090] A certain time passes after the encapsulation material 130 is formed, and thus, the build-up material included in the encapsulation material 130 may be hardened. On the other hand, a certain time does not pass after the first upper insulating layer 411A is formed, and thus, the first upper insulating layer 411A may not be completely hardened.

[0091] As follows Fig.8D As described above, when the first seed layer SD1A is formed by electroless plating, the first seed layer SD1A is formed before the first upper insulating layer 411A is completely hardened, and thus, adhesion between the first seed layer SD1A and the first upper insulating layer 411A may be greater than a case where the first seed layer SD1A is formed on the encapsulation material 130. That is, the first redistribution pattern 420 based on the first seed layer SD1A may be more stably formed and may also be maintained in a stable state.

[0092] Reference Figure 8C , you can Figure 8B The first through hole 420R is formed in the process product of the present invention. The first through hole 420R may be formed to pass through the first upper insulating layer 411A and through a portion of the encapsulation material 130 to expose a portion of the core layer 100. The first through hole 420R may be formed by laser processing, but is not limited thereto. The first through hole 420R may be formed and a desmear process may be performed thereon. Figure 8C The plurality of first upper via holes may pass through the first upper insulating layer and expose a portion of the core layer through the plurality of first upper via holes, corresponding to operation S220 of forming a plurality of first upper via holes by recessing a portion of the encapsulation material.

[0093] Due to the characteristics of a process of forming the upper via hole, the first upper via hole pattern 421 may have a tapered shape whose horizontal width increases as it moves away from the lower package substrate 300 .

[0094] Reference Fig.8D , electroless plating may be performed to form a first seed layer SD1A. The first seed layer SD1A may be formed in the first through hole 420R and on the upper surface of the first upper insulating layer 411A. The first seed layer SD1A may conformally cover the bottom surface and sidewall of the first through hole 420R and the upper surface of the first upper insulating layer 411A. The first seed layer SD1A may be formed of a conductive material or include a conductive material. For example, the first seed layer SD1A may include one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti) and gold (Au). Then, a resist pattern having a guide opening may be formed on the first seed layer SD1A. The resist pattern may include a dry film resist (DFR). The guide opening is used to form a first redistribution pattern 420.

[0095] Fig.8D The first redistribution pattern 420 may be formed by performing electroless plating using the first seed layer SD1A as an electrode. As described above, the first redistribution pattern 420 may include a first upper via pattern 421, a first upper line pattern 422, and a first fine pattern FP1. The first upper via pattern 421 and the first upper line pattern 422 may be formed by a single process.

[0096] According to an embodiment, the first redistribution pattern 420 may be formed by a plating process such as an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP). AP, SAP, and MSAP are each additive processes for forming fine patterns, and the three additive processes differ from each other in a method of forming a seed layer and a method of removing the seed layer. In SAP, an electroless copper layer may be used as a seed layer to plate a pattern, and the seed layer may be removed by rapid etching after the pattern is plated. MSAP refers to using a copper foil and an electroless copper layer as a seed layer, and removing the seed layer by rapid etching. Specifically, the first redistribution pattern 420 may be formed by SAP.

[0097] Then, the resist pattern may be removed, for example, by a stripping process. The first seed layer SD1A may be removed by an etching process having an etching selectivity to the first seed layer SD1A compared to the first redistribution pattern 420 . Fig.8D This may correspond to operation S230A of forming a first seed layer using an electroless plating process, and operation S240 of forming a plurality of first upper via patterns and a plurality of first upper line patterns in a plurality of first upper through holes.

[0098] Reference Fig. 8E , a second upper insulating layer 412 may be formed on a portion of the upper surface of the first upper insulating layer 411A and a portion of the upper surface of the first redistribution pattern 420. The second upper insulating layer 412 may be formed of or include an insulating material (e.g., PID resin). In this case, the second upper insulating layer 412 may further include an inorganic filler. For example, the second upper insulating layer 412 including the PID resin may be formed to be hardened, and the second through hole 430R may be formed by a photolithography process.

[0099] A sputtering process may be performed to form a second seed layer SD2. The second seed layer SD2 may be formed in the second through hole 430R and on the upper surface of the second upper insulating layer 412. The second seed layer SD2 may conformally cover the bottom surface and sidewall of the second through hole 430R and the upper surface of the second upper insulating layer 412. The second seed layer SD2 may be formed of a conductive material or include a conductive material. For example, the second seed layer SD2 may include one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).

[0100] Fig. 8E This may correspond to operation S320 of forming a plurality of second upper via holes passing through the second upper insulating layer and operation S330 of forming the second seed layer SD2 using a sputtering process.

[0101] Reference Figure 8F , a resist layer (e.g., resist layer) RL for plating may be formed on a portion of the upper surface of the second seed layer SD2 formed on the second upper insulating layer 412. For example, the resist layer RL for plating may be a liquid photoresist layer. The resist layer RL for plating may be formed to have a guide opening. The guide opening may be used as a guide for later forming the second redistribution pattern 430. The guide opening may be located on the second through hole 430R. That is, at least a portion of the upper surface of the second seed layer SD2 may be exposed through the guide opening.

[0102] Figure 8F This may correspond to operation S340 of forming a liquid photoresist layer on the second upper insulating layer.

[0103] Reference Figure 8G, a second redistribution pattern 430 may be formed on the guide opening of the resist layer RL for plating and the second through hole 430R by plating. The second redistribution pattern 430 may include a second upper via pattern 431, a second upper line pattern 432, and a second fine pattern FP2. The second upper via pattern 431 may be formed by plating the second through hole 430R, and the second upper line pattern 432 may be formed by filling the guide opening of the resist layer RL for plating. Figure 8G This may correspond to operation S350 of forming a plurality of second upper via patterns and a plurality of second upper line patterns on the plurality of second upper through holes.

[0104] As described above, the line width of the second seed layer SD2 may be smaller than the line width of the first seed layer SD1A.

[0105] Therefore, the line width of the second fine pattern FP2 of the second redistribution pattern 430 may be equal to or less than the line width of the first fine pattern FP1 of the first redistribution pattern 420. For example, the first line width LW1A and the first line spacing LS1A of the first fine pattern FP1 are respectively equal to or greater than the second line width LW2 and the second line spacing LS2 of the second fine pattern FP2. The first line width LW1A of the first fine pattern FP1 may be equal to or less than 10 μm, the first line spacing LS1A may be equal to or less than 13 μm, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 5 μm, and the second line spacing LS2 may be equal to or less than 5 μm.

[0106] Therefore, in the semiconductor package manufacturing method S1 according to the embodiment, the fine pattern of the second package substrate 400 corresponding to the post redistribution layer may be refined by materials and processes, thereby improving the semiconductor package manufactured by the semiconductor package manufacturing method S1.

[0107] Reference Figure 8H , the resist layer RL for plating may be stripped and removed, and the second seed layer SD2 on the upper surface of which the second redistribution pattern 430 is not formed may be removed. The second seed layer SD2 may be removed by an etching process having an etching selectivity to the second seed layer SD2 compared to the second redistribution pattern 430. Fig.8I, a metal plating layer 433 may be provided on an upper surface of a portion of the second upper line pattern 432. The metal plating layer 433 may be formed of or include a metal, and the metal includes, for example, gold (Au). Thereafter, an upper passivation layer 440 may be formed with a third hole 440R on an upper surface of the second upper insulating layer 412. The upper passivation layer 440 may protect the upper package substrate 400. The upper passivation layer 440 may be formed of or include an insulating material (e.g., a build-up material), but is not limited thereto.

[0108] Reference Figure 8J , the second carrier CR2 and the second adhesive layer CF2 for attaching the second carrier CR2 may be removed. At least a portion of the lower line pattern 322 may be exposed through the opening of the lower passivation layer 350, and the lower pad 330 may be provided on the exposed lower line pattern 322. The external connection terminals 340 may be electrically connected to the lower pads 330, respectively. The semiconductor package 1 according to the embodiment may be manufactured by the semiconductor package manufacturing method S1 described above.

[0109] Fig. 9 is a flowchart for explaining the semiconductor package manufacturing method S1 according to the embodiment in more detail.

[0110] Fig. 9 is a flowchart illustrating in more detail operation S200B of forming a first upper redistribution layer including a first upper insulating layer, a first upper via pattern, and a first upper line pattern, and operation S300 of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer.

[0111] Reference Fig. 9 , operation S200B of forming a first upper redistribution layer may include: forming a first upper insulating layer including a PID on an encapsulation material (S210B); forming a plurality of first upper through holes by recessing a portion of the first encapsulation material, the plurality of first upper through holes passing through the first upper insulating layer, and exposing a portion of the core layer through the plurality of first upper through holes (S220); forming a first seed layer using a sputtering process (S230B); and forming a plurality of first upper via patterns and a plurality of first upper line patterns on the plurality of first upper through holes (S240).

[0112] Operation S300 of forming a second upper redistribution layer may include: forming a second upper insulating layer including a PID on the first upper redistribution layer (S310); forming a plurality of second upper through holes passing through the second upper insulating layer (S320); forming a second seed layer using a sputtering process (S330); forming a liquid photoresist layer on the second upper insulating layer (S340); and forming a plurality of second upper via patterns and a plurality of second upper line patterns in the plurality of second upper through holes (S350).

[0113] Will refer to Fig. 9 and FIG. 10A to FIG. 10J A semiconductor package manufacturing method S1 according to an embodiment is described.

[0114] FIG. 10A to FIG. 10J 1 is a cross-sectional view for explaining a semiconductor package manufacturing method S1 according to an embodiment. FIG. 10A to FIG. 10J The described operations may correspond to operation S200B of forming a first upper redistribution layer including a first upper insulating layer, a first upper via pattern, and a first upper line pattern, and operation S300 of forming a second upper redistribution layer including a second upper line pattern, a second upper via pattern, and a second upper insulating layer.

[0115] Specifically, FIG. 10A to FIG. 10D may correspond to operation S200B of forming a first upper redistribution layer, and FIG. 10E to FIG. 10J This may correspond to operation S300 of forming the second upper redistribution layer.

[0116] Reference Fig. 10A , the first process structure may be removed from the first carrier CR1 using the first adhesive layer CF1, and the first process structure may be disposed on the second carrier CR2. The second adhesive layer CF2 may be disposed between the lower package substrate 300 and the second carrier CR2.

[0117] Reference Fig. 10B , the first adhesive layer CF1 may be removed from the encapsulation material 130, and a first upper insulating layer 411B may be formed on the encapsulation material 130. Figure 8B Differently, the first upper insulating layer 411B may be formed of or include an insulating material (eg, PID resin). In this case, the first upper insulating layer 411B may further include an inorganic filler. Fig. 10B This may correspond to operation S210B of forming a first upper insulating layer including a PID on the encapsulation material 130 .

[0118] Reference Fig. 10C , you can Fig. 10B The first through hole 420R is formed in the process product of the present invention. The first through hole 420R may be formed to pass through the first upper insulating layer 411B and through a portion of the encapsulation material 130 to expose a portion of the core layer 100. For example, the first upper insulating layer 411B including the PID resin may be formed to be hardened, and the second through hole 430R may be formed by a photolithography process. Fig. 10C The plurality of first upper via holes may pass through the first upper insulating layer and expose a portion of the core layer through the plurality of first upper via holes, corresponding to operation S220 of forming a plurality of first upper via holes by recessing a portion of the first encapsulating material.

[0119] Due to the characteristics of a process of forming the upper via hole, the first upper via hole pattern 421 may have a tapered shape whose horizontal width increases as it moves away from the lower package substrate 300 .

[0120] Reference Fig. 10D , a sputtering process may be performed to form a first seed layer SD1B. The first seed layer SD1B may be formed in the first through hole 420R and on the upper surface of the first upper insulating layer 411B. The first seed layer SD1B may conformally cover the bottom surface and sidewall of the first through hole 420R and the upper surface of the first upper insulating layer 411B. The first seed layer SD1B may be formed of or include a conductive material. For example, the first seed layer SD1B may include one or more materials selected from the group consisting of copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), chromium (Cr), titanium (Ti), and gold (Au).

[0121] The first redistribution pattern 420 may be formed on the first seed layer SD1B. According to an embodiment, the first redistribution pattern 420 may be formed by a plating process such as an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP). Specifically, the first redistribution pattern 420 may be formed of SAP.

[0122] The line width of the first seed layer SD1B formed by the sputtering process may be smaller than the line width of the first seed layer formed by the electroless plating. Therefore, the line width of the first fine pattern FP1 of the first redistribution pattern 420 may be further refined.

[0123] As an example, the first line width LW1B of the first fine pattern FP1 may be equal to or less than 9 μm, and the first line spacing LS1B may be equal to or less than 12 μm, and similarly, the second line width LW2 of the second fine pattern FP2 may be equal to or less than 9 μm, and the second line spacing LS2 may be equal to or less than 12 μm. Alternatively, the first line width LW1B and the second line width LW2 of the first fine pattern FP1 may be equal to or less than 5 μm, and the first line spacing LS1B and the second line spacing LS2 may be equal to or less than 5 μm.

[0124] Therefore, in the semiconductor package manufacturing method S1 according to the embodiment, the circuit of the second package substrate 400 corresponding to the rear redistribution layer may be refined, thereby improving the performance of the semiconductor package manufactured by the semiconductor package manufacturing method S1.

[0125] Fig. 10D This may correspond to operation S230B of forming a first seed layer using a sputtering process and operation S240 of forming a plurality of first upper via patterns and a plurality of first upper line patterns in the plurality of first upper through holes.

[0126] FIG. 10E to FIG. 10J and FIG. 8E to FIG. 8J The operations are basically the same, so separate descriptions are omitted.

[0127] The semiconductor package 1A according to the embodiment may be manufactured by the semiconductor package manufacturing method S1 described above.

[0128] Those skilled in the art will appreciate that the above-mentioned inventive concept can be practiced in other specific forms without changing its technical ideas or basic features. Therefore, it should be understood that the above-mentioned embodiments are illustrative and non-restrictive in all aspects.

[0129] As used herein, terms such as "same," "equal," "planar," "coplanar," "parallel," and "perpendicular" encompass identity or near identity, including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0130] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a lower packaging substrate, including a lower insulating layer; A first semiconductor device mounted on the lower package substrate; a core layer, on the lower package substrate, the core layer being laterally spaced apart from the first semiconductor device and comprising: a core substrate, core vias passing through the core substrate, and a core pattern connecting the core vias to each other; an encapsulation material surrounding the first semiconductor device and covering an upper portion of the core layer; and an upper packaging substrate, disposed on the encapsulation material, the upper packaging substrate comprising a first upper redistribution layer and a second upper redistribution layer, The first upper redistribution layer includes a first upper insulating layer and a first upper redistribution pattern on the first upper insulating layer. the second upper redistribution layer includes a second upper insulating layer on the first upper insulating layer and a second upper redistribution pattern on the second upper insulating layer, A first line width of a first fine pattern of the first upper redistribution pattern is greater than or equal to a corresponding second line width of a second fine pattern of the second upper redistribution pattern, and A first line pitch of the first fine pattern is greater than or equal to a corresponding second line pitch of the second fine pattern.

2. The semiconductor package according to claim 1, in, The first upper redistribution pattern includes a first upper via pattern and a first upper line pattern, the first upper via pattern passing through the first upper insulating layer, the first upper line pattern being on the first upper insulating layer and electrically connected to the first upper via pattern, and The first upper via patterns each penetrate the first upper insulating layer and the encapsulation material, and The first upper insulating layer and the encapsulation material each contact at least a portion of a side surface of each of the first upper via patterns.

3. The semiconductor package according to claim 2, in, The second upper redistribution pattern includes a second upper via pattern and a second upper line pattern, the second upper via pattern passing through the second upper insulating layer, the second upper line pattern being on the second upper insulating layer and electrically connected to the second upper via pattern, and The first upper via pattern and the second upper via pattern each have a tapered shape whose horizontal width increases as it moves away from the lower package substrate.

4. The semiconductor package according to claim 3, in, The first upper via pattern and the second upper via pattern each include a stacked via or a staggered via.

5. The semiconductor package according to claim 4, in, The first upper insulating layer includes a build-up layer material, and the second upper insulating layer includes a photo-imageable dielectric PID.

6. The semiconductor package according to claim 5, in, The first line width is about 5 μm to about 10 μm, and the first line spacing is about 5 μm to about 13 μm, and The second line width is about 3 μm to about 9 μm, and the second line spacing is about 3 μm to about 12 μm.

7. The semiconductor package according to claim 6, in, The first upper insulating layer and the encapsulation material include the same material.

8. The semiconductor package according to claim 3, in, The material of the lower insulating layer and the material of the second upper insulating layer are the same as each other, and The lower insulating layer and the second upper insulating layer each include a photoimageable dielectric PID.

9. The semiconductor package according to claim 3, in, Materials of the first upper insulating layer and the encapsulation material are different from each other, and the first upper insulating layer and the second upper insulating layer include the same material.

10. The semiconductor package according to claim 9, in, The encapsulating material comprises a build-up material, and The first upper insulating layer and the second upper insulating layer each include a photoimageable dielectric PID.

11. The semiconductor package according to claim 10, in, The first line width and the second line width are each about 3 μm to about 9 μm, and The first line pitch and the second line pitch are each about 3 μm to about 12 μm.

12. The semiconductor package according to claim 3, Also included is a second semiconductor device mounted on the upper package substrate.

13. The semiconductor package according to claim 3, in, The semiconductor package further includes a plurality of second upper redistribution layers stacked sequentially.

14. A method for manufacturing a semiconductor package, the method comprising: forming a first process structure, the first process structure comprising: a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate, and an encapsulation material surrounding the first semiconductor device on the lower package substrate, wherein the core layer is laterally spaced apart from the first semiconductor device, and the encapsulation material is on the core layer; forming a first upper redistribution layer, the first upper redistribution layer comprising: a first upper insulating layer on the encapsulation material of the first process structure, and a first upper redistribution pattern on the first upper insulating layer; and forming a second upper redistribution layer, the second upper redistribution layer comprising: a second upper insulating layer on the first upper redistribution layer, and a second upper redistribution pattern on the second upper insulating layer, Wherein, forming the first upper redistribution layer comprises: forming the first upper insulating layer on the encapsulation material; forming a plurality of first upper via holes by recessing a portion of the encapsulation material, the plurality of first upper via holes passing through the first upper insulating layer and exposing a portion of the core layer through the plurality of first upper via holes; forming a first seed layer on the first upper insulating layer having the plurality of first upper via holes; and forming a first upper via pattern in the plurality of first upper through holes, the first upper via pattern being electrically connected to the core layer, and forming a first upper line pattern on the first upper via pattern, Wherein, forming the second upper redistribution layer comprises: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper through holes passing through the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper through holes; forming a resist layer on the second upper insulating layer having the second seed layer formed thereon; and forming a second upper via hole pattern on the plurality of second upper through holes, and forming a second upper line pattern on the second upper via hole pattern, wherein the material of the first upper insulating layer and the material of the second upper insulating layer are different from each other, The first upper redistribution pattern and the second upper redistribution pattern are formed such that a first line width of a first fine pattern of the first upper redistribution pattern is greater than or equal to a corresponding second line width of a second fine pattern of the second upper redistribution pattern, The first upper redistribution pattern and the second upper redistribution pattern are formed such that a first line pitch of the first fine pattern is greater than or equal to a corresponding second line pitch of the second fine pattern, and The first seed layer is formed by electroless plating, and the second seed layer is formed using a sputtering process.

15. The method according to claim 14, in, The first upper insulating layer includes a build-up layer material, and the second upper insulating layer includes a photo-imageable dielectric PID.

16. The method according to claim 15, in, The first line width of the first fine pattern is about 5 μm to about 10 μm, and the first line spacing is about 5 μm to about 13 μm, and The second line width of the second fine pattern is about 3 μm to about 9 μm, and the second line spacing is about 3 μm to about 12 μm.

17. The method according to claim 16, in, The first upper redistribution pattern is formed using a semi-additive process (SAP), and The resist layer includes liquid photoresist LPR.

18. The method according to claim 15, wherein: The encapsulation material comprises a second build-up material, Wherein, forming the first upper redistribution layer comprises: before forming the first upper insulating layer, hardening the encapsulation material, and The first seed layer is formed on the first upper insulating layer before the first upper insulating layer is hardened.

19. A method for manufacturing a semiconductor package, the method comprising: forming a first process structure, the first process structure comprising: a lower package substrate, a first semiconductor device mounted on the lower package substrate, a core layer mounted on the lower package substrate, and an encapsulation material surrounding the first semiconductor device on the lower package substrate, the core layer being laterally spaced apart from the first semiconductor device, and the encapsulation material being on the core layer; forming a first upper redistribution layer, the first upper redistribution layer comprising: a first upper insulating layer on the encapsulation material of the first process structure, and a first upper redistribution pattern on the first upper insulating layer; and forming a second upper redistribution layer, the second upper redistribution layer comprising: a second upper insulating layer on the first upper redistribution layer, and a second upper redistribution pattern on the second upper insulating layer, Wherein, forming the first upper redistribution layer comprises: forming the first upper insulating layer on the encapsulation material; forming a plurality of first upper via holes by recessing a portion of the encapsulation material, the plurality of first upper via holes passing through the first upper insulating layer and exposing a portion of the core layer through the plurality of first upper via holes; forming a first seed layer on the first upper insulating layer having the plurality of first upper via holes; and forming a first upper via pattern in the plurality of first upper through holes, the first upper via pattern being electrically connected to the core layer, and forming a first upper line pattern on the first upper via pattern, Forming the second upper redistribution layer includes: forming a second upper insulating layer on the first upper redistribution layer; forming a plurality of second upper through holes passing through the second upper insulating layer; forming a second seed layer on the second upper insulating layer having the plurality of second upper through holes; forming a resist layer on the second upper insulating layer having the second seed layer formed thereon; and forming a second upper via hole pattern on the plurality of second upper through holes, and forming a second upper line pattern on the second upper via hole pattern, wherein the material of the first upper insulating layer and the material of the second upper insulating layer are the same as each other, and The first seed layer and the second seed layer are each formed using a sputtering process.

20. The method according to claim 19, in, The first upper insulating layer and the second upper insulating layer each include a photoimageable dielectric PID.

Images