Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor chip in which a pad is formed in a wafer state; a first passivation layer formed on the semiconductor chip to expose the pad, and a second passivation layer formed on the semiconductor chip to expose the pad; a first redistribution layer connected to the pad and extending on the first passivation layer; a conductive bump disposed on an electrical signal path leading to the pad, the first redistribution layer, and the substrate; and a capacitor formed to be electrically connected to the first redistribution layer at a wafer level prior to formation of the conductive bump.

Description

Technical Field

[0001] The following description relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device such as a wafer-level package (WLP) or a wafer-level chip-scale package (WLCSP) and a method for manufacturing the same. Background Art

[0002] As the operating voltage of semiconductor integrated circuits (ICs) decreases and the operating frequency increases, it is required to reduce power noise to ensure the normal operation of semiconductor ICs. In order to reduce power noise by reducing the impedance of the power delivery network (PDN) from an external substrate (e.g., a multilayer printed circuit board (PCB)) to the power input pad of the semiconductor IC or from the output pad of the semiconductor IC to the PDN connected to the application, a decoupling capacitor with low equivalent series resistance (ESR) and low equivalent series inductance (ESL) is used. As such a decoupling capacitor, a multilayer ceramic capacitor, a low inductance ceramic capacitor, or a three-dimensional (3D) silicon capacitor is used.

[0003] To minimize the impedance of the PDN, decoupling capacitors are usually placed near the input node (input pad), power node (power pad), or output node (output pad). Figure 1 As shown in the example of , the decoupling capacitor is arranged to minimize the length A as much as possible.

[0004] FIG. 2 is a set of diagrams showing a structure in which a decoupling capacitor is provided according to the related art. Figure 2A A structure is shown in which a decoupling capacitor DCAP is disposed on one side of a semiconductor chip die attachment of a package between two sides of a multi-layer PCB substrate (die-side capacitor). Figure 2B A structure is shown in which a decoupling capacitor DCAP is disposed in a multi-layer PCB substrate (ie, one layer among multiple layers of the multi-layer PCB substrate) (PCB embedded capacitor). Figure 2C A structure is shown in which a decoupling capacitor DCAP is disposed on the unattached side of the semiconductor chip die of the package between two sides of a multi-layer PCB substrate (pin side capacitor).

[0005] All PDNs between the semiconductor chip die and the die side capacitors, PCB embedded capacitors, and pin side capacitors exist in the multi-layer PCB substrate of FIG2. Therefore, due to the influence of the interconnection of the multi-layer PCB substrate, the impedance of the PDN increases, and the impedance of the bumps of the semiconductor chip die made of conductive material is also affected, limiting the reduction of the power noise applied to the semiconductor chip die. In addition, the resistance of the PDN is a factor that causes the voltage applied to the semiconductor chip die to drop. Summary of the invention

[0006] The present invention is directed to providing a semiconductor device having improved impedance characteristics and power noise reduction characteristics compared with the related art.

[0007] According to one aspect of the present invention, a semiconductor device is provided, which includes: a semiconductor chip in which a pad is formed in a wafer state; a first passivation layer formed on the semiconductor chip to expose the pad; a first redistribution layer connected to the pad and extending on the first passivation layer; a conductive bump arranged on an electrical signal path leading to the pad, the first redistribution layer and a substrate; and a capacitor formed to be electrically connected to the first redistribution layer at a wafer level before the conductive bump is formed.

[0008] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first passivation layer on a semiconductor chip to expose a pad formed in the semiconductor chip; forming a first redistribution layer connected to the pad and extending on the first passivation layer; forming a capacitor to be electrically connected to the first redistribution layer at a wafer level; and after forming the capacitor, forming a conductive bump on an electrical signal path leading to the pad, the first redistribution layer and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0010] Figure 1 is a set of diagrams showing a power delivery network (PDN) of a semiconductor integrated circuit (IC) according to the related art;

[0011] FIG. 2A to FIG. 2C is a diagram showing a structure in which a decoupling capacitor is provided according to the related art;

[0012] Figure 3is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

[0013] 4A to 4H is a cross-sectional view showing each operation of the method of manufacturing a semiconductor device according to the first exemplary embodiment of the present invention;

[0014] FIG. 5A to FIG. 5J is a cross-sectional view illustrating each operation of a method of manufacturing a semiconductor device according to a second exemplary embodiment of the present invention;

[0015] FIG. 6A to FIG. 6J is a cross-sectional view illustrating each operation of a method of manufacturing a semiconductor device according to a third exemplary embodiment of the present invention; and

[0016] Fig. 7A and Figure 7B is a diagram showing the structure of a semiconductor device in which a capacitor is provided according to the present invention.

[0017] Throughout the drawings and detailed description, unless otherwise described or provided, the same reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative sizes, proportions, and descriptions of the elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0018] The following detailed description is provided to help the reader fully understand the methods, devices and / or systems described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to those set forth herein, but may be changed, which will be apparent after understanding the disclosure of the present application, except for operations that must occur in a specific order.

[0019] The features described herein may be embodied in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0020] With reference to the embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the embodiments disclosed herein, but will be implemented in various forms. The embodiments of the present disclosure are provided in order to fully disclose the present disclosure, and those of ordinary skill in the art can fully understand the scope of the present disclosure. The present disclosure will only be defined by the scope of the attached claims. At the same time, the terms used in this specification are to explain the embodiments, not to limit the present disclosure.

[0021] Terms such as first, second, A, B, (a), (b) and the like may be used herein to describe components. Each of these terms is not used to define the nature, order or sequence of the corresponding component, but is only used to distinguish the corresponding component from other components. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component.

[0022] Throughout this specification, when a component is described as being “connected to” or “coupled to” another component, it may be directly “connected to” or “coupled to” another component, or one or more other components may be present in between. Conversely, when an element is described as being “directly connected to” or “directly coupled to” another element, there may not be other components in between.

[0023] Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms as well. It should be further understood that the terms "include" and / or "comprise" when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0024] For ease of description, spatially relative terms such as "above," "upper," "below," and "lower" may be used herein to describe the relationship of one element to another, as shown in the figures. In addition to the orientations depicted in the figures, such spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, an element described as "above" or "upper" relative to another element will then be "below" or "lower" relative to the other element. Therefore, the term "above" includes both above and below orientations, depending on the spatial orientation of the device. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0025] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include plural forms as well. The terms "comprise", "include" and "have" specify the presence of stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0026] Due to manufacturing techniques and / or tolerances, the shapes shown in the drawings may vary. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shapes that occur during manufacturing.

[0027] After understanding the disclosure of the present application, the features of the examples described herein can be combined in various ways, which will be apparent. In addition, although the examples described herein have multiple configurations, after understanding the disclosure of the present application, other configurations are also possible, which will be apparent.

[0028] Figure 3 is a flowchart illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0029] refer to Figure 3 , the method for manufacturing a semiconductor device according to the exemplary embodiment may include: an operation S110 of preparing a semiconductor chip 10 in which a pad BP is formed in a wafer state; an operation S120 of forming a first passivation layer 20 on the semiconductor chip 10 to expose the pad BP formed in the semiconductor chip 10; an operation S130 of forming a first redistribution layer 30 connected to the pad BP and extending on the first passivation layer 20; an operation S140 of forming a capacitor DCAP to be electrically connected to the first redistribution layer 30 at a wafer level; an operation S150 of forming a conductive bump B on an electrical signal path leading to the pad BP, the first redistribution layer 30 and a printed circuit board (PCB) substrate after forming the capacitor DCAP; and an operation S160 of cutting the semiconductor chip 10 in a wafer state after forming the conductive bump P. The capacitor DCAP may be a decoupling capacitor (e.g., a multilayer ceramic capacitor (MLCC), a low inductance ceramic capacitor (LICC), or a three-dimensional (3D) capacitor) configured to reduce the impedance of an electrical signal connected to the pad BP, the first redistribution layer 30, and the PCB substrate.

[0030] A wafer-level package (WLP) may be manufactured through operations S110 to S150, and a plurality of chip-scale packages (CSP) may be manufactured through a process of cutting the WLP in operation S160. Therefore, the semiconductor device to be manufactured in the present invention may be a WLP or a CSP.

[0031] According to the three embodiments, the present invention proposes three manufacturing processes according to the design specifications of the semiconductor device to be manufactured. The method of manufacturing the semiconductor device according to each embodiment will be described in detail below.

[0032] 1. First Exemplary Embodiment

[0033] 4A to 4H 1 are cross-sectional views illustrating each operation of the method of manufacturing the semiconductor device according to the first exemplary embodiment of the present invention.

[0034] refer to Figure 4A First, a semiconductor chip 10 is provided, in which a pre-designed circuit is integrated in a wafer state (S110). In this embodiment, the semiconductor chip 10 is a chip manufactured in a fabrication facility (FAB), and is therefore defined as including a die passivation layer (not shown) for protecting the circuit integrated in the semiconductor chip 10 (the die passivation layer may be implemented using silicon dioxide (SiO2), silicon nitride (SiN), or a stacked structure of silicon dioxide and silicon nitride). In the semiconductor chip 10, a plurality of pads BP serving as paths for electrical input and output of power supplies and circuits are formed to be exposed on one side of the active surface AS of the semiconductor chip 10 through pad openings. The die passivation layer is formed to expose the pads BP on one side of the active surface AS. As Figure 4A As shown, among the plurality of pads BP formed in the semiconductor chip 10, the pads concerned in this embodiment are defined as a first pad BP1 and a second pad BP2. For example, the first pad BP1 may be a pad for inputting power (e.g., VCC), and the second pad BP2 may be a pad for inputting ground GND.

[0035] Then, if Figure 4BAs shown, a first passivation layer 20 is formed on the semiconductor chip 10 to expose the pad BP (S120). In operation S120, the first passivation layer 20 is formed on the active surface AS of the semiconductor chip 10, and the active surface AS of the semiconductor chip 10 is coated with a photoresist except for the region where the pad BP is formed (all or some of the regions where the pad BP is formed). Thereafter, the photoresist is exposed and developed to expose the pad BP on one side of the active surface AS of the semiconductor chip 10. The first passivation layer 20 can be implemented using a photosensitive polymer or a polyimide material (this is the same for the second passivation layer 40 and the third passivation layer 60 to be described below).

[0036] Then, if Figure 4C As shown, the first redistribution layer 30 is formed to be connected to the pad BP and to extend on the first passivation layer 20 (S130). In other words, the first redistribution layer 30 is formed to be connected to the pad BP through the area where the pad BP is exposed through the first passivation layer 20, and to extend on the first passivation layer 20. The first redistribution layer 30 serves as a layer for rearranging the pad BP, and may be implemented using a conductive material such as copper (Cu). As is well known, the first redistribution layer 30 having a target layout may be formed by a seed layer forming process, an electroplating process, and a seed layer etching process. As shown in FIG. Figure 4C As shown, a portion of the first redistribution layer 30 connected to the first pad BP1 is defined as a first redistribution line 31, and a portion of the first redistribution layer 30 connected to the second pad BP2 is defined as a second redistribution line 32. Figure 4C As shown, an additional redistribution line 33 for rearranging an additional pad (not shown) may be formed in operation S130.

[0037] Then, if Figure 4D As shown, the second passivation layer 40 is formed on the first passivation layer 20 and the first redistribution layer 30 to expose at least a portion of the first redistribution layer 30 (S135A). In operation S135A, the second passivation layer 40 is formed to cover the first passivation layer 20 and the first redistribution layer 30, and the entire area except for the area where the conductive member 70 to be described below is to be formed is coated with a photoresist, and then the photoresist is exposed and developed to expose at least a portion of the first redistribution layer 30 on one side of the active surface AS of the semiconductor chip 10.

[0038] Then, if Figure 4EAs shown, a conductive member 70 is formed by an electroplating process in a region where the first redistribution layer 30 is exposed through the second passivation layer 40 (S135B). The conductive member 70 may be an Under-Bump Metal (UBM), which is provided to facilitate welding of the conductive bump B and the capacitor DCAP, which is to be described below. In order to clearly distinguish the terms, a conductive member on which a first conductive bump B1 to be described below is formed is defined as a first conductive member 71, a conductive member on which a second conductive bump B2 to be described below is formed is defined as a second conductive member 72, a conductive member connected to a first power input pad of the capacitor DCAP to be described below is defined as a third conductive member 73, and a conductive member connected to a second power input pad of the capacitor DCAP is defined as a fourth conductive member 74. The first conductive member 71 and the third conductive member 73 are electrically connected through the first redistribution line 31, and the second conductive member 72 and the fourth conductive member 74 are electrically connected through the second redistribution line 32. An additional conductive member 75 may also be formed on the additional redistribution line 33 described above. The first conductive member 71 and the second conductive member 72 and the third conductive member 73, the fourth conductive member 74, and the additional conductive member 75 may be formed by the same process in operation S135B. However, the first conductive member 71 and the second conductive member 72 may have different physical characteristics (e.g., thickness) from the third conductive member 73, the fourth conductive member 74, and the additional conductive member 75. The first conductive member 71 and the second conductive member 72 may have the same physical characteristics, and the third conductive member 73, the fourth conductive member 74, and the additional conductive member 75 may have the same physical characteristics (this is the same in the third exemplary embodiment to be described below).

[0039] Then, if Figure 4FAs shown, the capacitor DCAP is formed to be electrically connected to the first redistribution layer 30 at the wafer level (S140). The term "at the wafer level" means that the capacitor DCAP is formed in the WLP, rather than in the PCB substrate to which the packaged semiconductor chip 10 of the embodiment is attached. The capacitor DCAP may have a plurality of power input pads, for example, a first power input pad (for example, a VCC pad) and a second pad (for example, a GND pad). Therefore, in operation S140, the capacitor DCAP is mounted on the semiconductor chip 10 so that the solder cap of the bump (for example, a copper pillar bump) DCAP_B formed on the first power input pad of the capacitor DCAP contacts the third conductive member 73 electrically connected to the first redistribution line 31, and the solder cap of the bump (for example, a copper pillar bump formed on the second power input pad of the capacitor DCAP) DCAP_B contacts the fourth conductive member 74 electrically connected to the second redistribution line 32, and then a reflow process is performed to solder the capacitor DCAP to the third conductive member 73 and the fourth conductive member 74. When the capacitor DCAP has an additional power input pad, the additional power input pad of the capacitor DCAP may be formed to contact the additional conductive member 75 electrically connected to the additional redistribution line 33. In this manner, the first and second redistribution lines 31 and 32 and the additional redistribution line 33 are configured to function as a multi-node of the capacitor DCAP.

[0040] Then, if Figure 4G As shown, a conductive bump B is formed on an electrical signal path leading to the pad BP, the first redistribution layer 30, and a PCB substrate (not shown) to which the packaged semiconductor chip 10 (i.e., WLP) is to be attached (S150). When the electrical signal path leading to the first pad BP1, the first redistribution line 31, the first conductive member 71, and the PCB substrate is defined as a first electrical signal path, and the electrical signal path leading to the second pad BP2, the second redistribution line 32, the second conductive member 72, and the PCB substrate is defined as a second electrical signal path, the conductive bump B may include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Therefore, in operation S150, the first conductive bump B1 and the second conductive bump B2 are mounted on the semiconductor chip 10 so that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first redistribution line 31, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second redistribution line 32, and then a reflow process is performed to solder the first conductive bump B1 and the second conductive bump B2 to the first conductive member 71 and the second conductive member 72, respectively.

[0041] Meanwhile, the drawings of the embodiment show a structure in which the first redistribution line 31 is electrically connected to the first conductive bump B1 and the second redistribution line 32 is electrically connected to the second conductive bump B2, but in addition to the first conductive bump B1 and the second conductive bump B2, another conductive bump (a plurality of conductive bumps) may be provided in the embodiment. Therefore, the first redistribution line 31 or the second redistribution line 32 may be configured to be electrically connected to an additional conductive bump in addition to the first conductive bump B1 or the second conductive bump B2.

[0042] although Figure 4G An example in which the conductive bump B is implemented as a solder bump is shown, but according to the embodiment, the conductive bump B may be implemented as Figure 4H In other words, when the semiconductor chip 10 has high power consumption and requires a high operating voltage and a small number of input pads and output pads, it is preferred to apply relatively large-sized solder bumps, and when the semiconductor chip 10 has low power consumption and requires a low operating voltage and a large number of input pads and output pads, it is preferred to apply relatively small-sized copper pillar bumps.

[0043] A WLP (particularly a fan-in WLP) may be manufactured through operations S110 to S150. Specifically, the capacitor DCAP is electrically connected to a first electrical signal path (e.g., a VCC power input path) and a second electrical signal path (e.g., a ground path) through the first redistribution layer 30 to reduce the impedance of the first electrical signal path and the second electrical signal path. Therefore, improved impedance characteristics and power noise reduction characteristics may be obtained.

[0044] Meanwhile, after operation S150 , operation S160 of cutting the semiconductor chip 10 in a wafer state into a plurality of CSPs may be additionally performed.

[0045] 2. Second Exemplary Embodiment

[0046] FIG. 5A to FIG. 5J are cross-sectional views illustrating each operation of a method of manufacturing a semiconductor device according to the second exemplary embodiment of the present invention.

[0047] In the process of manufacturing the WLP, multiple redistribution layers may be required to rearrange the pads depending on the number of pads and the total layout area of ​​the semiconductor chip 10. The second exemplary embodiment focuses on a structure in which the capacitor DCAP is formed in the passivation layer and a process for forming the capacitor DCAP in the passivation layer when the WLP is configured to include multiple redistribution layers. The detailed description of the same structure and process as the first exemplary embodiment will be omitted, and the structure and process different from the first exemplary embodiment will be described. The same process and structure as the first exemplary embodiment will be indicated by the same reference numerals as the first exemplary embodiment.

[0048] refer to Figure 5A First, a semiconductor chip 10 in a wafer state is provided (S110). In the semiconductor chip 10, first and second pads BP1 and BP2 as paths for power supply and electrical input and output of a circuit are formed to be exposed on one side of an active surface AS of the semiconductor chip 10 through a pad opening.

[0049] Then, if Figure 5B As shown, a first passivation layer 20 is formed on the semiconductor chip 10 to expose the pads BP (S120). In operation S120, the first passivation layer 20 is formed on the semiconductor chip 10 to expose the first and second pads BP1 and BP2 on one side of the active surface AS of the semiconductor chip 10.

[0050] Then, if Figure 5C As shown, the first redistribution layer 30 is formed to be connected to the pad BP and to extend on the first passivation layer 20 (S130). A portion of the first redistribution layer 30 connected to the first pad BP1 is defined as a first redistribution line 31, and a portion of the first redistribution layer 30 connected to the second pad BP2 is defined as a second redistribution line 32. In addition, as shown in FIG. Figure 5C As shown, an additional redistribution line 33 for rearranging an additional pad (not shown) may be formed in operation S130.

[0051] Then, if Figure 5D As shown, the capacitor DCAP is formed to be electrically connected to the first redistribution layer 30 at the wafer level (S140). In operation S140, the capacitor DCAP may be formed to contact the first redistribution layer 30 by a surface mounting (SMT) process. Therefore, the first power input pad and the second power input pad of the capacitor DCAP are formed to contact the first redistribution line 31 and the second redistribution line 32, respectively. When the capacitor DCAP has an additional power input pad, the additional power input pad of the capacitor DCAP may be formed to contact the additional redistribution line 33 described above. In this way, the first redistribution line 31 and the second redistribution line 32 and the additional redistribution line 33 are configured to serve as a multi-node of the capacitor DCAP.

[0052] Then, if Figure 5EAs shown, a second passivation layer 40 is formed on the first passivation layer 20 and the first redistribution layer 30 (S145A). In operation S145A, the second passivation layer 40 is formed to cover the first passivation layer 20, the first redistribution layer 30, and the capacitor DCAP, and the entire area except for the area where the second redistribution layer 50 to be described below will be formed is coated with a photoresist, and then the photoresist is exposed and developed to expose at least a portion of the first redistribution layer 30 on one side of the active surface AS of the semiconductor chip 10.

[0053] Then, if Fig. 5F As shown, a second redistribution layer 50 is formed in a region where the first redistribution layer 30 is exposed through the second passivation layer 40 (S145B). A portion of the second redistribution layer 50 connected to the first redistribution line 31 is defined as a third redistribution line 51, and a portion of the second redistribution layer 50 connected to the second redistribution line 32 is defined as a fourth redistribution line 52. Fig. 5F As shown, the third redistribution line 51 and the fourth redistribution line 52 may have portions extending on the second passivation layer 40 .

[0054] Then, if Figure 5G As shown, a third redistribution layer 60 is formed on the second passivation layer 40 and the second redistribution layer 50 to expose at least a portion of the second redistribution layer 50 (S145C). In operation S145C, the third passivation layer 60 is formed to cover the second passivation layer 40 and the second redistribution layer 50, and the entire area except for the area where the conductive member 70 to be described below is to be formed is coated with a photoresist, and then the photoresist is exposed and developed to expose at least a portion of the second redistribution layer 50 on one side of the active surface AS of the semiconductor chip 10.

[0055] Then, if Figure 5H As shown, in the region where the second redistribution layer 50 is exposed through the third passivation layer 60, a conductive member 70 is formed by an electroplating process (S145B). The conductive member 70 may be a UBM, which is provided to facilitate soldering of the conductive bump B, which is described below. In order to clearly distinguish the terms, the conductive member on which the first conductive bump B1 is formed is defined as a first conductive member 71, and the conductive member on which the second conductive bump B2 is formed is defined as a second conductive member 72.

[0056] Then, if Fig.5IAs shown, a conductive bump B is formed on an electrical signal path leading to the pad BP, the first redistribution layer 30, and the PCB substrate (not shown) (S150). When the electrical signal path leading to the first pad BP1, the first redistribution line 31, the third redistribution line 51, the first conductive member 71, and the PCB substrate is defined as a first electrical signal path, and the electrical signal path leading to the second pad BP2, the second redistribution line 32, the fourth redistribution line 52, the second conductive member 72, and the PCB substrate is defined as a second electrical signal path, the conductive bump B may include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Therefore, in operation S150, the first conductive bump B1 and the second conductive bump B2 are mounted on the semiconductor chip 10 so that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first redistribution line 31 and the third redistribution line 51, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second redistribution line 32 and the fourth redistribution line 52, and then a reflow process is performed to solder the first conductive bump B1 and the second conductive bump B2 to the first conductive member 71 and the second conductive member 72, respectively. Although Fig.5I An example in which the conductive bump B is implemented as a solder bump is shown, but according to the embodiment, the conductive bump B may be implemented as Figure 5J The copper pillar bump is shown.

[0057] A WLP (specifically, a fan-in WLP) may be manufactured by operations S110 to S150. Specifically, the capacitor DCAP is electrically connected to a first electrical signal path (e.g., a VCC power input path) and a second electrical signal path (e.g., a ground path) through the first redistribution layer 30 and the second redistribution layer 50 to reduce the impedance of the first electrical signal path and the second electrical signal path. Therefore, improved impedance characteristics and power noise reduction characteristics may be obtained. In addition, since the capacitor DCAP is disposed between the first passivation layer 20 and the third passivation layer 60 (i.e., the capacitor DCAP is disposed in the passivation layer), the capacitor DCAP is not affected by interference and can maintain low equivalent series resistance (ESR) and equivalent series inductance (ESL) characteristics.

[0058] Meanwhile, after operation S150 , operation S160 of cutting the semiconductor chip 10 in a wafer state into a plurality of CSPs may be additionally performed.

[0059] 3. Third Exemplary Embodiment

[0060] FIG. 6A to FIG. 6J 2 are cross-sectional views illustrating each operation of a method of manufacturing a semiconductor device according to the third exemplary embodiment of the present invention.

[0061] As described above in the second exemplary embodiment, in the process of manufacturing the WLP, multiple redistribution layers may be required to rearrange the pads depending on the number of pads and the total layout area of ​​the semiconductor chip 10. In this case, as in the second exemplary embodiment, the capacitor DCAP may be set in the passivation layer. However, as the complexity of the redistribution layer increases, space for accommodating the capacitor DCAP may not be formed in the passivation layer. The third exemplary embodiment focuses on a structure in which the capacitor DCAP is formed outside the passivation layer and a process for forming the capacitor DCAP outside the passivation layer when the WLP is configured to include multiple redistribution layers. The detailed description of the same structures and processes as the first exemplary embodiment and the second exemplary embodiment will be omitted, and the structures and processes different from the first exemplary embodiment and the second exemplary embodiment will be described. The same processes and structures as the first exemplary embodiment and the second exemplary embodiment will be indicated with the same figure numerals as the first exemplary embodiment and the second exemplary embodiment.

[0062] refer to Fig. 6A First, a semiconductor chip 10 in a wafer state is provided (S110). In the semiconductor chip 10, first and second pads BP1 and BP2 as paths for power supply and electrical input and output of a circuit are formed to be exposed on one side of an active surface AS of the semiconductor chip 10 through a pad opening.

[0063] Then, if Figure 6B As shown, a first passivation layer 20 is formed on the semiconductor chip 10 to expose the pads BP (S120). In operation S120, the first passivation layer 20 is formed on the semiconductor chip 10 to expose the first and second pads BP1 and BP2 on one side of the active surface AS of the semiconductor chip 10.

[0064] Then, if Figure 6C As shown, the first redistribution layer 30 is formed to be connected to the pad BP and to extend on the first passivation layer 20 (S130). A portion of the first redistribution layer 30 connected to the first pad BP1 is defined as a first redistribution line 31, and a portion of the first redistribution layer 30 connected to the second pad BP2 is defined as a second redistribution line 32. In addition, as shown in FIG. Figure 6C As shown, an additional redistribution line 33 for rearranging an additional pad (not shown) may be formed in operation S130.

[0065] Then, if Fig.6DAs shown, the second passivation layer 40 is formed on the first passivation layer 20 and the first redistribution layer 30 to expose at least a portion of the first redistribution layer 30 (S135C). In operation S135C, the second passivation layer 40 is formed to cover the first passivation layer 20 and the first redistribution layer 30, and the entire area except for the area where the second redistribution layer 50 to be described below will be formed is coated with a photoresist, and then the photoresist is exposed and developed to expose at least a portion of the first redistribution layer 30 on one side of the active surface AS of the semiconductor chip 10.

[0066] Then, if Fig. 6E As shown, a second redistribution layer 50 is formed in a region where the first redistribution layer 30 is exposed through the second passivation layer 40 (S135D). A portion of the second redistribution layer 50 connected to the first redistribution line 31 is defined as a third redistribution line 51, and a portion of the second redistribution layer 50 connected to the second redistribution line 32 is defined as a fourth redistribution line 52. Fig. 6E As shown, the third redistribution line 51 and the fourth redistribution line 52 may have a portion extending on the second passivation layer 40. Fig. 6E As shown, in operation S135D, additional redistribution lines 53 for rearranging additional pads (not shown) may be formed on the additional redistribution lines 33 (in order to clearly distinguish between the additional redistribution lines 33 and 53, the additional redistribution lines 33 included in the first redistribution layer 30 may be displayed as first additional redistribution lines 33, and the additional redistribution lines 53 included in the second redistribution layer 50 may be displayed as second additional redistribution lines 53).

[0067] Then, if Fig. 6F As shown, a third passivation layer 60 is formed on the second passivation layer 40 and the second redistribution layer 50 to expose at least a portion of the second redistribution layer 50 (S135E). In operation S135E, the third passivation layer 60 is formed to cover the second passivation layer 40 and the second redistribution layer 50, and the entire area except for the area where the conductive member 70 to be described below is to be formed is coated with a photoresist, and then the photoresist is exposed and developed to expose at least a portion of the second redistribution layer 50 on one side of the active surface AS of the semiconductor chip 10.

[0068] Then, if Figure 6GAs shown, in the region where the second redistribution layer 50 is exposed through the third passivation layer 60, a conductive member 70 is formed by an electroplating process (S135F). The conductive member 70 may be a UBM, which is provided to facilitate the soldering of the conductive bump B, which is to be described below. In order to clearly distinguish the terms, the conductive member on which the first conductive bump B1 is formed is defined as the first conductive member 71, the conductive member on which the second conductive bump B2 is formed is defined as the second conductive member 72, the conductive member connected to the first power input pad of the capacitor DCAP to be described below is defined as the third conductive member 73, and the conductive member connected to the second power input pad of the capacitor DCAP is defined as the fourth conductive member 74. The first conductive member 71 and the third conductive member 73 are electrically connected through the first redistribution line 31, and the second conductive member 72 and the fourth conductive member 74 are electrically connected through the second redistribution line 32. When the capacitor DCAP has an additional power input pad, an additional conductive member 75 to which the additional power input pad of the capacitor DCAP is to be soldered may be formed on the second additional redistribution line 53.

[0069] Then, if Figure 6H As shown, the capacitor DCAP is formed to be electrically connected to the first redistribution layer 30 at the wafer level (S140). In operation S140, the capacitor DCAP is mounted on the semiconductor chip 10 so that the solder cap of the bump DCAP_B formed on the first power input pad of the capacitor DCAP contacts the third conductive member 73 electrically connected to the first redistribution line 31 and the third redistribution line 51, and the solder cap of the bump DCAP_B formed on the second power input pad of the capacitor DCAP contacts the fourth conductive member 74 electrically connected to the second redistribution line 32 and the fourth redistribution line 52, and then a reflow process is performed to solder the capacitor DCAP to the third conductive member 73 and the fourth conductive member 74. When the capacitor DCAP has an additional power input pad, the additional power input pad of the capacitor DCAP may be formed to contact the above-mentioned additional conductive member 75. In this way, the first redistribution line 31 and the second redistribution line 32 are configured to serve as a multi-node of the capacitor DCAP.

[0070] Then, if Fig.6IAs shown, a conductive bump B is formed on an electrical signal path leading to the pad BP, the first redistribution layer 30, and a PCB substrate (not shown) to which the packaged semiconductor chip 10 (i.e., WLP) is to be attached (S150). When the electrical signal path leading to the first pad BP1, the first redistribution line 31, the third redistribution line 51, the first conductive member 71, and the PCB substrate is defined as a first electrical signal path, and the electrical signal path leading to the second pad BP2, the second redistribution line 32, the fourth redistribution line 52, the second conductive member 72, and the PCB substrate is defined as a second electrical signal path, the conductive bump B may include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Therefore, in operation S150, the first conductive bump B1 and the second conductive bump B2 are mounted on the semiconductor chip 10 so that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first redistribution line 31 and the third redistribution line 51, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second redistribution line 32 and the fourth redistribution line 52, and then a reflow process is performed to solder the first conductive bump B1 and the second conductive bump B2 to the first conductive member 71 and the second conductive member 72, respectively. Although Fig.6I An example in which the conductive bump B is implemented as a solder bump is shown, but according to the embodiment, the conductive bump B may be implemented as Figure 6J The copper pillar bump is shown.

[0071] The WLP (particularly, the fan-in WLP) may be manufactured through operations S110 to S150. After operation S150, operation S160 of cutting the semiconductor chip 10 in a wafer state into a plurality of CSPs may be additionally performed.

[0072] Fig. 7A and Figure 7B 7 is a diagram showing the structure of a semiconductor device in which a capacitor is provided according to the present invention. Compared with the capacitor layout structure according to the related art, the distance between the pad and the capacitor can be significantly reduced because the capacitor is provided in the die. Although only two conductive bumps are shown in FIG. 7 for ease of understanding of the present invention, in an actual semiconductor device manufacturing process, a semiconductor chip can be attached to a PCB substrate via two or more conductive bumps.

[0073] According to the present invention, a capacitor (e.g., a decoupling capacitor) is not formed on a PCB substrate but is formed to be electrically connected to a redistribution layer at a wafer level, and thus the capacitor is included in a WLP package. Therefore, the distance between the pad and the capacitor (i.e., the length of the power delivery network (PDN), e.g., Figure 1The length A) can be significantly reduced. Therefore, the increase in PDN impedance caused by the influence of the interconnection of the multilayer PCB substrate and the influence of the resistance of the PDN can be minimized. Therefore, compared with the semiconductor device according to the related art, improved impedance characteristics and power noise reduction characteristics can be obtained.

[0074] According to the present invention, no capacitor is formed in the PCB substrate, so the PCB substrate area available for the SMT process can be increased.

[0075] According to the present invention, capacitors are directly applied to the input pads and output pads of the WLP. Therefore, the input signal and the output signal can be stabilized while reducing power noise.

[0076] According to the present invention, by using the redistribution layer of the WLP as multiple nodes of the capacitor, the number of capacitors required to reduce impedance is reduced. Therefore, the cost for implementing the semiconductor device can be reduced.

[0077] Although the present invention has been described above with reference to the embodiments shown in the accompanying drawings, these embodiments are merely exemplary, and those skilled in the art to which the present invention belongs will appreciate that various modifications and other embodiments equivalent to these embodiments may be made from these embodiments. Therefore, the scope of the present invention should be determined based on the following claims.

Claims

1. A semiconductor device, comprising: A semiconductor chip in which pads are formed in a wafer state; a first passivation layer formed on the semiconductor chip to expose the pad; a first redistribution layer connected to the pad and extending over the first passivation layer; a conductive bump disposed on an electrical signal path leading to the pad, the first redistribution layer, and the substrate; and A capacitor is formed to be electrically connected to the first redistribution layer at a wafer level before the conductive bump is formed.

2. The semiconductor device according to claim 1 , wherein the pad comprises a first pad and a second pad, The first passivation layer is formed on the semiconductor chip to expose the first pad and the second pad, The first redistribution layer includes a first redistribution line and a second redistribution line respectively connected to the first pad and the second pad and extending on the first passivation layer; The conductive bumps include a first conductive bump disposed on a first electrical signal path leading to the first pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path leading to the second pad, the second redistribution line, and the substrate, and The capacitor is electrically connected to the first and second redistribution lines and is disposed between the first and second conductive bumps.

3. The semiconductor device according to claim 2, further comprising: a second passivation layer formed on the first passivation layer and the first redistribution layer to expose at least a portion of the first redistribution layer; and a conductive member formed in a region of the first redistribution layer exposed by the second passivation layer, The first conductive bump, the second conductive bump and the capacitor are formed on the conductive member and are in contact with the conductive member.

4. The semiconductor device according to claim 2, further comprising: a second passivation layer formed on the first passivation layer and the first redistribution layer to expose at least a portion of the first redistribution layer; a second redistribution layer formed in a region of the first redistribution layer exposed by the second passivation layer; a third passivation layer formed on the second passivation layer and the second redistribution layer to expose at least a portion of the second redistribution layer; and a conductive member formed in a region of the second redistribution layer exposed by the third passivation layer, wherein the capacitor is formed on the first redistribution layer between the first passivation layer and the third passivation layer and contacts the first redistribution layer, and The first conductive bump and the second conductive bump are formed on the conductive member and contact the conductive member.

5. The semiconductor device according to claim 2, further comprising: a second passivation layer formed on the first passivation layer and the first redistribution layer to expose at least a portion of the first redistribution layer; a second redistribution layer formed in a region of the first redistribution layer exposed by the second passivation layer; a third passivation layer formed on the second passivation layer and the second redistribution layer to expose at least a portion of the second redistribution layer; and a conductive member formed in a region of the second redistribution layer exposed by the third passivation layer, The first conductive bump, the second conductive bump and the capacitor are formed on the conductive member and are in contact with the conductive member.

6. The semiconductor device according to claim 2, wherein the first redistribution line and the second redistribution line serve as a multi-node of the capacitor, and The first redistribution line or the second redistribution line is formed to be electrically connected to an additional conductive bump other than the first conductive bump or the second conductive bump. 7 . The semiconductor device according to claim 1 , wherein the conductive bump is implemented as a solder bump or a copper pillar bump. 8 . The semiconductor device according to claim 1 , wherein the semiconductor device is implemented as a wafer level package or a wafer level chip size package.

9. A method for manufacturing a semiconductor device, the method comprising: forming a first passivation layer on a semiconductor chip to expose a pad formed in the semiconductor chip; forming a first redistribution layer connected to the pad and extending on the first passivation layer; forming a capacitor to be electrically connected to the first redistribution layer at a wafer level; as well as After forming the capacitor, a conductive bump is formed on an electrical signal path leading to the pad, the first redistribution layer, and the substrate.

10. The method according to claim 9, wherein the pad comprises a first pad and a second pad, The first passivation layer is formed on the semiconductor chip to expose the first pad and the second pad, The first redistribution layer includes a first redistribution line and a second redistribution line respectively connected to the first pad and the second pad and extending on the first passivation layer, The conductive bumps include a first conductive bump disposed on a first electrical signal path leading to the first pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path leading to the second pad, the second redistribution line, and the substrate, and The capacitor is electrically connected to the first and second redistribution lines and is disposed between the first and second conductive bumps.

11. The method according to claim 10, further comprising, after forming the first redistribution layer: forming a second passivation layer on the first passivation layer and the first redistribution layer to expose at least a portion of the first redistribution layer; and forming a conductive member in a region of the first redistribution layer exposed by the second passivation layer, wherein in forming the capacitor, the capacitor is formed to be in contact with the conductive member electrically connected to the first redistribution line and the conductive member electrically connected to the second redistribution line, and In the forming of the conductive bumps, the first conductive bump is formed to contact the conductive member electrically connected to the first redistribution line, and the second conductive bump is formed to contact the conductive member electrically connected to the second redistribution line.

12. The method according to claim 10, wherein in the forming of the capacitor, the capacitor is formed on and in contact with the first redistribution layer, and The method further comprises, after forming the capacitor: forming a second passivation layer on the first passivation layer and the first redistribution layer to expose at least a portion of the first redistribution layer; forming a second redistribution layer in a region of the first redistribution layer exposed by the second passivation layer; forming a third passivation layer on the second passivation layer and the second redistribution layer to expose at least a portion of the second redistribution layer; as well as forming a conductive member in a region of the second redistribution layer exposed by the third passivation layer, In forming the conductive bumps, the first conductive bumps contacting the first redistribution lines are formed on the conductive members electrically connected to the first redistribution lines, and the second conductive bumps contacting the second redistribution lines are formed on the conductive members electrically connected to the second redistribution lines.

13. The method according to claim 10, further comprising, after forming the first redistribution layer: forming a second passivation layer on the first passivation layer and the first redistribution layer to expose at least a portion of the first redistribution layer; forming a second redistribution layer in a region of the first redistribution layer exposed by the second passivation layer; forming a third passivation layer on the second passivation layer and the second redistribution layer to expose at least a portion of the second redistribution layer; as well as forming a conductive member in a region of the second redistribution layer exposed by the third passivation layer, wherein in forming the capacitor, the capacitor is formed to be in contact with each of the conductive member electrically connected to the first redistribution line and the conductive member electrically connected to the second redistribution line, and In the forming of the conductive bumps, the first conductive bump is formed to contact the conductive member electrically connected to the first redistribution line, and the second conductive bump is formed to contact the conductive member electrically connected to the second redistribution line. 14 . The method according to claim 9 , further comprising cutting the semiconductor chip in a wafer state into chip size packages after forming the conductive bumps.

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