Method for dynamically adjusting sampling rate to balance PID algorithm and fundamental wave frequency precision

Abstract

The invention discloses a method for realizing balance between a PID algorithm and fundamental frequency precision by dynamically adjusting a sampling rate. The method comprises an ADC voltage acquisition board card, an FPGA control board card, a DAC voltage output board card and a touch screen LCD board card. A PID algorithm module, a waveform generation module, a sampling module, a DFT harmonic calculation module and a dynamic sampling clock module are arranged in the FPGA control board card; the ADC voltage acquisition board card is used for acquiring external voltage data, the DAC voltage output board card is a DAC module or an inverter module and is used for realizing voltage output in a specific range, and the ADC data sampling rate is greater than or equal to the DAC data output rate, that is, the ADC voltage acquisition board card is used for acquiring external voltage data; and the touch screen LCD board card is used for realizing functions of interacting with a user, including waveform setting and harmonic display. The technology capable of dynamically adjusting the sampling frequency so as to balance the PID control effect and the frequency precision when the fundamental wave frequency changes is particularly important. The technology can be applied to multiple fields of motor control, inverter design, power grid frequency stability control and the like.

Description

Technical Field

[0001] The present invention relates to a PID (Proportional-Integral-Differential) controller, and in particular to a method for dynamically adjusting a sampling rate to achieve a balanced PID algorithm and fundamental frequency accuracy. Background Art

[0002] At present, in the power electronics industry, the PID (proportional-integral-differential) control algorithm is one of the core technologies for achieving stable voltage output and controlling the behavior of switch tubes. Through the comprehensive adjustment of the proportional, integral and differential parts of the system error, the PID control algorithm can ensure the stable operation of power electronic equipment under different operating conditions and provide high-quality output voltage waveforms. At the same time, in order to further optimize the output performance, the maximum output rate supported by the inverter or digital-to-analog converter (DAC) is usually used as the calculation rate of the PID algorithm to improve the system response speed and control accuracy. However, in order to ensure that the PID control algorithm can still maintain a high control accuracy at different fundamental frequencies, the system needs to be adaptively adjusted according to the real-time fundamental frequency. This can not only improve the response speed of the system, but also ensure the stability and accuracy of the output voltage waveform.

[0003] When the system requires more sophisticated analysis and control of the voltage output waveform, especially in scenarios such as harmonic analysis and spectrum estimation, Fourier transform (DFT and FFT) is usually used to analyze the spectral characteristics of the signal. In the automatic control system using the PID control algorithm, accurate frequency control and real-time sampling are the key to ensuring system stability and performance optimization. The fluctuation of system frequency and the mismatch of sampling frequency will affect the control effect, resulting in unstable system output, slow response speed or large errors. Therefore, in order to ensure that the control system can respond quickly and remain stable, the selection and adjustment of the sampling frequency is crucial. Usually the sampling frequency needs to be higher than the highest frequency component in the signal to meet the Nyquist sampling theorem. However, in actual applications, the fundamental frequency of the system may fluctuate with changes in operating conditions, which puts forward new requirements for the system: it must be able to maintain the accuracy of frequency control at different fundamental frequencies, and optimize the control algorithm when the sampling frequency is insufficient to ensure the stability of the system.

[0004] Existing technology and defects:

[0005] Discrete Fourier Transform (DFT) is a common method for frequency domain analysis of discrete time signals. It can calculate sequences of any length and extract frequency components, harmonic amplitudes, and phase information from the signal. Because DFT has a high frequency resolution, the accuracy of its spectrum analysis can meet the needs of most power electronic systems for harmonic analysis, especially when the sequence length is large. However, the computational complexity of DFT is high, with a complexity of O(N 2), that is, the computing power required for calculation is proportional to the square of the sequence length N. This also means that when the sequence length is large, the calculation time of DFT will increase significantly, affecting the real-time performance and control efficiency of the system. Therefore, under high sampling rates and long time sequences, the calculation time of DFT will become a technical bottleneck, and it is difficult to adapt to the demand for rapid response of the system. Especially for real-time control systems, the high complexity of DFT makes it not advantageous in many application scenarios.

[0006] In order to overcome the disadvantage of high computational complexity of DFT, Fast Fourier Transform (FFT) is widely used. FFT is an optimized DFT algorithm, which is specially used for the case where the sequence length is 2 to the power of N. It reduces the computational complexity of DFT from O(N 2 ) is reduced to O(N log N), greatly improving computational efficiency. This makes FFT a mainstream technology in harmonic analysis and spectrum estimation, especially in real-time control systems, where it can calculate the frequency components of signals more quickly.

[0007] Despite its significant advantages in computing speed, FFT also has certain limitations in terms of sequence length and frequency resolution: FFT can only process sequences with a length of 2 to the power of N, which means that in practical applications, the length of the signal sequence must be adjusted to meet this condition. If the signal length does not meet this requirement, the signal needs to be zero-padded, which will introduce errors in spectrum analysis and reduce frequency resolution. And the frequency resolution depends on the sequence length, and a shorter sequence length will result in poorer frequency resolution. In addition, since FFT requires the signal length to be fixed and 2 to the power of N, when the input signal length does not meet this condition, additional signal processing operations such as truncation or padding are required, which to a certain extent increases the complexity of the algorithm and resource consumption during the processing.

[0008] In summary, the existing DFT and FFT calculation methods have their own advantages and disadvantages. DFT provides higher frequency resolution, but the calculation complexity is too high; FFT improves calculation efficiency, but its sequence length limit and frequency resolution are relatively low. These defects of the prior art make it difficult to simultaneously meet the requirements of control accuracy and real-time performance in application scenarios that require high accuracy and fast response. Therefore, in application scenarios that require high frequency resolution and real-time calculation, it is difficult for the prior art to simultaneously meet the requirements of real-time performance and accuracy.

[0009] Therefore, a technical solution is proposed that can dynamically adjust the sampling rate while taking into account both computational efficiency and accuracy, which has important technical value and application prospects.

[0010] In view of this, the present invention is proposed. Summary of the invention

[0011] The purpose of the present invention is to provide a method for dynamically adjusting the sampling rate to achieve a balance between the PID algorithm and the fundamental frequency accuracy, so as to solve the above-mentioned technical problems existing in the prior art.

[0012] The objective of the present invention is achieved through the following technical solutions:

[0013] The method of dynamically adjusting the sampling rate to achieve a balanced PID algorithm and fundamental frequency accuracy of the present invention comprises: an ADC voltage acquisition board, an FPGA control board, a DAC voltage output board and a touch screen LCD board;

[0014] The FPGA control board contains a PID algorithm module, a waveform generation module, a sampling module, a DFT harmonic calculation module and a dynamic sampling clock module;

[0015] The ADC voltage acquisition board is used to collect external voltage data. The maximum sampling rate of the ADC is recorded as f ADC_max ;

[0016] The DAC voltage output card is a DAC module or an inverter module, which is used to achieve a specific range of voltage output. The maximum sampling rate of the DAC is recorded as f DAC_max ;

[0017] The ADC data sampling rate is greater than or equal to the DAC data output rate, that is:

[0018] f ADC_max ≥f DAC_max ;

[0019] The touch screen LCD board is used to realize the functions of interacting with the user, including: waveform setting and harmonic wave display.

[0020] Compared with the prior art, the method of dynamically adjusting the sampling rate to achieve a balance between the PID algorithm and the fundamental frequency accuracy provided by the present invention is particularly important for dynamically adjusting the sampling frequency to balance the PID control effect and the frequency accuracy when the fundamental frequency changes. This technology can be applied to many fields such as motor control, inverter design, and grid frequency stability control. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the control module structure of an embodiment of the present invention.

[0022] Figure 2 Schematic diagram of PID and DFT input / output rates according to an embodiment of the present invention.

[0023] Figure 3 Schematic diagram of waveform output frequency control and DFT according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention; it is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0025] First, the terms that may be used in this article are explained as follows:

[0026] The term “and / or” means that either or both of them can be realized at the same time. For example, X and / or Y means both “X” or “Y” and “X and Y”.

[0027] The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0028] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than the technical feature elements explicitly listed, except for the conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in the clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0029] The contents not described in detail in the examples of the present invention belong to the prior art known to professionals in the field. If no specific conditions are specified in the examples of the present invention, the conditions are carried out according to the conventional conditions in the field or the conditions recommended by the manufacturer. If the manufacturer is not specified in the reagents or instruments used in the examples of the present invention, they are all conventional products that can be purchased commercially.

[0030] The method of dynamically adjusting the sampling rate to achieve a balanced PID algorithm and fundamental frequency accuracy of the present invention comprises: an ADC voltage acquisition board, an FPGA control board, a DAC voltage output board and a touch screen LCD board;

[0031] The FPGA control board contains a PID algorithm module, a waveform generation module, a sampling module, a DFT harmonic calculation module and a dynamic sampling clock module;

[0032] The ADC voltage acquisition board is used to collect external voltage data. The maximum sampling rate of the ADC is recorded as f ADC_max ;

[0033] The DAC voltage output card is a DAC module or an inverter module, which is used to achieve a specific range of voltage output. The maximum sampling rate of the DAC is recorded as f DAC_max ;

[0034] The ADC data sampling rate is greater than or equal to the DAC data output rate, that is:

[0035] f ADC_max ≥f DAC_max ;

[0036] The touch screen LCD board is used to realize the functions of interacting with the user, including: waveform setting and harmonic wave display.

[0037] The waveform setting includes: the user sets the waveform paradigm, amplitude, phase and frequency by touching the virtual key, and sends it to the FPGA control board;

[0038] The harmonic display includes: displaying the harmonic amplitude and phase calculated by the FPGA control board on an LCD screen.

[0039] In the FPGA control board:

[0040] 1) Waveform generation module:

[0041] Built-in sine wave / square wave / triangle wave and custom waveform paradigm, receive waveform, amplitude, phase and frequency setting data from touch screen LCD board, and output voltage data V that conforms to the set waveform ref To the PID algorithm module;

[0042] 2)PID algorithm module:

[0043] The PID algorithm uses position and / or incremental methods;

[0044] The position PID algorithm is as follows:

[0045]

[0046] K P is the proportional coefficient, K I is the integral coefficient Integral, K D is the derivative coefficient, e(k)=V ref (k)-V mea (k) is the setting value V ref With the measured value Vmea The difference at time k;

[0047] The incremental PID algorithm is as follows:

[0048] Δu(k)=u(k)-u(k-1)

[0049] =K P *[e(k)-e(k-1)]+K I *e(k)+K D *[e(k)-2e(k-1)+e(k-2)]

[0050] Take the DAC maximum output conversion rate f DAC_max As PID calculation rate;

[0051] 3) DFT harmonic calculation module:

[0052] Set the N value for DFT calculation and calculate the harmonic amplitude and phase of the input measurement voltage;

[0053]

[0054] 0≤k≤N-1

[0055] X(k) is a complex sequence, so X(k) is written as follows:

[0056] X(k)=X R (k)+jX I (k)

[0057] The amplitude values ​​of the harmonics are:

[0058]

[0059] According to the Nyquist sampling theorem, the sampling rate fs must be greater than twice the highest frequency component of interest in the measured signal; and due to the symmetry of the DFT results, usually only the first half of the results are used, that is, the results less than half of the sampling frequency, where X(0) is the DC component, X(1) is the fundamental frequency, and X(2) is the 2nd harmonic. N is often an even number, so 0 to N / 2-1 harmonics are valid.

[0060] The phase value of the harmonic is:

[0061]

[0062] DFT calculation gives the fundamental frequency f DFT_b and the data sampling rate f involved in the DFT calculation DFT_s The relationship between them is:

[0063]

[0064] 4) Dynamic clock sampling module:

[0065] Based on the N value of DFT and the fundamental frequency f DFT_b Get the sampling frequency f involved in calculating DFT DFT_s :

[0066] f DFT_s =f DFT_b *N

[0067] When the parameter N is selected, the calculated sampling frequency f DFT_s Satisfies the following formula:

[0068] f DAC_max ≤f DFT_s ≤f ADC_max

[0069] Because the fundamental frequency f DFT_b is a variable quantity, so it is impossible to select the sampling frequency f when the N value is selected. DFT_s All satisfy the above formula;

[0070] At this time, the formula after introducing the positive integer M is as follows:

[0071] f DFT_s =f DFT_b *N*M

[0072] f DAC_max ≤f DFT_s =f DFT_b *N*M≤f ADC_max

[0073] By calculating the positive integer M that satisfies the above formula, there are multiple values, and the smallest value of M can be taken;

[0074] The sampling frequency f that satisfies the above formula DFT_s As the actual sampling rate of the ADC voltage acquisition board;

[0075] 5) Sampling module:

[0076] The function of the sampling module is to take one data for every M data, so that the V involved in the DFT calculation mea The data sampling rate is reduced to f DFT_s 1 / M of the data rate involved in the DFT calculation is defined as f DFT_d , then:

[0077] f DFT_d =f DFT_s / M=f DFT_b *N

[0078] The calculated frequency resolution f′ DFT_b for:

[0079] f′ DFT_b =f DFT_s / N=f DFT_b *N / N=f DFT_b ;

[0080] This method achieves the fundamental frequency f DFT_b And calculation of its N / 2-1 times harmonics.

[0081] In summary, the method of dynamically adjusting the sampling rate to achieve a balance between the PID algorithm and the fundamental frequency accuracy in the embodiment of the present invention is particularly important for dynamically adjusting the sampling frequency to balance the PID control effect and the frequency accuracy when the fundamental frequency changes. This technology can be applied to many fields such as motor control, inverter design, and grid frequency stability control.

[0082] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the embodiments of the present invention are described in detail with specific embodiments below.

[0083] Example 1

[0084] like Figures 1 to 3 As shown:

[0085] 1. A method for dynamically adjusting the sampling rate to balance PID calculation and harmonic amplitude accuracy. Figure 1 Structurally, it is mainly divided into four parts: ADC voltage acquisition board, FPGA control board (FPGA Board), DAC voltage output board and touch screen LCD board; the FPGA board contains PID control algorithm, waveform generation module Wave_gen, sampling module Decimation, DFT algorithm for calculating harmonics and dynamic sampling clock module Dynamic_Sample Clock;

[0086] in:

[0087] 1. ADC voltage acquisition board:

[0088] The function is to collect external voltage data. The maximum sampling rate of ADC is recorded as f ADC_max ;

[0089] DAC voltage output board:

[0090] It can be a DAC module or an inverter module. Its function is to achieve a voltage output within a specific range. The maximum sampling rate of the DAC is recorded as f DAC_max ;

[0091] The present invention requires that the ADC data sampling rate is greater than or equal to the DAC data output rate, that is:

[0092] f ADC_max ≥f DAC_max .

[0093] 2. Touch-LCD board:

[0094] Implement functions for interaction with users: waveform setting and harmonic display;

[0095] Waveform setting: Users can set the waveform mode, amplitude, phase, frequency, etc. by touching virtual buttons and send them to the FPGA control board;

[0096] Harmonic display: Display the harmonic amplitude and phase calculated by the FPGA control board on the LCD screen;

[0097] 3. FPGA control board:

[0098] 1) Waveform generation module Wave_gen:

[0099] Built-in sine wave / square wave / triangle wave and custom waveform paradigms, receive setting data (waveform / amplitude / phase / frequency) from Touch-LCD board, and output voltage data V that conforms to the set waveform ref And given to PID algorithm;

[0100] 2)PID algorithm module:

[0101] Typical PID algorithms include position type and incremental type PID algorithms. The present invention can use both position type and incremental type.

[0102] The position PID algorithm is as follows:

[0103]

[0104] K P is the proportional coefficient, K I is the integral coefficient Integral, K D is the derivative coefficient, e(k)=V ref (k)-V mea (k) is the setting value V ref With the measured value V mea The difference at time k;

[0105] The incremental PID algorithm is as follows:

[0106] Δu(k)=u(k)-u(k-1)

[0107] =K P*[e(k)-e(k-1)]+K I *e(k)+K D *[e(k)-2e(k-1)+e(k-2)]

[0108] In order to obtain the optimal output waveform, the present invention takes the DAC maximum output conversion rate f DAC_max Calculates the rate as a PID.

[0109] 3) DFT harmonic calculation module:

[0110] Set the N value for DFT calculation and calculate the harmonic amplitude and phase of the input measurement voltage;

[0111]

[0112] 0≤k≤N-1

[0113] X(k) is a complex sequence, so X(k) is written as follows:

[0114] X(k)=X R (k)+jX I (k)

[0115] The amplitude values ​​of the harmonics are:

[0116]

[0117] From the Nyquist sampling theorem, we know that the sampling rate fs must be greater than twice the highest frequency component of interest in the measured signal; and due to the symmetry of the DFT results, usually only the first half of the results are used, that is, the results that are less than half of the sampling frequency, where X(0) is the DC component, X(1) is the fundamental frequency, and X(2) is the second harmonic. N is often an even number, so O to N / 2-1 harmonics are valid.

[0118] The phase value of the harmonic is:

[0119]

[0120] DFT calculation gives the fundamental frequency f DFT_b and the data sampling rate f involved in the DFT calculation DFT_s The relationship between them is:

[0121]

[0122] 4) Dynamic clock sampling module:

[0123] Based on the N value of DFT and the fundamental frequency f DFT_b Get the sampling frequency f involved in calculating DFT DFT_s :

[0124] fDFT_s =f DFT_b *N

[0125] When the parameter N is selected, the calculated sampling frequency f DFT_s Satisfies the following formula:

[0126] f DAC_max ≤f DFT_s ≤f ADC_max

[0127] Because the fundamental frequency f DFT_b is a variable quantity, so it is impossible to select the sampling frequency f when the N value is selected. DFT_s All satisfy the above formula;

[0128] At this time, the formula after introducing the positive integer M is as follows:

[0129] f DFT_s =f DFT_b *N*M

[0130] f DAC_max ≤f DFT_s =f DFT_b *N*M≤f ADC_max

[0131] There are multiple values ​​of the positive integer M that satisfies the above formula by calculation, and the smallest value of M can be taken.

[0132] The sampling frequency f that satisfies the above formula DFT_s As the actual sampling rate of the ADC voltage acquisition board.

[0133] 5) Decimation module

[0134] The function of the sampling module Decimation is to take one data for every M data, so that the V involved in the DFT calculation mea The data sampling rate is reduced to f DFT_s 1 / M of the data rate involved in the DFT calculation is defined as f DFT_d , then:

[0135] f DFT_d =f DFT_s / M=f DFT_b *N

[0136] The calculated frequency resolution f′ DFT_b for:

[0137] f′ DFT_b =f DFT_s / N=f DFT_b *N / N=f DFT_b

[0138] It can be seen that this method can achieve the base frequency f DFT_b And calculation of its N / 2-1 times harmonics.

[0139] Second, the specific embodiments are as follows:

[0140] The maximum sampling frequency of the ADC voltage data acquisition board is f ADC_max The output conversion rate of the DAC voltage output card is 500kSPS. DAC_max is 100kSPS, that is:

[0141] f ADC_max =500kSPS

[0142] f DAC_max =100kSPS

[0143] The calculation rate of the PID control algorithm takes the DAC's maximum output rate as 100kSPS, that is, the PID is calculated 100k times per second;

[0144] from Figure 2 It can be seen that the ADC sampling voltage value V mea The sampling rate is 100k~500kSPS, and the sampled data is sent to the PID algorithm module. The waveform reference value V generated by the waveform generation module Wave_gen ref The rate is 100k / s, and the PID algorithm outputs 100kSPS. Although the ADC sampling rate is greater than or equal to 100kSPS, the V mea Take V ref The closest value to the effective value is V ref A PID calculation starts at the effective moment, and the V output by the ADC sampling at this moment is taken mea Participate in PID calculation. The other path is sent to the Decimation sampling module and then to the DFT module to calculate the harmonic amplitude and phase.

[0145] from Figure 3 It can be seen that Touch-LCD sets the output waveform and the frequency f of the output waveform re_set Sent to the dynamic clock sampling module Dynamic_Sample Clock, where f re_set This is the base frequency f that will be displayed on the Touch-LCD. DFT_b ,have:

[0146] f DFT_b =f re_set

[0147] The value range is 0~f ADC_max / (N*M), taking the length of DFT N as 100, M=1, we have:

[0148] f DFT_b ≤500k / (100*1)=5k

[0149] The dynamic clock sampling module Dynamic_Sample C|ock calculates the minimum positive integer M value as the paper sampling coefficient and passes it to the sampling module Decimation. The sampling module Decimation takes one data for every M data and sends it to the DFT module to participate in harmonic calculation. Because N = 100, the sampled voltage data V mea After DFT calculation, the amplitude and phase of DC, fundamental frequency to 49th harmonic are obtained;

[0150] Because N=100, the frequency resolution of the fundamental frequency can reach 0.01Hz.

[0151] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A method for dynamically adjusting the sampling rate to achieve a balance between the PID algorithm and the fundamental frequency accuracy, characterized in that: include: ADC voltage acquisition board, FPGA control board, DAC voltage output board and touch screen LCD board; The FPGA control board contains a PID algorithm module, a waveform generation module, a sampling module, a DFT harmonic calculation module and a dynamic sampling clock module; The ADC voltage acquisition board is used to collect external voltage data. The maximum sampling rate of the ADC is recorded as f ADC_max ; The DAC voltage output card is a DAC module or an inverter module, which is used to achieve a specific range of voltage output. The maximum sampling rate of the DAC is recorded as f DAC_max ; The ADC data sampling rate is greater than or equal to the DAC data output rate, that is: f ADC_max ≥f DAC_max ; The touch screen LCD board is used to realize the functions of interacting with the user, including: waveform setting and harmonic wave display.

2. The method for dynamically adjusting the sampling rate to achieve a balance between the PID algorithm and the fundamental frequency accuracy according to claim 1, characterized in that: The waveform setting includes: the user sets the waveform paradigm, amplitude, phase and frequency by touching the virtual key, and sends it to the FPGA control board; The harmonic display includes: displaying the harmonic amplitude and phase calculated by the FPGA control board on an LCD screen.

3. The method for dynamically adjusting the sampling rate to achieve a balance between the PID algorithm and the fundamental frequency accuracy according to claim 1 or 2, characterized in that: In the FPGA control board: 1) Waveform generation module: Built-in sine wave / square wave / triangle wave and custom waveform paradigm, receive waveform, amplitude, phase and frequency setting data from touch screen LCD board, and output voltage data V that conforms to the set waveform ref To the PID algorithm module; 2)PID algorithm module: The PID algorithm uses position and / or incremental methods; The position PID algorithm is as follows: K P is the proportional coefficient, K I is the integral coefficient, K D is the differential coefficient, e(k)=V ref (k)-V mea (k) is the setting value V ref With the measured value V mea The difference at time k; The incremental PID algorithm is as follows: Δu(k)=u(k)-u(k-1) =K P *[e(k)-e(k-1)]+K I *e(k)+K D *[e(k)-2e(k-1)+e(k-2)] Take the DAC maximum output conversion rate f DAC_max As PID calculation rate; 3) DFT wave calculation module: Set the N value for DFT calculation and calculate the harmonic amplitude and phase of the input measurement voltage; X(k) is a complex sequence, so X(k) is written as follows: X(k)=X R (k)+jX I (k) The amplitude values ​​of the harmonics are: According to the Nyquist sampling theorem, the sampling rate fs must be greater than twice the highest frequency component of interest in the measured signal; and due to the symmetry of the DFT results, usually only the first half of the results are used, that is, the results less than half of the sampling frequency, where X(0) is the DC component, X(1) is the fundamental frequency, and X(2) is the 2nd harmonic. N is often an even number, so 0 to N / 2-1 harmonics are valid. The phase value of the harmonic is: DFT calculation gives the fundamental frequency f DFT_b and the data sampling rate f involved in the DFT calculation DFT_s The relationship between them is: 4) Dynamic clock sampling module: Based on the N value of DFT and the fundamental frequency f DFT_b Get the sampling frequency f involved in calculating DFT DFT_s : f DFT_s =f DFT_b *N When the parameter N is selected, the calculated sampling frequency f D FT_s satisfies the following formula: f DAC_max ≤f DFT_s ≤f ADC_max Because the fundamental frequency f DFT_b is a variable quantity, so it is impossible to select the sampling frequency f when the N value is selected. DFT_s All satisfy the above formula; At this time, the formula after introducing the positive integer M is as follows: f DFT_s =f DFT_b *N*M f DAC_max ≤f DFT_s =f DFT_b *N*M≤f ADC_max By calculating the positive integer M that satisfies the above formula, there are multiple values, and the smallest value of M can be taken; The sampling frequency f that satisfies the above formula DFT_s As the actual sampling rate of the ADC voltage acquisition board; 5) Sampling module: The function of the sampling module is to take one data for every M data, so that the V involved in the DFT calculation mea The data sampling rate is reduced to f DFT _s is 1 / M, and the data rate involved in the DFT calculation is defined as f DFT_d , then: f DFT_d =f DFT_s / M=f DFT_b *N The calculated frequency resolution f′ DFT_b for: f′ DFT_b =f DFT_s / N=f DFT_b *N / N=f DFT_b ; This method achieves the fundamental frequency f DFT_b And calculation of its N / 2-1 times harmonics.

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