An automatic time offset compensation method for ultra-wideband chip baseband

Abstract

The application belongs to the technical field of integrated circuits, and discloses an automatic time offset compensation method for an ultra-wideband chip baseband, which divides Symbol signals entering an SHR into I-path real part signals and Q-path imaginary part signals, adopts an interpolation algorithm, and outputs compensation phase adjustment interpolation positions through a time offset compensation module; the number of Preamble synchronizations is judged, the amplitude of signals is estimated and low-pass filtered, and time offset compensation with different precisions is selected; phase compensation is dynamically adjusted; after detecting an SFD frame synchronization signal, the time offset phase difference of the current Symbol is locked, tracking compensation is performed, and the compensated signals are sent into a decoding module for decoding. The application can flexibly select time offset compensation modes with different precisions according to current channel conditions, and overcome interference problems caused by noise; through dynamic adjustment of compensation precision, communication reliability is significantly improved while power consumption is reduced, so that the overall performance of the system is comprehensively improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an automatic time offset compensation method for ultra-wideband chip baseband. Background Technology

[0002] Ultra-wideband (UWB) communication technology is a short-range wireless communication technology that uses nanosecond-level non-sinusoidal narrow pulses to transmit data. It boasts numerous advantages, including strong anti-interference capabilities, high positioning accuracy, and ultra-low power consumption. With the continuous development of UWB technology, UWB communication chips are now widely used in smart communication devices and smart cars, and also have considerable application prospects in other consumer markets.

[0003] Current UWB technology uses the IEEE 802.15.4a protocol, a revised version of IEEE 802.15.4, which supports higher data rates, extended communication range, and enhanced anti-interference capabilities. According to the IEEE 802.15.4a protocol, a UWB data frame is divided into three parts: the SHR part for synchronization, the PHR part for indicating basic data frame information and ranging, and the Payload part containing the specific data payload, such as... Figure 1 As shown, the Synchronization Receiver (SHR) specified in IEEE 802.15.4a is divided into two parts: the preamble, which constitutes the majority of the total SHR length, and the Separator Function Delimiter (SFD), used to separate the SHR and the Preamble Receiver (PHR). For the preamble, according to the IEEE 802.15.4a protocol, 24 different sequences can be used, with sequences 1-8 having a length of 31 and sequences 9-24 having a length of 127; and 8 different numbers of synchronizations can be selected, with a minimum of 256 and a maximum of 2048.

[0004] When communicating at a data bit rate of 6.8 Mb / s as specified in the IEEE 802.15.4a protocol, a synchronization sequence of length 127 should be selected according to the protocol. At this data rate, each symbol in the data portion contains an average of 2 pulses, while each symbol in the SHR portion contains an average of 508 pulses. The typical mean pulse repetition frequency (MPRF) of the preamble is 62.89 MHz, and the corresponding MPRF for the PHR and payload portions is 15.6 MHz. A higher MPRF represents a higher transmission rate, meaning the signal will be distorted due to multipath effects. Without proper time-off compensation to assist in channel estimation response matching and filtering to maximize the output signal-to-noise ratio, unpacking errors will occur, affecting normal communication.

[0005] Traditional time offset compensation process such as Figure 2 As shown, the traditional time offset compensation processing mode has the following problems:

[0006] 1. In order to adapt to the complex channel changes in real time, the number of Preamble synchronizations will also be adjusted accordingly, and the time offset convergence bandwidth coefficient will change with the duration of the Preamble. However, in traditional time offset compensation modules, the convergence bandwidth of the loop filter is usually a fixed value, which is difficult to effectively cope with the complex and ever-changing channel conditions in actual communication environments.

[0007] 2. For UWB chips, the time offset compensation module needs to select the appropriate accuracy of time offset correction according to different signal-to-noise ratio levels. However, traditional time offset compensation modules use fixed loop filter coefficient accuracy and usually estimate and compensate the phase by roughly comparing the energy values ​​of the sampling points before and after sampling. In complex environments, this method is difficult to resist the influence of noise, resulting in the sampling time not being able to be accurately adjusted, which can easily lead to inter-symbol interference.

[0008] Therefore, if we continue to use traditional time offset compensation, it will be impossible to ensure that the UWB chip can work normally in complex and ever-changing channels. This will also cause the system to fail to meet the requirements of adaptability and real-time performance, resulting in non-convergence or unpacking errors, which will seriously degrade the overall performance of the UWB communication baseband. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention provides an automatic time offset compensation method for ultra-wideband chip baseband. It flexibly selects time offset compensation methods of varying precision based on the current channel conditions, combining time division of coarse and fine convergence modes to ensure greater adaptability in response to channel changes. This significantly improves communication reliability while reducing power consumption, thereby comprehensively enhancing the overall system performance.

[0010] The automatic time offset compensation method for ultra-wideband chip baseband according to the present invention includes the following steps:

[0011] Step 1: Divide a Symbol signal entering the SHR symbol detection module into the real part of the I-path signal of the same direction component and the imaginary part of the Q-path signal of the quadrature component. Use an interpolation algorithm and output the compensation phase through the time offset compensation module to adjust the interpolation position to obtain the impulse response values ​​of the I and Q-path signals of the current phase P-path, the first three phases E1 / E2 / E3-path, and the last three phases L1 / L2 / L3-path.

[0012] Step 2: Determine the number of Preamble synchronizations and compare it with the experimental value. Set the amplitude estimation time. During the amplitude estimation time, perform correlation accumulation on the received I-channel real part signal and Q-channel imaginary part signal to estimate the signal amplitude. Input the obtained amplitude signal into the alpha filter for low-pass filtering. Select time offset compensation of different precision according to the signal-to-noise ratio level.

[0013] Step 3: Synchronize the count counter T via Preamble. update The phase compensation is dynamically adjusted based on the real-time determination of the Preamble length.

[0014] Step 4: After detecting the SFD frame synchronization signal, lock the time offset phase difference of the current Symbol, enter the time offset compensation module for tracking compensation, send the compensated signal to the decoding module for decoding, decode the original baseband data, and complete the communication.

[0015] Furthermore, in step 1, the interpolation algorithm uses a piecewise parabolic interpolator, the mathematical expression of which is:

[0016]

[0017] Among them, C -1 (μ) is the interpolated phase of the previous sampling point, C0(μ) is the interpolated phase of the current sampling point, C1(μ) is the estimated interpolated phase of the next sampling point, and μ is the compensation phase output by the time offset compensation module. This invention uses the value 1 / 2, which is relatively simple to implement on the hardware platform. During the operation, only a shift operation is required, avoiding multiplication operations and simplifying the computational complexity.

[0018] Furthermore, in step 2, the mathematical expression for the alpha filter is:

[0019] s[t+1] = (1-α)*s[t] + x[t+1]

[0020] Where s[t+1] is the output at the current sampling time, s[t] is the sampling output at the previous time, α is the coefficient of the alpha filter, and x[t+1] is the input at the current sampling time. This invention simplifies the expression of the alpha filter, making hardware implementation more efficient and less complex compared to filters in the prior art.

[0021] Furthermore, step 3 specifically involves:

[0022] When the estimated high signal-to-noise ratio is used, the synchronization counter 0 < T update When the value is less than 512, the loop filter coefficient C0 increases by a factor of 32, while the loop filter coefficient C1 remains unchanged; the synchronization counter 512 < T update When the value is less than 1024, the loop filter coefficient C0 increases by a factor of 16, and the loop filter coefficient C1 decreases by a factor of 4; the synchronization counter count is 1024 < T. update At that time, the loop filter coefficient C0 increases by a factor of 8, and the loop filter coefficient C1 decreases by a factor of 16;

[0023] When the estimated signal-to-noise ratio is low, the synchronization counter is 0 < T. update When the value is less than 512, the loop filter coefficient C0 increases by a factor of 16, and the loop filter coefficient C1 decreases by a factor of 4; the synchronization counter 512 < T update When the value is less than 1024, the loop filter coefficient C0 increases by a factor of 8, and the loop filter coefficient C1 decreases by a factor of 16; the synchronization counter is less than 1024. update At that time, the loop filter coefficient C0 increases by a factor of 4, and the loop filter coefficient C1 decreases by a factor of 32;

[0024] C0 is the gain coefficient of the feedback path, which determines the contribution of the feedback path to the output signal; a larger value indicates a more significant impact. C1 is the gain coefficient of the forward transmission path, which determines the amplification of the input signal in the forward transmission path. Choosing these two parameters allows for filtering and enhancement of signals at different frequencies, improving signal quality and reliability. The loop filter coefficients transition from coarse convergence mode to fine convergence mode as the number of synchronization counters increases.

[0025] After receiving the input signal, the phase detection module samples it and performs a convolution operation with the fractional phase waveform pre-stored in the waveform lookup table to obtain the E-path real part E_i and imaginary part E_q of the previous sampling point, and the L-path real part L_i and imaginary part L_q of the next sampling point, for subsequent phase difference analysis. When there is a phase difference in the signal, the phase difference Δy1 of the current input signal is calculated as follows:

[0026] Δy1=(L_i+L_q / 4)-(E_i+E_q / 4)

[0027] If Δy1 > 2, then enter the loop filter for phase correction 8; if Δy1 > 1.5, then phase correction 4; if Δy1 > 1.25, then phase correction 2; otherwise, phase correction 0.

[0028] The coarse convergence mode is used for initial adjustment to quickly eliminate large time offsets. The phase difference obtained in this mode is often relatively large, basically belonging to the stage of Δy1>2, and phase correction is performed. The fine convergence mode is used for fine adjustment to further reduce convergence error and make the synchronization process reach a high level of precision. The phase difference obtained in this mode is relatively small, and fine adjustment is gradually performed to make the phase difference 0.

[0029] Furthermore, in step 4, when the SFD frame synchronization signal is detected, the system immediately locks the time offset phase difference of the current Symbol and enters the demodulation time offset compensation module. The pulse signals in the current Symbol of the E, P and L paths are accumulated through the early and late gates to obtain the overall energy value in a Symbol.

[0030] By obtaining the difference Δy2 between the E-path energy and the L-path energy, the system will dynamically adjust the phase correction; if Δy2>4, the phase correction will be 7 in the loop filter; if Δy2>2, the phase correction will be 4; if Δy2>1.5, the phase correction will be 2; if Δy2>1.25, the phase correction will be 1; otherwise, the phase correction will be 0.

[0031] The system's phase is adjusted in real time by detecting phase differences to ensure that the signal and the reference are optimally matched. After time offset compensation and phase synchronization are completed, the compensated signal is sent to the decoding module for decoding, and finally the original baseband data is decoded to complete the entire communication process.

[0032] The beneficial effects of this invention are as follows:

[0033] 1) This invention proposes an adaptive synchronization method suitable for complex and variable channels. The number of preamble synchronizations dynamically changes according to channel conditions, and the bandwidth coefficient for time-off convergence is adjusted accordingly with the duration of the preamble. To ensure that the convergence process is neither too time-consuming nor too slow, this invention designs a time-off compensation control strategy based on the preamble length. This strategy combines time division of coarse and fine convergence modes to ensure higher adaptability in response to channel changes. The operation modes of coarse and fine convergence are controlled by real-time judgment of the preamble length. The coarse convergence mode is suitable for initial adjustments, quickly eliminating large time offsets and achieving rapid adaptation to complex channels. The fine convergence mode is used for refined adjustments, further reducing convergence errors and achieving high precision in the synchronization process. This two-stage convergence control strategy can flexibly respond to real-time fluctuations in channel conditions, ensuring optimal synchronization performance under different channel conditions. In addition, another significant advantage of the present invention is the significant reduction in power consumption. Due to the time division of coarse convergence and fine convergence and its adaptive adjustment, the long-term high-bandwidth operation that may occur in the traditional single mode is avoided, thereby effectively reducing unnecessary energy consumption.

[0034] 2) This invention provides an adaptive time offset compensation scheme for different signal-to-noise ratio (SNR) levels. It can flexibly select different precision time offset compensation methods based on the current channel conditions, thereby effectively overcoming interference problems caused by noise. In this design, by dynamically adjusting the compensation precision, the system can adjust optimally under various noise environments, achieving a significant improvement in communication reliability while reducing power consumption, thus comprehensively enhancing the overall system performance. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the UWB frame structure specified in the IEEE 802.15.4a protocol;

[0036] Figure 2 This is a flowchart of time offset tracking and compensation in traditional design;

[0037] Figure 3 This is a flowchart of the method described in this invention;

[0038] Figure 4 This is a flowchart of the time offset tracking, compensation, and demodulation part of the present invention;

[0039] Figure 5 This is a flowchart of the interpolation algorithm;

[0040] Figure 6 This is a waveform diagram of the impact response lookup table;

[0041] Figure 7This is a schematic diagram of the phase detector structure in the embodiment;

[0042] Figure 8 This is a diagram illustrating the energy accumulation process of the early and late gates E, P, and L in the embodiment.

[0043] Figure 9 This is a flowchart of the time offset tracking and compensation process of the demodulation module in the embodiment;

[0044] Figure 10 This is a schematic diagram of the convergence curve before the improvement, where the number of Preamble synchronizations was 256;

[0045] Figure 11 This is a schematic diagram of the convergence curve after the Preamble synchronization number is improved to 256;

[0046] Figure 12 This is a schematic diagram of the convergence curve before the improvement, where the number of Preamble synchronizations was 2048.

[0047] Figure 13 This is a schematic diagram of the convergence curve after the Preamble synchronization number is improved to 2048.

[0048] Figure 14 This is a diagram comparing the packet error rates of two different time-off modules;

[0049] Figure 15 This is a diagram comparing the bit error rates of two different time-off modules. Detailed Implementation

[0050] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0051] like Figure 3 He Ru Figure 4 As shown, the automatic time offset compensation method for ultra-wideband chip baseband according to the present invention includes the following steps:

[0052] Step 1: This invention addresses the case where the UWB system synchronization preamble sequence length is 127 as specified in the IEEE 802.15.4a protocol. With a preamble MPRF of 62.89MHz, a single Symbol contains a fixed 508 effective pulses. The Preamble synchronization count is set to 2048, and the signal-to-noise ratio is -5dB. When the signal enters the SHR symbol detection module, the relevant energy... Where n represents the number of Symbols, and r is the baseband signal. * Here, p is the local scrambling sequence, p is the initial phase of the received signal, k is the summation coefficient, and ΔL is the UWB spreading coefficient specified in the protocol. Begin calculating the impulse response value h for each Symbol. iand h q ,like Figure 5 ,like Figure 6 As shown; time offset can cause the loss of amplitude or phase information of the signal during the interpolation process, affecting the signal restoration or accumulation results. The impulse response lookup table provides a predefined interpolation filter response, which can accurately compensate for the error of the fractional phase, thereby minimizing the impact of time offset on the signal; the compensation phase output by the time offset compensation module adjusts the interpolation position and changes the starting phase p of the received signal in real time. Figure 6 The lookup table represents the envelope of the impulse response values ​​corresponding to different fractional delays. The lookup table is used to find the impulse response value required for the corresponding fractional delay value, which is then used for interpolation. This lookup table design not only allows for direct mapping to hardware, reducing implementation complexity, but also decreases computational complexity.

[0053] Step 2: Determine the number of preamble synchronizations. The IEEE 802.15.4a protocol specifies eight different preamble synchronization numbers, with a minimum of 64 and a maximum of 4096. If the number of preamble synchronizations is less than the experimental value of 512, amplitude estimation will continue for 16 Symbols to indicate the signal-to-noise ratio level and select the accuracy of the loop coefficients; otherwise, it will continue for 512 Symbols. During amplitude estimation, the I / Q symbols are correlated and accumulated to calculate the amplitude, which is then low-pass filtered by the alpha filter to reduce the impact of noise.

[0054] Since the number of preamble synchronizations is determined to be 2048 > 512, a longer amplitude estimation time is adopted, set to 512 Symbol times. During amplitude estimation, correlation accumulation is performed on the received I-channel real part signal and Q-channel imaginary part signal to estimate the signal amplitude. The accumulation process involves summing the squares of the I-channel and Q-channel components at each sampling point, and then calculating their amplitude values.

[0055]

[0056] Where A(t) is the amplitude at the current sampling time, and I(t) and Q(t) represent the I-path component and Q-path component at the current time, respectively. The obtained amplitude signal is input into the alpha filter for low-pass filtering to reduce the influence of noise.

[0057] The mathematical expression for the alpha filter is: s[t+1]=(1-α)*s[t]+x[t+1], where s[t+1] is the output at the current sampling time, s[t] is the sampling output at the previous time, α is the coefficient of the alpha filter, and x[t+1] is the input at the current sampling time; substituting the value of A(t) into x[t+1], we get s[t+1].

[0058] Step 3: Following the method in Step 1, the impulse response values ​​of the I / Q signals of the current (Present) phase P path, the first three (Earlier) phases E1 / E2 / E3 paths, and the last three (Later) phases L1 / L2 / L3 paths are entered into the chip time offset compensation module. Simultaneously, through the monitoring module, the signal-to-noise ratio (SNR) level is characterized by s[t+1] obtained in Step 2. That is, -5dB is considered a high SNR level, and the system uses lower precision time offset compensation to reduce computational complexity and energy consumption. In the time offset compensation module, given a high SNR and a Preamble synchronization count of 2048, the synchronization count counter is 0 < T. update When the value is less than 512, the loop filter coefficient C0 increases by a factor of 32, while the loop filter coefficient C1 remains unchanged. The synchronization counter 512 < T update When the value is less than 1024, the loop filter coefficient C0 increases by a factor of 16, and the loop filter coefficient C1 decreases by a factor of 4. The synchronization counter has a count of 1024 < T. update When the loop filter coefficient C0 is increased by a factor of 8, the loop filter coefficient C1 is decreased by a factor of 16; when the estimated signal-to-noise ratio is low, the synchronization counter 0 < T. update When the value is less than 512, the loop filter coefficient C0 increases by a factor of 16, and the loop filter coefficient C1 decreases by a factor of 4. The synchronization counter 512 < T update When the value is less than 1024, the loop filter coefficient C0 increases by a factor of 8, and the loop filter coefficient C1 decreases by a factor of 16. The synchronization counter has a count of 1024 < T. update At this time, the loop filter coefficient C0 increases by a factor of 4, while the loop filter coefficient C1 decreases by a factor of 32. This dynamic adjustment mechanism ensures finer phase adjustment under signal-to-noise ratio conditions, thereby ensuring the accuracy and stability of system synchronization.

[0059] After receiving the input signal, the phase detector module first performs specific sampling on these signals, see... Figure 7The phase detection module acquires the current phase (Present) P-channel signal, as well as the impulse response values ​​of seven sampling points from the preceding three phases (Earlier) E1, E2, E3 and the following three phases (Later) L1, L2, L3 as input, to more accurately track the phase changes of the signal. These sampling point signals are convolved with the envelope values ​​of the fractional phase waveforms pre-stored in the waveform lookup table (RRC memory) at the previous and following sampling point times to ensure the accuracy of the calculation results. This process yields the real part (E_i) and imaginary part (E_q) of the E-channel from the preceding sampling point, and the real part (L_i) and imaginary part (L_q) of the L-channel from the following sampling point. These data are used for subsequent phase difference analysis. The pre-stored waveform lookup table stores the designed waveform envelope signal R(τ), which is actually the inverse of the input signal X(τ). However, its inverse does not change the shape of the envelope. Matching filtering is performed between its envelope and the envelope of the input signal to obtain the maximum amplitude in the time domain. When the signals have no phase difference, the time-domain convolution formula is used: Y(τ) = X(τ) * R(τ + τ0), where X(μ) is the input signal, R(τ) is the signal of the pre-stored phase waveform RRC, Yi(τ) is the output signal, v is the phase sampling point, and τ0 is the phase offset point. If there is no fractional phase difference at the ideal sampling time, then Y(τ + τ0) = X(τ) * R(τ + τ0) and Y(τ - τ0) = X(τ) * R(τ - τ0) have equal peak values ​​at the fractional sampling points offset by τ = -τ0 and τ = τ0, and are symmetrical near the phase difference of 0. In reality, there may be a certain phase difference between signals, which will cause the sampling points to shift. As time goes on, the phase difference gradually accumulates, causing a change in the matching between the output signal and the reference signal.

[0060] When a phase difference exists in the signal, the result of convolution changes in the time domain. The difference between the two, Δy1 = (L_i + L_q / 4) - (E_i + e_q / 4), can be used to approximate the phase difference of the current input signal. When Δy1 > 2, phase correction 8 is performed in the loop filter; when Δy1 > 1.5, phase correction 4 is performed; when Δy1 > 1.25, phase correction 2 is performed; otherwise, phase correction 0 is performed. Then, the initial phase p of the received signal in step 1 is adjusted to compensate for this phase difference. The system uses the loop filter to provide feedback adjustment to the currently detected phase error, thereby gradually reducing the phase difference until it approaches zero.

[0061] Step 4: Upon detecting the SFD frame synchronization signal, the system immediately locks the time offset phase difference of the current Symbol and enters the demodulation time offset compensation module to continue tracking and compensation. Time offset compensation: Accumulates the pulses within the current Symbol from the E-path (representing the phase information of the previous time point), P-path (representing the phase information of the current Symbol), and L-path (representing the phase information of the next time point), such as... Figure 8 The overall energy value within a Symbol is obtained, maximizing the peak value. When there is no phase difference in the signal, the P-path energy is the ideal peak value, and the E-path energy and L-path energy are equal. When there is a phase difference in the signal, the phase difference of the current signal is approximately represented by the difference Δy2 between the E-path energy and the L-path energy. When Δy2 > 4, phase correction 7 is performed in the loop filter; when Δy2 > 2, phase correction 4; when Δy2 > 1.5, phase correction 2; when Δy2 > 1.25, phase correction 1; otherwise, phase correction 0. The phase of the system is adjusted in real time based on the detected phase difference, thereby continuously reducing the phase difference until it approaches zero, ensuring that the signal reaches the optimal matching state with the reference reference and reducing the bit error rate. After completing time offset compensation and phase synchronization, the compensated signal is sent to the decoding module for decoding, and finally the original baseband data is decoded, successfully completing the entire communication process. The time offset tracking and compensation process is as follows: Figure 9 As shown.

[0062] So far, steps 1 to 4 constitute a complete automatic time offset compensation loop. Repeating steps 1 to 4 will complete the time offset tracking and compensation of the UWB signal under the current channel environment.

[0063] The method described in this invention was used to conduct simulation experiments in an algorithm simulation system for UWB chips. The simulation system includes a frame generation module, a pulse formation module, a simulation channel module, an AD module, a synchronization module, a time offset compensation module, and a depacketization module. The actual effectiveness of the method described in this invention was verified through data packet transmission and reception simulations.

[0064] (1) Simulation experiment to verify the effectiveness of time offset compensation algorithm

[0065] According to the IEEE 802.15.4a protocol for HRP-UWB communication systems, the simulation system's transmitter is configured to operate in BPRF mode with a data rate of 6.80 Mbps. In this mode, the MPRF of the preamble is 62.89 MHz, and the MPRF of the data portion is 15.60 MHz. To simulate a complex channel environment with high noise levels, the simulation channel is configured with a signal-to-noise ratio (SNR) of -5 dB, a time offset of 10 PPM (Percent Per Million), a data packet length of 60 bytes, and a preamble sequence of 127 bits (sequence number 18) as specified in the IEEE 802.15.4a protocol. The preamble synchronization counts are a minimum of 256 and a maximum of 2048. This configuration is typical for simulation, and an 8-bit SFD sequence (sequence number 2) is used for simulation testing.

[0066] In the simulation test of time offset compensation in digital baseband, the extreme value configuration of the Preamble synchronization number is ultimately intended to cope with interference under different complex environments. The convergence curve of the module indicates its working status under the current environment.

[0067] Because time offset has a cumulative characteristic, if it is not compensated in time, it will accumulate to a certain extent and cause serious signal misalignment and constellation diagram rotation, which will lead to the convergence curve failing to converge normally. Figure 10 This demonstrates the convergence process of a traditional time-biased module with 256 Preamble synchronizations. Due to the accumulation of a large amount of time bias, synchronization ultimately fails and convergence fails. Figure 11 The convergence curve of the method of the present invention is shown. By dynamically controlling the time-bias compensation process according to the Preamble length and combining coarse convergence and fine convergence modes, the problem of non-convergence in traditional methods when the number of Preamble synchronizations is small is effectively solved.

[0068] However, this also raises another issue: controlling the convergence time. To ensure the UWB chip functions properly in complex and variable channel environments while meeting low power consumption requirements, the convergence time must be strictly controlled. An excessively long convergence time will lead to increased power consumption. Figure 12 The paper demonstrates the fine convergence process of a traditional time-biased module with 2048 preamble synchronizations. Although it eventually converges, the process is time-consuming and increases power consumption. In contrast, Figure 13 The method of the present invention is demonstrated, which avoids the problem of excessively long convergence time by combining coarse convergence and fine convergence adjustments, thereby reducing power consumption.

[0069] Simulation results show that the method of the present invention, by dynamically adjusting the time-off convergence bandwidth coefficient during the preamble duration, can not only prevent convergence failure caused by excessively long or fast convergence times, but also effectively cope with real-time changes in complex channels, thus improving the robustness of the chip baseband in complex channels.

[0070] (2) Verification of the performance of the time offset compensation algorithm in improving the signal-to-noise ratio under different signal-to-noise ratios

[0071] Another beneficial effect of the method described in this invention compared to traditional time offset compensation methods is that by judging different signal-to-noise ratio levels, time offset compensation schemes with different accuracies can be selected, overcoming the influence of noise, reducing power consumption while improving communication reliability, and further improving the overall system performance. According to the IEEE 802.15.4a protocol for HRP-UWB communication systems, the simulation system's transmitter is configured to operate in BPRF mode with a data rate of 6.80 Mbps. At this time, the MPRF of the preamble is 62.89 MHz, and the MPRF of the data section is 15.60 MHz. To simulate a complex channel environment with high noise levels, the initial signal-to-noise ratio was configured as -5dB, with a step value of -1dB, cutoff to -15dB, and a time offset of 10PPM (Percent Per Million). The simulation test used an SFD sequence with sequence number 18 and a length of 127 bits as the preamble and sequence number 2 and a length of 8 bits as the SFD sequence in the IEEE 802.15.4a protocol. The data packet length was 60 bytes, and 1000 data packets were tested each time.

[0072] Figure 14 , Figure 15 The performance comparison between the traditional time offset compensation method and the time offset compensation method of the present invention is shown when the receiving UWB transmitter transmits signals in BPRF mode. It can be seen that the time offset compensation method of the present invention has a significant performance improvement over the traditional time offset compensation method. When the signal-to-noise ratio is greater than -12dB, no packet errors or bit errors occur when receiving 1000 data packets. The overall system performance only deteriorates significantly when the signal-to-noise ratio is less than -13dB. Compared with the traditional frequency offset and time offset compensation method, it has a performance improvement of 7-8dB, enabling the UWB communication baseband to work normally in high-noise and complex environments.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to further limit the present invention. All equivalent changes made based on the description and drawings of the present invention are within the protection scope of the present invention.

Claims

1. An automatic time offset compensation method for ultra-wideband chip baseband, characterized in that, Includes the following steps: Step 1: Divide a Symbol signal entering the synchronous SHR symbol detection module into the real part of the I-path signal of the same direction component and the imaginary part of the Q-path signal of the quadrature component. Use an interpolation algorithm and output the compensation phase through the time offset compensation module to adjust the interpolation position to obtain the impulse response values ​​of the I and Q-path signals of the current phase P-path, the first three phases E1 / E2 / E3-path, and the last three phases L1 / L2 / L3-path. Step 2: Determine the number of preamble synchronizations and compare it with the experimental value. Set the amplitude estimation time. During the amplitude estimation time, perform correlation accumulation on the received I-channel real part signal and Q-channel imaginary part signal to estimate the signal amplitude. Input the obtained amplitude signal into the alpha filter for low-pass filtering. Select time offset compensation of different precision according to the signal-to-noise ratio level. Step 3: Input the impulse response value into the chip timing compensation module, and calculate the number of preamble synchronizations T based on the preamble synchronization count counter. update At the given stage, the filter coefficients are dynamically adjusted in conjunction with the signal-to-noise ratio level to achieve precise control of phase compensation. Step 4: After detecting the SFD frame synchronization signal, lock the time offset phase difference of the current Symbol, enter the time offset compensation module for tracking compensation, send the compensated signal to the decoding module for decoding, decode the original baseband data, and complete the communication. Step 3 specifically includes: When the estimated high signal-to-noise ratio is used, the synchronization count counter T update Values At that time, the loop filter coefficients Increased by 32 times, loop filter coefficient Unchanged; Synchronization Count Counter T update Values At that time, the loop filter coefficients Increased by 16 times, loop filter coefficient Reduced by a factor of 4; Synchronization count counter At that time, the loop filter coefficients Increased by 8 times, loop filter coefficient Shrink by 16 times; When the estimated signal-to-noise ratio is low, the synchronization count counter At that time, the loop filter coefficients Increased by 16 times, loop filter coefficient Reduced by a factor of 4; Synchronization count counter At that time, the loop filter coefficients Increased by 8 times, loop filter coefficient Reduced by a factor of 16; Synchronization Count Counter At that time, the loop filter coefficients Increased by 4 times, loop filter coefficient Shrink by 32 times; After receiving the input signal, i.e., the impulse response value, the phase detection module samples it and performs a convolution operation with the sampled signal and the fractional phase waveform pre-stored in the waveform lookup table. This yields the E-path real part E_i and imaginary part E_q of the previous sampling point, and the L-path real part L_i and imaginary part L_q of the next sampling point, which are then used for subsequent phase difference analysis. When a phase difference exists in the signal, the phase difference of the current input signal is... The formula is as follows: ， like If >2, then it enters the loop filter for phase correction. If >1.5, then the phase correction is 4. If the value is greater than 1.25, then the phase correction is 2; otherwise, the phase correction is 0.

2. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that, In step 1, the interpolation algorithm uses a piecewise parabolic interpolator, the mathematical expression of which is: ， in, It is the interpolated phase of the previous sampling point. It is the interpolated phase of the current sampling point. It is the interpolated phase of the predicted next sampling point. It is the compensation phase output by the time offset compensation module.

3. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that, In step 2, the mathematical expression for the alpha filter is: ， in, This is the output at the current sampling time. It is the sampled output from the previous time step. These are the coefficients of the alpha filter. It is the input at the current sampling time.

4. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that, In step 4, when the SFD frame synchronization signal is detected, the system immediately locks the time offset phase difference of the current Symbol and enters the demodulation time offset compensation module. The pulse signals in the current Symbol of the E, P and L paths are accumulated through the early and late gates to obtain the overall energy value in a Symbol. By obtaining the difference between the energy of path E and the energy of path L. The system will dynamically adjust the phase correction; if If >4, then enter the loop filter for phase correction 7. If >2, then the phase correction is 4, if If the value is greater than 1.5, then the phase correction is 2. If the value is greater than 1.25, then the phase correction is 1; otherwise, the phase correction is 0. The system's phase is adjusted in real time by detecting phase differences to ensure that the signal and the reference are optimally matched. After time offset compensation and phase synchronization are completed, the compensated signal is sent to the decoding module for decoding, and finally the original baseband data is extracted, completing the entire communication process.

Images