Wireless transmission error rate prediction

Abstract

The invention relates to wireless transmission error rate prediction. Apparatus, systems, and techniques for predicting wireless transmission error rates. In at least one embodiment, a processor includes one or more circuitry to predict one or more wireless transmission error rates based at least in part on one or more signal-to-noise ratio (SNR) measurements.

Description

Technical Field At least one embodiment relates to processing resources for performing wireless packet transmission scheduling. For example, at least one embodiment relates to a processor and / or computing system for predicting a block error rate (BLER) and generating a packet transmission order metric for Ultra-Reliable Low Latency Communication (URLLC) packets based at least in part on the predicted BLER according to various novel techniques described herein. Background Art Wireless packet scheduling and transmission consumes a lot of computing resources and time. Methods for wireless packet scheduling and transmission can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram illustrating a system according to at least one embodiment; Figure 2 A flow chart illustrating a technique for selecting a modulation and coding scheme and the number of resource blocks to use in accordance with at least one embodiment; Figure 3 A flow chart illustrating a technique for scheduling and transmitting packets in accordance with at least one embodiment; Figure 4 is a block diagram illustrating an example of a processor according to at least one embodiment; Figure 5 is a block diagram illustrating a driver and / or runtime environment according to at least one embodiment; Figure 6 An example data center system is shown in accordance with at least one embodiment; Figure 7A An example of an autonomous vehicle according to at least one embodiment is shown; Figure 7B According to at least one embodiment, Figure 7A Examples of camera positions and fields of view for autonomous vehicles in [1]. Figure 7C According to at least one embodiment Figure 7A A block diagram of an example system architecture for an autonomous vehicle in FIG. Figure 7D is a diagram illustrating a method for performing a multi-processor communication between a cloud-based server and a Figure 7A Schematic diagram of a system for communication between autonomous vehicles; Figure 8 is a block diagram illustrating a computer system according to at least one embodiment; Figure 9 is a block diagram illustrating a computer system according to at least one embodiment; Figure 10 A computer system according to at least one embodiment is shown; Figure 11A computer system according to at least one embodiment is shown; Figure 12A A computer system according to at least one embodiment is shown; Figure 12B A computer system according to at least one embodiment is shown; Figure 12C A computer system according to at least one embodiment is shown; Figure 12D A computer system according to at least one embodiment is shown; Figure 12E and Figure 12F illustrates a shared programming model according to at least one embodiment; Figure 13 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment; Figure 14A and Figure 14B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment; Figure 15A and Figure 15B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment; Figure 16 A computer system according to at least one embodiment is shown; Figure 17A A parallel processor according to at least one embodiment is shown; Figure 17B shows a partition unit according to at least one embodiment; Figure 17C illustrates a processing cluster according to at least one embodiment; Figure 17D A graphics multiprocessor is shown in accordance with at least one embodiment; Figure 18 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment; Figure 19 A graphics processor according to at least one embodiment is shown; Figure 20 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Figure 21 illustrates at least a portion of a graphics processor according to one or more embodiments; Figure 22 illustrates at least a portion of a graphics processor according to one or more embodiments; Figure 23 illustrates at least a portion of a graphics processor according to one or more embodiments; Figure 24 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Figure 25 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment; Figure 26A and Figure 26B Thread execution logic is shown, which includes an array of processing elements of a graphics processor core; Figure 27 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment; Figure 28 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment; Figure 29 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment; Figure 30 A streaming multiprocessor is shown in accordance with at least one embodiment; Figure 31 A network for transmitting data within a 5G wireless communication network according to at least one embodiment is shown; Figure 32 illustrates a network architecture for a 5G LTE wireless network according to at least one embodiment; Figure 33 is a schematic diagram illustrating some basic functions of a mobile telecommunications network / system operating according to LTE and 5G principles, according to at least one embodiment; Figure 34 illustrates a radio access network that may be part of a 5G network architecture in accordance with at least one embodiment; Figure 35 An example illustration of a 5G mobile communication system in which multiple different types of devices are used is provided according to at least one embodiment; Figure 36 An example high-level system according to at least one embodiment is shown; Figure 37 shows the architecture of a network system according to at least one embodiment; Figure 38 illustrates example components of a device according to at least one embodiment; Figure 39 illustrates an example interface for a baseband circuit according to at least one embodiment; Figure 40 An example of an uplink channel according to at least one embodiment is shown; Figure 41 shows the architecture of a network system according to at least one embodiment; Figure 42illustrates a control plane protocol stack according to at least one embodiment; Figure 43 illustrates a user plane protocol stack according to at least one embodiment; Figure 44 illustrates components of a core network according to at least one embodiment; and Figure 45 Components of a system supporting network functions virtualization (NFV) are shown in accordance with at least one embodiment. DETAILED DESCRIPTION In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it is apparent to one skilled in the art that the present invention can be practiced without one or more of these specific details. Figure 1 1 is a block diagram illustrating a system 100 according to at least one embodiment. In at least one embodiment, system 100 includes a base station 102 that communicates radio signals with a group of user equipment devices (UEs) 104. In at least one embodiment, the UEs are mobile communication devices (e.g., smartphones, cell phones, cellular-enabled tablets, and / or any other suitable wireless mobile communication devices). In at least one embodiment, base station 102 is a gNodeB (gNB). In at least one embodiment, base station 102 and the UEs in group 104 communicate according to one or more Third Generation Partnership Project (3GPP) protocols (e.g., Fifth Generation (5G) New Radio (NR), 6G, and / or some other suitable protocols and / or standards). In at least one embodiment, base station 102 uses one or more signal-to-noise ratio (SNR) measurements to predict a block error rate (BLER) of packets to be sent to the UEs in group 104, and selects a modulation and coding scheme (MCS) and number of resource blocks (RBs) to be used to transmit the packets based on the predicted BLER. In at least one embodiment, base station 102 generates one or more transmission priority metrics based at least in part on the selected number of resource blocks and schedules packets for transmission based at least in part on the generated transmission priority metrics. In at least one embodiment, UE 104 includes a first UE 106 and a second UE 108. In at least one embodiment, base station 102 includes an antenna 110 for receiving signals from UEs in UE group 104. In at least one embodiment, antenna 110 is also used to transmit signals to UEs in UE group 104. In at least one embodiment, antenna 110 is a multi-element antenna. In at least one embodiment, antenna 110 includes a group of antenna elements 112. In at least one embodiment, an antenna element in a group of antenna elements 112 is referred to as an antenna. In at least one embodiment, antenna element group 112 includes a first antenna 114 and a second antenna 116. In at least one embodiment, antenna element group 112 includes a power of two number of antennas (e.g., two, four, eight, or sixteen antennas), or some other suitable number of antennas. In at least one embodiment, signals transmitted by UEs in UE group 104 are received using multiple antennas in antenna element group 112. In at least one embodiment, signals transmitted to UEs in UE group 104 are transmitted using multiple antennas in antenna element group 112. In at least one embodiment, base station 102 includes a beamformer 152. In at least one embodiment, base station 102 will use beamforming (eg, using beamformer 152 ) to transmit and / or receive signals using antennas in antenna element group 112 . In at least one embodiment, base station 102 includes a processor 118. In at least one embodiment, base station 102 includes a memory 120. In at least one embodiment, base station 102 includes an accelerator 122. In at least one embodiment, accelerator 122 includes one or more graphics processing units (GPUs). In at least one embodiment, accelerator 122 includes one or more parallel processing units (PPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and / or some other suitable accelerator. In at least one embodiment, base station 102 includes a varying number of processors (e.g., more than one processor 118), a varying amount of memory (e.g., more than one memory 120), and / or a varying number of accelerators (e.g., more than one accelerator 122). In at least one embodiment, processor 118 is a central processing unit (CPU). In at least one embodiment, at least one component of base station 102 is included in a virtual radio access network (vRAN). In at least one embodiment, base station 102 uses multiple-input multiple-output (MIMO) (e.g., digital massive MIMO) to form beams and transmit data to multiple UEs using the same set of time and frequency resources. In at least one embodiment, UE 106 includes a processor 124. In at least one embodiment, UE 106 includes a memory 126. In at least one embodiment, UE 106 includes a different number of processors (e.g., more than one processor 124), a different number of memories (e.g., more than one memory 126), one or more accelerators, and / or one or more other suitable components (e.g., one or more user interface components, one or more antennas, and / or one or more other components), not shown for clarity. In at least one embodiment, other UEs in UE group 104 (e.g., UE 108) include components not shown for clarity, such as those shown and / or described for UE 106. In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contradicted, terms such as "module" and nominalized verbs (e.g., channel quality information generator, error rate predictor, MCS selector, channel estimator, beamformer, resource block determiner, packet transmission scheduler, BLER estimation module, MCS determination module, RB determination module, order metric generation module, packet transmission scheduling module, controller, and / or other terms) each refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry, alone or in any combination. In at least one embodiment, modules may be collectively or individually embodied as circuitry that constitutes part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), and the like. In at least one embodiment, UE 106 includes a channel quality information (CQI) generator 128. In at least one embodiment, CQI generator 128 generates CQI 130. In at least one embodiment, CQI 130 includes information that can be used to generate an SNR. In at least one embodiment, CQI 130 includes information indicative of the SNR. In at least one embodiment, UE 106 transmits CQI 130 to base station 102. In at least one embodiment, base station 102 generates one or more indications of SNR 132 based at least in part on CQI 130. In at least one embodiment, when CQI 130 includes information indicative of the SNR, base station 102 stores one or more aspects of CQI 130 as one or more indications of SNR 132. In at least one embodiment, base station 102 includes an error rate predictor 134 for predicting one or more BLERs based at least in part on one or more indications of SNR 132. In at least one embodiment, the prediction by error rate predictor 134 is referred to as estimation. In at least one embodiment, the prediction by error rate predictor 134 is referred to as generation of a predicted BLER and / or generation of an estimated BLER. In at least one embodiment, error rate predictor 134 generates one or more indications of SNR 132 based at least in part on CQI 130 received from one or more UEs. In at least one embodiment, one or more other components of base station 102 generate one or more indications of SNR 132. In at least one embodiment, error rate predictor 134 uses packet information 136 and one or more indications of SNR 132 to predict the BLER for a particular packet to be transmitted. In at least one embodiment, for each URLLC packet to be transmitted, the packet information 136 includes a BLER target (e.g., 0.001% or lower, or some other suitable value), a latency requirement (e.g., 1 millisecond (ms), 0.5 ms, or some other suitable value), a weight, and a packet size. In at least one embodiment, the packet information 136 includes one or more other types of information instead of and / or in addition to this information. In at least one embodiment, the packet information 136 includes fewer types of information and / or information about other types of packets to be transmitted. In at least one embodiment, base station 102 includes an MCS selector 138. In at least one embodiment, MCS selector 138 selects a modulation and coding scheme (e.g., identified using an MCS index) to be used for transmission of each URLLC packet based, at least in part, on the BLER predicted by error rate predictor 134 to occur using that MCS. In at least one embodiment, MCS selector 138 stores the selected MCS for each packet to be transmitted as packet MCS information 140. In at least one embodiment, the MCS level determines the relative portion of the radio transmission resources used to transmit bits and error correction information. In at least one embodiment, a higher MCS level has a higher code rate than a lower MCS level. In at least one embodiment, a modulation order (e.g., 2, 4, 6, 8, or some other suitable value) is associated with each MCS level, with some MCS levels having the same modulation order. In at least one embodiment, a particular MCS level defines the number of useful bits (e.g., not used for error correction information) to be transmitted per symbol. In at least one embodiment, base station 102 includes a resource block (RB) determiner 142. In at least one embodiment, RB determiner 142 determines the number of RBs to be used for transmission of each URLLC packet based at least in part on the BLER predicted by error rate predictor 134 to use the number of RBs. In at least one embodiment, RB determiner 142 stores the determined number of RBs to be used for transmission of each URLLC packet as RB information 144. In at least one embodiment, an RB includes 12 consecutive subcarriers in the frequency domain. In at least one embodiment, error rate predictor 134 includes MCS selector 138 and / or RB determiner 142. In at least one embodiment, the selection of an MCS is referred to as determining an MCS and / or generating an indication of an MCS to be used. In at least one embodiment, the determination of the number of RBs to be used is referred to as selecting the number of RBs to be used and / or generating an indication of the number of RBs to be used. In at least one embodiment, the base station 102 includes a packet transmission scheduler 146. In at least one embodiment, the packet transmission scheduler 146 generates one or more transmission priority metrics 148. In at least one embodiment, the transmission priority metrics 148 are referred to as scheduling metrics or some other suitable terminology. In at least one embodiment, the packet transmission scheduler 146 generates a transmission priority metric for each URLLC packet to be transmitted. In at least one embodiment, the packet transmission scheduler 146 generates a transmission priority metric for one or more other types of packets to be transmitted. In at least one embodiment, the packet transmission scheduler 146 generates the transmission priority metric 148 based at least in part on the RB information 144. In at least one embodiment, the packet transmission scheduler 146 is a sequence-based scheduler. In at least one embodiment, one or more base stations (e.g., gNodeBs such as base station 102) in a 5G NR network use multiple antenna elements (e.g., elements of antenna 110). In at least one embodiment, one or more base stations operate at least partially in a lower frequency band (e.g., sub-6 GHz range and / or millimeter wave (mmWave) band). In at least one embodiment, one or more base stations (e.g., base station 102) and UEs (e.g., UEs in UE group 104) operate using one or more of enhanced mobile broadband (eMBB), ultra-reliable low latency communications (URLLC), and / or massive machine type communications (mMTC). In at least one embodiment, to achieve high downlink user throughput, a base station (BS) performs beamforming based on channel estimation. In at least one embodiment, when downlink-uplink channel reciprocity is available, the BS obtains channel state information (CSI) by channel measurement and / or performing channel estimation using uplink signals (e.g., sounding reference signals). In at least one embodiment, the base station 102 includes a channel estimator 150 that performs channel estimation and equalization of wireless signals received at the base station 102. In at least one embodiment, the channel estimator 150 performs channel estimation based at least in part on a reference signal received from a UE (e.g., a sounding reference signal (SRS)). In at least one embodiment, the beamformer 152 is configured to calculate and / or determine one or more beam directions for transmitting one or more downlink signals based at least in part on the channel estimation (e.g., performed by the channel estimator 150). In at least one embodiment, predicting the BLER based at least in part on the SNR, selecting the MCS using the predicted BLER, determining the RB using the predicted BLER, and / or scheduling packet transmission based at least in part on the predicted BLER has advantages over conventional techniques for selecting the MCS, determining the RB, and / or scheduling packet transmission that do not predict the BLER using the SNR, at least because predicting and / or estimating the BLER based at least in part on the SNR is faster than conventional techniques for calculating the BLER and can transmit a greater number of packets in a manner that meets the requirements of URLLC communications, thereby better utilizing computing and transmission resources. In at least one embodiment, one or more techniques use mini-slots as scheduling units. In at least one embodiment, the packet transmission scheduler 146 uses mini-slots as scheduling units. In at least one embodiment, each packet (e.g., URLLC packet) has a BLER target, a latency requirement, a weight, and a packet size (e.g., stored as packet information 136). In at least one embodiment, the BLER target for packet i is represented as In at least one embodiment, the delay requirement of packet i is represented as d iIn at least one embodiment, the delay requirement is referred to as a deadline. In at least one embodiment, packets exceeding the deadline are discarded. In at least one embodiment, the weight of packet i is represented by w i In at least one embodiment, the weight is referred to as priority. In at least one embodiment, the packet size of packet i is represented as L i In at least one embodiment, the size of a packet is referred to as a length. In at least one embodiment, a packet is referred to as a user and / or more packets are referred to as users. In at least one embodiment, the number of resource blocks (RBs) allocated to packet i in mini-slot t is denoted as n i (t). In at least one embodiment, the modulation and coding scheme (MCS) of packet i in mini-slot t is denoted as m i (t). In at least one embodiment, the base station 102 determines the number of RBs to allocate to the packet and / or the MCS of the packet. In at least one embodiment, the packet transmission scheduler 146 maximizes the sum of the weights of the served packets while meeting the BLER and latency requirements of the packets. In at least one embodiment, the packet transmission scheduler 146 includes one or more of the error rate predictor 134, the MCS selector 138, and / or the RB determiner 142. In at least one embodiment, the transmission scheduler 146 is based on d i 、w i and L i Packets are scheduled in each mini-slot to ensure BLER and deadline requirements. In at least one embodiment, base station 102 schedules packets based at least in part on performing a first stage (e.g., using error rate predictor 134, MCS selector 138, and RB determiner 142) that determines a minimum number of RBs. and MCS (e.g., optimal MCS), thus and BLER target is met, where N sym is the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols per mini-slot (e.g., 2, 3, 5, or 7, depending on the system configuration), N sub is the number of subcarriers in an RB (e.g., 12 subcarriers), MCS level The data rate, L i In at least one embodiment, base station 102 schedules packets based at least in part on performing a second phase (e.g., using packet transmission scheduler 146) that schedules packets such that the size of each packet is used. To maximize the sum of the weights of the served groups. In at least one embodiment, the For use in Phase 2. In at least one embodiment, the error rate predictor 134 performs a BLER prediction. In at least one embodiment, the error rate predictor 134 performs an estimate of the BLER for a packet (e.g., a URLLC packet). In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on an indication of the SNR. In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on an indication of the SNR and the number of RBs per packet. In at least one embodiment, the error rate predictor 134 predicts the BLER using an additive white Gaussian noise (AWGN) channel assumption without frequency selective fading (e.g., all RBs have the same SNR). In at least one embodiment, the error rate predictor 134 predicts the BLER as: BLER = Where C is the channel capacity, n is the block length, V is the channel dispersion, R is the coding rate, c is the calibration term, and In at least one embodiment, this is referred to as predicting the BLER using a calibrated bound (e.g., a calibrated Polyanskiy bound). In at least one embodiment, the error rate predictor 134 uses the assumption of AWGN, such that the channel capacity C = log2(1+γ), and the channel dispersion Where γ is the SNR. In at least one embodiment, the calibration term c is a constant value (eg, 0.1 or some other suitable value). In at least one embodiment, the calibration term c to be used is a predetermined value (eg, determined using simulated decoder performance). In at least one embodiment, the calibration term c varies with different MCSs and / or RB numbers used. In at least one embodiment, the error rate predictor 134 predicts the BLER as: BLER = in is in MCS m and N b Calibration under RB conditions. In at least one embodiment, the calibration term is a predetermined value (for example, using a b In at least one embodiment, a set of calibration terms The calibration term is included to be used with each combination of MCS (e.g., each MCS level) and the number of RBs that can be used. In at least one embodiment, if a set of calibration terms does not include one or more previously determined calibration terms for one or more combinations of MCS and number of RBs, then the set of calibration terms In at least one embodiment, a set of calibration items includes one or more default calibration items to be used. is stored (e.g., in memory 120) for use by error rate predictor 134 in predicting the BLER. In at least one embodiment, a set of calibration terms The terms in are determined by the MCS m and N used to select a specific calibration term. b RB indexes or otherwise associated therewith. In at least one embodiment, for example, When 6 RBs are used at MCS=0, the BLER is 0.147, when 12 RBs are used at MCS=0, the BLER is 0.138, and when 24 RBs are used at MCS=0, the BLER is 0.139. In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on the SNR using other suitable techniques and / or based at least in part on using other suitable formulas, calibrations, and / or bounds. In at least one embodiment, the error rate predictor 134 predicts the BLER based at least in part on the SNR using one or more neural networks (NNs). In at least one embodiment, the NN used by the error rate predictor 134 is a trained NN (e.g., trained using supervised learning techniques to generate a predicted BLER based at least in part on the SNR). In at least one embodiment, one or more of the MCS selector 138 and / or the RB determiner 142 is configured to select an MCS and / or determine the number of RBs to use based at least in part on some other suitable technique. In at least one embodiment, one or more of the MCS selector 138 and / or the RB determiner 142 is operable to select an MCS and / or determine the number of RBs using one or more NNs (e.g., trained using supervised learning techniques to generate an indication of an MCS and / or number of RBs to use based at least in part on SNR, BLER requirements, packet size, and latency requirements as inputs). In at least one embodiment, base station 102 determines the minimum number of RBs to use for transmission of each packet. and MCS (e.g., optimal MCS), such that and in is the BLER target for packet i (e.g., the BLER assigned to URLLC packets, such as 0.001% or lower), and the other parameters are as described above. In at least one embodiment, one or more of the error rate predictor 134, the MCS selector 138, and the RB determiner 142 determines the minimum number of RBs. and MCS In at least one embodiment, the base station 102 determines the minimum number of RBs within a specific time duration (e.g., within a mini-slot as short as 2 symbols, where 2 symbols equal 71 microseconds under number 1). and MCS In at least one embodiment, base station 102 determines the minimum number of RBs in real time. and MCS Wherein real time refers to within a predetermined time duration (e.g., expressed in microslots, symbols, or microseconds). In at least one embodiment, one or more processors (e.g., one or more GPUs and / or other suitable accelerators, such as accelerator 122) determine in parallel and In at least one embodiment, the base station 102 determines the number of RBs to use (e.g., using the RB determiner 142) (e.g., the minimum number of RBs that meets the BLER and can transmit the packet size) based at least in part on predicting the BLER for each MCS level (e.g., each MCS level that can be used to transmit packets from the base station to the UE in 5G NR) for each packet (e.g., using the error rate predictor 134), and selects the highest MCS level that can be used while still meeting the BLER requirement for the packet (e.g., using the MCS selector 138). In at least one embodiment, the base station 102 predicts the possible BLER for each MCS level (e.g., 29 possible MCS levels (MCS 0-28) or some other suitable number of MCS levels). In at least one embodiment, the base station 102 and / or some other suitable mobile wireless network component uses an accelerator (e.g., a GPU) to predict the BLER of packets to be transmitted to UEs in one or more cells. In at least one embodiment, the use of GPUs to predict the BLER of packets can be performed in parallel to determine the MCS and number of RBs to be used for each packet, thereby meeting the URLLC BLER and latency requirements for transmitting multiple packets (e.g., when the number of packets is less than 4000, the average runtime of a single GPU is less than 40 microseconds). In at least one embodiment, the base station uses additional GPUs and / or other accelerators to expand to additional numbers of packets while still meeting the URLLC BLER and latency requirements of the packets. In at least one embodiment, the packet transmission scheduler 146 generates a metric for each packet i In at least one embodiment, packet transmission scheduler 146 stores these metrics as transmission priority metrics 148. In at least one embodiment, packets with larger v i Those packets with the same metric value have higher priority. In at least one embodiment, the packet transmission scheduler 146 arbitrarily breaks ties (e.g., by randomly or pseudo-randomly selecting one of the packets with the same metric value). In at least one embodiment, f increases with w i Increase, with and d iIn at least one embodiment, the packet transmission scheduler 146 uses an order-based scheduling that assigns an order to all packets in each mini-time slot. In at least one embodiment, the packet transmission scheduler 146 uses a scheduling strategy that assigns an order to all packets in each mini-time slot. RBs are allocated to the packet with the highest order (e.g., to completely transmit the packet), and then RBs are allocated to the packet with the second highest order, and so on. In at least one embodiment, if there are not enough RBs in a mini-slot to completely transmit a packet, the packet transmission scheduler 146 allocates all remaining RBs in the mini-slot to the packet. In at least one embodiment, the packet transmission scheduler 146 schedules at most one packet for partial transmission in each mini-slot. In at least one embodiment, partial transmission means that a packet is not completely transmitted in a particular mini-slot, and some remaining bits will be transmitted in a subsequent mini-slot. In at least one embodiment, the packet transmission scheduler 146 schedules packets for transmission using the assumption that packets arrive at the queue for transmission with a Poisson-type arrival distribution at a rate λ. In at least one embodiment, the packet transmission scheduler 146 schedules packets based, at least in part, on a technique that provides good performance (e.g., above a predetermined metric) for varying λ. In at least one embodiment, the packet transmission scheduler generates a transmission priority metric v for each packet. i , making In at least one embodiment, w i is the weight value assigned to the group, is the number of RBs to be used for transmitting packets, d i is an indication of the delay requirement of the packet, and β is the value of the transmission priority metric v when the packet transmission scheduler 146 generates i Time Impact Item relative to Term. In at least one embodiment, β is greater than zero. In at least one embodiment, β is a predetermined value (e.g., determined by simulation). In at least one embodiment, the packet transmission scheduler uses a constant value β for different packet arrival rates λ. In at least one embodiment, the packet transmission scheduler 146 uses a β value of 1. In at least one embodiment, the packet transmission scheduler 146 uses a β value greater than 1 (e.g., a higher β value when λ is smaller). In at least one embodiment, the packet transmission scheduler 146 sets the β value to minimize the drop rate Where D is the sum of the weights of the dropped packets and A is the sum of the weights of the arriving packets (e.g., packets that were successfully received after transmission). In at least one embodiment, a larger value of β is used to generate the metric in a manner that more closely resembles the Earliest Deadline First (EDF) policy, where This ensures that when λ is very small, all packets will meet their deadlines. In at least one embodiment, using smaller values ​​of β generates metrics in a manner that more closely approximates a maximum weight strategy, where This maximizes the transmission weight per RB and works well when λ is very large. In at least one embodiment, the packet transmission scheduler 146 generates the transmission priority metric using some other suitable technique and / or based at least in part on some other suitable formula. In at least one embodiment, the packet transmission scheduler 146 generates the transmission priority metric using one or more neural networks (e.g., one or more neural networks trained using supervised learning techniques to generate the transmission priority metric for the packets based at least in part on the number of RBs to use, the latency requirement, and the weight per packet). Figure 2 is a flow chart of a technique 200 for selecting a modulation and coding scheme and the number of resource blocks to use, according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 200 are determined by Figure 1 One or more aspects shown or described herein (e.g., processor 118, accelerator 122, error rate predictor 134, MCS selector 138, and / or RB determiner 142) and / or performed with respect to one or more components, techniques, and / or other aspects shown or described in other figures herein. In at least one embodiment, at block 202, technique 200 includes determining packet information and requirements. In at least one embodiment, the packet information and requirements include one or more of a BLER target for each packet, a latency requirement for each packet, a weight assigned to each packet, a packet size, and / or other suitable packet information. In at least one embodiment, the packet information and requirements are stored as packet information 136. In at least one embodiment, Figure 1 Error rate predictor 134 determines packet information stored as packet information 136 as part of the retrieved information that will be used to predict one or more BLERs using one or more indications of SNR. In at least one embodiment, at block 204, technique 200 includes predicting one or more error rates. In at least one embodiment, the error rate is a block error rate of a packet. In at least one embodiment, the error rate is a block error rate of a packet to be transmitted from a base station to a user equipment (UE) device. In at least one embodiment, Figure 1 The error rate predictor 134 at block 204 generates an error rate prediction signal based at least in part on one or more indications of SNR (e.g., Figure 1 The error rate may be predicted based on one or more indications of SNR 132) and packet information (e.g., one or more aspects of packet information 136). In at least one embodiment, at block 206, technique 200 includes determining a modulation and coding scheme. Figure 1 The MCS selector 138 of the packet determines the MCS at block 206. In at least one embodiment, determining the MCS includes storing the packet MCS information (e.g., Figure 1 In at least one embodiment, determining the MCS is based at least in part on using the determined MCS to predict a BLER that meets a BLER requirement (eg, at block 204). In at least one embodiment, at block 208, technique 200 includes determining a number of resource blocks. In at least one embodiment, a resource block is the number of resource blocks used to transmit a packet. In at least one embodiment, Figure 1 The RB determiner 142 of FIGURE 2 determines the number of RBs at block 208. In at least one embodiment, determining the number of RBs includes storing RB information (e.g., Figure 1 In at least one embodiment, determining the RB information is based at least in part on using the determined RB information to predict a BLER that meets the BLER requirement (eg, at block 204). In at least one embodiment, at block 210, technique 200 includes performing other actions. In at least one embodiment, performing other actions includes returning to block 202 to determine additional packet information and requirements for more packets (e.g., packets that have recently entered a queue for transmission). In at least one embodiment, performing other actions includes scheduling and transmitting packets (e.g., using Figure 3 Technology 300). Figure 3 is a flow chart of a technique 300 for scheduling and transmitting packets according to at least one embodiment. In at least one embodiment, one or more aspects of the technique 300 are described in detail. Figure 1 One or more aspects shown or described (e.g., processor 118, accelerator 122, and / or packet transmission scheduler 146) and / or performed with respect to one or more components, techniques, and / or other aspects shown or described in other figures herein. In at least one embodiment, at block 302, technique 300 includes determining packet information and requirements. In at least one embodiment, the packet information and requirements include the number of RBs used to transmit each packet (e.g., using Figure 1 RB information 144), weights and / or delay requirements (e.g., using Figure 1 In at least one embodiment, packet transmission scheduler 146 determines the packet information and requirements for scheduling and transmitting packets. In at least one embodiment, at block 304, technique 300 includes generating one or more metrics. In at least one embodiment, the one or more metrics include one or more transmission priority metrics (e.g., Figure 1 In at least one embodiment, Figure 1 The packet transmission scheduler 146 in generates one or more metrics at block 304 . In at least one embodiment, at block 306, technique 300 includes scheduling packet transmissions. In at least one embodiment, scheduling packet transmissions is based at least in part on one or more metrics generated at block 304. In at least one embodiment, scheduling packet transmissions includes scheduling packet transmissions in a sequence-based manner based on metric values ​​assigned to the packets. In at least one embodiment, scheduling packet transmissions includes scheduling packet transmissions in a non-sequence-based manner. In at least one embodiment, Figure 1 The packet transmission scheduler 146 schedules the packets at block 306. In at least one embodiment, scheduling packet transmissions includes scheduling packets based at least in part on the use of Figure 1 The number of RBs determined by RB determiner 142 (eg, using RB information 144) is used to allocate a particular RB to a particular packet to be transmitted. In at least one embodiment, at block 308, technique 300 includes transmitting a packet. In at least one embodiment, a base station (e.g., Figure 1 The base station 102 in the example embodiment transmits packets to one or more UEs (e.g., UEs in the UE group 104). In at least one embodiment, transmitting the packets includes transmitting the packets according to a scheduled order using RBs allocated to each packet. In at least one embodiment, transmitting the packets includes transmitting the packets using a determined MCS level to be used for each packet (e.g., packet MCS information 140). In at least one embodiment, at block 310, technique 300 includes performing other actions. In at least one embodiment, performing other actions includes returning to block 302 to determine packet information and a requirement for additional packets to be scheduled and transmitted. In at least one embodiment, performing other actions includes checking information indicating whether the packet was successfully received. In at least one embodiment, performing other actions includes retransmitting one or more packets. In at least one embodiment, Figure 2 TECH 200 and / or Figure 3 One or more aspects of the technique 300 include providing a method for providing a plurality of SNR measurements based at least in part on one or more SNR measurements (e.g., Figure 1In at least one embodiment, one or more aspects of technique 200 and / or technique 300 further include selecting an MCS based at least in part on the predicted one or more radio transmission error rates (e.g., Figure 1 In at least one embodiment, Figure 2 TECH 200 and / or Figure 3 One or more aspects of the technique 300 include selecting a number of resource blocks (e.g., Figure 1 RB information 144). In at least one embodiment, Figure 2 TECH 200 and / or Figure 3 One or more aspects of the technique 300 include selecting an MCS and a number of RBs to be used for transmitting data based at least in part on one or more predicted radio transmission error rates. In at least one embodiment, the radio transmission error rates are to be obtained from a base station (e.g., Figure 1 The block error rate (BLER) of packets transmitted by the base station 102 to one or more UE devices (e.g., one or more UEs in the UE group 104). In at least one embodiment, the wireless transmission error rate is the BLER of the packets, and Figure 2 TECH 200 and / or Figure 3 One or more aspects of the technique 300 further include selecting an MCS and a number of RBs to be used for transmitting data based at least in part on one or more predicted radio transmission error rates, and generating one or more scheduling metrics based at least in part on the number of RBs. In at least one embodiment, a non-transitory computer-readable medium has a set of instructions stored thereon that, if executed by one or more processors (e.g., Figure 1 processor 118 and / or accelerator 122, and / or Figure 4 402) will cause one or more processors to execute at least Figure 2 TECH 200 and / or Figure 3 One or more aspects of technology 300. Figure 4is a block diagram illustrating an example of a processor 400 according to at least one embodiment. In at least one embodiment, the processor 402 performs one or more processes (e.g., the processes described herein) to predict one or more BLERs based at least in part on the SNR and / or to determine an MCS to use and a number of RBs to use for transmission of one or more packets based at least in part on the predicted BLER. In at least one embodiment, the processor 402 performs one or more processes (e.g., the processes described herein) to schedule one or more packets for transmission based at least in part on the number of RBs determined using the predicted BLER. In at least one embodiment, processor 402 performs Figure 1 One or more aspects described by the processor 118, the accelerator 122, the error rate predictor 134, the MCS selector 138, the RB determiner 142, and / or the packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 ART 300 and / or Figure 5 In at least one embodiment, the processor 402 executes one or more processes, such as in conjunction with one or more APIs 510. Figure 1-3 The processes described. In at least one embodiment, processor 402 includes one or more processors, such as a processor in conjunction with Figure 1and / or one or more of the processors shown and / or described in the figures described below. In at least one embodiment, processor 402 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, processor 402 includes a block error rate (BLER) estimation module 404, a modulation and coding scheme (MCS) determination module 406, a resource block (RB) determination module 408, a sequence metric generation module 410, and a packet transmission scheduling module 412. In at least one embodiment, BLER estimation module 404, MCS determination module 406, RB determination module 408, sequence metric generation module 410, and / or packet transmission scheduling module 412 are part of processor 402 and / or one or more other processors. In at least one embodiment, the BLER estimation module 404, the MCS determination module 406, the RB determination module 408, the order metric generation module 410, and / or the packet transmission scheduling module 412 are distributed across multiple processors, which communicate via a bus, a network, writing to a shared memory, and / or any other suitable communication process (e.g., the communication process described herein). In at least one embodiment, the BLER estimation module 404 is referred to as a BLER prediction module and / or some other suitable name. In at least one embodiment, the MCS determination module 406 is referred to as an MCS selection module and / or some other suitable name. In at least one embodiment, the RB determination module 408 is referred to as an RB selection module and / or some other suitable name. In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or clearly to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, while "hardware," as used in any implementation described herein, may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware that stores instructions run and / or executed by programmable circuitry, alone or in any combination. In at least one embodiment, modules may be embodied collectively or individually as circuitry that constitutes part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or the like. In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, the BLER estimation module 404 is based at least in part on the SNR (e.g., Figure 1In at least one embodiment, the BLER estimation module 404 is a module that predicts the BLER based at least in part on the SNR. In at least one embodiment, the BLER estimation module 404 performs the following operations: Figure 1 Error rate predictor 134 and / or Figure 2 In at least one embodiment, the MCS determination module 406 is a module that determines and / or selects one or more MCSs (e.g., Figure 1 In at least one embodiment, the MCS determination module 406 performs the following steps: Figure 1 The MCS selector 138 and / or Figure 2 In at least one embodiment, the RB determination module 408 is a module that determines and / or selects the number of RBs to be used for transmitting one or more packets (e.g., Figure 1 In at least one embodiment, the RB determination module 408 performs the following steps: Figure 1 RB determiner 142 and / or Figure 2 One or more aspects of the technology 200 shown or described. In at least one embodiment, the order metric generation module 410 generates one or more order metrics (eg, Figure 1 The order metric generation module 410 performs the following steps: Figure 1 The packet transmission scheduler 146 and / or Figure 3 In at least one embodiment, the packet transmission scheduling module 412 is a module that schedules packet transmissions based at least in part on a transmission order metric generated using the order metric generation module 410. In at least one embodiment, the packet transmission scheduling module 412 includes the order metric generation module 410. In at least one embodiment, the packet transmission scheduling module performs Figure 1 The packet transmission scheduler 142 and / or Figure 3 One or more aspects of the technology 300 shown or described. In at least one embodiment, a processor (e.g., Figure 4 The processor 402 and / or Figure 1The processor 118 and / or the accelerator 122 of the embodiment of the present invention may include one or more circuits for determining the accuracy of the signal processing of the signal processing unit based at least in part on one or more SNR measurements (e.g., Figure 1 In at least one embodiment, one or more circuits are configured to select a modulation and coding scheme (e.g., packet MCS information 140) based at least in part on the predicted one or more radio transmission error rates. In at least one embodiment, one or more circuits are configured to select a number of resource blocks (e.g., Figure 1 RB information 144). In at least one embodiment, one or more circuits are configured to select a modulation and coding scheme and a number of resource blocks based at least in part on one or more predicted radio transmission error rates. In at least one embodiment, one or more SNR measurements are based at least in part on one or more channel quality indicators (e.g., Figure 1 In at least one embodiment, one or more circuits are configured to select an MCS based at least in part on the predicted one or more radio transmission error rates, and to transmit one or more packets based at least in part on the selected MCS. In at least one embodiment, one or more circuits are configured to cause a number of resource blocks to be selected based at least in part on the predicted one or more radio transmission error rates, and to cause one or more transmission priority metrics (e.g., Figure 1 148 in the transmission priority metrics), and causing one or more packets to be transmitted based at least in part on the generated one or more transmission priority metrics. In at least one embodiment, a system (e.g., Figure 1 The system 100 includes one or more processors (e.g., Figure 4 The processor 402 and / or Figure 1 118 and / or accelerator 122) for determining a signal level based at least in part on one or more SNR measurements (e.g., Figure 1 One or more radio transmission error rates are predicted based on one or more indications of the SNR 132. In at least one embodiment, the one or more radio transmission error rates are block error rates (BLERs) of packets to be transmitted to one or more UE devices. In at least one embodiment, the one or more processors are configured to cause selection of an MCS (e.g., Figure 1In at least one embodiment, the one or more processors are configured to cause selection of a number of resource blocks (e.g., Figure 1 In at least one embodiment, one or more SNR measurements are based at least in part on the RB information 144 provided by the gNodeB (e.g., Figure 1 102) from one or more UE devices (e.g., Figure 1 One or more channel quality indicators (e.g., Figure 1 In at least one embodiment, the one or more processors are further configured to cause selection of a number of resource blocks for transmission of a particular packet based at least in part on the predicted one or more radio transmission error rates, and to cause scheduling of the particular packet for transmission based at least in part on the number of resource blocks. Figure 5 5 is a block diagram illustrating a driver and / or runtime environment 500 including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, the software program 502 is a software module. In at least one embodiment, the software program 502 includes one or more software modules, including but not limited to at least Figure 4 In at least one embodiment, the software module is as described in Figure 4 In at least one embodiment, one or more APIs 510 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, executing the software instructions includes running the software instructions. In at least one embodiment, in conjunction with Figure 4 One or more aspects of the one or more software modules shown or described are embodied in part in a software program 502 (e.g., instructions and / or code that call a function when executed by a processor) and in part in one or more APIs 510 and / or functions 512 (e.g., instructions and / or code that implement the called function when executed by a processor). In at least one embodiment, one or more APIs 510 are distributed or otherwise provided as part of one or more libraries 506, drivers and / or runtimes 504 and / or any other grouping of software, non-transitory computer-readable instructions and / or executable code as further described herein. In at least one embodiment, one or more APIs 510 perform one or more computing operations in response to a call from a software program 502. In at least one embodiment, a software program 502 is a collection of software code, commands, instructions, or other text sequences that instructs a computing device to perform one or more computing operations and / or call one or more other instruction sets (e.g., APIs 510 or API functions 512) for execution. In at least one embodiment, the functionality provided by one or more APIs 510 includes software functions 512, for example, software functions that can be used to accelerate one or more portions of a software program 502 using one or more parallel processing units (PPUs) such as a graphics processing unit (GPU). In at least one embodiment, the APIs 510 and / or API functions 512 include functions for performing operations related to a particular computing device. Figure 1 error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 TECH 200 and / or Figure 3 APIs and / or functions of one or more aspects shown or described in the technology 300. In at least one embodiment, the API 510 is a hardware interface to one or more circuits for performing one or more computing operations. In at least one embodiment, the one or more software APIs 510 described herein are implemented as one or more circuits for performing the operations described herein in conjunction with Figure 1-4 In at least one embodiment, one or more software programs 502 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform the techniques described herein. Figure 1-4 In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by a driver and / or runtime 504 to manage virtual memory and / or allocate or otherwise reserve one or more blocks of memory 514 for one or more PPUs (e.g., GPUs). In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 provided by a driver and / or runtime 504 to manage virtual memory and / or allocate or otherwise reserve blocks of memory. In at least one embodiment, a software program 502 (e.g., a user-implemented software program) utilizes one or more application programming interfaces (APIs) 510 to perform various computational operations, such as memory reservations, matrix multiplications, arithmetic operations, or any computational operations performed by a parallel processing unit (PPU), such as a graphics processing unit (GPU), as further described herein. In at least one embodiment, the one or more APIs 510 provide a set of callable functions 512 (referred to herein as APIs, API functions, and / or functions) that individually perform one or more computational operations, such as computational operations associated with parallel computing. In at least one embodiment, the processor utilizes an API that includes a predicted block error rate function 516. In at least one embodiment, the predicted block error rate function 516 performs Figure 1 Error rate predictor 134, Figure 2 TECH 200 and / or Figure 4 In at least one embodiment, the processor uses an API that includes a select MCS function 518. In at least one embodiment, the select MCS function 518 performs Figure 1 MCS selector 138, Figure 2 TECH 200 and / or Figure 4 In at least one embodiment, the processor uses an API including a determine resource block (RB) number function 520. In at least one embodiment, the determine RB number function 520 performs Figure 1 RB determiner 142, Figure 2 TECH 200 and / or Figure 4 In at least one embodiment, the processor uses an API including a generate order metric function 522. In at least one embodiment, the generate order metric function 522 performs Figure 1 Packet transmission scheduler 146, Figure 3 Technology 300, Figure 4 The sequential metric generation module 410 and / or Figure 4 In at least one embodiment, the callable function set 512 includes a different number of functions (e.g., for performing Figure 4 A separate function of one or more aspects of the packet transmission scheduling module 412). In at least one embodiment, one or more software programs 502 interact or otherwise communicate with one or more APIs 510 to perform one or more computing operations using one or more PPUs (e.g., GPUs). In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations that are at least partially performed by the one or more PPUs for acceleration. In at least one embodiment, the one or more software programs 502 interact with one or more APIs 510 to facilitate parallel computing using remote or local interfaces. In at least one embodiment, an interface is software instructions that, if executed, provide access to one or more functions 512 provided by one or more APIs 510. In at least one embodiment, a software program 502 uses a native interface when a software developer compiles one or more software programs 502 in conjunction with one or more libraries 506 that include or otherwise provide access to the one or more APIs 510. In at least one embodiment, the one or more software programs 502 are statically compiled in conjunction with precompiled libraries 506 or uncompiled source code that include instructions to implement the one or more APIs 510. In at least one embodiment, the one or more software programs 502 are dynamically compiled and linked to the one or more precompiled libraries 506 that include the one or more APIs 510 using a linker. In at least one embodiment, a software program 502 uses a remote interface when the software program utilizes or otherwise communicates with a library 506 containing one or more APIs 510 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 506 containing one or more APIs 510 are executed by a remote computing service (e.g., a computing resource service provider). In another embodiment, the one or more libraries 506 containing one or more APIs 510 are executed by any other computing host that provides the one or more APIs 510 to the one or more software programs 502. In at least one embodiment, a processor executing or using one or more software programs 502 calls, uses, executes, or otherwise implements one or more APIs 510 to allocate and otherwise manage memory to be used by the software programs 502. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 to allocate and otherwise manage memory to be used by one or more portions of the software programs 502 for acceleration using one or more PPUs (e.g., GPUs or any other accelerators or processors described further herein). In at least one embodiment, an API in one or more APIs 510 is an API for facilitating parallel computing. In at least one embodiment, one or more APIs 510 include any other APIs further described herein. In at least one embodiment, one or more APIs 510 are provided by a driver and / or runtime 504. In at least one embodiment, an API in one or more APIs 510 is provided by a CUDA user-mode driver. In at least one embodiment, an API in one or more APIs 510 is provided by a CUDA runtime. In at least one embodiment, a driver 504 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 512 of an API 510 during the loading and execution of one or more portions of a software program 502. In at least one embodiment, a driver and / or runtime 504 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 512 of an API 510 during the execution of a software program 502. In at least one embodiment, one or more software programs 502 utilize one or more APIs 510 implemented or otherwise provided by a driver and / or runtime 504 to perform combined arithmetic operations by the one or more software programs 502 during execution by one or more PPUs (e.g., GPUs). Data Center Figure 6 An example data center 600 is shown in which at least one embodiment may be used. In at least one embodiment, data center 600 includes a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640. In at least one embodiment, Figure 6 As shown, the data center infrastructure layer 610 may include a resource coordinator 612, grouped computing resources 614, and node computing resources ("node CRs") 616(1)-616(N), where "N" represents any integer, positive integer. In at least one embodiment, the node CRs 616(1)-616(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 616(1)-616(N) may be servers having one or more of the above-mentioned computing resources. In at least one embodiment, the grouped computing resources 614 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 614 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination. In at least one embodiment, resource coordinator 612 may configure or otherwise control one or more nodes CR 616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, resource coordinator 612 may comprise a software design infrastructure ("SDI") management entity for data center 600. In at least one embodiment, resource coordinator 612 may comprise hardware, software, or some combination thereof. In at least one embodiment, Figure 6As shown, the framework layer 620 includes a job scheduler 632, a configuration manager 634, a resource manager 636, and a distributed file system 638. In at least one embodiment, the framework layer 620 may include a framework that supports the software 632 of the software layer 630 and / or one or more applications 642 of the application layer 640. In at least one embodiment, the software 632 or the application 642 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 620 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize the distributed file system 638 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 632 may include a Spark driver to facilitate scheduling workloads supported by the various layers of the data center 600. In at least one embodiment, the configuration manager 634 may be capable of configuring different layers, such as the software layer 630 and the framework layer 620, which includes Spark and a distributed file system 638 for supporting large-scale data processing. In at least one embodiment, the resource manager 636 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 638 and the job scheduler 632. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 614 on the data center infrastructure layer 610. In at least one embodiment, the resource manager 636 can coordinate with the resource coordinator 612 to manage these mapped or allocated computing resources. In at least one embodiment, the software 632 included in the software layer 630 may include software used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 638 of the framework layer 620. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software. In at least one embodiment, the one or more applications 642 included in the application layer 640 may include one or more types of applications used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 638 of the framework layer 620. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments. In at least one embodiment, any of configuration manager 634, resource manager 636, and resource coordinator 612 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 600 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center. In at least one embodiment, data center 600 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 600. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 600. In at least one embodiment, the data center 600 can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services. In at least one embodiment, Figure 6 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 6One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority indicator, or otherwise perform operations related to Figure 1-5 In at least one embodiment, at least one of the packet computation resource 614 and the node CR 616 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority indicators 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one of the packet computation resource 614 and the node CR 616 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 7A An example of an autonomous vehicle 700 according to at least one embodiment is shown. In at least one embodiment, autonomous vehicle 700 (alternatively referred to herein as "vehicle 700") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 700 can be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 700 can be an aircraft, a robotic vehicle, or another type of vehicle. Autonomous vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") under the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 700 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 700 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment. In at least one embodiment, the vehicle 700 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 700 may include, but is not limited to, a propulsion system 750, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 750 may be connected to a drive train of the vehicle 700, which may include, but is not limited to, a transmission, to enable propulsion of the vehicle 700. In at least one embodiment, the propulsion system 750 may be controlled in response to receiving a signal from a throttle / accelerator 752. In at least one embodiment, when the propulsion system 750 is operating (e.g., when the vehicle is traveling), a steering system 754 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 700 (e.g., along a desired path or route). In at least one embodiment, the steering system 754 may receive signals from a steering actuator 756. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 746 may be used to operate the vehicle brakes in response to signals received from a brake actuator 748 and / or brake sensors. In at least one embodiment, the controller 736 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 7A) and / or a graphics processing unit ("GPU") provides signals (e.g., representing commands) to one or more components and / or systems of the vehicle 700. For example, in at least one embodiment, the controller 736 can send signals to operate vehicle brakes via a brake actuator 748, operate a steering system 754 via one or more steering actuators 756, and operate a propulsion system 750 via one or more throttles / accelerators 752. In at least one embodiment, the one or more controllers 736 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist the driver in driving the vehicle 700. In at least one embodiment, the one or more controllers 736 may include a first controller 736 for autonomous driving functionality, a second controller 736 for functional safety functionality, a third controller 736 for artificial intelligence functionality (e.g., computer vision), a fourth controller 736 for infotainment functionality, a fifth controller 736 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 736 may handle two or more of the above functions, two or more controllers 736 may handle a single function, and / or any combination thereof. In at least one embodiment, the one or more controllers 736 provide signals for controlling one or more components and / or systems of the vehicle 700 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 758 (e.g., one or more global positioning system sensors), one or more RADAR sensors 760, one or more ultrasonic sensors 762, one or more LIDAR sensors 764, one or more inertial measurement unit (IMU) sensors 766 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 796, one or more stereo cameras 768, one or more wide angle cameras 770 (e.g., fisheye cameras), one or more infrared cameras 772, one or more surround cameras 774 (e.g., 360 degree cameras), long range cameras (e.g., infrared cameras), and / or a combination of these. Figure 7A Not shown), mid-range camera ( Figure 7A), one or more speed sensors 744 (e.g., for measuring the speed of the vehicle 700), one or more vibration sensors 742, one or more steering sensors 740, one or more brake sensors (e.g., as part of a brake sensor system 746), and / or other sensor types are received. In at least one embodiment, one or more controllers 736 may receive input (e.g., represented by input data) from a dashboard 732 of the vehicle 700 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 734, an audible annunciator, a speaker, and / or other components of the vehicle 700. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 7A ), location data (e.g., the location of the vehicle 700, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 736, etc. For example, in at least one embodiment, the HMI display 734 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.). In at least one embodiment, the vehicle 700 further includes a network interface 724 that can communicate over one or more networks using one or more wireless antennas 726 and / or one or more modems. For example, in at least one embodiment, the network interface 724 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 726 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN, SigFox, etc.) to enable communication between objects in the environment (e.g., vehicles, mobile devices). In at least one embodiment, Figure 7A At least one component shown or described is used to implement the combination Figure 1-5 In at least one embodiment, in combination with the techniques and / or functions described herein, Figure 1-5The described techniques and / or functionality can receive signals from the vehicle 700 for autonomous operation of the vehicle 700 and / or can be used to provide a remote operator with the ability to remotely control the vehicle 700. In at least one embodiment, in conjunction with Figure 1-5 The described techniques and / or functions may perform one or more operations related to transmitting information (e.g., in URLLC packets) to the vehicle 700 (e.g., using CQI and / or scheduling packets from the vehicle 700 to predict BLER). In at least one embodiment, the vehicle 700 will perform a combined Figure 1 Techniques and / or functionality may be described for one or more UEs (e.g., UE 106) in a group of UEs 104. Figure 7B According to at least one embodiment, Figure 7A Examples of camera positions and fields of view for autonomous vehicle 700 are shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on vehicle 700. In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 700. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity. In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video). In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the vehicle (e.g., reflections of the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin. In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 700 can be used for surround vision, as well as to help identify the forward path and obstacles with the assistance of one or more controllers 736 and / or control SoCs, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition). In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 770 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 7B Only one wide-angle camera 770 is shown in FIG. 1 , however, in other embodiments, any number (including zero) of wide-angle cameras 770 may be present on the vehicle 700. In at least one embodiment, any number of remote cameras 798 (e.g., a remote stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 798 may also be used for object detection and classification, as well as basic object tracking. In at least one embodiment, any number of stereo cameras 768 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 768 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 700, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 768 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that may measure the distance from the vehicle 700 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 768 may be used in addition to those described herein. In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 700 (e.g., a side view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, the surround camera 774 (e.g., Figure 7B Four surround cameras 774 (shown) can be positioned on the vehicle 700. In at least one embodiment, the one or more surround cameras 774 can include, but are not limited to, any number and combination of wide-angle cameras 770, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 700. In at least one embodiment, the vehicle 700 can use three surround cameras 774 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera. In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 700 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 798 and / or one or more mid-range cameras 776, one or more stereo cameras 768, one or more infrared cameras 772, etc.), as described herein. In at least one embodiment, Figure 7B At least one component shown or described is used to implement the combination Figure 1-5In at least one embodiment, in combination with the techniques and / or functions described herein, Figure 1-5 The described techniques and / or functionality can receive signals from the vehicle 700 for autonomous operation of the vehicle 700 and / or can be used to provide a remote operator with the ability to remotely control the vehicle 700. In at least one embodiment, in conjunction with Figure 1-5 The described techniques and / or functions may perform one or more operations related to transmitting information (e.g., in URLLC packets) to the vehicle 700 (e.g., using CQI and / or scheduling packets from the vehicle 700 to predict BLER). In at least one embodiment, the vehicle 700 will perform a combined Figure 1 Techniques and / or functionality may be described for one or more UEs (e.g., UE 106) in a group of UEs 104. Figure 7C According to at least one embodiment, Figure 7A A block diagram of an example system architecture for an autonomous vehicle 700 is provided. In at least one embodiment, Figure 7C Each of one or more components, one or more features, and one or more systems of vehicle 700 is shown as being connected via bus 702. In at least one embodiment, bus 702 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 700 that helps control various features and functions of vehicle 700, such as brake actuation, acceleration, braking, steering, wipers, etc. In one embodiment, bus 702 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 702 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 702 may be an ASIL B compliant CAN bus. In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of buses 702, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 702 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 702 may be used for collision avoidance functionality, and a second bus 702 may be used for actuation control. In at least one embodiment, each bus 702 may communicate with any component of the vehicle 700, and two or more buses 702 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips ("SoCs") 704, each of one or more controllers 736, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 700) and may be connected to a common bus, such as a CAN bus. In at least one embodiment, the vehicle 700 may include one or more controllers 736, such as those described herein with respect to Figure 7A In at least one embodiment, one or more controllers 736 can be used for multiple functions. In at least one embodiment, the controller 736 can be coupled to any of the various other components and systems of the vehicle 700 and can be used to control the vehicle 700, the artificial intelligence of the vehicle 700, the infotainment and / or other functions of the vehicle 700. In at least one embodiment, the vehicle 700 may include any number of SoCs 704. In at least one embodiment, each of the SoCs 704 may include, but is not limited to, a central processing unit ("CPU(s)") 706, a graphics processing unit ("GPU(s")) 708, one or more processors 710, one or more caches 712, one or more accelerators 714, one or more data storage devices 716, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 704 may be used to control the vehicle 700 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 704 may be combined in a system (e.g., a system of the vehicle 700) with a high-definition ("HD") map 722 that may be downloaded from one or more servers (e.g., a system of the vehicle 700) via a network interface 724. Figure 7C ) to obtain map refreshes and / or updates. In at least one embodiment, one or more CPUs 706 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 706 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 706 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 706 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 706 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 706 may be active at any given time. In at least one embodiment, one or more CPUs 706 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently powered; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 706 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, where the work is offloaded to the microcode. In at least one embodiment, the processing core is referred to as a compute unit or compute unit. In at least one embodiment, one or more GPUs 708 may include an integrated GPU (or referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 708 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 708 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 708 may include one or more streaming microprocessors, each of which may include a level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 708 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 708 may use a computing application programming interface (API). In at least one embodiment, one or more GPUs 708 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model). In at least one embodiment, one or more GPUs 708 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 708 can be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming. In at least one embodiment, one or more GPUs 708 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory. In at least one embodiment, the one or more GPUs 708 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow the one or more GPUs 708 to directly access the one or more CPU 706 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in the one or more GPUs 708 experiences a miss, an address translation request may be sent to the one or more CPUs 706. In response, in at least one embodiment, the one or more CPUs 706 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 708. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 706 and the one or more GPUs 708, thereby simplifying programming the one or more GPUs 708 and porting applications to the one or more GPUs 708. In at least one embodiment, one or more GPUs 708 may include any number of access counters that can track the frequency with which one or more GPUs 708 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors. In at least one embodiment, one or more SoCs 704 may include any number of caches 712, including those described herein. For example, in at least one embodiment, one or more caches 712 may include a level 3 ("L3") cache available to one or more CPUs 706 and one or more GPUs 708 (e.g., connected to the CPUs 706 and GPUs 708). In at least one embodiment, one or more caches 712 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used. In at least one embodiment, one or more SoCs 704 may include one or more accelerators 714 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 704 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 708 and offload some tasks of one or more GPUs 708 (e.g., freeing up more cycles of one or more GPUs 708 to perform other tasks). In at least one embodiment, one or more accelerators 714 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks ("CNN"), recurrent neural networks ("RNN"), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network ("RCNN") and a fast RCNN (e.g., as used for object detection) or other types of CNN. In at least one embodiment, one or more accelerators 714 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs") that may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and generally significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone 796; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events. In at least one embodiment, a DLA can perform any function of one or more GPUs 708, and by using an inference accelerator, for example, a designer can target any function to one or more DLAs or one or more GPUs 708. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 708 and / or one or more accelerators 714. In at least one embodiment, one or more accelerators 714 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 738, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors. In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM. In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 706. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride. In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed. In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, except on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security. In at least one embodiment, one or more accelerators 714 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to the one or more accelerators 714. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory to the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB). In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used. In at least one embodiment, one or more SoCs 704 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of an object (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses. In at least one embodiment, one or more accelerators 714 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that is used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the algorithmic domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, an autonomous vehicle, such as in vehicle 700, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations. For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm can be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching on the fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras. In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data. In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 766 associated with vehicle 700 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 764 or one or more RADAR sensors 760), etc. In at least one embodiment, one or more SoCs 704 (e.g., a hardware acceleration cluster) may include one or more data stores 716 (e.g., memory). In at least one embodiment, the one or more data stores 716 may be on-chip memory of the one or more SoCs 704 that may store neural networks to be executed on one or more GPUs 708 and / or DLAs. In at least one embodiment, the one or more data stores 716 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the one or more data stores 712 may include an L2 or L3 cache. In at least one embodiment, one or more SoCs 704 may include any number of processors 710 (e.g., embedded processors). In at least one embodiment, one or more processors 710 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 704 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, one or more SoCs 704 thermal and temperature sensor management, and / or one or more SoCs 704 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 704 may use the ring oscillator to detect the temperature of one or more CPUs 706, one or more GPUs 708, and / or one or more accelerators 714. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 704 into a lower power consumption state and / or place the vehicle 700 into a driver's safe parking pattern (e.g., bringing the vehicle 700 to a safe stop). In at least one embodiment, one or more processors 710 may further include a set of embedded processors that can be used as an audio processing engine, which can be an audio subsystem that can provide hardware with full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM. In at least one embodiment, one or more processors 710 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic. In at least one embodiment, one or more processors 710 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 710 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 710 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline. In at least one embodiment, one or more processors 710 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to generate the final video to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 770, one or more surround cameras 774, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of the SoC 704, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled. In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image. In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, and does not require one or more GPUs 708 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 708 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 708 to improve performance and responsiveness. In at least one embodiment, one or more of the SoCs 704 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface, a high-speed interface, and / or a video input block for receiving video and input from a camera. In at least one embodiment, one or more of the SoCs 704 may further include an input / output controller that may be software controlled and may be used to receive I / O signals that are not assigned to a specific role. In at least one embodiment, one or more of the SoCs 704 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 704 may be configured to process data from cameras (e.g., connected via Gigabit multimedia serial links and Ethernet channels), sensors (e.g., one or more LIDAR sensors 764, one or more RADAR sensors 760, etc., which may be connected via Ethernet channels), data from the bus 702 (e.g., vehicle 700 speed, steering wheel position, etc.), data from one or more GNSS sensors 758 (e.g., connected via Ethernet buses or CAN buses), etc. In at least one embodiment, one or more of the SoCs 704 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 706 from routine data management tasks. In at least one embodiment, one or more SoCs 704 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 704 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 714, when combined with one or more CPUs 706, one or more GPUs 708, and one or more data storage devices 716, can provide a fast and efficient platform for level 3-5 autonomous vehicles. In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles. The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined together to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 720) may include text and word recognition, thereby allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that can recognize, interpret, and provide semantic understanding of the signs and pass this semantic understanding to a path planning module running on the CPU Complex. In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: Flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the warning sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 708. In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 700. In at least one embodiment, the always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 704 provide protection against theft and / or carjacking. In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 796 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 704 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 758. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 762 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes. In at least one embodiment, the vehicle 700 may include one or more CPUs 718 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 704 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, for example, the one or more CPUs 718 may include an X86 processor. The one or more CPUs 718 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 704, and / or monitoring the status and health of one or more controllers 736 and / or an infotainment system on a chip ("infotainment SoC") 730. In at least one embodiment, the vehicle 700 may include one or more GPUs 720 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 704 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 720 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input (e.g., sensor data) from sensors of the vehicle 700. In at least one embodiment, the vehicle 700 may further include a network interface 724, which may include, but is not limited to, one or more wireless antennas 726 (e.g., one or more wireless antennas 726 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 724 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via an internet cloud service (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between the vehicle 700 and the other vehicle, and / or an indirect link may be established (e.g., via a network and over the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide the vehicle 700 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind the vehicle 700). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of the vehicle 700. In at least one embodiment, the network interface 724 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 736 to communicate over a wireless network. In at least one embodiment, the network interface 724 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols. In at least one embodiment, the vehicle 700 may further include one or more data storage devices 728, which may include, but are not limited to, off-chip (e.g., one or more SoCs 704) storage. In at least one embodiment, the one or more data storage devices 728 may include, but are not limited to, one or more memory elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data. In at least one embodiment, the vehicle 700 may further include one or more GNSS sensors 758 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 758 may be used, including, for example, but not limited to, a GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet. In at least one embodiment, the vehicle 700 may further include one or more RADAR sensors 760. In at least one embodiment, the one or more RADAR sensors 760 may be used by the vehicle 700 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the one or more RADAR sensors 760 may use the CAN bus and / or bus 702 (e.g., to transmit data generated by the one or more RADAR sensors 760) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 760 may be suitable for front, rear, and side RADAR use. In at least one embodiment, the one or more RADAR sensors 760 are pulse Doppler RADAR sensors. In at least one embodiment, one or more RADAR sensors 760 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 760 can help distinguish between static and moving objects and can be used by the ADAS system 738 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 760 included in the long-range RADAR system may include, but are not limited to, a single-base multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas can create a focused beam pattern designed to record the surroundings of the vehicle 700 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas can expand the field of view, allowing for rapid detection of vehicles 700 entering or leaving the lane. In at least one embodiment, as an example, the medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, the short-range RADAR system may include, but is not limited to, any number of RADAR sensors 760 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 738 for blind spot detection and / or lane change assistance. In at least one embodiment, the vehicle 700 may further include one or more ultrasonic sensors 762. In at least one embodiment, one or more ultrasonic sensors 762, which may be positioned at the front, rear, and / or side of the vehicle 700, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 762 may be used, and different ultrasonic sensors 762 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 762 may operate at an ASIL B functional safety level. In at least one embodiment, the vehicle 700 can include one or more LIDAR sensors 764. In at least one embodiment, the one or more LIDAR sensors 764 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 764 can operate at functional safety level ASIL B. In at least one embodiment, the vehicle 700 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 764 that can use Ethernet (e.g., provide data to a Gigabit Ethernet switch). In at least one embodiment, the one or more LIDAR sensors 764 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 764 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors 764 may be used. In such an embodiment, the one or more LIDAR sensors 764 may comprise a small device that can be embedded in the front, rear, side, and / or corner locations of the vehicle 700. In at least one embodiment, the one or more LIDAR sensors 764 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 764 may be configured for a horizontal field of view between 45 and 135 degrees. In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 700. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 700 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 700. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data. In at least one embodiment, the vehicle may further include one or more IMU sensors 766. In at least one embodiment, the one or more IMU sensors 766 may be located at the center of the rear axle of the vehicle 700. In at least one embodiment, the one or more IMU sensors 766 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 766 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 766 may include, but not limited to, accelerometers, gyroscopes, and magnetometers. In at least one embodiment, one or more IMU sensors 766 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 766 can enable the vehicle 700 to estimate heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 766 without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 766 and one or more GNSS sensors 758 can be combined in a single integrated unit. In at least one embodiment, the vehicle 700 can include one or more microphones 796 positioned within and / or around the vehicle 700. In at least one embodiment, the one or more microphones 796 can be used for emergency vehicle detection and identification, among other things. In at least one embodiment, the vehicle 700 may further include any number of camera types, including one or more stereo cameras 768, one or more wide angle cameras 770, one or more infrared cameras 772, one or more surround cameras 774, one or more long range cameras 798, one or more mid range cameras 776, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 700. In at least one embodiment, the type of camera used depends on the vehicle 700. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 700. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 700 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 7A and Figure 7B Each camera can be described in more detail. In at least one embodiment, the vehicle 700 can further include one or more vibration sensors 742. In at least one embodiment, the one or more vibration sensors 742 can measure vibrations of components (e.g., axles) of the vehicle 700. For example, in at least one embodiment, changes in vibration can indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 742 are used, the difference between the vibrations can be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft). In at least one embodiment, the vehicle 700 may include an ADAS system 738. In at least one embodiment, the ADAS system 738 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 738 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof. In at least one embodiment, the ACC system may utilize one or more RADAR sensors 760, one or more LIDAR sensors 764, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle in close proximity to the vehicle 700 and automatically adjusts the speed of the vehicle 700 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 700 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW. In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 724 and / or one or more wireless antennas 726. In at least one embodiment, a direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while an indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 700 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 700, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion. In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 760, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses. In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or braking on impending collisions. In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 700 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 700 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 700. In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 700 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 700 itself decides whether to follow the results of the primary computer or the secondary computer (e.g., the first controller 736 or the second controller 736). For example, in at least one embodiment, the ADAS system 738 can be a backup and / or auxiliary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 738 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation. In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result. In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 704. In at least one embodiment, the ADAS system 738 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the main computer, and the different software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer will not cause a significant error. In at least one embodiment, the output of the ADAS system 738 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 738 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives. In at least one embodiment, the vehicle 700 may further include an infotainment SoC 730 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 730 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 730 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 700. For example, the infotainment SoC 730 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 734, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 730 may be further configured to provide information (e.g., visual and / or auditory) to a vehicle user, such as information from an ADAS system 738, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information. In at least one embodiment, the infotainment SoC 730 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 730 can communicate with other devices, systems, and / or components of the vehicle 700 via bus 702 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 730 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of the main controller 736 (e.g., the vehicle's 700 main computer and / or backup computer). In at least one embodiment, the infotainment SoC 730 can cause the vehicle 700 to enter a driver-to-safety stop mode, as described herein. In at least one embodiment, the vehicle 700 may further include an instrument panel 732 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 732 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). The instrument panel 732 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 730 and the instrument panel 732. In at least one embodiment, the instrument panel 732 may be included as part of the infotainment SoC 730, and vice versa. In at least one embodiment, Figure 7C At least one component shown or described is used to implement the combination Figure 1-5 In at least one embodiment, in combination with the techniques and / or functions described herein, Figure 1-5 The described techniques and / or functionality can receive signals from the vehicle 700 for autonomous operation of the vehicle 700 and / or can be used to provide a remote operator with the ability to remotely control the vehicle 700. In at least one embodiment, in conjunction with Figure 1-5 The described techniques and / or functions may perform one or more operations related to transmitting information (e.g., in URLLC packets) to the vehicle 700 (e.g., using CQI and / or scheduling packets from the vehicle 700 to predict BLER). In at least one embodiment, the vehicle 700 will perform a combined Figure 1 Techniques and / or functionality may be described for one or more UEs (e.g., UE 106) in a group of UEs 104. Figure 7D In accordance with at least one embodiment, a cloud-based server and Figure 7A7. A diagram of a system 777 for communicating between autonomous vehicles 700 and a plurality of autonomous vehicles 700. In at least one embodiment, system 777 may include, but is not limited to, one or more servers 778, one or more networks 790, and any number and type of vehicles, including vehicle 700. In at least one embodiment, one or more servers 778 may include, but are not limited to, multiple GPUs 784(A)-784(H) (collectively referred to herein as GPUs 784), PCIe switches 782(A)-782(D) (collectively referred to herein as PCIe switches 782), and / or CPUs 780(A)-780(B) (collectively referred to herein as CPUs 780). GPUs 784, CPUs 780, and PCIe switches 782 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 788 and / or PCIe connections 786 developed by NVIDIA. In at least one embodiment, GPUs 784 are connected via NVLink and / or NVSwitch SoCs, and GPUs 784 and PCIe switches 782 are connected via PCIe interconnects. In at least one embodiment, although eight GPUs 784, two CPUs 780, and four PCIe switches 782 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 778 may include, but is not limited to, any combination of any number of GPUs 784, CPUs 780, and / or PCIe switches 782. For example, in at least one embodiment, one or more servers 778 may each include eight, sixteen, thirty-two, and / or more GPUs 784. In at least one embodiment, one or more servers 778 may receive image data representing an image from a vehicle via one or more networks 790 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 778 may transmit a neural network 792, an updated neural network 792, and / or map information 794, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 790. In at least one embodiment, updates to the map information 794 may include, but not limited to, updates to the HD map 722, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 792, the updated neural network 792, and / or the map information 794 may be generated based on new training and / or experience derived from data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 778 and / or other servers). In at least one embodiment, one or more servers 778 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 790, and / or the machine learning model can be used by one or more servers 778 to remotely monitor the vehicle. In at least one embodiment, one or more servers 778 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 778 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 784, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 778 can include the deep learning infrastructure of a data center using CPU power. In at least one embodiment, the deep learning infrastructure of one or more servers 778 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 700. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 700, such as an image sequence and / or objects that the vehicle 700 has located in that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 700, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 700 is malfunctioning, the one or more servers 778 may send a signal to the vehicle 700 to instruct the vehicle's 700 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver. In at least one embodiment, one or more servers 778 may include one or more GPUs 784 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-powered servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers powered by CPUs, FPGAs, and other processors can be used for inference.

[0001] Computer system Figure 8 800, which may include an execution unit to execute instructions. In at least one embodiment, the computer system 800 may include, but is not limited to, components such as a processor 802, whose execution unit includes logic to execute algorithms for processing data in accordance with the present disclosure, such as the embodiments described herein. In at least one embodiment, the computer system 800 may include a processor such as the Intel® processor 802 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment. In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the system 800 is a single-processor desktop or server system, but in another embodiment, the system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800. In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register. In at least one embodiment, an execution unit 808, including but not limited to logic for performing integer and floating point operations, is also located in the processor 802. In at least one embodiment, the processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in the instruction set of the general-purpose processor 802, as well as associated circuitry for executing the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 802. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may not require transferring smaller units of data across the processor's data bus to perform one or more operations one data element at a time. In at least one embodiment, execution unit 808 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another storage device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802. In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814. In at least one embodiment, the computer system 800 may use system I / O 822, which is a proprietary hub interface bus, to couple the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a legacy I / O controller 823 including a user input and keyboard interface, a serial expansion port 827 (e.g., a universal serial bus (USB)), and a network controller 834. In at least one embodiment, the data store 824 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. In at least one embodiment, Figure 8 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 8 A system on a chip (SoC) may be shown. In at least one embodiment, Figure 8 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 800 are interconnected using a Compute Express Link (CXL) interconnect. In at least one embodiment, Figure 8 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 8 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, at least one of the processor 802 and the graphics card 812 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one of the processor 802 and the graphics card 812 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 in accordance with at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device. In at least one embodiment, the system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 910 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 9 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 9An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 9 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines. In at least one embodiment, Figure 9 The system may include a display 924, a touch screen 925, a touchpad 930, a near field communication unit ("NFC") 945, a sensor hub 940, a thermal sensor 939, a fast chipset ("EC") 935, a trusted platform module ("TPM") 938, a BIOS / firmware / flash memory ("BIOS, FW Flash") 922, a DSP 960, a drive "SSD or HDD" 920 (e.g., a solid-state disk ("SSD") or a hard disk drive ("HDD")), a wireless local area network unit ("WLAN") 950, a Bluetooth unit 952, a wireless wide area network unit ("WWAN") 956, a global positioning system (GPS) 955, a camera ("USB 3.0 camera") 954 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented in, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner. In at least one embodiment, other components may be communicatively coupled to the processor 910 via the components described above. In at least one embodiment, an accelerometer 941, an ambient light sensor (“ALS”) 942, a compass 943, and a gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, a thermal sensor 939, a fan 937, a keyboard 936, and a touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, a speaker 963, an earpiece 964, and a microphone (“mic”) 965 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 964, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 964 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF). In at least one embodiment, Figure 9 At least one component shown or described in Figure 1-5In at least one embodiment, Figure 9 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, the processor 910 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating a transmission priority metric 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, the processor 910 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 10 A computer system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1000 is configured to implement the various processes and methods described throughout this disclosure. In at least one embodiment, computer system 1000 includes, but is not limited to, at least one central processing unit ("CPU") 1002 connected to a communication bus 1010 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1000 includes, but is not limited to, main memory 1004 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1004 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1022 provides an interface to other computing devices and networks for receiving data from computer system 1000 and transmitting data to other systems. In at least one embodiment, computer system 1000 includes, but is not limited to, input device 1008, parallel processing system 1012, and display device 1006, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1008 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the aforementioned modules can be located on a single semiconductor platform to form a processing system. In at least one embodiment, Figure 10 At least one component shown or described in Figure 1-5 Related technologies and / or functions. In at least one embodiment, Figure 10 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform operations related to Figure 1-5 In at least one embodiment, at least one of the parallel processing system 1012 and the CPU 1002 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one of the parallel processing system 1012 and the CPU 1002 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 11 A computer system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1100 includes, but is not limited to, a computer 1110 and a USB stick 1120. In at least one embodiment, computer 1110 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1110 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer. In at least one embodiment, the USB stick 1120 includes, but is not limited to, a processing unit 1130, a USB interface 1140, and USB interface logic 1150. In at least one embodiment, the processing unit 1130 can be any instruction execution system, device, or device capable of executing instructions. In at least one embodiment, the processing unit 1130 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1130 includes an application-specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1130 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1130 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning inference operations. In at least one embodiment, USB interface 1140 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1140 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1140 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1150 can include any number and type of logic that enables processing unit 1130 to connect to a device (e.g., computer 1110) via USB connector 1140. In at least one embodiment, Figure 11 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 11 One or more components shown or described herein include logic or functions for predicting one or more radio transmission error rates, determining and / or selecting an MCS and / or number of RBs, generating a transmission priority metric, or performing a combination thereof based at least in part on one or more SNR measurements. Figure 1-5 In at least one embodiment, the computer 1110 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating a transmission priority metric 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, the computer 1110 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 12A An exemplary architecture is shown in which multiple GPUs 1210-1213 are communicatively coupled to multiple multi-core processors 1205-1206 via high-speed links 1240-1243 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, high-speed links 1240-1243 support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. Furthermore, in one embodiment, two or more GPUs 1210-1213 are interconnected via high-speed links 1229-1230, which may be implemented using the same or different protocols / links as used for high-speed links 1240-1243. Similarly, two or more multi-core processors 1205-1206 may be connected via high-speed link 1228, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 12A All communications between the various system components shown in . In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to processor memory 1201-1202 via memory interconnects 1226-1227, respectively, and each GPU 1210-1213 is communicatively coupled to GPU memory 1220-1223 via GPU memory interconnects 1250-1253, respectively. Memory interconnects 1226-1227 and 1250-1253 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1201-1202 and GPU memory 1220-1223 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1201-1202 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy). As described herein, although the various processors 1205-1206 and GPUs 1210-1213 may each be physically coupled to a specific memory 1201-1202, 1220-1223, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 1201-1202 may each include 64GB of system memory address space, and the GPU memories 1220-1223 may each include 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example). Figure 12B 12 shows additional details for the interconnection between the multi-core processor 1207 and the graphics acceleration module 1246 according to an exemplary embodiment. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card that is coupled to the processor 1207 via the high-speed link 1240. Alternatively, the graphics acceleration module 1246 may be integrated on the same package or chip as the processor 1207. In at least one embodiment, the illustrated processor 1207 includes a plurality of cores 1260A-1260D, each having a translation lookaside buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, the cores 1260A-1260D may include various other components, not shown, for executing instructions and processing data. The caches 1262A-1262D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1256 may be included in the caches 1262A-1262D and shared by each group of cores 1260A-1260D. For example, one embodiment of the processor 1207 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1207 and the graphics acceleration module 1246 are connected to the system memory 1214, which may include Figure 12A Processor memory 1201-1202 in. Coherence is maintained for data and instructions stored in the various caches 1262A-1262D, 1256, and system memory 1214 via inter-core communication over the coherence bus 1264. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1264 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1264 to snoop cache accesses. In one embodiment, proxy circuitry 1225 communicatively couples graphics acceleration module 1246 to coherence bus 1264, thereby allowing graphics acceleration module 1246 to participate in a cache coherence protocol as a peer of cores 1260A-1260D. Interface 1235 provides connectivity to proxy circuitry 1225 via high-speed link 1240 (e.g., PCIe bus, NVLink, etc.), and interface 1237 connects graphics acceleration module 1246 to link 1240. In one implementation, the accelerator integrated circuit 1236 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1231, 1232, N of the graphics acceleration module 1246. The graphics processing engines 1231, 1232, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, N may selectively comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1246 may be a GPU having multiple graphics processing engines 1231-1232, N, or the graphics processing engines 1231-1232, N may be individual GPUs integrated into a common package, line card, or chip. In one embodiment, the accelerator integrated circuit 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1214. The MMU 1239 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1238 may store commands and data for efficient access by graphics processing engines 1231-1232, N. In one embodiment, data stored in cache 1238 and graphics memory 1233-1234, M is kept consistent with core caches 1262A-1262D, 1256, and system memory 1214. As previously described, this task may be accomplished via proxy circuitry 1225 acting on behalf of cache 1238 and graphics memory 1233-1234, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1262A-1262D, 1256 to cache 1238 and receiving updates from cache 1238). A set of registers 1245 stores context data for threads executed by graphics processing engines 1231, 1232, N, and context management circuitry 1248 manages thread contexts. For example, context management circuitry 1248 can perform save and restore operations to save and restore the context of each thread during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1248 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon a context switch. The register values ​​can then be restored upon returning to the context. In one embodiment, interrupt management circuitry 1247 receives and processes interrupts received from system devices. In one implementation, the MMU 1239 translates virtual / effective addresses from the graphics processing engine 1231 into real / physical addresses in the system memory 1214. One embodiment of the accelerator integrated circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. The graphics accelerator module 1246 can be dedicated to a single application executing on the processor 1207, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1231, 1232, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications. In at least one embodiment, the accelerator integrated circuit 1236 acts as a bridge to the system for the graphics acceleration module 1246 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1236 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1231-1232. Because the hardware resources of the graphics processing engines 1231-1232, N are explicitly mapped into the real address space seen by the host processor 1207, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 1236 is to physically separate the graphics processing engines 1231-1232, N so that they appear to the system as independent units. In at least one embodiment, one or more graphics memories 1233-1234, M are respectively coupled to each graphics processing engine 1231-1232, N. Graphics memories 1233-1234, M store instructions and data, which are processed by each graphics processing engine 1231-1232, N. Graphics memories 1233-1234, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, to reduce data traffic on link 1240, biasing techniques can be used to ensure that the data stored in graphics memories 1233-1234, M is the data most frequently used by graphics processing engines 1231-1232, N, and preferably is not used (at least not frequently) by cores 1260A-1260D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1231-1232, N) in the cores' caches 1262A-1262D, 1256 and system memory 1214. Figure 12C Another exemplary embodiment is shown in which an accelerator integrated circuit 1236 is integrated into the processor 1207. In this embodiment, the graphics processing engines 1231-1232, N communicate directly with the accelerator integrated circuit 1236 via interfaces 1237 and 1235 (which may also utilize any form of bus or interface protocol) through a high-speed link 1240. The accelerator integrated circuit 1236 can perform operations related to Figure 12BThe operations described above are identical to those described above. However, due to its close proximity to the coherence bus 1264 and caches 1262A-1262D, 1256, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1236 and a programming model controlled by the graphics acceleration module 1246. In at least one embodiment, graphics processing engines 1231-1232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition. In at least one embodiment, graphics processing engines 1231-1232, N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1231-1232, N to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1231-1232, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1231-1232, N to provide access to each process or application. In at least one embodiment, the graphics acceleration module 1246 or each graphics processing engine 1231-1232, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in the system memory 1214 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1231-1232, N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list. Figure 12DAn exemplary accelerator integrated slice 1290 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1236. The application effective address space 1282 in the system memory 1214 stores a process element 1283. In one embodiment, the process element 1283 is stored in response to a GPU call 1281 from an application 1280 executing on the processor 1207. The process element 1283 includes the process state of the corresponding application 1280. The work descriptor (WD) 1284 included in the process element 1283 can be a single job requested by the application, or can include a pointer to a job queue. In at least one embodiment, the WD 1284 is a pointer to a job request queue in the address space 1282 of the application. The graphics acceleration module 1246 and / or the individual graphics processing engines 1231-1232, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1284 to the graphics acceleration module 1246 to start a job in a virtualized environment can be included. In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns a graphics acceleration module 1246 or an individual graphics processing engine 1231. Since the hypervisor initializes the accelerator integrated circuit 1236 for the owned partition when the graphics acceleration module 1246 is owned by a single process, the operating system initializes the accelerator integrated circuit 1236 for the owned process when the graphics acceleration module 1246 is assigned. In operation, the WD fetch unit 1291 in the accelerator integrated slice 1290 fetches the next WD 1284, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1246. Data from the WD 1284 can be stored in registers 1245 and used by the MMU 1239, interrupt management circuitry 1247, and / or context management circuitry 1248, as shown. For example, one embodiment of the MMU 1239 includes segment / page roaming circuitry for accessing segment / page tables 1286 within the OS virtual address space 1285. The interrupt management circuitry 1247 can process interrupt events 1292 received from the graphics acceleration module 1246. When executing graphics operations, the effective addresses 1293 generated by the graphics processing engines 1231-1232, N are converted into real addresses by the MMU 1239. In one embodiment, the same set of registers 1245 is replicated for each graphics processing engine 1231-1232, N, and / or graphics acceleration module 1246, and the registers 1245 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1290. Example registers that can be initialized by the hypervisor are shown in Table 1. Example registers that may be initialized by the operating system are shown in Table 2. In one embodiment, each WD 1284 is specific to a particular graphics acceleration module 1246 and / or graphics processing engine 1231-1232, N. It includes all the information necessary for the graphics processing engine 1231-1232, N to complete the work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be done. Figure 12E 1296 , which virtualizes the graphics acceleration module engine for the operating system 1295 . In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1246. In at least one embodiment, there are two programming models where the graphics acceleration module 1246 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing. In this model, the hypervisor 1296 owns the graphics acceleration module 1246 and makes its functionality available to all operating systems 1295. For the graphics acceleration module 1246 to support virtualization through the hypervisor 1296, the graphics acceleration module 1246 may adhere to the following: (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1246 must provide a context save and restore mechanism, (2) the graphics acceleration module 1246 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1246 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1246 processes must be ensured when operating in a directed shared programming model. In at least one embodiment, an application 1280 is required to make an operating system 1295 system call using a graphics acceleration module 1246 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1246 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1246 and can take the form of a graphics acceleration module 1246 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 1246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1236 and graphics acceleration module 1246 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1296 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 1283. In at least one embodiment, the CSRP is one of the registers 1245 that contains the effective address of an area in the application's address space 1282 for the graphics acceleration module 1246 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory. Upon receiving the system call, the operating system 1295 may verify that the application 1280 has been registered and granted permission to use the graphics acceleration module 1246. The operating system 1295 then uses The information shown in Table 3 is used to call the management program 1296. Upon receiving the hypervisor call, the hypervisor 1296 verifies that the operating system 1295 has registered and been granted permission to use the graphics acceleration module 1246. The hypervisor 1296 then places the process element 1283 into a linked list of process elements of the corresponding graphics acceleration module 1246 type. The process element may include the information shown in Table 4. In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1290 registers 1245 . like Figure 12F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 1201-1202 and GPU memories 1220-1223. In this implementation, operations executed on GPUs 1210-1213 utilize the same virtual / effective memory address space to access processor memories 1201-1202, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1201, a second portion is allocated to second processor memory 1202, a third portion is allocated to GPU memory 1220, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1201-1202 and GPU memories 1220-1223, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory. In one embodiment, bias / coherency management circuitry 1294A-1294E within one or more MMUs 1239A-1239E ensures cache coherency between the caches of one or more host processors (e.g., 1205) and GPUs 1210-1213 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. In at least one embodiment, while Figure 12F Multiple instances of bias / coherence management circuits 1294A- 1294E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1205 and / or within an accelerator integrated circuit 1236 . One embodiment allows GPU attached memory 1220-1223 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU attached memory 1220-1223 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows software of the host processor 1205 to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU attached memory 1220-1223 without cache coherence overhead can be critical to the execution time of offloaded computations. For example, in situations with large amounts of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1210-1213. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading. In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1220-1223, with or without a bias cache in GPUs 1210-1213 (e.g., to cache frequently / recently used entries in the bias table). Alternatively, the entire bias table can be maintained within the GPU. In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1220-1223 is accessed, resulting in the following operations. First, local requests from GPUs 1210-1213 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1220-1223. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1205 (e.g., via a high-speed link as described above). In one embodiment, requests from processor 1205 that find the requested page in the host processor bias complete a request similar to a normal memory read. Alternatively, requests directed to GPU biased pages can be forwarded to GPUs 1210-1213. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism. One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1205 bias to GPU bias, but not for the reverse migration. In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1205. To access these pages, processor 1205 may request access from GPU 1210, which may or may not immediately grant access. Therefore, to reduce communication between processor 1205 and GPU 1210, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1205, and vice versa. In at least one embodiment, utilizing Figures 12A-12F One or more of the components shown or described in the embodiment of the present invention can be combined to realize Figure 1-5 In at least one embodiment, the techniques and / or functions described herein are Figure 12A One or more components shown or described in FIG. 1 include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, regarding Figure 12A -F at least one GPU and / or multi-core processor includes logic or otherwise predicts one or more wireless transmission error rates based on one or more SNR measurements, determines and / or selects an MCS and / or number of RBs, generates a transmission priority metric, or otherwise performs a combination of Figure 1-5 Describes the operation. Figure 12A -F is used to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmission. In at least one embodiment, Figure 12A -F at least one GPU and / or multi-core processor performs Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510. Figure 13 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Figure 13is a block diagram illustrating an exemplary system on a chip integrated circuit 1300 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1300 includes peripheral or bus logic, including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I2S / I2C controller 1340. In at least one embodiment, integrated circuit 1300 may include a display device 1345 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industry Processor Interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1370 . In at least one embodiment, Figure 13 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 13 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, the graphics processor 1310 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating a transmission priority metric 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. ... Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figures 14A-14B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Figures 14A-14B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 14A An exemplary graphics processor 1410 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Figure 14B An additional exemplary graphics processor 1440 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, Figure 14A The graphics processor 1410 is a low power graphics processor core. In at least one embodiment, Figure 14B The graphics processor 1440 is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1410, 1440 can be Figure 13 A variant of the graphics processor 1310. In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D through 1415N-1 and 1415N). In at least one embodiment, the graphics processor 1410 can execute different shader programs via separate logic, such that the vertex processor 1405 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1415A-1415N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1415A-1415N use the primitives and vertex data generated by the vertex processor 1405 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1415A-1415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API. In at least one embodiment, graphics processor 1410 additionally includes one or more memory management units (MMUs) 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, one or more MMUs 1420A-1420B provide a mapping of virtual to physical addresses for graphics processor 1410, including mapping of virtual to physical addresses for vertex processor 1405 and / or fragment processors 1415A-1415N, which may reference vertex or image / texture data stored in memory in addition to reference to vertex or image / texture data stored in one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1505, graphics processor 1515, and / or video processor 1520 of FIG. 15 , so that each processor 1505-1520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable graphics processor 1410 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection. In at least one embodiment, graphics processor 1440 includes Figure 14A 14. In at least one embodiment, graphics processor 1440 includes one or more MMUs 1420A-1420B, caches 1425A-1425B, and circuit interconnects 1430A-1430B of graphics processor 1410. In at least one embodiment, graphics processor 1440 includes one or more shader cores 1455A-1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F through 1455N-1 and 1455N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1440 includes an inter-core task manager 1445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1455A-1455N and a tiling unit 1458 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches. In at least one embodiment, using Figure 14A and 14BAt least one component shown or described in the embodiment is implemented in combination Figure 1-5 In at least one embodiment, Figure 14A One or more components shown or described in and / or 14B include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, the graphics processor 1410 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating a transmission priority metric 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. ... Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figures 15A-15B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 15A Shows that can be included in Figure 13 Graphics core 1500 within graphics processor 1310 of FIG. 1 , and in at least one embodiment, may be such as Figure 14B Unified shader cores 1455A-1455N are shown. Figure 15B A highly parallel, general-purpose graphics processing unit 1530 suitable for deployment on a multi-chip module in at least one embodiment is shown. In at least one embodiment, graphics core 1500 includes a shared instruction cache 1502, texture units 1518, and cache / shared memory 1520, which are common to execution resources within graphics core 1500. In at least one embodiment, graphics core 1500 may include multiple slices 1501A-1501N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1500. Slices 1501A-1501N may include support logic including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and a set of registers 1510A-1510N. In at least one embodiment, slices 1501A-1501N may include a set of additional function units (AFUs 1512A-1512N), floating point units (FPUs 1514A-1514N), integer arithmetic logic units (ALUs 1516A-1516N), address calculation units (ACUs 1513A-1513N), double-precision floating point units (DPFPUs 1515A-1515N), and matrix processing units (MPUs 1517A-1517N). In at least one embodiment, the FPUs 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1515A-1515N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1516A-1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1517A-1517N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 1512A-1512N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.). In at least one embodiment, using Figure 15A At least one component shown or described in the Figure 1-5 In at least one embodiment, Figure 15A One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5In at least one embodiment, at least one graphics processor 1500 is used to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one graphics processor 1500 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 15B A general purpose processing unit (GPGPU) 1530 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1530 can be directly linked to other instances of GPGPU 1530 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1530 includes a host interface 1532 to enable connection to a host processor. In at least one embodiment, host interface 1532 is a PCI Express interface. In at least one embodiment, host interface 1532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1530 receives commands from the host processor and uses a global scheduler 1534 to assign execution threads associated with those commands to a group of compute clusters 1536A-1536H. In at least one embodiment, compute clusters 1536A-1536H share a cache memory 1538. In at least one embodiment, cache memory 1538 may serve as a higher level of cache for cache memory within compute clusters 1536A-1536H. In at least one embodiment, GPGPU 1530 includes memory 1544A-1544B coupled to compute clusters 1536A-1536H via a set of memory controllers 1542A-1542B. In at least one embodiment, memory 1544A-1544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, computing clusters 1536A-1536H each include a set of graphics cores, e.g. Figure 15A The graphics core 1500 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1536A-1536H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations. In at least one embodiment, multiple instances of GPGPU 1530 can be configured to function as a compute cluster. In at least one embodiment, the communications used by compute clusters 1536A-1536H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 to a GPU link 1540, enabling direct connections to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 reside in separate data processing systems and communicate via a network device accessible through host interface 1532. In at least one embodiment, GPU link 1540 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1532 . In at least one embodiment, the GPGPU 1530 can be configured to train a neural network. In at least one embodiment, the GPGPU 1530 can be used within an inference platform. In at least one embodiment, where the GPGPU 1530 is used for inference, the GPGPU can include fewer compute clusters 1536A-1536H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1544A-1544B can differ between the inference and training configurations, with the higher bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1530 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network. In at least one embodiment, using Figure 15B At least one component shown or described is implemented in combination Figure 1-5 In at least one embodiment, the techniques and / or functions described herein are Figure 15B One or more components shown or described include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, at least one GPGPU 1530 is used to perform the selection of packet MCS information 140, the determination of RB information 144, the generation of transmission priority metrics 148, the generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one GPGPU 1530 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 16A block diagram of a computer system 1600 is shown, according to at least one embodiment. In at least one embodiment, computer system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604, which communicates via an interconnect path that may include a memory hub 1605. In at least one embodiment, memory hub 1605 may be a separate component within a chipset assembly or may be integrated within one or more processors 1602. In at least one embodiment, memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, I / O subsystem 1611 includes an I / O hub 1607, which enables computer system 1600 to receive input from one or more input devices 1608. In at least one embodiment, I / O hub 1607 enables a display controller, which may be included in one or more processors 1602, to provide output to one or more display devices 1610A. In at least one embodiment, the one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices. In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to the memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 can be any of a number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1612 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one of one or more display devices 1610A coupled via the I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1610B. In at least one embodiment, system storage unit 1614 can be connected to I / O hub 1607 to provide a storage mechanism for computer system 1600. In at least one embodiment, I / O switch 1616 can be used to provide an interface mechanism to enable connections between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1620. In at least one embodiment, network adapter 1618 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices. In at least one embodiment, computer system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1607. In at least one embodiment, interconnection may be achieved using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 16 Communication paths for various components in a SoC, such as NV-Link high-speed interconnect or interconnect protocol. In at least one embodiment, one or more parallel processors 1612 include circuits optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuits optimized for general-purpose processing. In at least one embodiment, the components of computer system 1600 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, memory hub 1605, processor 1602, and I / O hub 1607 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 1600 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1600 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computer system. In at least one embodiment, Figure 16 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 16One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, at least one of the processor 1602 and the parallel processor 1612 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one of the processor 1602 and the parallel processor 1612 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. processor Figure 17A 1700 in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1700 is shown as a processor according to an exemplary embodiment. Figure 16 A variation of the one or more parallel processors 1612 is shown. In at least one embodiment, parallel processor 1700 includes parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I / O unit 1704 can be directly connected to other devices. In at least one embodiment, I / O unit 1704 connects to other devices using a hub or switch interface (e.g., memory hub 1705). In at least one embodiment, the connection between memory hub 1705 and I / O unit 1704 forms a communication link. In at least one embodiment, I / O unit 1704 is connected to a host interface 1706 and a memory crossbar switch 1716, where host interface 1706 receives commands for performing processing operations and memory crossbar switch 1716 receives commands for performing memory operations. In at least one embodiment, when host interface 1706 receives command buffers via I / O unit 1704, host interface 1706 can direct work operations to execute those commands to front end 1708. In at least one embodiment, front end 1708 is coupled to scheduler 1710, which is configured to distribute commands or other work items to processing cluster array 1712. In at least one embodiment, scheduler 1710 ensures that processing cluster array 1712 is properly configured and in a valid state before distributing tasks to processing cluster array 1712. In at least one embodiment, scheduler 1710 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1712. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 1712 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1712 by scheduler 1710 logic within a microcontroller that includes scheduler 1710 . In at least one embodiment, processing cluster array 1712 may include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of processing cluster array 1712 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1710 may allocate work to clusters 1714A-1714N of processing cluster array 1712 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 1710 or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by processing cluster array 1712. In at least one embodiment, different clusters 1714A-1714N of processing cluster array 1712 may be assigned to process different types of programs or to perform different types of computations. In at least one embodiment, processing cluster array 1712 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1712 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1712 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations. In at least one embodiment, processing cluster array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1712 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1712 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1702 may transfer data from system memory via I / O units 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory. In at least one embodiment, when parallel processing unit 1702 is used to perform graphics processing, scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1714A-1714N of processing cluster array 1712. In at least one embodiment, portions of processing cluster array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1714A-1714N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1714A-1714N for further processing. In at least one embodiment, processing cluster array 1712 can receive processing tasks to be executed via scheduler 1710, which receives commands defining the processing tasks from front end 1708. In at least one embodiment, a processing task can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 1710 can be configured to obtain an index corresponding to a task, or can receive the index from front end 1708. In at least one embodiment, front end 1708 can be configured to ensure that processing cluster array 1712 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.). In at least one embodiment, each of one or more instances of parallel processing unit 1702 can be coupled to parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 can be accessed via memory crossbar 1716, which can receive memory requests from processing cluster array 1712 and I / O unit 1704. In at least one embodiment, memory crossbar 1716 can access parallel processor memory 1722 via memory interface 1718. In at least one embodiment, memory interface 1718 can include a plurality of partition units (e.g., partition unit 1720A, partition unit 1720B, through partition unit 1720N), which can each be coupled to a portion of parallel processor memory 1722 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 1720A-1720N are configured to be equal to the number of memory cells, such that the first partition unit 1720A has a corresponding first memory cell 1724A, the second partition unit 1720B has a corresponding memory cell 1724B, and the Nth partition unit 1720N has a corresponding Nth memory cell 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of memory devices. In at least one embodiment, memory units 1724A-1724N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 may be eliminated in favor of a unified memory design that utilizes system memory in combination with local cache memory. In at least one embodiment, any of the clusters 1714A-1714N in the processing cluster array 1712 can process data to be written to any memory unit 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 can be configured to transmit the output of each cluster 1714A-1714N to any partition unit 1720A-1720N or another cluster 1714A-1714N, which can perform other processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with a memory interface 1718 via the memory crossbar 1716 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1716 has connections to memory interface 1718 for communicating with I / O unit 1704, and to local instances of parallel processor memory 1722, thereby enabling processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to parallel processing unit 1702. In at least one embodiment, memory crossbar 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N. In at least one embodiment, multiple instances of parallel processing unit 1702 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1702 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1702 or parallel processor 1700 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. Figure 17B is a block diagram of a partition unit 1720 according to at least one embodiment. In at least one embodiment, the partition unit 1720 is Figure 17A1720N。In at least one embodiment, the partition unit 1720 includes an L2 cache 1721, a frame buffer interface 1725 and an ROP 1726 (raster operation unit). The L2 cache 1721 is a read / write cache that is configured to perform load and store operations received from the memory crossbar switch 1716 and the ROP 1726. In at least one embodiment, the L2 cache 1721 outputs read misses and urgent write back requests to the frame buffer interface 1725 for processing. In at least one embodiment, updates can also be sent to the frame buffer via the frame buffer interface 1725 for processing. In at least one embodiment, the frame buffer interface 1725 communicates with memory units in the parallel processor memory (such as Figure 17A interacts with one of the memory units 1724A-1724N (e.g., within parallel processor memory 1722). In at least one embodiment, ROP 1726 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1726 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1726 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1726 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis. In at least one embodiment, ROP 1726 is included within each processing cluster (e.g., Figure 17A In at least one embodiment, read and write requests for pixel data are transmitted through the memory crossbar 1716 rather than through the pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device such as a Figure 16 1610), routed by processor 1602 for further processing, or by Figure 17A One of the processing entities within parallel processor 1700 is routed for further processing. Figure 17C is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 17AIn at least one embodiment, processing cluster 1714 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster. In at least one embodiment, the operation of the processing cluster 1714 can be controlled by a pipeline manager 1732 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 Figure 17A Scheduler 1710 receives instructions and manages the execution of these instructions via graphics multiprocessor 1734 and / or texture unit 1736. In at least one embodiment, graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 1714. In at least one embodiment, one or more instances of graphics multiprocessor 1734 may be included within processing cluster 1714. In at least one embodiment, graphics multiprocessor 1734 may process data, and data crossbar 1740 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 1732 may facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossbar 1740. In at least one embodiment, each graphics multiprocessor 1734 within a processing cluster 1714 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present. In at least one embodiment, instructions transmitted to processing cluster 1714 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1734. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1734. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1734, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1734. In at least one embodiment, the graphics multiprocessor 1734 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 1734 can abandon the internal cache and use cache memory within the processing cluster 1714 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 can also access a partition unit (e.g., Figure 17A L2 cache within partition units 1720A-1720N) of the graphics multiprocessor 1734 is shared across all processing clusters 1714 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1734 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1702 can be used as global memory. In at least one embodiment, processing cluster 1714 includes multiple instances of graphics multiprocessor 1734, which can share common instructions and data, which can be stored in L1 cache 1748. In at least one embodiment, each processing cluster 1714 may include a memory management unit ("MMU") 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1745 may reside in Figure 17A1718. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1745 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1734 or L1 cache or processing cluster 1714. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss. In at least one embodiment, processing clusters 1714 can be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs processed tasks to a data crossbar 1740 to provide the processed tasks to another processing cluster 1714 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 1716. In at least one embodiment, a preROP 1742 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1734 and direct the data to a ROP unit, which can communicate with a partition unit (e.g., a partition unit) as described herein. Figure 17A In at least one embodiment, the PreROP 1742 unit may perform optimizations for color blending, organize pixel color data, and perform address translation. In at least one embodiment, using Figures 17A-17C At least one component shown or described in the Figure 1-5 In at least one embodiment, one or more components shown or described in FIG. 17 include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5In at least one embodiment, at least one parallel processor 1700 is used to perform the selection of packet MCS information 140, the determination of RB information 144, the generation of transmission priority metrics 148, the generation of one or more indications of SNR 132, and / or one or more other aspects of predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one parallel processor 1700 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 17D A graphics multiprocessor 1734 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1734 is coupled to a pipeline manager 1732 of a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general purpose graphics processing unit (GPGPU) cores 1762, and one or more load / store units 1766. The GPGPU cores 1762 and the load / store units 1766 are coupled to a cache memory 1772 and a shared memory 1770 via a memory and cache interconnect 1768. In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, the instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In at least one embodiment, the instruction unit 1754 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 1762. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 1766. In at least one embodiment, register file 1758 provides a set of registers for the functional units of graphics multiprocessor 1734. In at least one embodiment, register file 1758 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 1762, load / store unit 1766) connected to graphics multiprocessor 1734. In at least one embodiment, register file 1758 is divided between each functional unit such that a dedicated portion of register file 1758 is allocated to each functional unit. In at least one embodiment, register file 1758 is divided between the different warps being executed by graphics multiprocessor 1734. In at least one embodiment, the GPGPU cores 1762 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1734. In at least one embodiment, the GPGPU cores 1762 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1762 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1734 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic. In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit. In at least one embodiment, memory and cache interconnect 1768 is an interconnect network that connects each functional unit of graphics multiprocessor 1734 to register file 1758 and shared memory 1770. In at least one embodiment, memory and cache interconnect 1768 is a crossbar interconnect that allows load / store unit 1766 to perform load and store operations between shared memory 1770 and register file 1758. In at least one embodiment, register file 1758 can operate at the same frequency as GPGPU core 1762, resulting in very low latency for data transfers between GPGPU core 1762 and register file 1758. In at least one embodiment, shared memory 1770 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1734. In at least one embodiment, cache memory 1772 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 1736. In at least one embodiment, shared memory 1770 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1772, threads executing on GPGPU core 1762 may programmatically store data in shared memory. In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions included in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions. In at least one embodiment, using Figure 17D At least one component shown or described in the Figure 1-5 In at least one embodiment, Figure 17D One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5In at least one embodiment, at least one graphics multiprocessor 1734 is used to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one graphics multiprocessor 1734 performs operations related to Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 18 A multi-GPU computing system 1800 is shown in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, host interface switch 1804 is a PCI Express switch device that couples processor 1802 to a PCI Express bus, over which processor 1802 can communicate with GPGPUs 1806A-D. GPGPUs 1806A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 1816. In at least one embodiment, GPU-to-GPU links 1816 connect to each of GPGPUs 1806A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 1816 enable direct communication between each GPGPU 1806A-D without requiring communication through host interface bus 1804 to which processor 1802 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 1816, host interface bus 1804 remains available for system memory access or communication with other instances of multi-GPU computing system 1800, e.g., via one or more network devices. While in at least one embodiment, GPGPUs 1806A-D are connected to processor 1802 via host interface switch 1804, in at least one embodiment, processor 1802 includes direct support for P2P GPU link 1816 and can connect directly to GPGPUs 1806A-D. In at least one embodiment, Figure 18At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 18 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, at least one GPGPU 1806 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one GPGPU 1806 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 19 FIG1 is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, graphics processor 1900 includes a ring interconnect 1902, a pipeline front end 1904, a media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, ring interconnect 1902 couples graphics processor 1900 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1900 is one of many processors integrated within a multi-core processing system. In at least one embodiment, graphics processor 1900 receives batches of commands via ring interconnect 1902. In at least one embodiment, the incoming commands are interpreted by command streamer 1903 in pipeline front end 1904. In at least one embodiment, graphics processor 1900 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, command streamer 1903 provides commands to geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, command streamer 1903 provides commands to video front end 1934, which is coupled to media engine 1937. In at least one embodiment, media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing, and a multi-format encoding / decoding (MFX) 1933 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A. In at least one embodiment, graphics processor 1900 includes scalable thread execution resources featuring modular cores 1980A-1980N (sometimes referred to as core slices), each graphics core having multiple sub-cores 1950A-1950N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1900 can have any number of graphics cores 1980A-1980N. In at least one embodiment, graphics processor 1900 includes graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, graphics processor 1900 is a low-power processor having a single sub-core (e.g., 1950A). In at least one embodiment, graphics processor 1900 includes multiple graphics cores 1980A-1980N, each graphics core including a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each of the sub-cores 1950A-1950N, 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, Figure 19 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 19 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, at least one graphics processor 1900 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. In at least one embodiment, at least one graphics processor 1900 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. Figure 1processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 20 is a block diagram illustrating a microarchitecture for processor 2000, which may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, processor 2000 may execute instructions including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), and the like. In at least one embodiment, processor 2010 may include registers for storing packed data, such as the 64-bit-wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in integer and floating-point form, may operate with packed data elements with Single Instruction Multiple Data ("SIMD") and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit-wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, processor 2010 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference. In at least one embodiment, the processor 2000 includes an in-order front end ("front end") 2001 to fetch instructions to be executed and prepare the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2001 may include several units. In at least one embodiment, an instruction prefetcher 2026 retrieves instructions from memory and provides the instructions to an instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2028 decodes the received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2028 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2030 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2034 for execution. In at least one embodiment, when trace cache 2030 encounters a complex instruction, microcode ROM 2032 provides the microinstructions necessary to complete the operation. In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2028. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2032. In at least one embodiment, the trace cache 2030 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2032 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2032 completes the micro-op sequencing for the instruction, the front end 2001 of the machine may resume fetching micro-ops from the trace cache 2030. In at least one embodiment, an out-of-order execution engine ("OOO engine") 2003 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. In at least one embodiment, the OOO engine 2003 includes, but is not limited to, an allocator / register renamer 2040, a memory microinstruction queue 2042, an integer / floating-point microinstruction queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2004, and a simple floating-point scheduler ("simple FP scheduler") 2006. In at least one embodiment, the fast scheduler 2002, the slow / general purpose floating-point scheduler 2004, and the simple floating-point scheduler 2006 are also collectively referred to as "microinstruction schedulers 2002, 2004, 2006." In at least one embodiment, the allocator / register renamer 2040 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2040 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2040 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2042 for memory operations and an integer / floating-point microinstruction queue 2044 for non-memory operations, preceding the memory scheduler 2046 and the microinstruction schedulers 2002, 2004, and 2006. In at least one embodiment, the microinstruction schedulers 2002, 2004, and 2006 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2002 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2004 and the simple floating-point scheduler 2006 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2002, 2004, 2006 arbitrate among dispatch ports to schedule microinstructions for execution. In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / branch network 2008, floating-point register file / branch network ("FP register file / branch network") 2010, address generation units ("AGUs") 2012 and 2014, fast arithmetic logic units ("fast ALUs") 2016 and 2018, slow arithmetic logic unit ("slow ALU") 2020, floating-point ALU ("FP") 2022, and floating-point move unit ("FP move") 2024. In at least one embodiment, integer register file / branch network 2008 and floating-point register file / bypass network 2010 are also referred to herein as "register files 2008, 2010." In at least one embodiment, AGUs 2012 and 2014, fast ALUs 2016 and 2018, slow ALU 2020, floating-point ALU 2022, and floating-point move unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024." In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination). In at least one embodiment, register files 2008 and 2010 may be arranged between microinstruction schedulers 2002, 2004, and 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / branch network 2008 performs integer operations. In at least one embodiment, floating-point register file / branch network 2010 performs floating-point operations. In at least one embodiment, each of register files 2008 and 2010 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2008 and 2010 can communicate data with each other. In at least one embodiment, integer register file / branch network 2008 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2010 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide. In at least one embodiment, execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024 may execute instructions. In at least one embodiment, register files 2008 and 2010 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2000 may include, but is not limited to, any number of execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024, and combinations thereof. In at least one embodiment, floating-point ALU 2022 and floating-point move unit 2024 may execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2022 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware may be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2016 and 2018. In at least one embodiment, the fast ALUs 2016 and 2018 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to the slow ALU 2020, as the slow ALU 2020 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by the ALUs 2012 and 2014. In at least one embodiment, the fast ALUs 2016, 2018, and 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALUs 2016, 2018, and 2020 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2022 and floating point shift unit 2024 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2022 and floating point shift unit 2024 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions. In at least one embodiment, microinstruction schedulers 2002, 2004, and 2006 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2000, processor 2000 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations. In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data. In at least one embodiment, Figure 20 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 20 One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, at least one processor 2000 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. ... Figure 1processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 21 A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2100 includes one or more processors 2102 and one or more graphics processors 2108, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2102 or processor cores 2107. In at least one embodiment, system 2100 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, the system 2100 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the system 2100 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2100 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2100 is a television or set-top box device having one or more processors 2102 and a graphical interface generated by one or more graphics processors 2108. In at least one embodiment, one or more processors 2102 each include one or more processor cores 2107 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2107 is configured to process a specific instruction set 2109. In at least one embodiment, the instruction set 2109 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computed by very long instruction words (VLIW). In at least one embodiment, the processor cores 2107 can each process a different instruction set 2109, which can include instructions that contribute to emulating other instruction sets. In at least one embodiment, the processor cores 2107 can also include other processing devices, such as a digital signal processor (DSP). In at least one embodiment, the processor 2102 includes a cache memory 2104. In at least one embodiment, the processor 2102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2102. In at least one embodiment, the processor 2102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 2107 using known cache coherence techniques. In at least one embodiment, the processor 2102 further includes a register file 2106. The processor may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2106 may include general purpose registers or other registers. In at least one embodiment, one or more processors 2102 are coupled to one or more interface buses 2110 to transmit communication signals, such as address, data, or control signals, between the processors 2102 and other components in the system 2100. In at least one embodiment, the interface bus 2110 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2110 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2102 includes an integrated memory controller 2116 and a platform controller hub 2130. In at least one embodiment, the memory controller 2116 facilitates communication between memory devices and other components of the processing system 2100, while the platform controller hub (PCH) 2130 provides connections to input / output (I / O) devices via a local I / O bus. In at least one embodiment, the memory device 2120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, the memory device 2120 can be used as system memory for the processing system 2100 to store data 2122 and instructions 2121 for use when one or more processors 2102 execute applications or processes. In at least one embodiment, the memory controller 2116 is also coupled to an optional external graphics processor 2112, which can communicate with one or more graphics processors 2108 in the processors 2102 to perform graphics and media operations. In at least one embodiment, a display device 2111 can be connected to the processor 2102. In at least one embodiment, the display device 2111 can include one or more internal display devices, such as in a mobile electronic device or laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2111 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications. In at least one embodiment, the platform controller hub 2130 enables peripheral devices to connect to the storage device 2120 and the processor 2102 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2146, a network controller 2134, a firmware interface 2128, a wireless transceiver 2126, a touch sensor 2125, and a data storage device 2124 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2128 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2134 can enable network connections to wired networks. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2110. In at least one embodiment, the audio controller 2146 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2100 includes an optional legacy I / O controller 2140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 2130 can also be connected to one or more universal serial bus (USB) controllers 2142, which connect input devices such as a keyboard and mouse 2143 combination, a camera 2144, or other USB input devices. In at least one embodiment, instances of the memory controller 2116 and the platform controller hub 2130 may be integrated into a discrete external graphics processor, such as the external graphics processor 2112. In at least one embodiment, the platform controller hub 2130 and / or the memory controller 2116 may be external to one or more processors 2102. For example, in at least one embodiment, the system 2100 may include the external memory controller 2116 and the platform controller hub 2130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2102. In at least one embodiment, Figure 21 At least one component shown or described in Figure 1-5 In at least one embodiment, Figure 21One or more components shown or described herein include logic or otherwise to predict one or more radio transmission error rates based on one or more SNR measurements, determine and / or select an MCS and / or number of RBs, generate a transmission priority metric, or otherwise perform a combination thereof. Figure 1-5 In at least one embodiment, the at least one graphics processor 2108 is configured to perform one or more other aspects of selecting packet MCS information 140, determining RB information 144, generating transmission priority metrics 148, generating one or more indications of SNR 132, and / or predicting BLER based on SNR and / or scheduling wireless packet transmissions. ... Figure 1 processor 118, accelerator 122, processor 124, error rate predictor 134, MCS selector 138, RB determiner 142 and / or packet transmission scheduler 146, Figure 2 Technology 200, Figure 3 Technology 300, Figure 4 The processor 402 and / or Figure 5 At least one aspect of one or more APIs 510 described. Figure 22 is a block diagram of a processor 2200 having one or more processor cores 2202A-2202N, an integrated memory controller 2214, and an integrated graphics processor 2208, in accordance with at least one embodiment. In at least one embodiment, the processor 2200 may include additional cores, up to and including the additional core 2202N represented by the dashed box. In at least one embodiment, each processor core 2202A-2202N includes one or more internal cache units 2204A-2204N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2206. In at least one embodiment, the internal cache units 2204A-2204N and the shared cache unit 2206 represent a cache memory hierarchy within the processor 2200. In at least one embodiment, the cache memory units 2204A-2204N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2206 and 2204A-2204N. In at least one embodiment, the processor 2200 may further include a set of one or more bus controller units 2216 and a system agent core 2210. In at least one embodiment, the one or more bus controller units 2216 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2210 provides management functions for various processor components. In at least one embodiment, the system agent core 2210 includes one or more integrated memory controllers 2214 to manage access to various external memory devices (not shown). In at least one embodiment, one or more processor cores 2202A-2202N include support for simultaneous multithreading. In at least one embodiment, system agent core 2210 includes components for coordinating and operating cores 2202A-2202N during multithreaded processing. In at least one embodiment, system agent core 2210 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 2202A-2202N and graphics processor 2208. In at least one embodiment, the processor 2200 further includes a graphics processor 2208 for performing graphics processing operations. In at least one embodiment, the graphics processor 2208 is coupled to a shared cache unit 2206 and a system agent core 2210 including one or more integrated memory controllers 2214. In at least one embodiment, the system agent core 2210 further includes a display controller 2211 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2211 may also be a separate module coupled to the graphics processor 2208 via at least one interconnect, or may be integrated within the graphics processor 2208. In at least one embodiment, a ring-based interconnect 2212 is used to couple the internal components of the processor 2200. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2208 is coupled to the ring interconnect 2212 via an I / O link 2213. In at least one embodiment, I / O link 2213 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various proces...

Claims

1. A processor, comprising: One or more circuits are configured to predict one or more wireless transmission error rates based at least in part on one or more signal-to-noise ratio (SNR) measurements.

2. The processor according to claim 1, wherein: The one or more circuits are configured to cause selection of a modulation and coding scheme based at least in part on the one or more wireless transmission error rates.

3. The processor according to claim 1, wherein: The one or more circuits are configured to cause selection of a number of resource blocks based at least in part on the one or more radio transmission error rates.

4. The processor according to claim 1, wherein: The one or more circuits are configured to cause selection of a modulation and coding scheme and a number of resource blocks based at least in part on the one or more wireless transmission error rates.

5. The processor according to claim 1, wherein: The one or more SNR measurements are based at least in part on one or more channel quality indications between the base station and one or more user equipment (UE) devices.

6. The processor of claim 1, wherein: The one or more circuits are configured to cause selection of a modulation and coding scheme based at least in part on the one or more wireless transmission error rates and to cause transmission of one or more packets based at least in part on the modulation and coding scheme.

7. The processor according to claim 1, wherein: The one or more circuits are configured to: cause a number of resource blocks to be selected based at least in part on the one or more radio transmission error rates; cause one or more transmission priority metrics to be generated based at least in part on the number of resource blocks; and causing transmission of one or more packets based at least in part on the one or more transmission priority metrics.

8. A system comprising: One or more processors configured to predict one or more wireless transmission error rates based at least in part on one or more signal-to-noise ratio (SNR) measurements.

9. The system according to claim 8, wherein: The one or more radio transmission error rates are block error rates BLER of packets to be transmitted to one or more user equipment UE devices.

10. The system according to claim 8, wherein: The one or more processors are configured to cause selection of a modulation and coding scheme based at least in part on the one or more wireless transmission error rates.

11. The system according to claim 8, wherein: The one or more processors are configured to cause selection of a number of resource blocks for transmission of a particular packet based at least in part on the one or more wireless transmission error rates.

12. The system according to claim 8, wherein: The one or more SNR measurements are based at least in part on one or more channel quality indications received by the gNodeB from one or more user equipment (UE) devices.

13. The system according to claim 8, wherein: The one or more processors are further configured to cause selection of a number of resource blocks for transmission of a particular packet based at least in part on the one or more radio transmission error rates and to schedule the particular packet for transmission based at least in part on the number of resource blocks.

14. A method comprising: One or more wireless transmission error rates are predicted based at least in part on the one or more signal-to-noise ratio (SNR) measurements.

15. The method according to claim 14, further comprising: A modulation and coding scheme is selected based at least in part on the one or more wireless transmission error rates.

16. The method according to claim 14, further comprising: A number of resource blocks to be used for transmitting data is selected based at least in part on the one or more radio transmission error rates.

17. The method according to claim 14, further comprising: A modulation and coding scheme and a number of resource blocks to be used to transmit data are selected based at least in part on the one or more radio transmission error rates.

18. The method according to claim 14, wherein: The radio transmission error rate is a block error rate BLER of packets to be transmitted from a base station to one or more user equipment UE devices.

19. The method according to claim 14, wherein: The radio transmission error rate is a block error rate BLER of the packet, and the method further comprises: selecting a modulation and coding scheme MCS and a number of resource blocks to be used for transmitting data based at least in part on the one or more radio transmission error rates; and generating one or more scheduling metrics based at least in part on the number of resource blocks.

20. A non-transitory computer readable medium having stored thereon a set of instructions which, when executed by one or more processors, cause the one or more processors to at least perform the method of claim 14.

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