A link error checking method, device, apparatus and readable storage medium

Abstract

The application discloses a link error checking method, comprising the following steps: acquiring switch identification information corresponding to each switch; acquiring line connection relationships between each switch and each uplink device and each downlink device; determining port identification numbers corresponding to each switch identification information according to the line connection relationships; acquiring state flag bits of each index item of each port corresponding to each port identification number; and performing link error checking according to the state flag bits of each index item of each port. The application has the advantages of improving error detection accuracy, enhancing system stability and reliability, shortening troubleshooting time and reducing maintenance cost. The application also discloses a link error checking device, equipment and storage medium, which have corresponding technical effects.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer application, in particular to a link error checking method, device, equipment and computer readable storage medium. BACKGROUND

[0002] In computer and communication systems, the performance and reliability of switches are crucial. As a key channel for data transmission, the stability and accuracy of Peripheral Component Interconnect Express (PCIe) links directly affect the operation of the entire system.

[0003] However, the uplink and downlink PCIe links with switch chips often have errors due to various factors such as electromagnetic interference, hardware failure, software errors, etc., which can cause data loss, system crashes, and other serious problems.

[0004] In summary, how to effectively solve the problem of PCIe links frequently having errors due to various factors, which can cause data loss, system crashes, and other serious problems, is a problem that needs to be solved by the technical personnel in the field. SUMMARY

[0005] The purpose of the present application is to provide a link error checking method that improves error detection accuracy, enhances system stability and reliability, shortens troubleshooting time, and reduces maintenance costs. Another purpose of the present application is to provide a link error checking device, equipment and computer readable storage medium.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] A link error checking method, comprising:

[0008] Obtaining switch identification information corresponding to each switch respectively;

[0009] Obtaining the line connection relationship between each switch and each uplink device and each downlink device;

[0010] Determining the port identification number corresponding to each switch identification information according to the line connection relationship;

[0011] Obtaining the state flag bit of each index item of the port corresponding to each port identification number;

[0012] Performing link error checking according to the state flag bit of each index item of each port.

[0013] In one specific embodiment of the present application, the state flag bits of each index item of each port corresponding to the port identification number are acquired, including:

[0014] The state flag bits of the receiving port, the transport layer, the data link layer, the receiver, the physical link and the serial transceiver of each port corresponding to the port identification number are acquired;

[0015] Correspondingly, the link error checking is performed according to the state flag bits of each index item of each port, including:

[0016] The link error checking is performed according to the state flag bits of the receiving port, the transport layer, the data link layer, the receiver, the physical link and the serial transceiver of each port.

[0017] In one specific embodiment of the present application, the link error checking is performed according to the state flag bits of the receiving port, the transport layer, the data link layer, the receiver, the physical link and the serial transceiver of each port, including:

[0018] When it is determined that the state flag bits of the receiving port, the transport layer, the data link layer, the receiver and the serial transceiver of each port are all 0, and the state flag bits of the physical link except the last bit are also all 0, it is determined that the link is normal.

[0019] In one specific embodiment of the present application, the link error checking is performed according to the state flag bits of the receiving port, the transport layer, the data link layer, the receiver, the physical link and the serial transceiver of each port, including:

[0020] When there is a non-0 bit in the state flag bits of the receiving port, the transport layer, the data link layer, the receiver, the physical link and the serial transceiver except the last bit of the physical link state flag bit, it is determined that the link is abnormal.

[0021] In one specific embodiment of the present application, when there is a non-0 bit in the state flag bits of the receiving port, the transport layer, the data link layer, the receiver, the physical link and the serial transceiver except the last bit of the physical link state flag bit, it is determined that the link is abnormal, including:

[0022] When there is a non-0 bit in the state flag bits of the receiving port, it is determined that the link to which the port corresponding to the state flag bits of the receiving port belongs is abnormal.

[0023] When the non-0 bit exists in the transport layer status flag bit, it is determined that the link to which the port corresponding to the transport layer status flag bit belongs is abnormal in physical layer transmission of the data packet;

[0024] When the non-0 bit exists in the data link layer status flag bit, it is determined that the link to which the port corresponding to the data link layer status flag bit belongs is abnormal in deserializer;

[0025] When the non-0 bit exists in the receiver status flag bit except the last bit, it is determined that the link to which the port corresponding to the receiver status flag bit belongs is abnormal in receiver;

[0026] When the non-0 bit exists in the serial transceiver status flag bit, it is determined that the link to which the port corresponding to the serial transceiver status flag bit belongs is abnormal in serial transceiver;

[0027] When the non-0 bit exists in the physical link status flag bit, it is determined that the link to which the port corresponding to the physical link status flag bit belongs is abnormal in physical link.

[0028] In one specific embodiment of the present application, the line connection relationship between each switch and each uplink device and each downlink device is obtained, comprising:

[0029] The uplink binding relationship between each switch and each uplink device is obtained;

[0030] The downlink binding relationship between each switch and each downlink device is obtained;

[0031] The line connection relationship is determined according to the uplink binding relationship and the downlink binding relationship.

[0032] In one specific embodiment of the present application, the link error checking is performed according to the index item status flag bit of each port, comprising:

[0033] The link error checking is performed on the link to which each port belongs according to the index item status flag bit of each port respectively, and each sub-link error detection result is obtained;

[0034] The total link error detection result is determined according to each sub-link error detection result.

[0035] In one specific embodiment of the present application, the link error checking is performed according to the index item status flag bit of each port, comprising:

[0036] If the current test scene is a direct current periodic test scene or an alternating current periodic test scene, the physical link status flag bit in the index item status flag bit corresponding to each port is taken as the index item status flag bit with the highest priority for link error checking;

[0037] If the current test scenario is a whole machine voltage stabilization test scenario, the transmission layer state flag bit and the data link layer state flag bit in the state flag bit of each index item corresponding to each port are taken as the state flag bits of the index items with the highest priority for link error checking.

[0038] If the current test scenario is a large data impact test scenario, the serial transceiver state flag bit in the state flag bit of each index item corresponding to each port is taken as the state flag bit of the index item with the highest priority for link error checking.

[0039] A link error checking device comprises:

[0040] A memory for storing a computer program;

[0041] A processor for implementing the steps of the link error checking method as described above when executing the computer program.

[0042] A computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the link error checking method as described above.

[0043] The link error checking method provided by the application comprises the following steps: obtaining switch identification information corresponding to each switch; obtaining line connection relationships between each switch and each uplink device and each downlink device; determining port identification numbers corresponding to each switch identification information according to the line connection relationships; obtaining state flag bits of each index item of each port corresponding to each port identification number; and performing link error checking according to the state flag bits of each index item of each port.

[0044] According to the above technical solution, the state flag bits of each index item of each port corresponding to each port identification number are obtained according to the line connection relationships between each switch and each uplink device and each downlink device, and automatic link error checking is performed according to the state flag bits of each index item of each port. Various subtle and complex errors can be accurately captured, reducing the situation of missed detection and false detection, and significantly improving the error detection accuracy. Errors in the link can be found and repaired in time, reducing the risk of system failure, enhancing the stability and reliability of the system, and ensuring the continuity of critical services. Clear and accurate error reporting and positioning are achieved, the error link and link can be quickly locked out, and the troubleshooting time is shortened. Errors can be prevented in advance and solved in time, reducing the cost of hardware replacement and maintenance, reducing maintenance costs, and improving user experience.

[0045] Correspondingly, the application also provides a link error checking device, a device and a computer readable storage medium corresponding to the above link error checking method, which have the above technical effects, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0047] Figure 1 An implementation flowchart of a link error checking method in an embodiment of the present application, which can include the following steps:

[0048] Figure 2 Another implementation flowchart of a link error checking method in an embodiment of the present application.

[0049] Figure 3 A schematic diagram of an uplink and downlink connection structure of a switch in an embodiment of the present application.

[0050] Figure 4 A structure block diagram of a link error checking device in an embodiment of the present application.

[0051] Figure 5 A structure block diagram of a link error checking device in an embodiment of the present application.

[0052] Figure 6 A specific structure schematic diagram of a link error checking device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the person skilled in the art better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0054] Reference Figure 1 , Figure 1 An implementation flowchart of a link error checking method in an embodiment of the present application, which can include the following steps:

[0055] S101: Obtain switch identification information corresponding to each switch respectively.

[0056] Each switch (Switch) in the system respectively has its corresponding switch identification information (Switch ID), and the switch identification information corresponding to each switch respectively is obtained.

[0057] S102: Obtain a line connection relationship between each switch and each uplink device and each downlink device.

[0058] Each switch in the system has a corresponding uplink device and downlink device, and there is a line connection between the switch, the uplink device, and the downlink device, and the corresponding relationship between each switch, each uplink device, and each downlink device can be preconfigured. Obtain a line connection relationship between each switch and each uplink device and each downlink device.

[0059] The uplink device can be set as a central processing unit (CPU), and the downlink device can be set as a graphics processing unit (GPU), a hard disk, etc.

[0060] S103: Determine the port identification number corresponding to each switch identification information according to the line connection relationship.

[0061] Each uplink device and each downlink device has a corresponding port. After obtaining the line connection relationship between each switch and each uplink device and each downlink device, the port identification number corresponding to each switch identification information is determined according to the line connection relationship. For example, in a PCIE link with a PCIE switch under a Linux system, the port Port ID of the PCIE switch is obtained through the system's own tool lspci.

[0062] S104: Obtain the index item state flag bit of each port corresponding to each port identification number.

[0063] Each port has an index item state flag bit indicating the state of each index item. After determining the port identification number corresponding to each switch identification information according to the line connection relationship, the index item state flag bit of each port corresponding to each port identification number is obtained. For example, according to the determination rule, an automatic recognition script is edited, and the script will automatically scan the index item state flag bit of each port of the uplink and downlink link according to the detection requirements.

[0064] S105: Perform link error checking according to the index item state flag bit of each port.

[0065] Each index item state flag bit indicates the state of each corresponding index item. After obtaining the index item state flag bit of each port corresponding to each port identification number, link error checking is performed according to the index item state flag bit of each port. The setting state of the index item state flag bit can be pre-set to indicate the normal state and the abnormal state of the index item, and whether each index item is in a normal state is determined by each index item state flag bit, and then the link state is determined according to the index item state.

[0066] According to the technical scheme, the line connection relationship between each switch and each uplink device and each downlink device is acquired, each index item state flag bit of each port corresponding to each port identification number is acquired, and automatic link error checking is performed according to each index item state flag bit of each port. The various subtle and complex errors can be accurately captured, the missed detection and false detection can be reduced, the error detection accuracy is significantly improved, the errors in the link can be found and repaired in time, the risk of system failure is reduced, the system stability and reliability are enhanced, the continuity of the key service is ensured, the clear and accurate error report and positioning are realized, the error link and link can be quickly locked, the troubleshooting time is shortened, the errors can be prevented in advance and solved in time, the hardware replacement and maintenance cost are reduced, the maintenance cost is reduced, and the user experience is improved.

[0067] It should be noted that based on the above embodiment, the present embodiment also provides a corresponding improvement scheme. In subsequent embodiments, the steps involved in the above embodiments or the corresponding steps can be mutually referenced, and the corresponding beneficial effects can also be mutually referenced. In the following improved embodiments, it will not be repeated.

[0068] Referring to Figure 2 , Figure 2 Another embodiment of the link error checking method in the present embodiment is provided. The method can include the following steps:

[0069] S201: Obtain the switch identification information corresponding to each switch respectively.

[0070] Referring to Figure 3 , Figure 3 A schematic diagram of an uplink and downlink connection structure of a switch is provided in the present embodiment. Figure 3 The 16-card 4 switch can obtain switch identification information 1, 3, 5, 7, etc.

[0071] S202: Obtain the line connection relationship between each switch and each uplink device and each downlink device.

[0072] S203: Determine each port identification number corresponding to each switch identification information according to the line connection relationship.

[0073] S204: Obtain the receiving port state flag bit, the transmission layer state flag bit, the data link layer state flag bit, the receiver state flag bit, the physical link state flag bit and the serial transceiver state flag bit of the port corresponding to each port identification number respectively.

[0074] The status flag bits of each index item of the port include a port RX status flag bit (PortRX), a transport layer status flag bit (BadTLP), a data link layer status flag bit (BadDLLP), a receiver status flag bit (RecDiag), a physical link status flag bit (LinkDown), and a serial transceiver status flag bit (SerdesError), etc. The port RX status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit, and the serial transceiver status flag bit of the port corresponding to each port identification number are acquired.

[0075] S205: Perform link error checking according to the port RX status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit, and the serial transceiver status flag bit of each port.

[0076] After acquiring the port RX status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit, and the serial transceiver status flag bit of the port corresponding to each port identification number, link error checking is performed according to the port RX status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit, and the serial transceiver status flag bit of each port. The receiving port status of the link to which the port belongs can be determined through the port RX status flag bit, the transport layer status of the link to which the port belongs can be determined through the transport layer status flag bit, the data link layer status of the link to which the port belongs can be determined through the data link layer status flag bit, the receiver status of the link to which the port belongs can be determined through the receiver status flag bit, the physical link status of the link to which the port belongs can be determined through the physical link status flag bit, and the serial transceiver status of the link to which the port belongs can be determined through the serial transceiver status flag bit. Thus, the link status can be determined according to the receiving port status, the transport layer status, the data link layer status, the receiver status, the physical link status, and the serial transceiver status, and the accuracy of link status checking is improved.

[0077] Compared with the traditional link error checking method, more potential and difficult-to-detect errors can be found. The false positives and false negatives are reduced, the credibility of the detection results is improved, the test process and algorithm are optimized, and the test time is shortened. Multiple PCIe links can be tested simultaneously, and the parallelism of the test is improved. Various error types in the PCIe link can be comprehensively and accurately detected and identified, and the test results can be effectively verified and analyzed. Errors in the PCIe link can be found and repaired in a timely manner, the risk of system failure is reduced, the stable operation of the system is ensured, and the user experience is improved.

[0078] In one specific embodiment of the present application, step S205 can include the following steps:

[0079] When it is determined that the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit of each port are all 0, and the bits of the physical link status flag bit except the last bit are also all 0, it is determined that the link is normal.

[0080] The receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit, the physical link status flag bit and the serial transceiver status flag bit can be represented by preset bits, for example, 8-bit flag bits. When it is determined that the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit of each port are all 0, and the bits of the physical link status flag bit except the last bit are also all 0, it is determined that the link is normal. By using the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit, and the bits of the physical link status flag bit except the last bit, the complexity of link status detection is greatly simplified.

[0081] In one specific embodiment of the present application, step S205 can include the following steps:

[0082] When there is a non-0 bit in the bits of the physical link status flag bit except the last bit, the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit, it is determined that the link is abnormal.

[0083] When there is a non-0 bit in the bits of the physical link status flag bit except the last bit, the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit, it is determined that the link is abnormal. By using the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit, or the bits of the physical link status flag bit except the last bit, as long as there is a non-0 bit, it is determined that the link is abnormal, and the complexity of link error checking is greatly simplified.

[0084] In one specific embodiment of the present application, when there is a non-0 bit in the bits of the physical link status flag bit except the last bit, the receiving port status flag bit, the transport layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit, it is determined that the link is abnormal, which can include the following steps:

[0085] Step one: when the receiving port status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the receiving port status flag bit belongs is abnormal;

[0086] Step two: when the transmission layer status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the transmission layer status flag bit belongs is abnormal in physical layer transmission of the data packet;

[0087] Step three: when the data link layer status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the data link layer status flag bit belongs is abnormal in deserializer;

[0088] Step four: when the receiver status flag bit has a non-0 bit except the last bit, it is determined that the link to which the port corresponding to the receiver status flag bit belongs is abnormal in receiver;

[0089] Step five: when the serial transceiver status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the serial transceiver status flag bit belongs is abnormal in serial transceiver;

[0090] Step six: when the physical link status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the physical link status flag bit belongs is abnormal in physical link.

[0091] For the convenience of description, the above six steps can be combined for description.

[0092] When the receiving port status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the receiving port status flag bit belongs is abnormal; when the transmission layer status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the transmission layer status flag bit belongs is abnormal in physical layer transmission of the data packet; when the data link layer status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the data link layer status flag bit belongs is abnormal in deserializer; when the receiver status flag bit has a non-0 bit except the last bit, it is determined that the link to which the port corresponding to the receiver status flag bit belongs is abnormal in receiver; when the serial transceiver status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the serial transceiver status flag bit belongs is abnormal in serial transceiver; when the physical link status flag bit has a non-0 bit, it is determined that the link to which the port corresponding to the physical link status flag bit belongs is abnormal in physical link. Through the setting state of the receiving port status flag bit, the transmission layer status flag bit, the data link layer status flag bit, the receiver status flag bit and the serial transceiver status flag bit corresponding to each other, the accurate determination of the link abnormality reason is realized.

[0093] The embodiments of the present application can accurately capture various subtle and complex errors, reduce missed and false detection cases, and significantly improve the error detection accuracy. Errors in the link can be found and repaired in a timely manner, reducing the risk of system failure, such as avoiding data loss or system crash caused by PCIe link errors, ensuring the continuity of critical business, and enhancing system stability and reliability. Through accurate error detection and processing, the efficiency and quality of data transmission are improved, for example, reducing retransmission and delay caused by errors, improving the overall response speed of the system, and optimizing system performance. Stable and reliable system performance provides users with a better user experience, such as reducing service interruptions caused by link errors in server scenarios, meeting users' high requirements for service quality, and improving user satisfaction.

[0094] The embodiments of the present application can clearly and accurately report and locate errors, helping technicians quickly find the root cause of the problem. If a fault occurs, it is no longer necessary to spend a lot of time checking step by step, and the faulty link and link can be quickly locked out, greatly shortening the troubleshooting time. Errors can be prevented and solved in a timely manner, reducing hardware replacement and maintenance costs, for example, avoiding damage to the entire Switch or related equipment caused by serious errors, saving hardware procurement costs, and reducing maintenance costs. Further optimize PCIe link technology and related products to provide valuable data and experience, for example, through analysis of detection results, promote the research and development of new error correction algorithms and hardware design, and promote technological innovation and development.

[0095] As shown in Figure 3 , the self-developed black box tool scans the information under the port Port ID of the PCIE switch, captures the read values of PortRX, BadTLP, BadDLLP, RecDiag, LinkDown, SerdesError, etc. under the Port port, such as obtaining the number of PCIe errors (errors) of 4 switches respectively;

[0096] . / self-developed black box tool -i 1 counters;

[0097] . / self-developed black box tool -i 3 counters;

[0098] . / self-developed black box tool -i 5 counters;

[0099] . / self-developed black box tool -i 7 counters;

[0100] The -i parameter represents scanning; 1, 3, 5, 7, etc. represent the port number of each switch and link; Counters represents scanning count.

[0101] Obtain the following information of the PCIE link under each switch port number:

[0102]

[0103] In one embodiment of the present application, obtaining the line connection relationship between each switch and each uplink device and each downlink device can include the following steps:

[0104] Step one: obtaining the uplink binding relationship between each switch and each uplink device;

[0105] Step two: obtaining the downlink binding relationship between each switch and each downlink device;

[0106] Step three: determining the line connection relationship according to the uplink binding relationship and the downlink binding relationship.

[0107] For convenience of description, the above three steps can be combined for description.

[0108] Obtaining the uplink binding relationship between each switch and each uplink device and obtaining the downlink binding relationship between each switch and each downlink device, and determining the line connection relationship according to the uplink binding relationship and the downlink binding relationship. Through the uplink binding relationship and the downlink binding relationship, the accurate determination of the line connection relationship is realized.

[0109] In one embodiment of the present application, the link error checking according to the state flag bit of each index item of each port can include the following steps:

[0110] Step one: performing link error checking on the link to which each port belongs according to the state flag bit of each index item of each port, to obtain each sub-link error detection result;

[0111] Step two: determining the total link error detection result according to each sub-link error detection result.

[0112] For convenience of description, the above two steps can be combined for description.

[0113] According to the state flag bit of each index item of each port, performing link error checking on the link to which each port belongs, to obtain each sub-link error detection result, and determining the total link error detection result according to each sub-link error detection result. Through the error checking of each sub-link, the error checking result corresponding to each sub-link is obtained, when the error checking result of each sub-link is link normal, the total link error detection result is determined as link normal; when there is an error checking result of a sub-link that is link abnormal, the total link error detection result is determined as link abnormal. Thus, through the error checking result of each sub-link, the accurate determination of the total link error detection result is realized.

[0114] In one specific embodiment of the present application, the link error checking according to the state flag of each index item of each port can include the following steps:

[0115] If the current test scenario is a direct current cycle test scenario or an alternating current cycle test scenario, the physical link state flag in the state flag of each index item corresponding to each port is taken as the state flag of the index item with the highest priority for link error checking.

[0116] If the current test scenario is a whole machine voltage stabilization test scenario, the transmission layer state flag and the data link layer state flag in the state flag of each index item corresponding to each port are taken as the state flags of the index items with the top two priorities for link error checking.

[0117] If the current test scenario is a large data impact test scenario, the serial transceiver state flag in the state flag of each index item corresponding to each port is taken as the state flag of the index item with the highest priority for link error checking.

[0118] The test scenario can be set in advance. If the current test scenario is a direct current cycle (DC cycle) test scenario or an alternating current cycle (AC cycle) test scenario, since the link is involved in voltage impact, chip logic scheduling, and clock collection adaptation during cold start, when the physical link state flag is not all zeros, it is generally a situation of device drop or device loss. Therefore, the physical link state flag in the state flag of each index item corresponding to each port is taken as the state flag of the index item with the highest priority for link error checking.

[0119] If the current test scenario is a whole machine voltage stabilization test scenario, since the PCIE link has stable chip logic scheduling and clock adaptation, only the reliability of the data link transmission layer under the stable voltage condition needs to be considered. When the transmission layer state flag is not all zeros, it is generally a situation of waveform jitter causing high and low level reset not in time. When the data link layer state flag is not all zeros, it is generally a situation of data handshake protocol misjudgment. Therefore, the transmission layer state flag and the data link layer state flag in the state flag of each index item corresponding to each port are taken as the state flags of the index items with the top two priorities for link error checking.

[0120] If the current test scenario is a large data impact test scenario, such as a ticket rush or a concentrated burst high scenario, since there is a large amount of data exchange, the probability of PCIE link problems can be screened. Therefore, the serial transceiver state flag in the state flag of each index item corresponding to each port is taken as the state flag of the index item with the highest priority for link error checking.

[0121] By adaptively setting the priority of the link flag bit checking according to different test scenes, the state flag bit of the link abnormal flag indicator is more easily checked in the corresponding test scene, and once the link error is checked, other indicator state flag bits do not need to be checked, thereby further improving the checking efficiency of the link error checking. By obtaining different test scenes and obtaining the indicator state flag bit of each port in different test scenes, the comprehensiveness of the link error test is improved.

[0122] After determining the link abnormality, the method further comprises:

[0123] obtaining a target port corresponding to a non-0 bit except the last bit of the physical link state flag bit;

[0124] determining a link to which the target port belongs as an abnormal link;

[0125] connecting the abnormal link to an oscilloscope, and performing waveform test on the abnormal link by using the oscilloscope;

[0126] comparing a target waveform obtained by the test with a standard waveform, and performing abnormal reason investigation according to a comparison result.

[0127] After determining the link abnormality, a target port corresponding to a non-0 bit except the last bit of the physical link state flag bit is obtained, a link to which the target port belongs is determined as an abnormal link, the abnormal link is connected to an oscilloscope, and waveform test is performed on the abnormal link by using the oscilloscope. A target waveform obtained by the test is compared with a standard waveform, and abnormal reason investigation is performed according to a comparison result. By performing waveform test on the abnormal link after determining the link abnormality, and comparing the target waveform obtained by the test with the standard waveform, accurate and rapid abnormal reason investigation of the link is realized.

[0128] Corresponding to the above method embodiment, the application further provides a link error checking device, and the link error checking device described below can be mutually referred to the link error checking method described above.

[0129] Referring to Figure 4 , Figure 4 is a structural block diagram of a link error checking device in an embodiment of the application. The device can comprise:

[0130] a switch identification information obtaining module 41, configured to obtain switch identification information corresponding to each switch respectively;

[0131] a line connection relationship obtaining module 42, configured to obtain a line connection relationship between each switch and each uplink device and each downlink device;

[0132] The port identifier determination module 43 is configured to determine the port identifiers corresponding to the switch identifier information according to the line connection relationship;

[0133] The index item state flag bit acquisition module 44 is configured to acquire the index item state flag bits of the ports corresponding to the port identifiers.

[0134] The link error checking module 45 is configured to perform link error checking according to the index item state flag bits of the ports.

[0135] According to the above technical solution, the index item state flag bits of the ports corresponding to the port identifiers are acquired according to the line connection relationship between the switches and the uplink devices and the downlink devices, and automatic link error checking is performed according to the index item state flag bits of the ports. Various subtle and complex errors can be accurately captured, the missed detection and false detection situations are reduced, and the error detection accuracy is significantly improved. Errors in the link can be discovered and repaired in a timely manner, the risk of system failure is reduced, the system stability and reliability are enhanced, the continuity of key services is ensured, clear and accurate error reports and positioning are realized, the error link and link can be quickly locked, the troubleshooting time is shortened, errors can be prevented and solved in a timely manner, the cost of hardware replacement and maintenance is reduced, the maintenance cost is reduced, and the user experience is improved.

[0136] In one specific embodiment of the application, the index item state flag bit acquisition module 44 is specifically a module that acquires the receiving port state flag bit, the transmission layer state flag bit, the data link layer state flag bit, the receiver state flag bit, the physical link state flag bit, and the serial transceiver state flag bit of the ports corresponding to the port identifiers.

[0137] The link error checking module 45 is specifically configured to perform link error checking according to the receiving port state flag bit, the transmission layer state flag bit, the data link layer state flag bit, the receiver state flag bit, the physical link state flag bit, and the serial transceiver state flag bit of the ports.

[0138] In one specific embodiment of the application, the link error checking module 45 is specifically a module that determines that the link is normal when the receiving port state flag bit, the transmission layer state flag bit, the data link layer state flag bit, the receiver state flag bit, and the serial transceiver state flag bit of the ports are all 0, and the physical link state flag bit is also all 0 except the last bit.

[0139] In an embodiment of the present application, the link error checking module 45 is specifically a module for determining a link abnormality when there is a non-0 bit in the physical link status flag bits except the last bit, the receiving port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, and the serial transceiver status flag.

[0140] In an embodiment of the present application, the link error checking module 45 includes:

[0141] a receiving port abnormality determining submodule for determining that the link to which the port corresponding to the receiving port status flag belongs is a receiving port abnormality when there is a non-0 bit in the receiving port status flag;

[0142] a physical layer transmission abnormality determining submodule for determining that the link to which the port corresponding to the transport layer status flag belongs is a data packet physical layer transmission abnormality when there is a non-0 bit in the transport layer status flag;

[0143] a deserializer abnormality determining submodule for determining that the link to which the port corresponding to the data link layer status flag belongs is a deserializer abnormality when there is a non-0 bit in the data link layer status flag;

[0144] a receiver abnormality determining submodule for determining that the link to which the port corresponding to the receiver status flag belongs is a receiver abnormality when there is a non-0 bit in the receiver status flag except the last bit;

[0145] a physical link abnormality determining submodule for determining that the link to which the port corresponding to the serial transceiver status flag belongs is a serial transceiver abnormality when there is a non-0 bit in the serial transceiver status flag;

[0146] a physical link abnormality determining submodule for determining that the link to which the port corresponding to the physical link status flag belongs is a physical link abnormality when there is a non-0 bit in the physical link status flag.

[0147] In an embodiment of the present application, the line connection relationship obtaining module includes:

[0148] an uplink binding relationship obtaining submodule for obtaining uplink binding relationships between each switch and each uplink device;

[0149] a downlink binding relationship obtaining submodule for obtaining downlink binding relationships between each switch and each downlink device;

[0150] a line connection relationship determining submodule for determining the line connection relationship according to the uplink binding relationships and the downlink binding relationships.

[0151] In an embodiment of the present application, the link error checking module 45 includes:

[0152] The sub-module for determining the total link error detection result is configured to determine the total link error detection result according to the sub-link error detection results.

[0153] The sub-module for determining the total link error detection result is configured to determine the total link error detection result according to the sub-link error detection results.

[0154] In one specific embodiment of the present application, the link error checking module 45 comprises:

[0155] The first link error checking sub-module is configured to, if the current test scenario is the direct current period test scenario or the alternating current period test scenario, perform link error checking on the physical link state flag in the respective indicator item state flag corresponding to each port as the indicator item state flag with the highest priority.

[0156] The second link error checking sub-module is configured to, if the current test scenario is the whole machine voltage stabilization test scenario, perform link error checking on the transmission layer state flag and the data link layer state flag in the respective indicator item state flag corresponding to each port as the indicator item state flags with the top two priorities.

[0157] The third link error checking sub-module is configured to, if the current test scenario is the large data impact test scenario, perform link error checking on the serial transceiver state flag in the respective indicator item state flag corresponding to each port as the indicator item state flag with the highest priority.

[0158] Corresponding to the above method embodiments, refer to Figure 5 , Figure 5 The schematic diagram of the link error checking device provided by the present application can comprise:

[0159] The memory 332 is configured to store the computer program.

[0160] The processor 322 is configured to execute the computer program to implement the steps of the link error checking method of the above method embodiments.

[0161] Specifically, refer to Figure 6 , Figure 6A specific structure diagram of a link error checking device provided in the embodiment is shown in the figure. The link error checking device can have great differences in configuration and performance, and can include a central processing unit (CPU) 322 (for example, one or more processors) and a memory 332 storing one or more computer programs 342 or data 344. The memory 332 can be temporary storage or persistent storage. The programs stored in the memory 332 can include one or more modules (not shown in the figure), each of which can include a series of instruction operations in the data processing device. Further, the processor 322 can be configured to communicate with the memory 332 and execute the series of instruction operations in the memory 332 on the link error checking device 301.

[0162] The link error checking device 301 can further include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input / output interfaces 358, and / or one or more operating systems 341.

[0163] The steps in the link error checking method described above can be implemented by the structure of the link error checking device.

[0164] Corresponding to the above method embodiment, the application further provides a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the following steps can be implemented:

[0165] Obtaining switch identification information corresponding to each switch respectively; obtaining line connection relationships between each switch and each uplink device and each downlink device; determining port identification numbers corresponding to each switch identification information respectively according to the line connection relationships; obtaining state flag bits of each index item of each port corresponding to each port identification number respectively; and performing link error checking according to the state flag bits of each index item of each port.

[0166] The computer readable storage medium can include a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0167] For the computer readable storage medium provided by the application, please refer to the above method embodiment, and the application will not be described here.

[0168] Corresponding to the above method embodiment, the application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the above link error checking method are implemented.

[0169] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0170] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A link error checking method, characterized in that, include: Obtain the switch identification information corresponding to each switch; Obtain the line connection relationships between each switch and each uplink and downlink device; Based on the line connection relationship, determine the port identification number corresponding to each switch identification information; Obtain the status flag bits of each indicator item for each port corresponding to each port identifier; Perform link error checks based on the status flags of each indicator item on each port; This includes obtaining the status flag bits of each indicator item for each port corresponding to each port identifier, including: Obtain the receiver status flag, transport layer status flag, data link layer status flag, receiver status flag, physical link status flag, and serial transceiver status flag for each port ID. Accordingly, link error checks are performed based on the status flags of each indicator item on each port, including: Link error checking is performed based on the receiver port status flag, transport layer status flag, data link layer status flag, receiver status flag, physical link status flag, and serial transceiver status flag for each port.

2. The link error checking method according to claim 1, characterized in that, Link error checking is performed based on the receiver port status flags, transport layer status flags, data link layer status flags, receiver status flags, physical link status flags, and serial transceiver status flags of each port, including: When the receiver status flag, transport layer status flag, data link layer status flag, receiver status flag, and serial transceiver status flag of each port are all 0, and the physical link status flag is also all 0 except for the last bit, the link is considered to be normal.

3. The link error checking method according to claim 1, characterized in that, Link error checking is performed based on the receiver port status flags, transport layer status flags, data link layer status flags, receiver status flags, physical link status flags, and serial transceiver status flags of each port, including: A link anomaly is determined when any of the following bits (excluding the last bit) in the physical link status flag, the receiver port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, and the serial transceiver status flag contain a non-zero bit:

4. The link error checking method according to claim 3, characterized in that, A link anomaly is determined when any of the following bits (excluding the last bit) in the physical link status flag, the receiver port status flag, the transport layer status flag, the data link layer status flag, the receiver status flag, and the serial transceiver status flag contain a non-zero bit: When the receiving port status flag has a non-zero bit, it is determined that the link to which the port corresponding to the receiving port status flag belongs is abnormal. When the transport layer status flag has a non-zero bit, it is determined that the link to which the port corresponding to the transport layer status flag belongs is experiencing a data packet transmission anomaly at the physical layer. When the data link layer status flag has a non-zero bit, it is determined that the link to which the port corresponding to the data link layer status flag belongs is a deserializer malfunction. When any bit other than the last bit in the receiver status flag is non-zero, the link to which the port corresponding to the receiver status flag belongs is determined to be an abnormal receiver. When the serial transceiver status flag has a non-zero bit, it is determined that the link to which the port corresponding to the serial transceiver status flag belongs is a serial transceiver malfunction. When the physical link status flag has a non-zero bit, it is determined that the link to which the port corresponding to the physical link status flag belongs is physically abnormal.

5. The link error checking method according to claim 1, characterized in that, Obtain the line connection relationships between each switch and each uplink and downlink device, including: Obtain the uplink binding relationship between each switch and each uplink device; Obtain the downlink binding relationship between each switch and each downlink device; The line connection relationships are determined based on each uplink binding relationship and each downlink binding relationship.

6. The link error checking method according to any one of claims 1 to 5, characterized in that, Link error checks are performed based on the status flags of each indicator item on each port, including: Based on the status flags of each indicator item of each port, link error checks are performed on the links to which each port belongs, and the error detection results of each sub-link are obtained. The overall link error detection result is determined based on the error detection results of each sub-link.

7. The link error checking method according to claim 1, characterized in that, Link error checks are performed based on the status flags of each indicator item on each port, including: If the current test scenario is a DC cycle test scenario or an AC cycle test scenario, then the physical link status flag bit in the status flag bit of each indicator item corresponding to each port will be used as the highest priority indicator item status flag bit for link error checking. If the current test scenario is a whole machine voltage regulation test scenario, then the transport layer status flag and data link layer status flag in the status flag bits of each indicator item corresponding to each port will be used as the first two priority indicator item status flag bits for link error checking. If the current test scenario is a big data impact test scenario, then the serial transceiver status flag bit in the status flag bits of each indicator item corresponding to each port will be used as the highest priority indicator item status flag bit for link error checking.

8. A link error checking device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the link error checking method as described in any one of claims 1 to 7 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the link error checking method as described in any one of claims 1 to 7.

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