Data transmission platform based on programmable SoC

Abstract

According to the data transmission platform based on the programmable SoC provided by the invention, data transmission between external equipment and the FPGA is realized by using the programmable SoC of the FPGA through a self-defined peripheral, and a test verification platform carrying a 6G chip is established, so that performance test can be carried out on the 6G chip; the method is high in data transmission speed and high in configurability, and can be applied to processing and transmission of specific data.

Description

Technical Field

[0001] The present invention relates to the field of verification platforms, and in particular to a data transmission platform based on a programmable SoC. Background Art

[0002] At present, a new round of global technological revolution and industrial transformation is accelerating. The widespread application of new generation information and communication technologies such as artificial intelligence (AI), VR / AR, three-dimensional (3D) media and the Internet of Things has generated huge amounts of transmission data. Data shows that in 2010, global mobile data traffic was 7.462EB / month, and by 2030, this figure will reach 5016EB / month. The rapid growth of mobile data traffic has put forward higher requirements for the iteration of mobile communication systems. In addition, in various fields of society such as manufacturing, transportation, education, medical care and commerce, intelligence is becoming an irreversible trend.

[0003] In order to overcome the performance limitations of 5G in meeting new challenges, it is necessary to develop 6G wireless systems with new functional features. On the one hand, 6G will integrate all the functions of traditional cellular networks, such as supporting network densification, high throughput, high reliability, low energy consumption, and large-scale connections. On the other hand, 6G will use new technologies to expand services and businesses, including AI, smart wearable devices, self-driving cars, extended reality (XR), and 3D projection.

[0004] At present, the performance of 6G network is still in the stage of research and improvement, so it is necessary to build a configurable verification platform for 6G network performance indicators. FPGA is a very convenient configurable hardware platform. Through the supporting equipment equipped with RF, 6G chips can be tested for certain performance. The existing technology lacks a 6G chip test and verification platform with fast transmission speed, strong configurability, and can be applied to the processing and transmission of specific data. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a data transmission platform based on a programmable SoC to solve the above-mentioned problems of the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a data transmission platform based on a programmable SoC, which is applied to an FPGA using a programmable SoC, and includes: a data acquisition module, a programmable data parsing module and a high-speed data transmission module; wherein the data acquisition module is used to receive input signal data in the form of analog signals from an external device and store the converted digital signal data in an on-chip memory, and / or send output signal data in the form of analog signals converted from packaged parsed data in the form of digital signals stored in the on-chip memory to an external device; the high-speed data transmission module is used to receive input signal data in the form of digital signals from an external device and store them in the on-chip memory, and / or send packaged parsed data in the form of digital signals stored in the on-chip memory as output signal data to an external device; the programmable data parsing module is communicatively connected with the data acquisition module and the high-speed data transmission module, and is used to perform a customized package parsing operation based on the corresponding data stored in the on-chip memory obtained from the data acquisition module or the high-speed data transmission module when the programmable SoC sends a test instruction, and the data acquisition module or the high-speed data transmission module sends output signal data in the form of analog signals or digital signals to the external device based on the packaged parsed data.

[0007] In one embodiment of the present invention, the data acquisition module includes: an ADC interface module, a DAC interface module and a data sampling storage module; wherein the ADC interface module is used to receive analog signal data from an external device and convert it into digital signal data; the DAC interface module is used to convert the received parsed data in the form of digital signals into output signal data in the form of analog signals and send them to the corresponding external device; the data sampling storage module is connected to the ADC interface module and the DAC interface module, and is used to store the digital signal data received from the ADC interface module and / or the parsed data in the form of digital signals received from the programmable data parsing module in the on-chip storage according to a specific data bit width.

[0008] In one embodiment of the present invention, the high-speed data transmission module includes: a storage data transmission module and a high-speed digital signal transmission interface; wherein the high-speed digital signal transmission interface is used to receive data packets from an external device and / or send data packets stored in an on-chip storage received from the storage data transmission module to an external device; the storage data transmission module is communicatively connected to the high-speed digital signal transmission interface, and is used to store data packets received from a programmable data parsing module and / or data packets from the high-speed digital signal transmission interface in the on-chip storage according to a specific data bit width.

[0009] In one embodiment of the present invention, the programmable data parsing module includes: a programmable exchange data packaging module, which is used to perform one or more packaging operations according to specific requirements based on the digital signal data obtained from the data sampling storage module according to a configurable bit width, generate each data packet in sequence, and send them to the storage data transmission module in sequence to store each data packet in an on-chip storage; a programmable exchange data parsing module, which is used to perform parsing operations in sequence according to specific requirements based on each data packet obtained from the storage data transmission module according to a configurable bit width, obtain corresponding parsed data in sequence, and send them to the data sampling storage module to store each parsed data in an on-chip storage.

[0010] In one embodiment of the present invention, the packing operation includes: calculating a check value based on the acquired digital signal data; editing the acquired digital signal data and the check value according to a specific sequence corresponding to the tested 6G wireless communication protocol to generate header information of a data packet; merging the corresponding digital signal data and header information and writing the checksum to generate a data packet, and performing a packing operation corresponding to generating the next data packet after the data packet is generated.

[0011] In one embodiment of the present invention, the parsing operation includes: parsing the header information of the current data packet; verifying the current data packet by parsing the header information, and parsing the data packet to obtain corresponding parsing data if the verification passes, and performing the parsing operation of the next data packet after the parsing of the current data packet is completed.

[0012] In one embodiment of the present invention, if input signal data in the form of an analog signal from an external device is received, the data transmission method of the data transmission test platform includes: receiving the analog signal data from the external device through the ADC interface module and converting it into digital signal data, and then storing the received digital signal data in the on-chip storage according to a specific data bit width by the data sampling and storage module; when the programmable SoC sends a test instruction, obtaining the corresponding digital signal data stored in the on-chip storage from the data sampling and storage module according to the corresponding configurable bit width through the programmable exchange data packaging module and performing one or more packaging operations, generating each data packet in turn, and sending them to the storage data transmission module to store each data packet in on-chip storage; if there is a demand for output signal data in the form of digital signals, each data packet received from the storage data transmission module is sent to an external device in sequence through a high-speed digital signal transmission interface; if there is a demand for output signal data in the form of analog signals, the programmable exchange data parsing module obtains each data packet from the storage data transmission module based on a configurable bit width, and performs parsing operations in sequence according to specific requirements, obtains corresponding parsed data in sequence, and sends the parsed data to the data sampling storage module to store the parsed data in the on-chip storage; the parsed data received from the data sampling storage module is converted into output signal data in the form of analog signals through the DAC interface module and sent to the corresponding external device.

[0013] In one embodiment of the present invention, if input signal data in the form of a digital signal from an external device is received, the data transmission test platform data transmission method includes: receiving a data packet from an external device through the high-speed digital signal transmission interface, and the storage data transmission module stores the data packet in the on-chip storage according to a specific data bit width; when the programmable SoC sends a test instruction, the programmable exchange data parsing module performs parsing operations in sequence based on each data packet obtained from the storage data transmission module according to a configurable bit width, and obtains corresponding parsed data in sequence according to specific requirements, and sends it to the data sampling storage module to store the parsed data in the on-chip storage; if there is an analog signal in the form of If there is a need for output signal data in the form of an analog signal, the DAC interface module converts the parsed data received from the data sampling storage module into output signal data in the form of an analog signal and sends it to the corresponding external device; if there is a need for output signal data in the form of a digital signal, the programmable exchange data packaging module obtains the corresponding parsed data stored in the on-chip storage from the data sampling storage module according to the corresponding configurable bit width and performs one or more packaging operations to generate each data packet in sequence, and sends them to the storage data transmission module respectively to store each data packet in the on-chip storage; and each data packet received from the storage data transmission module is sent to the external device in sequence through the high-speed digital signal transmission interface.

[0014] In one embodiment of the present invention, the ADC interface module supports 8 channels and 12-bit precision data transmission; the DAC interface module supports 8 channels and 14-bit precision data transmission.

[0015] In one embodiment of the present invention, the high-speed digital signal transmission interface supports simultaneous transmission of 4 channels of 25 Gbps data.

[0016] As described above, the present invention is a data transmission platform based on a programmable SoC, which has the following beneficial effects: the present invention uses a programmable SoC of an FPGA to realize data transmission between an external device and the FPGA through custom peripherals, establishes a test and verification platform equipped with a 6G chip, and then can perform performance testing on the 6G chip; the present invention not only has fast data transmission speed and strong configurability, but can also be applied to the processing and transmission of specific data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a schematic diagram of the structure of a data transmission platform based on a programmable SoC in one embodiment of the present invention.

[0018] Figure 2 Shown is a schematic diagram of the structure of a data transmission platform based on a programmable SoC in one embodiment of the present invention.

[0019] Figure 3 Shown is a schematic diagram of the operation flow of a data transmission platform based on a programmable SoC in one embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0021] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0022] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0023] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0024] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0025] The present invention provides a data transmission platform based on a programmable SoC, which uses the programmable SoC of FPGA to realize data transmission between external devices and FPGA through custom peripherals, and establishes a test and verification platform equipped with a 6G chip, thereby being able to perform performance tests on the 6G chip; the present invention not only has fast data transmission speed and strong configurability, but can also be applied to the processing and transmission of specific data.

[0026] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0027] like Figure 1 A schematic structural diagram of a data transmission platform based on a programmable SoC in an embodiment of the present invention is shown.

[0028] Applied to an FPGA using Xilinx programmable SoC; FPGA equipped with this platform can establish a test and verification platform equipped with 6G chips, which is used to perform performance testing on 6G chips;

[0029] FPGA receives input signal data sent by external devices through a data transmission platform based on a programmable SoC, and sends output signal data to the external device, thereby realizing data transmission with the external device and further realizing chip testing; it should be noted that the external device that sends input signal data to the FPGA and the external device that receives output signal data sent by the FPGA can be the same external device or different external devices, without limitation. The external device can be an external test device or other external devices, such as a host computer, other FPGAs equipped with a test system SoC, or other platforms, without limitation.

[0030] In order to realize the transmission of analog signal data and digital signal data with external devices, the platform sets up a data acquisition module 1 and a high-speed data transmission module 2 to respectively realize the communication of analog signal data and digital signal data between FPGA and external devices;

[0031] The data acquisition module 1 is used to receive input signal data in the form of analog signals from an external device and store the converted digital signal data in an on-chip storage, and / or send output signal data in the form of analog signals converted from packaged and parsed data in the form of digital signals to an external device; specifically, the FPGA receives the analog signal data sent by the external device through the data acquisition module 1, and stores the data samples in the on-chip storage of the FPGA after analog-to-digital conversion to complete the collection of the input signal data for subsequent platform customized package and parsing operations; the FPGA sends output signal data in the form of analog signals converted from packaged and parsed data obtained by the platform customized package and parsing operations and stored in the on-chip storage to the external device through the data acquisition module.

[0032] The high-speed data transmission module 2 is used to receive input signal data in the form of digital signals from an external device and store it in the on-chip storage, and / or send output signal data in the form of digital signals to an external device; specifically, the FPGA receives the digital signal data sent by the external device through the high-speed data transmission module 3 for subsequent platform customized packaging and parsing operations; the FPGA sends the packaged parsed data processed data in the form of digital signals obtained by the platform customized packaging and parsing operations as output signal data to the external device through the high-speed data transmission module 3;

[0033] The platform performs customized packaging and parsing operations according to the data stored in the on-chip storage by the data acquisition module 1 or the high-speed data transmission module 2 by setting a programmable data parsing module 3;

[0034] The programmable data analysis module 3 is communicatively connected with the data acquisition module 1 and the high-speed data transmission module 2, and is used to obtain the corresponding digital signal data stored in the on-chip storage from the data acquisition module 1 or the high-speed data transmission module 2 when the programmable SoC sends a test instruction, and perform customized packaging and analysis operations based on the acquired digital signal data to obtain packaged and analyzed data, so that the data acquisition module 1 and the high-speed data transmission module 2 can send output signal data in the form of analog signals or digital signals to an external device based on the packaged and analyzed data.

[0035] In one embodiment, if Figure 2 , the data acquisition module 1 includes: an ADC interface module 11, a DAC interface module 12 and a data sampling storage module 13;

[0036] The ADC interface module 11 is used to receive analog signal data from an external device and convert it into digital signal data;

[0037] The DAC interface module 12 is used to convert the analytical data in the form of digital signals received from the data sampling storage module 13 into output signal data in the form of analog signals and send them to the corresponding external device;

[0038] The data sampling storage module 13 is connected to the ADC interface module 11 and the DAC interface module 12, and is used to store the digital signal data received from the ADC interface module 11 and / or the parsed data in the form of digital signals received from the programmable data parsing module 3 in the on-chip storage according to a specific data bit width. It should be noted that the specific data bit width for storing the digital signal data received from the ADC interface module 11 can be set according to the specific data bit width, and the parsed data in the form of digital signals received from the programmable data parsing module 3 can be stored according to the specific data bit width previously stored.

[0039] For the collected external analog test data, the ADC interface module 11 converts the data and stores it in the on-chip memory through the data sampling and storage module 13. The test instructions sent by the programmable SoC are exchanged between the on-chip memory and the programmable data analysis module 3 through the data sampling and storage module 13. The packaged analysis data obtained by the programmable data analysis module 3 can also be sent to the DAC interface module and converted into analog signal output.

[0040] In a preferred embodiment, the ADC interface module 11 transmits analog signal data from an external device to a data transmission platform of a programmable SoC. The maximum sampling rate of a single channel of the ADC interface module 11 is 4.096Gsps, the maximum number of channels is 8, the total sampling rate exceeds 32Gsps, and 12-bit accuracy is supported. The collected analog signal data is converted to generate corresponding digital signal data and transmitted to the data sampling storage module 13 via the AXI bus protocol.

[0041] The DAC interface module 12 outputs digital signal data from the on-chip memory to external devices in the form of analog signals to verify the accuracy of the data inside the system platform. The DAC interface module 12 has a maximum sampling rate of 6.554Gsps per channel, a maximum number of channels of 8, a total sampling rate of more than 50Gsps, and supports 14-bit accuracy.

[0042] In one embodiment, if Figure 2 , the high-speed data transmission module 2 includes: a storage data transmission module 21 and a high-speed digital signal transmission interface 22;

[0043] Wherein, the high-speed digital signal transmission interface 22 is used to receive digital signal data from an external device and / or send data packets stored in the on-chip storage received from the storage data transmission module to the external device;

[0044] The storage data transmission module 21 is in communication connection with the high-speed digital signal transmission interface 22, and is used to store the data packets received from the programmable data analysis module and / or the digital signal data from the high-speed digital signal transmission interface in the on-chip storage according to the specific data bit width. It should be noted that the specific data bit width of the digital signal data received from the high-speed digital signal transmission interface 22 can be set according to the specific data bit width, and the data packets received from the programmable data analysis module 3 can be stored according to the specific data bit width of the data packets stored before.

[0045] The collected external digital test data is stored in the on-chip memory by the storage data transmission module 21. The test instructions sent by the programmable SoC are exchanged between the on-chip memory and the programmable data parsing module 3 through the storage data transmission module 21. The data packets obtained by the programmable data parsing module 3 can also be sent to the high-speed digital signal transmission interface 22 for output.

[0046] In a preferred embodiment, the high-speed digital signal transmission interface 22 transmits data packets from an external device to the data transmission platform of the programmable SoC, or transmits data packets from the data transmission platform of the programmable SoC to an external device; the high-speed digital signal transmission interface 22 transmits data at a maximum rate of 25Gbps per channel. The transmission interface supports simultaneous transmission of 4 channels of 25Gbps data, and can reach a transmission rate of up to 100Gbps. The interface supports high-speed data transmission and high-speed data reception.

[0047] In one embodiment, if Figure 2 , the programmable data parsing module 3 comprises:

[0048] A programmable exchange data packaging module 31, used to perform one or more packaging operations according to specific requirements based on the digital signal data obtained from the data sampling storage module 13 according to the configurable bit width, generate each data packet in sequence, and send them to the storage data transmission module 22 in sequence to store each data packet in the on-chip storage;

[0049] The programmable exchange data parsing module 32 is used to perform parsing operations in sequence according to specific requirements based on each data packet obtained from the storage data transmission module 22 according to the configurable bit width, obtain corresponding parsing data in sequence, and send it to the data sampling storage module 13 to store each parsing data in the on-chip storage.

[0050] In a specific embodiment, the packaging operation includes:

[0051] Calculate the check value according to the acquired digital signal data;

[0052] The acquired digital signal data and check value are edited according to the specific sequence corresponding to the 6G wireless communication protocol to be tested to generate the header information of the data packet; wherein the header information includes: 6G source address, destination address, data packet length, check value and other data packet attribute information;

[0053] The corresponding digital signal data and header information are merged and written into the checksum to generate a data packet, and after the data packet is generated, a packing operation corresponding to generating the next data packet is performed.

[0054] In a specific embodiment, the parsing operation includes: parsing the header information of the current data packet; verifying the current data packet by parsing the header information, and parsing the data packet to obtain corresponding parsing data if the verification passes, and performing the parsing operation of the next data packet after the parsing of the current data packet is completed.

[0055] It should be noted that the data packets to be parsed are packaged according to the method of the previous embodiment.

[0056] Based on the differences in signal forms of input signal data and output signal data, the data transmission test platform of the present invention has the following implementation methods for data transmission, which will now be described in conjunction with specific embodiments.

[0057] In one embodiment, if input signal data in the form of an analog signal from an external device is received, combined with the signal form requirements of the output signal data, the data transmission test platform transmits data in the following two ways:

[0058] The first method: If the output signal data requirement is in the form of a digital signal, the data transmission process includes:

[0059] The analog signal data from the external device is received through the ADC interface module 11 and converted into digital signal data, and then the received digital signal data is stored in the on-chip storage according to a specific data bit width by the data sampling storage module 13;

[0060] When the programmable SoC sends a test instruction, the programmable exchange data packaging module 31 obtains the corresponding digital signal data stored in the on-chip memory from the data sampling storage module 13 according to the corresponding configurable bit width and performs one or more packaging operations to generate each data packet in sequence, and sends them to the storage data transmission module 22 to store each data packet in the on-chip memory;

[0061] The data packets received from the storage data transmission module 22 are sequentially sent to the external device through the high-speed digital signal transmission interface 21 .

[0062] The second method: If there is an output signal data requirement in the form of an analog signal, the data transmission process includes:

[0063] The analog signal data from the external device is received through the ADC interface module 11 and converted into digital signal data, and then the received digital signal data is stored in the on-chip storage according to a specific data bit width by the data sampling storage module 13;

[0064] When the programmable SoC sends a test instruction, the programmable exchange data packaging module 31 obtains the corresponding digital signal data stored in the on-chip memory from the data sampling storage module 13 according to the corresponding configurable bit width and performs one or more packaging operations to generate each data packet in sequence, and sends them to the storage data transmission module 22 to store each data packet in the on-chip memory;

[0065] The programmable exchange data parsing module 32 performs parsing operations in sequence according to specific requirements based on each data packet obtained from the high-speed data transmission module 22 according to the configurable bit width, obtains corresponding parsed data in sequence, and sends the parsed data to the data sampling storage module 13 to store the parsed data in the on-chip storage;

[0066] The DAC interface module 12 converts the parsed data received from the data sampling storage module 13 into output signal data in the form of analog signals and sends the data to the corresponding external device.

[0067] In one embodiment, if input signal data in the form of a digital signal is received from an external device, combined with the signal form requirements of the output signal data, the data transmission test platform transmits data in the following two ways:

[0068] The first method: If there is an output signal data requirement in the form of an analog signal, the data transmission process includes:

[0069] The high-speed digital signal transmission interface 21 receives a data packet from an external device, and the storage data transmission module 22 stores the data packet in the on-chip storage according to a specific data bit width;

[0070] When the programmable SoC sends a test instruction, the programmable exchange data parsing module 32 performs parsing operations in sequence based on the data packets obtained from the storage data transmission module according to the configurable bit width, and obtains corresponding parsed data in sequence according to specific requirements, and sends the parsed data to the data sampling storage module 13 to store the parsed data in the on-chip storage;

[0071] The DAC interface module 12 converts the parsed data received from the data sampling storage module 13 into output signal data in the form of analog signals and sends them to the corresponding external device.

[0072] The second method: If the output signal data requirement is in the form of a digital signal, the data transmission process includes:

[0073] The high-speed digital signal transmission interface 21 receives a data packet from an external device, and the storage data transmission module 22 stores the data packet in the on-chip storage according to a specific data bit width;

[0074] When the programmable SoC sends a test instruction, the programmable exchange data parsing module 32 performs parsing operations in sequence according to specific requirements based on each data packet obtained from the storage data transmission module according to the configurable bit width, obtains corresponding parsing data in sequence, and sends it to the data sampling storage module 13 to store the parsing data in the on-chip storage;

[0075] The programmable exchange data packaging module 31 obtains the corresponding parsed data stored in the on-chip storage from the data sampling storage module 13 according to the corresponding configurable bit width and performs one or more packaging operations, generates each data packet in sequence, and sends them to the storage data transmission module 22 to store each data packet in the on-chip storage; the high-speed digital signal transmission interface 21 sends each data packet received from the storage data transmission module 22 to the external device in sequence.

[0076] In order to better illustrate the above-mentioned data transmission platform based on programmable SoC, the present invention provides the following specific embodiments.

[0077] Embodiment 1: A data transmission platform based on programmable SoC. Figure 3 The diagram is a schematic diagram of the operation flow of the data transmission platform based on programmable SoC.

[0078] The platform includes: a data acquisition module, a programmable data analysis module and a high-speed data transmission module;

[0079] The data acquisition module includes:

[0080] The ADC interface module is used to receive analog signal data sent from the test equipment to the SoC and convert it into digital signals. The ADC interface module transmits data from the external test equipment to the programmable SoC platform. Its main purpose is to receive analog signal data and collect the data into the system at a single channel sampling rate of up to 4.096Gsps. The ADC interface module supports up to 8 channels and 12-bit accuracy for collection. The collected analog signal data is converted to generate corresponding digital signal data and transmitted to the data sampling storage module through the AXI bus protocol.

[0081] The DAC interface module is used to send the received digital signal data and convert it into the corresponding analog signal and output it to the external test equipment. The DAC interface module outputs the data from the on-chip memory to the external test equipment to verify the accuracy of the internal data of the system platform. The main purpose is to convert the on-chip digital signal data into analog signal data and output it to the external test system. The internal digital data conversion is converted into analog signal output at a single-channel maximum sampling rate of 6.554Gsps. The DAC interface module supports 8 channels and 14-bit accuracy for acquisition. The acquired digital module generates the corresponding analog signal data after conversion.

[0082] The data sampling and storage module is used to store the converted signal data in the on-chip memory; wherein the data sampling and storage module sets a configurable data bit width, packages the external test data collected by the ADC interface module into a specific bit width, and stores it in the on-chip memory. After the on-chip processor receives the host computer signal, it converts the stored specific data bit width data packet into digital-to-analog data through the DAC interface module and outputs it to the outside.

[0083] The programmable data analysis module has the following two functions:

[0084] The programmable exchange data packaging function is used to package data according to specific requirements; specifically, the data is extracted from the data acquisition module to the programmable data parsing module. The extracted data is packaged according to the configurable bit width, and the corresponding check value is calculated. The data and the check value are edited according to a specific sequence to generate the header information of the data packet. After the data is written into the header information of the data packet, the checksum is written, and the data packet generation is completed, and the next data packet is generated.

[0085] The programmable exchange data parsing function is used to parse the received data packets according to specific requirements; specifically, the data is taken out through the storage data transmission module and unpacked using the configurable bit width. A group of data packets are read in at the same time according to the bit width, and then the data packet header information is parsed, and the data body is verified through the checksum information. Once the data packet parsing is completed, the parsing of the next data packet will continue.

[0086] High-speed data transmission module, including:

[0087] High-speed digital signal transmission interface, used to transmit data packets through the high-speed transmission interface; the high-speed digital signal transmission interface transmits data from the on-chip SoC through the high-speed interface to other FPGAs equipped with the test system SoC. The main purpose is to transmit digital signal data at high speed and transmit data at a maximum rate of 25Gbps per channel. The transmission interface supports simultaneous transmission of 4 channels of 25Gbps data, with a maximum transmission rate of 100Gbps. The interface supports high-speed data transmission and high-speed data reception.

[0088] The storage data transmission module is used to store the received high-speed digital signal stream in the on-chip memory; wherein the storage data transmission module sets a configurable data bit width and stores the high-speed data stream received by the high-speed digital signal transmission interface module in the on-chip memory. After the on-chip processor receives the host computer signal, the stored specific data is analyzed by the programmable analysis module and transmitted to the data sampling storage module for subsequent output.

[0089] The specific operation process of the data transmission platform based on programmable SoC includes:

[0090] Connect the signal line, FPGA receives analog signal data through the data acquisition module, and stores the data in the on-chip memory after conversion. According to the instructions sent by the host computer to the FPGA, the on-chip memory exchanges data with the programmable data analysis module through the data acquisition module. The data is packaged into customized data packets through the customized programmable exchange data packaging function of the programmable data analysis module. The data packets will be sent to the high-speed data transmission module for output according to the task, or the data packets will be obtained from the high-speed data transmission module through the programmable data analysis module for unpacking, and the original data of the data packets will be passed to the data acquisition module for conversion and then output as analog signal data;

[0091] Another implementation method is that the FPGA receives the customized data packet through the high-speed data transmission module and stores it in the on-chip memory. According to the instructions sent by the host computer to the FPGA, the on-chip memory exchanges data with the programmable data analysis module through the high-speed data transmission module. The data is unpacked by the programmable data analysis module through the customized programmable exchange data analysis function, and the unpacked raw data is passed to the data acquisition module to output the analog signal data after conversion, or the data is encapsulated into a customized data packet through the customized programmable exchange data packaging function of the programmable data analysis module and sent to the high-speed data transmission module for output.

[0092] Compared with the prior art, the present invention has the following advantages:

[0093] 1. The present invention adopts a combination of software and hardware to design the data transmission module, which has low cost and fast deployment.

[0094] 2. The IP core of the present invention is generated by the XILINX tool, and different contents can be designed according to different data packet characteristics.

[0095] 3. The present invention adopts configurable parameter design, and the transmission rate and sampling rate can be independently selected.

[0096] In summary, the data transmission platform based on programmable SoC of the present invention enables the programmable SoC using FPGA to realize data transmission between external devices and FPGA through custom peripherals, establishes a test and verification platform equipped with 6G chips, and then can perform performance tests on 6G chips; the present invention not only has fast data transmission speed and strong configurability, but can also be applied to the processing and transmission of specific data. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A data transmission platform based on a programmable SoC, characterized in that: Applied to an FPGA using a programmable SoC, including: a data acquisition module, a programmable data analysis module and a high-speed data transmission module; Wherein, the data acquisition module is used to receive input signal data in the form of analog signals from an external device and store the converted digital signal data in an on-chip memory, and / or send output signal data in the form of analog signals converted from the packaged parsed data in the form of digital signals stored in the on-chip memory to the external device; The high-speed data transmission module is used to receive input signal data in the form of digital signals from an external device and store it in the on-chip memory, and / or send the packaged parsed data in the form of digital signals stored in the on-chip memory as output signal data to the external device; The programmable data analysis module is communicatively connected with the data acquisition module and the high-speed data transmission module, and is used for obtaining packaged analysis data by performing customized packaged analysis operations based on corresponding data stored in the on-chip storage and obtained from the data acquisition module or the high-speed data transmission module when the programmable SoC sends a test instruction, and the data acquisition module or the high-speed data transmission module sends output signal data in the form of analog signals or digital signals to an external device based on the packaged analysis data.

2. The data transmission platform based on programmable SoC according to claim 1, characterized in that: The data acquisition module includes: an ADC interface module, a DAC interface module and a data sampling storage module; Wherein, the ADC interface module is used to receive analog signal data from an external device and convert it into digital signal data; The DAC interface module is used to convert the received parsed data in the form of digital signals into output signal data in the form of analog signals and send them to the corresponding external device; The data sampling storage module is connected to the ADC interface module and the DAC interface module, and is used to store the digital signal data received from the ADC interface module and / or the parsed data in the form of digital signals received from the programmable data parsing module in the on-chip storage according to a specific data bit width.

3. The data transmission platform based on programmable SoC according to claim 2, characterized in that: The high-speed data transmission module includes: a storage data transmission module and a high-speed digital signal transmission interface; Wherein, the high-speed digital signal transmission interface is used to receive a data packet from an external device and / or send a data packet stored in an on-chip storage and received from the storage data transmission module to an external device; The storage data transmission module is communicatively connected to the high-speed digital signal transmission interface, and is used to store the data packets received from the programmable data parsing module and / or the data packets from the high-speed digital signal transmission interface into the on-chip storage according to a specific data bit width.

4. The data transmission platform based on programmable SoC according to claim 3, characterized in that: The programmable data parsing module comprises: A programmable exchange data packaging module, used to perform one or more packaging operations according to specific requirements based on the digital signal data obtained from the data sampling storage module according to the configurable bit width, generate each data packet in sequence, and send them to the storage data transmission module in sequence to store each data packet in the on-chip storage; The programmable exchange data parsing module is used to perform parsing operations in sequence according to specific requirements based on each data packet obtained from the storage data transmission module according to the configurable bit width, obtain corresponding parsing data in sequence, and send them to the data sampling storage module to store each parsing data in the on-chip storage.

5. The data transmission platform based on programmable SoC according to claim 4, characterized in that: The packaging operation includes: Calculate the check value according to the acquired digital signal data; The acquired digital signal data and check value are edited according to a specific sequence corresponding to the tested 6G wireless communication protocol to generate header information of the data packet; The corresponding digital signal data and header information are merged and written into the checksum to generate a data packet, and after the data packet is generated, a packing operation corresponding to generating the next data packet is performed.

6. The data transmission platform based on programmable SoC according to claim 5, characterized in that: The parsing operation includes: Parse the header information of the current data packet; The current data packet is verified by parsing the header information, and if the verification passes, the data packet is parsed to obtain the corresponding parsed data, and the parsing operation of the next data packet is performed after the parsing of the current data packet is completed.

7. The data transmission platform based on programmable SoC according to claim 4, characterized in that: If input signal data in the form of an analog signal from an external device is received, the data transmission test platform data transmission methods include: The analog signal data from the external device is received through the ADC interface module and converted into digital signal data, and then the received digital signal data is stored in the on-chip storage according to a specific data bit width by the data sampling storage module; When the programmable SoC sends a test instruction, the programmable exchange data packaging module obtains the corresponding digital signal data stored in the on-chip storage from the data sampling storage module according to the corresponding configurable bit width and performs one or more packaging operations, generates each data packet in sequence, and sends them to the storage data transmission module to store each data packet in the on-chip storage; If there is a demand for output signal data in the form of digital signals, each data packet received from the storage data transmission module is sequentially sent to an external device via a high-speed digital signal transmission interface; If there is a need for output signal data in the form of an analog signal, the programmable exchange data analysis module obtains each data packet from the storage data transmission module according to the configurable bit width, and performs analysis operations in sequence according to specific requirements, obtains corresponding analysis data in sequence, and sends them to the data sampling storage module to store the analysis data in the on-chip storage; the DAC interface module converts the analysis data received from the data sampling storage module into output signal data in the form of an analog signal and sends them to the corresponding external device.

8. The data transmission platform based on programmable SoC according to claim 4, characterized in that: If input signal data in the form of a digital signal is received from an external device, the data transmission test platform data transmission method includes: Receiving a data packet from an external device through the high-speed digital signal transmission interface, and storing the data packet in the on-chip storage according to a specific data bit width by the storage data transmission module; When the programmable SoC sends a test instruction, the programmable exchange data parsing module sequentially performs parsing operations based on each data packet obtained from the storage data transmission module according to the configurable bit width and according to specific requirements, obtains corresponding parsed data in turn, and sends it to the data sampling storage module to store the parsed data in the on-chip storage; If there is a demand for output signal data in the form of an analog signal, the DAC interface module converts the parsed data received from the data sampling storage module into output signal data in the form of an analog signal and sends it to the corresponding external device; If there is a need for output signal data in the form of a digital signal, the programmable exchange data packaging module obtains the corresponding parsed data stored in the on-chip storage from the data sampling storage module according to the corresponding configurable bit width and performs one or more packaging operations, generates each data packet in turn, and sends them to the storage data transmission module to store each data packet in the on-chip storage; and sends each data packet received from the storage data transmission module to an external device in turn through a high-speed digital signal transmission interface.

9. The data transmission platform based on programmable SoC according to claim 1, characterized in that: The ADC interface module supports 8 channels and 12-bit precision data transmission; the DAC interface module supports 8 channels and 14-bit precision data transmission.

10. The data transmission platform based on programmable SoC according to claim 1, characterized in that: The high-speed digital signal transmission interface supports simultaneous transmission of 4 channels of 25 Gbps data.

Images