Semiconductor device and method for manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. A method for manufacturing a semiconductor device includes forming an isolation layer defining a plurality of active regions over a substrate; forming a bit line stack over the substrate; forming a main hard mask layer over the bit line stack; forming a plurality of first sacrificial mask layers over the main hard mask layer; forming a plurality of second sacrificial mask layers overlapping both side end portions of the first sacrificial mask layer over the first sacrificial mask layer; forming a main hard mask layer pattern by using the first sacrificial mask layer and the second sacrificial mask layer as barriers and etching the main hard mask layer; and forming a bit line structure by using the main hard mask layer pattern as a barrier and etching the bit line stack.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0113524, filed on August 29, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a non-linear bit line and a method for manufacturing the semiconductor device. Background Art

[0004] As semiconductor devices become more highly integrated, individual patterns are becoming increasingly finer in order to position more elements of the semiconductor device in the same area. That is, as the degree of integration of semiconductor devices increases, the design rules of the constituent elements of the semiconductor device are decreasing, and the problem of such interference between adjacent elements becomes more difficult to solve effectively. Therefore, new innovative solutions are needed. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device that reduces interference between adjacent patterns, and a method for manufacturing the semiconductor device.

[0006] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an isolation layer defining multiple active areas above a substrate; forming a bit line stack above the substrate; forming a main hard mask layer above the bit line stack; forming multiple first sacrificial mask layers above the main hard mask layer; forming multiple second sacrificial mask layers overlapping two side ends of the first sacrificial mask layer above the first sacrificial mask layer; forming a main hard mask layer pattern by using the first sacrificial mask layer and the second sacrificial mask layer as barriers and etching the main hard mask layer; and forming a bit line structure by using the main hard mask layer pattern as a barrier and etching the bit line stack.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a substrate; an isolation layer formed above the substrate and defining a plurality of active regions; a bit line contact plug coupled to a portion of the active region; and a bit line formed above the bit line contact plug, wherein the bit line includes: a first line portion intersecting the active region; and a second line portion extending in a direction different from that of the first line portion and overlapping the isolation layer.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a plurality of active regions separated by an isolation layer; and a bit line stack structure coupled to at least a portion of the active regions; wherein the bit line stack structure includes a nonlinear bit line, the nonlinear bit line includes alternating multiple first line segments and multiple second line segments, and wherein the first line segments and the second line segments extend in a first direction and a second direction, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic simplified plan view illustrating a semiconductor device according to one embodiment of the present invention.

[0010] Figure 1B is along Figure 1A Schematic simplified cross-sectional view taken along line AA' shown in FIG.

[0011] Figure 1C is along Figure 1A Schematic simplified cross-sectional view taken along line BB' shown in FIG.

[0012] FIG. 2A to FIG. 12C is a simplified schematic diagram for illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0013] FIG. 13A to FIG. 13I is a simplified schematic diagram for illustrating a method for forming a main hard mask layer pattern.

[0014] Fig.14 is a simplified schematic diagram illustrating a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0015] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout the present disclosure, throughout the various drawings and embodiments of the present invention, similar reference numerals refer to similar parts.

[0016] The drawings are not necessarily to scale, and in some instances, the proportions may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, this refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0017] Figure 1A is a schematic simplified plan view illustrating a semiconductor device according to one embodiment of the present invention. Figure 1B is along Figure 1ASchematic simplified cross-sectional view taken along line AA' shown in FIG. Figure 1C is along Figure 1A Schematic simplified cross-sectional view taken along line BB' shown in FIG.

[0018] refer to Figures 1A to 1C The semiconductor device 100 may include a plurality of memory cells. Each memory cell may include a cell transistor and a bit line 214 , wherein the cell transistor includes a buried word line 207 .

[0019] Hereinafter, the semiconductor device 100 will be described in detail.

[0020] An isolation layer 202 and active regions 203 may be formed over the substrate 201. A plurality of active regions 203 may be defined by the isolation layer 202. The substrate 201 may be a material suitable for semiconductor processing. The substrate 201 may include a semiconductor substrate. The substrate 201 may be formed of a material containing silicon. The substrate 201 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 201 may also include other semiconductor materials, such as germanium. The substrate 201 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The substrate 201 may include a silicon on insulator (SOI) substrate. The isolation layer 202 may be formed by a shallow trench isolation (STI) process.

[0021] The gate trench 205 may be formed in the substrate 201. The gate dielectric layer 206 may be conformally formed on the surface of the gate trench 205. A buried word line 207 may be formed over the gate dielectric layer 206 to partially fill the gate trench 205. More specifically, the buried word line 207 may fill the lower portion of the gate trench and expose the remaining dielectric layer 206. A gate capping layer 208 may be formed over the buried word line 207 and the remaining exposed gate dielectric layer 206 to completely fill any remaining space within the gate trench 205. The top surface of the buried word line 207 may be disposed at a level lower than the surface of the substrate 201. The buried word line 207 may be formed of a low resistance metal material. For example, the buried word line 207 may be formed by sequentially stacking titanium nitride and tungsten. According to another embodiment of the present invention, the buried word line 207 may be formed only of titanium nitride (may be only TiN). The buried word line 207 may also be referred to as a “buried gate electrode.” The buried word line 207 may have a line shape from a plan view, and a major axis thereof may extend along the first direction D1.

[0022] The first impurity region 209 and the second impurity region 210 may be formed in the substrate 201. The first impurity region 209 and the second impurity region 210 may be spaced apart from each other by the gate trench 205. The first impurity region and the second impurity region may be formed on both sides of each gate trench 205. The first impurity region 209 and the second impurity region 210 may also be referred to as a source region / drain region. The first impurity region 209 and the second impurity region 210 may include N-type impurities such as arsenic (As) or phosphorus (P). The buried word line 207 together with the first impurity region 209 and the second impurity region 210 may form a cell transistor. Due to the buried word line 207 structure, the cell transistor may exhibit an improved short channel effect.

[0023] The bit line contact plug 212 may be formed over the substrate 201. The bit line contact plug 212 may be coupled to the first impurity region 209. The bit line contact plug 212 may be disposed in the bit line contact hole 211. The bit line contact hole 211 may extend toward the substrate 201 through the hard mask layer 204. The hard mask layer 204 may be formed over the substrate 201. The hard mask layer 204 may include a dielectric material. The bit line contact hole 211 may expose the first impurity region 209. The lower surface of the bit line contact plug 212 may be lower than the top surface of the isolation layer 202 and the top surface of the active region 203. The bit line contact plug 212 may be formed of polysilicon. The bit line contact plug 212 may be formed of a metal material. A portion of the bit line contact plug 212 may have a line width smaller than the diameter of the bit line contact hole 211. The bit line barrier 213 may be formed over the top surface of the bit line contact plug 212, and the bit line 214 may be formed over the top surface of the bit line barrier 213. The bit line hard mask 215 may be formed over the top surface of the bit line 214.

[0024] The stacked structure of the bit line contact plug 212, the bit line barrier 213, the bit line 214, and the bit line hard mask 215 may also be referred to as a bit line structure. Figure 1A As can be seen in FIG. 1 , the bit line 214 may have a nonlinear line shape extending in the second direction D2 intersecting the buried word line 207. A portion of the bit line 214 may be coupled to the bit line contact plug 212. The bit line 214 and the bit line contact plug 212 may have the same line width in the first direction D1. Therefore, the bit line 214 may extend in the second direction D2 while covering the bit line contact plug 212. The bit line barrier 213 may include a metal nitride, such as titanium nitride. The bit line 214 may include a metal material, such as tungsten. The bit line hard mask 215 may include a dielectric material, such as silicon nitride.

[0025] A spacer structure 216 may be formed on the sidewall of the bit line structure. The spacer structure 216 may extend to be disposed on the sidewall of the bit line contact plug 212, but may only cover a portion of the bit line contact plug 212, leaving the remaining portion of the bit line contact plug 212 in direct contact with the isolation layer 202, such as Figure 1B . The spacer structure 216 may include silicon nitride, silicon oxide, a low-k material, or a combination thereof. The low-k material may include SiBN, SiCO, SiCN, SiBCN, or a combination thereof. For example, the spacer structure 216 may include a NKON, NKNAN, NKOK, NKOKN, NKAKN, KOK, or KAK multilayer structure, where N refers to silicon nitride, and K refers to a low-k material, and O refers to silicon oxide, and A refers to an air gap. According to another embodiment of the present invention, the outermost spacer of the spacer structure 216 may include a low-k material.

[0026] The storage node contact plug SNC may be formed between a pair of adjacent bit line structures. The storage node contact plug SNC may be coupled to the second impurity region 210. The storage node contact plug SNC may include polysilicon, metal nitride, metal material, metal silicide, or a combination thereof. According to one embodiment of the present invention, the storage node contact plug SNC may be formed by sequentially stacking polysilicon, cobalt silicide, and tungsten (in the above order).

[0027] From the perspective of a direction parallel to the bit line structure, a plug isolation layer 217 may be formed between adjacent storage node contact plugs SNC. The plug isolation layer 217 may be formed between adjacent bit line structures. Adjacent storage node contact plugs SNC may be isolated by the plug isolation layer 217 in the second direction D2. Between adjacent bit line structures, a plurality of plug isolation layers 217 and a plurality of storage node contact plugs SNC may be alternately arranged in the second direction D2. The storage node contact plug SNC may include a stack of a lower plug 219 and an upper plug 220. The storage node contact plug SNC may be formed in a storage node contact hole 218. The storage node contact hole 218 may be formed between the plug isolation layer 217 and the bit line structure. A plug capping layer 221 may be formed between adjacent upper plugs 220. The plug capping layer 221 may include silicon oxide, silicon nitride, silicon oxycarbide, or a combination thereof.

[0028] The memory element 222 may be formed above the storage node contact plug SNC. The memory element 222 may include a capacitor including a storage node. The storage node may be columnar. Although not shown, a dielectric layer and a plate node may be further formed above the storage node. In a variation of this embodiment, the storage node may have a cylindrical shape instead of a columnar shape.

[0029] The plug isolation layer 217 may include silicon nitride or a low-k material. When the plug isolation layer 217 includes a low-k material, parasitic capacitance between adjacent storage node contact plugs SNC (having the plug isolation layer 217 therebetween) may be reduced. The plug isolation layer 217 may include SiCO, SiCN, SiOCN, SiBN, or SiBCN.

[0030] according to Figures 1A to 1C , the bit line 214 may have a nonlinear structure. From a top view perspective, the bit line 214 may have a hybrid line shape in which a plurality of first line portions L1 and a plurality of second line portions L2 are merged in an alternating pattern. Figure 1A As shown in , the plurality of first line portions L1 may each be aligned along the second direction D2, and the plurality of second line portions L2 may be parallel to each other and oriented in a third direction D3 forming an acute angle with the second direction D2. Like the bit line 214, the bit line hard mask 215 may also have a nonlinear structure, i.e., a hybrid line shape.

[0031] The first line portion L1 and the second line portion L2 may have different directions. For example, the first line portion L1 may extend in the second direction D2, and the second line portion L2 may extend in the third direction D3. Here, the third direction D3 may be the same as the direction of the active region 13.

[0032] The first line portion L1 may overlap the bit line contact plug 212 vertically, and the second line portion L2 may overlap the isolation layer 202 vertically. Each of the first line portion L1 and the second line portion L2 may have an island shape, a strip shape, or a small line shape. The first line portion L1 and the second line portion L2 may be coupled to each other in an alternating pattern. The first line portion L1 may extend in a direction intersecting the active area 203, and the second line portion L2 may overlap the isolation layer 202 vertically. The second line portion L2 may not overlap the active area 203. The second line portion L2 and the active area 203 may extend in a third direction D3. The second line portion L2 and the active area 203 may have a non-overlapping direction.

[0033] Both sidewalls of the bit line 214 may have nonlinearity according to the direction in which the bit line 214 extends. The first line portion L1 and the second line portion L2 may be alternately arranged in the direction in which the bit line 214 extends.

[0034] from Figure 1AFrom the perspective of the BB' direction shown in FIG. 2 , two storage node contact plugs SNC and one bit line 214 may be coupled to one active region 203. In this case, the second line portion L2 of the bit line 214 may be adjacent to the storage node contact plug SNC in the first direction D1. The storage node contact plug SNC may be coupled to the edge of each of the active regions 203, and the bit line 214 may be coupled to the center of each of the active regions 203 through the bit line contact plug 212.

[0035] As described above, since the bit line 214 has a nonlinear structure including the first line portion L1 and the second line portion L2, interference between the storage node contact plug SNC and the bit line 214 can be minimized. Since the second line portion L2 of the bit line 214 does not overlap the active region 203, a space sufficient to form the storage node contact plug SNC can be secured.

[0036] As a comparative example, when the second line portion L2 extends in the second direction D2 in the same manner as the first line portion L1, the active region 203 and the second line portion L2 may overlap. Therefore, the space for forming the storage node contact plug SNC may be narrowed. Therefore, the resistance of the storage node contact plug SNC may increase.

[0037] FIG. 2A to FIG. 12C A method for manufacturing a semiconductor device according to an embodiment of the present invention is illustrated. Figures 2B to 12B The diagram along FIG. 2A to FIG. 12A The line AA' shown in FIG. Figures 2C to 12C The diagram along FIG. 2A to FIG. 12A The manufacturing method is obtained by the line BB' shown in FIG.

[0038] refer to FIG. 2A to FIG. 2C , an isolation layer 12 may be formed over the substrate 11. A plurality of active regions 13 may be defined by the isolation layer 12. The isolation layer 12 may be formed by a shallow trench isolation (STI) process. The STI process may include etching the substrate 11 to form an isolation trench (whose reference numerals are omitted), and then filling the isolation trench with a dielectric material to form the isolation layer 12. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. A chemical vapor deposition (CVD) process or other deposition process may be performed to fill the isolation trench with a dielectric material. A planarization process such as chemical mechanical polishing (CMP) may be additionally performed.

[0039] Subsequently, a buried word line structure may be formed in the substrate 11. The buried word line structure may include a gate trench 15, a gate dielectric layer 16 conformally covering a bottom and sidewall of the gate trench 15, a buried word line 17 filling a portion of the gate trench 15 over the gate dielectric layer 16, and a gate capping layer 18 formed over the buried word line 17.

[0040] The method of forming a buried word line structure may be performed as follows: First, a gate trench 15 may be formed in a substrate 11. The gate trench 15 may have a line shape intersecting the active region 13 and the isolation layer 12. The gate trench 15 may be formed by forming a mask pattern (not shown) above the substrate 11 and performing an etching process using the mask pattern as an etching mask. In order to form the gate trench 15, a hard mask layer 14 may be used as an etching barrier. The hard mask layer 14 may have a shape patterned by a mask pattern. The hard mask layer 14 may include silicon oxide. The hard mask layer 14 may include tetraethyl orthosilicate (TEOS). The bottom surface of the gate trench 15 may be set at a level higher than the bottom surface of the isolation layer 12.

[0041] Although not shown, a portion of the isolation layer 12 may be recessed to protrude the active region 13 below the gate trench 15. For example, the isolation layer 12 below the gate trench 15 may be selectively recessed in the longitudinal direction of the gate trench 15. As a result, a fin region (whose reference numeral is omitted) may be formed below the gate trench 15. The fin region may be a portion of the channel region.

[0042] Subsequently, a gate dielectric layer 16 may be formed on the bottom and sidewalls of the gate trench 15. Before forming the gate dielectric layer 16, etching damage on the surface of the gate trench 15 may be restored. For example, after forming a sacrificial oxide through a thermal oxidation process, the sacrificial oxide may be removed.

[0043] The gate dielectric layer 16 may be formed by a thermal oxidation process. For example, the gate dielectric layer 16 may be formed by oxidizing the bottom and sidewalls of the gate trench 15 .

[0044] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate dielectric layer 16 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, and a combination thereof.

[0045] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by depositing a pad polysilicon layer and then radically oxidizing the pad polysilicon layer.

[0046] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by forming a pad silicon nitride layer and then radically oxidizing the pad silicon nitride layer.

[0047] Subsequently, a buried word line 17 may be formed over the gate dielectric layer 16. In order to form the buried word line 17, a conductive layer (not shown) may be formed to fill the gate trench 15, and then a recess process may be performed. The recess process may be performed by performing an etch-back process, or by sequentially performing a chemical mechanical polishing (CMP) process and performing an etch-back process. The buried word line 17 may have a recessed shape that fills a portion of the gate trench 15. The top surface of the buried word line 17 may be disposed at a level lower than the top surface of the active area 13. The buried word line 17 may include a metal, a metal nitride, or a combination thereof. For example, the buried word line 17 may be formed of titanium nitride (TiN), tungsten (W), or a stack (TiN / W) of titanium nitride / tungsten. The titanium nitride / tungsten (TiN / W) stack may be a structure in which titanium nitride is conformally formed and then the gate trench 15 is partially filled with tungsten. Titanium nitride may be used alone as the buried word line 17, and may also be referred to as a "TiN-only" structured buried word line 17. As the buried word line 17, a dual gate structure of a titanium nitride / tungsten (TiN / W) stack and a polysilicon layer may be used.

[0048] Subsequently, a gate capping layer 18 may be formed over the buried word line 17. The gate capping layer 18 may include a dielectric material. The remaining portion of the gate trench 15 over the buried word line 17 may be filled with the gate capping layer 18. The gate capping layer 18 may include silicon nitride. According to another embodiment of the present invention, the gate capping layer 18 may include silicon oxide. According to yet another embodiment of the present invention, the gate capping layer 18 may have a nitride-oxide-nitride (NON) structure. The top surface of the gate capping layer 18 may be set at the same level as the top surface of the hard mask layer 14. For this purpose, a chemical mechanical polishing (CMP) process may be performed when forming the gate capping layer 18.

[0049] After forming the gate capping layer 18, impurity regions 19 and 20 may be formed. The impurity regions 19 and 20 may be formed by a doping process such as implantation. The impurity regions 19 and 20 may include a first impurity region 19 and a second impurity region 20. The first impurity region 19 and the second impurity region 20 may be doped with impurities of the same conductivity type. The first impurity region 19 and the second impurity region 20 may have the same depth. According to another embodiment of the present invention, the first impurity region 19 may be deeper than the second impurity region 20. The first impurity region 19 and the second impurity region 20 may also be referred to as a source region / drain region. The first impurity region 19 may be a region to which a bit line contact plug is to be coupled, and the second impurity region 20 may be a region to which a storage node contact plug is to be coupled. The first impurity region 19 and the second impurity region 20 may be disposed in different active regions 13. Moreover, the first impurity region 19 and the second impurity region 20 may be respectively disposed in active regions 13 spaced apart from each other by gate trenches 15. For example, the first impurity region 19 may be formed between two adjacent gate trenches 15. The second impurity region 20 may be formed between the gate trench 15 and the isolation layer 12 .

[0050] A cell transistor of a memory cell may be formed by the buried word line 17 and the first and second impurity regions 19 and 20 .

[0051] refer to FIG. 3A to FIG. 3C , a bit line contact hole 21 may be formed. In order to form the bit line contact hole 21, the hard mask layer 14 may be etched by using a contact mask (not shown). From the perspective of a schematic simplified plan view, the bit line contact hole 21 may have a circular shape or an elliptical shape. A portion of the substrate 11 may be exposed through the bit line contact hole 21. The bit line contact hole 21 may have a diameter controlled to be a predetermined line width. The bit line contact hole 21 may be shaped to expose a portion of the active region 13. For example, the first impurity region 19 may be exposed through the bit line contact hole 21. The bit line contact hole 21 may have a diameter greater than the width of the short axis of the active region 13. Therefore, in the etching process for forming the bit line contact hole 21, a portion of the first impurity region 19, the isolation layer 12, and the gate capping layer 18 may be etched. The gate capping layer 18, the first impurity region 19, and the isolation layer 12 below the bit line contact hole 21 may be recessed to a predetermined depth. Therefore, the bottom surface of the bit line contact hole 21 may extend into the substrate 11. As the bit line contact hole 21 expands, the surface of the first impurity region 19 may be recessed, and the surface of the first impurity region 19 may be disposed at a lower level than the surface of the active region 13 .

[0052] refer to FIG. 4A to FIG. 4C, a preliminary plug 22A may be formed in the bit line contact hole 21. The preliminary plug 22A may be formed by a selective epitaxial growth (SEG) process. For example, the preliminary plug 22A may include a phosphorus-doped epitaxial layer, such as SEGSiP. Using a selective epitaxial growth process for forming the preliminary plug 22A is advantageous because the preliminary plug is formed without a void. According to another embodiment of the present invention, the preliminary plug 22A may be formed by depositing a polysilicon layer and performing a CMP process. The preliminary plug 22A may fill the bit line contact hole 21. The top surface of the preliminary plug 22A may be set at the same level as the top surface of the hard mask layer 14.

[0053] Subsequently, the bit line barrier layer 23A, the bit line conductive layer 24A, and the bit line hard mask layer 25A may be sequentially stacked above the preliminary plug 22A and the hard mask layer 14 in the stated order. The bit line barrier layer 23A and the bit line conductive layer 24A may include a material containing a metal. The bit line barrier layer 23A and the bit line conductive layer 24A may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to one embodiment of the present invention, the bit line barrier layer 23A may include titanium nitride, and the bit line conductive layer 24A may include tungsten (W). The bit line hard mask layer 25A may be formed of a dielectric material having an etching selectivity relative to the bit line conductive layer 24A and the preliminary plug 22A. The bit line hard mask layer 25A may include silicon oxide or silicon nitride. According to one embodiment of the present invention, the bit line hard mask layer 25A may be formed of silicon nitride.

[0054] The stack of the preliminary plug 22A, the bit line barrier layer 23A, the bit line conductive layer 24A, and the bit line hard mask layer 25A may also be referred to as a “bit line stack”.

[0055] Subsequently, a double patterning process may be performed to form a bit line structure.

[0056] refer to FIG. 5A to FIG. 5C , a main hard mask layer MHM may be formed over the bit line hard mask layer 25A of the bit line stack. The main hard mask layer MHM may include a material having an etching selectivity relative to the bit line barrier layer 23A, the bit line conductive layer 24A, and the bit line hard mask layer 25A. For example, the main hard mask layer MHM may include a carbon-containing material formed, for example, by a spin coating process.

[0057] A plurality of first sacrificial mask layers SM1 may be formed over the main hard mask layer MHM. The main hard mask layer MHM and the first sacrificial mask layer SM1 may be formed of different materials. The first sacrificial mask layer SM1 may include silicon oxide. From the perspective of the top view, as indicated by the arrow "V1", the first sacrificial mask layer SM1 and the bit line contact hole 21 may overlap vertically with each other, and as also indicated by the arrow "V1", the first sacrificial mask layer SM1 and the preliminary plug 22A may also overlap vertically with each other. The first sacrificial mask layer SM1 may have an island shape, a stripe shape, or a small line shape.

[0058] refer to FIG. 6A to FIG. 6C , an intermediate sacrificial mask layer SMM may be formed over the first sacrificial mask layer SM1. The intermediate sacrificial mask layer SMM and the first sacrificial mask layer SM1 may be formed of different materials. The intermediate sacrificial mask layer SMM and the main hard mask layer MHM may be formed of the same material. The intermediate sacrificial mask layer SMM may include, for example, a carbon-containing material formed by a spin coating process.

[0059] A plurality of second sacrificial mask layers SM2 may be formed above the intermediate sacrificial mask layer SMM. The second sacrificial mask layer SM2 and the intermediate sacrificial mask layer SMM may be formed of different materials. The first sacrificial mask layer SM1 and the second sacrificial mask layer SM2 may be formed of the same material. The second sacrificial mask layer SM2 and the main hard mask layer MHM may be formed of different materials. The second sacrificial mask layer SM2 may include silicon oxide. From the perspective of the top view, as indicated by the arrow "V2", the second sacrificial mask layer SM2 and the isolation layer 12 may overlap vertically with each other. From the perspective of the top view, the two side ends of the second sacrificial mask layer SM2 and the two side ends of the first sacrificial mask layer SM1 may overlap vertically with each other (see Fig. 6A ). The second sacrificial mask layer SM2 may have an island shape, a stripe shape, or a small line shape.

[0060] The first sacrificial mask layer SM1 and the second sacrificial mask layer SM2 may have different directions. For example, the first sacrificial mask layer SM1 may extend in the second direction D2, and the second sacrificial mask layer SM2 may extend in the third direction D3. Here, the third direction D3 may be the same as the direction of the active area 13.

[0061] refer to 7A to 7C, a main hard mask layer pattern MHM' may be formed by using the first sacrificial mask layer SM1 and the second sacrificial mask layer SM2. The process of forming the main hard mask layer pattern MHM' may include: forming an intermediate sacrificial mask layer pattern SMM' by using the second sacrificial mask layer SM2 as a barrier and etching the intermediate sacrificial mask layer SMM, and forming the main hard mask layer pattern MHM' by using the first sacrificial mask layer SM1, the intermediate sacrificial mask layer pattern SMM', and the second sacrificial mask layer SM2 as a barrier and etching the main hard mask layer MHM.

[0062] From the perspective of the top view, each main hard mask layer pattern MHM' may have a shape in which the shape of the first sacrificial mask layer SM1 and the shape of the second sacrificial mask layer SM2 are merged. Each main hard mask layer pattern MHM' may include a first portion HM and a second portion HM2 coupled in an alternating pattern. The first portion HM1 corresponds to the shape of the first sacrificial mask layer SM1. The second portion HM2 corresponds to the shape of the second sacrificial mask layer SM2. The first portion HM1 of the individual main hard mask layer pattern MHM' may vertically overlap with the bit line contact hole 21, as indicated by the arrow "V11". The first portion HM1 of the individual main hard mask layer pattern MHM' and the preliminary plug 22A may also vertically overlap with each other (also indicated by the arrow "V11").

[0063] The second portion HM2 of the individual main hard mask layer pattern MHM′ may vertically overlap the isolation layer 12 , as indicated by an arrow “ V12 ”.

[0064] The first portion HM1 and the second portion HM2 of the individual main hard mask layer pattern MHM′ may be coupled to each other to form a continuous strip having non-linear polygonal sides including differently oriented line segments.

[0065] As described above, each of the main hard mask layer patterns MHM′ may have a hybrid line shape in which a plurality of first portions HM1 and a plurality of second portions HM2 are merged.

[0066] refer to FIG. 8A to FIG. 8C , a plurality of bit line structures BL may be formed by performing a bit line patterning process. The process of forming the individual bit line structures BL may include etching the bit line stack by using the main hard mask layer pattern MHM' as a barrier, and etching the preliminary plug 22A by using the main hard mask layer pattern MHM' as a barrier. The process of etching the bit line stack may include sequentially etching the bit line hard mask layer 25A, the bit line conductive layer 24A, and the bit line barrier layer 23A by using the main hard mask layer pattern MHM' as a barrier. During the bit line patterning process using the individual main hard mask layer pattern MHM' as a barrier, the intermediate sacrificial mask layer pattern SMM', the first sacrificial mask layer SM1, and the second sacrificial mask layer SM2 may be removed.

[0067] Each bit line structure BL may include a stack of a bit line contact plug 22, a bit line barrier 23, a bit line 24, and a bit line hard mask 25. The bit line hard mask 25 may be formed by etching a bit line hard mask layer 25A, and the bit line 24 may be formed by etching a bit line conductive layer 24A. The bit line barrier 23 may be formed by etching a bit line barrier layer 23A, and the bit line contact plug 22 may be formed by etching a preliminary plug 22A. The preliminary plug 22A may be formed to have the same line width as that of the bit line 24. The bit line contact plug 22 may be formed above the first impurity region 19. The bit line contact plug 22 may couple the first impurity region 19 and the bit line 24 to each other. The bit line contact plug 22 may be formed in the bit line contact hole 21. The line width of the bit line contact plug 22 may be smaller than the diameter of the bit line contact hole 21. Therefore, a gap 22G may be defined on both sides of the bit line contact plug 22.

[0068] As described above, when the bit line contact plug 22 is formed, the gap 22G may be formed in the bit line contact hole 21. This is because the bit line contact plug 22 is formed by being etched to be smaller than the diameter of the bit line contact hole 21. The gap 22G may be independently formed on both sidewalls of the bit line contact plug 22 without having a surrounding shape surrounding the bit line contact plug 22. One bit line contact plug 22 and a pair of gaps 22G may be provided in the bit line contact hole 21, and the pair of gaps 22G may be separated by the bit line contact plug 22. The bottom surface of the gap 22G may extend to the inside of the gate capping layer 18. The bottom surface of the gap 22G may be provided at a level lower than the recessed top surface of the first impurity region 19.

[0069] From a top view perspective, each of the bit line structures BL may have a hybrid line shape in which a plurality of first line portions L1 and a plurality of second line portions L2 are merged.

[0070] The first line portion L1 and the second line portion L2 may have different directions. For example, the first line portion L1 may extend in the second direction D2, and the second line portion L2 may extend in the third direction D3. Here, the third direction D3 may be the same as the direction of the active region 13.

[0071] The first line portion L1 may correspond to the first portion HM1 of the individual main hard mask layer pattern MHM', and the second line portion L2 may correspond to the second portion HM2 of the individual main hard mask layer pattern MHM'. The first line portion L1 may vertically overlap the bit line contact plug 22 (see arrow "V21"), and the second line portion L2 may vertically overlap the isolation layer 12 (see arrow "V22"). Each of the first line portion L1 and the second line portion L2 may have an island shape, a bar shape, or a small line shape. The first line portion L1 and the second line portion L2 may be coupled to each other.

[0072] The first line portion L1 may extend in a direction intersecting the active region 13 , and the second line portion L2 may vertically overlap the isolation layer 12 .

[0073] refer to 9A to 9C , after removing the main hard mask layer pattern MHM', a spacer layer 26A may be formed over the bit line structure BL. The spacer layer 26A may cover both sidewalls and the top surface of the bit line structure BL. The spacer layer 26A may extend to be disposed on both sidewalls of the bit line contact plug 22. The spacer layer 26A may include a dielectric material. The spacer layer 26A may include silicon oxide, silicon nitride, silicon carbide oxide, or a combination thereof. The spacer layer 26A may be a multilayer spacer, such as NON (nitride-oxide-nitride). The spacer layer 26A may include materials with different dielectric constants.

[0074] Subsequently, a plug isolation layer 27 may be formed. The plug isolation layer 27 may include silicon nitride. The plug isolation layer 27 may be disposed between the bit line structures BL. The plug isolation layer 27 may be formed by sequentially depositing silicon nitride and performing an etching process.

[0075] The storage node contact hole 28 may be defined by the plug isolation layer 27 .

[0076] Since the bit line structure BL (particularly the second line portion L2 of the bit line 24) does not overlap the active region 13, the opening area of ​​the storage node contact hole 28 can be sufficiently ensured. Therefore, the non-opening phenomenon of the storage node contact hole 28 can be prevented.

[0077] refer to FIG. 10A to FIG. 10C , the spacer layer 26A may be etched to form the spacer 26. Subsequently, the underlying material may be etched to be self-aligned with the spacer 26. As a result, the storage node contact hole 28 may extend between the bit line structures. The storage node contact hole 28 may expose a portion of the active region 13.

[0078] refer to FIG. 11A to FIG. 11C, a storage node contact plug SNC may be formed. The storage node contact plug SNC may include a stack of a lower plug 29 and an upper plug 30. The lower plug 29 may include polysilicon or single crystal silicon. The upper plug 30 may include a metal material. The lower plug 29 may fill a lower region of the storage node contact hole 28, and the upper plug 30 may cover an upper region of the storage node contact hole 28 and may extend to also at least partially cover the top surface of the bit line structure BL.

[0079] As described above, since the bit line 24 has a nonlinear structure including the first line portion L1 and the second line portion L2, interference between the storage node contact plug SNC and the bit line 24 can be significantly reduced or completely eliminated. Since the second line portion L2 of the bit line 24 does not overlap with the active region 13, a space in which the storage node contact plug SNC is to be formed can be sufficiently ensured. Therefore, an increase in the resistance of the storage node contact plug SNC can be suppressed.

[0080] refer to FIG. 12A to FIG. 12C , a plug capping layer 31 may be formed over the storage node contact plug SNC. The plug capping layer 31 may be filled between the upper plugs 30.

[0081] The capacitor 32 may be formed over the plug capping layer 31 and the storage node contact plug SNC. The capacitor 32 may include a lower electrode, a dielectric layer, and an upper electrode, and the lower electrode may have a cylindrical shape or a pillar shape.

[0082] According to the above-described embodiments of the present invention, by minimizing the interference between the storage node contact plug SNC and the bit line 24, the opening area of ​​the storage node contact hole 28 can be maximized, and through this, the occurrence of non-opening defects that may be caused by line width scaling and defects originating from increased resistance can be suppressed.

[0083] FIG. 13A to FIG. 13I A method for forming a main hard mask layer pattern is illustrated.

[0084] refer to Fig.13A , a first separation pattern P11 may be formed over the main hard mask layer MHM. The first separation pattern P11 may include a carbon-containing material. The first separation pattern P11 may be elongated in the second direction D2.

[0085] The first spacer lines S11 may be formed on both sidewalls of the first separation pattern P11. The first spacer lines S11 may include silicon oxide.

[0086] refer to Fig. 13B , the first separation pattern P11 may be removed. As a result, the first spacer lines S11 may be arranged to be spaced apart from each other in the first direction D1.

[0087] refer to Fig. 13C , a plurality of first cutting mask layers CM1 may be formed over the first spacer lines S11. The first cutting mask layers CM1 may be disposed over the first spacer lines S11. The first cutting mask layers CM1 may include a photoresist pattern.

[0088] refer to Fig.13D , the first spacer lines S11 may be etched using the first cutting mask layer CM1 as a barrier. As a result, a plurality of first sacrificial mask layers SM1 may be formed over the main hard mask layer MHM.

[0089] refer to Fig.13E , a middle sacrificial mask layer SMM may be formed over the first sacrificial mask layer SM1.

[0090] The second separation pattern P12 may be formed over the middle sacrificial mask layer SMM. The second separation pattern P12 may include a carbon-containing material. The second separation pattern P12 may extend in the third direction D3.

[0091] Subsequently, second spacer lines S12 may be formed on both sidewalls of the second partition pattern P12. The second spacer lines S12 may include silicon oxide. The second spacer lines S12 may extend in the third direction D3.

[0092] refer to Fig.13F , the second separation pattern P12 may be removed. As a result, the second spacer lines S12 may be arranged to be spaced apart from each other in the first direction.

[0093] refer to Figure 13G , a plurality of second cutting mask layers CM2 may be formed over the second spacer lines S12. The second cutting mask layers CM2 may be disposed over the second spacer lines S12. The second cutting mask layers CM2 may include a photoresist pattern.

[0094] refer to Fig.13H , the second spacer line S12 may be etched using the second cutting mask layer CM2 as a barrier. As a result, a plurality of second sacrificial mask layers SM2 may be formed over the middle sacrificial mask layer SMM.

[0095] refer to Fig.13I , after removing the second cutting mask layer CM2, the main hard mask layer MHM may be etched by using the first sacrificial mask layer SM1 and the second sacrificial mask layer SM2 as a barrier. As a result, a plurality of main hard mask layer patterns MHM' may be formed. The individual main hard mask layer patterns MHM' may include a first portion HM1 corresponding to the shape of the first sacrificial mask layer SM1 and a second portion HM2 corresponding to the shape of the second sacrificial mask layer SM2.

[0096] Fig.14 A semiconductor device 300 according to another embodiment of the present invention is shown.

[0097] Fig.14 The semiconductor device 300 may be similar to Figure 1A A semiconductor device 100 is provided.

[0098] refer to Fig.14 , the semiconductor device 300 may include a substrate 301, a plurality of active regions 303, and an isolation layer 302. The semiconductor device 300 may also include a plurality of bit lines BL10. Each bit line BL10 may include a first line portion L1 and a second line portion L2. The first line portion L1 may extend in a direction intersecting the active region 303. The second line portion L2 may overlap the isolation layer 302. The individual bit lines BL10 may have a zigzag shape in which the first line portion L1 and the second line portion L2 are alternately arranged. The active regions 303 may be regularly and symmetrically arranged in the first direction D1.

[0099] According to an embodiment of the present invention, the opening area of ​​the storage node contact hole can be maximized by minimizing interference between the storage node contact plug and the bit line, thereby suppressing non-opening defects that may be caused by line width scaling and defects that may be caused by increased resistance.

[0100] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming an isolation layer defining a plurality of active regions over the substrate; forming a bit line stack over the substrate; forming a main hard mask layer over the bit line stack; forming a plurality of first sacrificial mask layers over the main hard mask layer; forming a plurality of second sacrificial mask layers overlying two side ends of the first sacrificial mask layer above the first sacrificial mask layer; forming a main hard mask layer pattern by using the first sacrificial mask layer and the second sacrificial mask layer as a barrier and etching the main hard mask layer; as well as A bit line structure is formed by using the main hard mask layer pattern as a barrier and etching the bit line stack.

2. The method according to claim 1, wherein the first sacrificial mask layer extends in a first direction, and The second sacrificial mask layer extends in a second direction intersecting the first direction.

3. The method according to claim 1, wherein the first sacrificial mask layer extends in a direction intersecting the active region, and The second sacrificial mask layer overlaps the isolation layer.

4. The method according to claim 1, wherein the main hard mask layer pattern comprises: a first portion corresponding to the first sacrificial mask layer; as well as corresponds to a second portion of the second sacrificial mask layer, and The first portion and the second portion are disposed at the same horizontal level.

5. The method according to claim 4, wherein the bit line structure comprises: a first line portion corresponding to the first portion; as well as a second line portion corresponding to the second portion, and The first line portion and the second line portion are disposed at the same horizontal level.

6. The method according to claim 1, wherein forming the first sacrificial mask layer comprises: forming a first separation pattern over the main hard mask layer; forming first spacer lines on both sidewalls of the first separation pattern; removing the first partition pattern; forming a first cutting mask layer over the first spacer line; as well as The first sacrificial mask layer is formed by using the first cutting mask layer as a barrier and etching the first spacer line.

7. The method according to claim 1, wherein forming the second sacrificial mask layer comprises: forming a second separation pattern over the first sacrificial mask layer; forming second spacer lines on both sidewalls of the second separation pattern; removing the second partition pattern; forming a second cutting mask layer over the second spacer line; as well as The second sacrificial mask layer is formed by using the second cutting mask layer as a barrier and etching the second spacer line.

8. The method according to claim 1, further comprising: Before forming the second sacrificial mask layer, An intermediate sacrificial mask layer is formed over the first sacrificial mask layer.

9. A semiconductor device comprising: substrate; an isolation layer formed over the substrate and defining a plurality of active regions; a bit line contact plug coupled to a portion of the active region; as well as a bit line formed over the bit line contact plug, The bit lines include: a first line portion intersecting the active region; as well as A second line portion extends in a direction different from that of the first line portion and overlaps the isolation layer.

10. The semiconductor device according to claim 9, further comprising: a gate trench formed in the active region; as well as A buried word line is formed in the gate trench.

11. The semiconductor device according to claim 9, further comprising: A spacer structure is formed on two sidewalls of the bit line. 12 . The semiconductor device according to claim 9 , wherein both side walls of the bit line have nonlinearity in a direction in which the bit line extends. 13 . The semiconductor device according to claim 9 , wherein the first line portions and the second line portions are alternately arranged in a direction in which the bit line extends. 14 . The semiconductor device of claim 9 , wherein the first line portion and the second line portion include a same material. 15 . The semiconductor device according to claim 9 , wherein the first line portion and the second line portion have the same width and length.

16. The semiconductor device according to claim 9, further comprising: a bit line hard mask over the bit line contact plug, The bit line hard mask has the same shape as that of the bit line. 17 . The semiconductor device according to claim 9 , wherein the bit line comprises a zigzag shape in which the first line portions and the second line portions are alternately arranged.

18. The semiconductor device according to claim 9, further comprising: a storage node contact plug adjacent to the second line portion, The storage node contact plug is coupled to an edge of the active region.

19. The semiconductor device according to claim 9, wherein the second line portion and the active region have non-overlapping directions.

20. A semiconductor device comprising: multiple active regions separated by isolation layers; as well as a bit line stack structure coupled to at least a portion of the active region; wherein the bit line stack structure comprises a nonlinear bit line, the nonlinear bit line comprises a plurality of alternating first line segments and a plurality of second line segments, and The first line segment and the second line segment extend in a first direction and a second direction respectively.

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