Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a semiconductor substrate which is provided with a tunneling dielectric layer, a conductive layer and a mask layer; etching the semiconductor substrate, the tunneling dielectric layer, the conductive layer and the mask layer to define a plurality of stacked structures and a plurality of grooves; forming a lining layer on the side wall of the stack structure; forming an isolation structure in the trench; removing the mask layer to form an opening and expose the conductive layer; filling a conductive material in the opening, so that the conductive material and the conductive layer form a floating gate, and the floating gate comprises a lower part of which the side wall is covered by the lining layer and an upper part of which the side wall is not covered by the lining layer; performing concave etching on the isolation structure to expose the side wall of the upper part of the floating gate, wherein the lining layer protects the tunneling dielectric layer during concave etching; forming an inter-gate dielectric layer on the isolation structure and the floating gate; and forming a control gate on the inter-gate dielectric layer.

Description

Technical Field

[0001] The present invention discloses a semiconductor structure and a forming method thereof, and in particular, a flash memory structure and a forming method thereof. Background Art

[0002] Non-volatile memory includes a floating gate for capturing and storing electrons, a control gate for controlling the potential, and a tunnel oxide layer (TOX layer) as an electron tunneling channel effect. With the trend of semiconductor miniaturization, the size of non-volatile memory continues to shrink to increase integration and improve performance. However, the continuous reduction in size makes the process prone to the defect of corner thinning of the tunnel oxide layer, which will have an adverse effect on the performance of the memory. Therefore, there are still some problems that need to be overcome in the existing semiconductor structure and its formation method. Summary of the invention

[0003] The embodiment disclosed in the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate on which a tunneling dielectric layer, a conductive layer and a mask layer (hard mask layer) are formed; etching the semiconductor substrate, the tunneling dielectric layer, the conductive layer and the mask layer to define a plurality of stacked structures and a plurality of trenches; forming a liner on the sidewall of the stacked structure; forming an isolation structure in the trench; removing the mask layer to form an opening and expose the conductive layer; filling the opening with a conductive material so that the conductive material and the conductive layer constitute a floating gate, and the floating gate includes a lower portion of the sidewall covered by the liner and an upper portion of the sidewall not covered by the liner; etching the isolation structure to expose the sidewall of the upper portion of the floating gate, and the liner protects the tunneling dielectric layer during the etching process; forming an inter-gate dielectric layer on the isolation structure and the floating gate; and forming a control gate on the inter-gate dielectric layer.

[0004] The embodiments disclosed in the present invention further provide a semiconductor structure, comprising: a semiconductor substrate; a plurality of tunneling dielectric layers disposed on the semiconductor substrate; a plurality of floating gates disposed on the tunneling dielectric layers, and each floating gate includes an upper portion and a lower portion; a plurality of lining layers covering the sidewalls of the lower portion of the floating gate; an isolation structure disposed between the floating gates; an inter-gate dielectric layer disposed on the floating gates and the isolation structure; and a control gate disposed on the inter-gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1-Figure 8 , Fig.9A FIG. 4 is a schematic cross-sectional view illustrating an intermediate stage of forming a semiconductor structure according to some embodiments of the present invention.

[0006] Fig. 9BAccording to some embodiments of the present invention, Fig.9A A top view of the semiconductor structure taken along section line AA'.

[0007] Figure 10-Figure 14 FIG. 4 is a schematic cross-sectional view illustrating an intermediate stage of forming another semiconductor structure according to some embodiments of the present invention.

[0008]

Explanation of symbols

[0009] 100,200:Semiconductor structure

[0010] 102:Semiconductor substrate

[0011] 102a: substrate protrusion

[0012] 104, 104a: tunnel dielectric layer

[0013] 106, 106a: Conductive layer

[0014] 108, 108a: Dielectric layer

[0015] 110: Mask layer

[0016] 110a: Hard mask

[0017] 112: Groove

[0018] 113,113': stacked structure

[0019] 114: Lining

[0020] 116: Isolation Structure

[0021] 118: Opening

[0022] 120: floating gate

[0023] 120a: lower part

[0024] 120b: upper part

[0025] 121: Dielectric material layer

[0026] 121a: Sacrificial spacer

[0027] 122: inter-gate dielectric layer

[0028] 124: Control gate

[0029] A-A': section line

[0030] w1: first width

[0031] w2: second width

[0032] d1: first depth

[0033] d2: second depth DETAILED DESCRIPTION

[0034] Figure 1-9A FIG. 1 is a cross-sectional view showing an intermediate stage of forming a semiconductor structure 100 according to some embodiments of the present invention. Figure 1 , a semiconductor substrate 102 is provided and a tunnel dielectric layer 104 , a conductive layer 106 , a dielectric layer 108 and a mask layer 110 are sequentially formed thereon.

[0035] The material of the tunnel dielectric layer 104 may include an oxide (e.g., silicon oxide (SiOx)), and the tunnel dielectric layer 104 may be formed by thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other suitable processes. After the tunnel dielectric layer 104 is formed, a conductive layer 106 is deposited on the tunnel dielectric layer 104. The material of the conductive layer 106 may be, for example, undoped polycrystalline silicon (polycrystalline silicon), doped polycrystalline silicon, amorphous silicon (amorphous silicon), metal, polycrystalline metal silicide (polycide), the like, or a combination thereof. For example, in some embodiments, the material of the conductive layer 106 is doped polycrystalline silicon.

[0036] Continue to see Figure 1 , a dielectric layer 108 and a mask layer 110 are formed on the conductive layer 106. In some embodiments, the material of the dielectric layer 108 is silicon oxide and can be formed by atomic layer deposition (ALD). The material of the mask layer 110 can be, for example, silicon nitride.

[0037] See also Figure 2 , the mask layer 110, the dielectric layer 108, the conductive layer 106, the tunnel dielectric layer 104, and the semiconductor substrate 102 are sequentially etched to form a plurality of stacked structures 113 and trenches 112 located between the stacked structures 113. Each stacked structure 113 is located on the substrate protrusion 102a between the trenches 112, and includes a portion of the etched tunnel dielectric layer 104a, the conductive layer 106a, the dielectric layer 108a, and the hard mask 110a.

[0038] See also Figure 3 , forming a liner 114 on the sidewall of the stacked structure 113. Figure 2 The liner 114 is further formed on the sidewalls of the substrate protrusion 102a and the stacked structure 113. The liner 114 can be formed in the subsequent recessed opening 118 ( Figure 5 ) and isolation structure 116( Fig.12 ), the liner 114 protects the tunnel dielectric layer 104a, the conductive layer 106a or the floating gate 120 covered by it. In some embodiments, the liner 114 is a dense oxide layer formed by in-situ steam generation (ISSG), and its material may be, for example, silicon oxide. The liner 114 surrounds the entire sidewall of the conductive layer 106a.

[0039] See also Figure 4 , a process such as spin on glass (SOG), chemical vapor deposition, high density plasma chemical vapor deposition (HDP-CVD), atomic layer deposition, other suitable processes, or a combination of the above processes (e.g., combining HDP-CVD and SOG) is performed to fill the trench 112 with a dielectric material, and then a planarization process (e.g., chemical mechanical planarization (CMP)) is performed to remove excess dielectric material, thereby forming an isolation structure 116 whose top surface is flush with the top surface of the stacked structure 113. In some embodiments, the isolation structure 116 may be made of the same material as the liner 114. However, it is worth noting that, based on the difference in the process of forming the isolation structure 116 and the liner 114, even if both use the same material, the liner 114 and the isolation structure 116 may still have an interface and / or property difference at a microscopic level. For example, the materials of the liner 114 and the isolation structure 116 are both silicon oxide, however, the liner 114 is formed by in-situ vapor generation (ISSG) and the isolation structure 116 is formed by high density plasma chemical vapor deposition (HDP-CVD) or spin-on glass (SOG) process, so the liner 114 has a denser oxide structure than the isolation structure 116, and the two have different etching rates. Therefore, the liner 114 can provide sufficient protection for the tunnel dielectric layer 104a and the conductive layer 106a covered by it during the etching process.

[0040] Next, see Figure 5, an etching process is performed to remove the hard mask 110a and the dielectric layer 108a to form a plurality of openings 118 exposing the underlying conductive layer 106a. During the etching process, the liner 114 can protect the tunnel dielectric layer 104a and the conductive layer 106a covered thereon, and reduce the thinning of the corners caused by damage to the tunnel dielectric layer 104a. The above etching will also remove a portion of the liner 114 and the isolation structure 116, so that the width of the opening 118 is greater than the original width of the hard mask 110a, and a portion of the sidewall of the conductive layer 106a is exposed.

[0041] See also Figure 6 , firstly fill the opening 118 with a conductive material, and then perform a planarization process to make the top surface of the filled conductive material flush with the top surface of the isolation structure 116, thereby obtaining a floating gate 120 composed of the conductive material and the conductive layer 106a, wherein the floating gate 120 includes a lower portion 120a whose sidewall is covered by the liner 114 and an upper portion 120b whose sidewall is not covered by the liner 114. In the following text, the stacked structure 113' will represent the stacked structure including the floating gate 120 and the tunneling dielectric layer 104a. The opening 118 can be filled in any suitable manner to form the floating gate 120, such as: PVD, CVD, ALD, LPCVD, or other suitable processes. In some embodiments, the sidewall profile of the upper portion 120b is curved and the sidewall profile of the lower portion 120a is straight. The top surface of the upper portion 120b has a first width W1 and the top surface of the lower portion 120a has a second width W2, and the first width W1 is greater than the second width W2. The cross section of the upper portion 120b of the floating gate 120 is bowl-shaped. The conductive material is the same material as the conductive layer 106a. In other embodiments, the conductive material is a material different from the conductive layer 106a. The process of forming the floating gate 120 may further include an ion implantation process. For example, a polysilicon layer may be first deposited using silane as a gas source through a deposition process such as LPCVD, and then dopants may be implanted to form the floating gate 120.

[0042] See also Figure 7 , the isolation structure 116 is recessed to expose a portion of the sidewall of the floating gate 120. In some embodiments, the top surface of the recessed isolation structure 116 is located between the top surface and the bottom surface of the upper portion 120b of the floating gate 120. That is, the etching process exposes a portion of the sidewall of the upper portion 120b of the floating gate 120, but does not expose the sidewall of the lower portion 120a of the floating gate 120 and / or the liner 114. Figure 7 In the embodiment of FIG. 1 , the recessed isolation structure 116 has a flat top surface.

[0043] See also Figure 8, an inter-gate dielectric layer 122 is conformably formed on the semiconductor structure 100 to cover the top surface and sidewalls of the floating gate 120, and the top surface of the isolation structure 116. In some embodiments, the inter-gate dielectric layer 122 may be a single-layer structure or a multi-layer structure, and the material of the inter-gate dielectric layer 122 may include oxide, nitride, or a combination thereof. For example, the inter-gate dielectric layer 122 may be an oxide / nitride / oxide (ONO) structure. The inter-gate dielectric layer 122 does not directly contact the lower portion 120a of the floating gate 120 and the liner 114.

[0044] See also Fig.9A , a control gate 124 is formed on the inter-gate dielectric layer 122, thereby obtaining the semiconductor structure 100. In some embodiments, the control gate 124 may be a single-layer or multi-layer structure, and the material of the control gate 124 may include polysilicon, metal, metal silicide, similar conductive materials, or a combination thereof. After forming the control gate 124, other conventional processes may be continued to be performed to complete a semiconductor device such as a memory, which will not be described in detail herein.

[0045] Fig. 9B According to some embodiments of the present invention, Fig.9A The top view of the semiconductor structure 100 is taken along the section line AA'. Fig.9A and Fig. 9B As shown, in some embodiments, all sidewalls of the tunnel dielectric layer 104a and the lower portion 120a of the floating gate 120 of the semiconductor structure 100 are surrounded by the liner 114, thereby providing protection for the lower portion 120a of the floating gate 120 and the tunnel dielectric layer 104a during the etching process and reducing corner thinning caused by damage to the tunnel dielectric layer 104a.

[0046] Figure 10-Figure 14 2 is a cross-sectional view showing an intermediate stage of forming a semiconductor structure 200 according to some other embodiments of the present invention. Fig.10 , its continuation Figure 7 In this embodiment, the isolation structure 116 is etched back for the second time to form a concave top surface of the isolation structure 116. Figure 7After the first recessed etching process, a dielectric material layer 121 is conformally formed on the semiconductor structure 200. That is, the dielectric material layer 121 follows the contours of the floating gate 120 and the isolation structure 116, covering the top surface and exposed sidewalls of the floating gate 120 and the top surface of the isolation structure 116. In some embodiments, the dielectric material layer 121 can be formed by processes such as CVD and atomic layer deposition (ALD). The dielectric material layer 121 is an oxide, such as silicon oxide formed using tetraethoxysilane (TEOS) as a precursor.

[0047] See also Fig.11 , an anisotropic etching process is performed on the semiconductor structure 200 to remove a portion of the dielectric material layer 121 and form a plurality of sacrificial spacers 121a on opposite sidewalls of the floating gate 120. The sacrificial spacers 121a may be formed by any suitable process, such as reactive ion etching (RIE). The sacrificial spacers 121a are used to cover the top surface and a portion of the sidewalls of the floating gate 120 to protect the floating gate 120 from being over-etched in the subsequent etching process of the isolation structure 116. In some embodiments, the sacrificial spacers 121a only cover the top surface and sidewalls of the floating gate 120, but do not cover the top surface of the isolation structure 116 (not shown).

[0048] See also Fig.12 , a second recessed etching process is performed on the semiconductor structure 200 to remove the sacrificial spacer 121a and further recessed the isolation structure 116. In some embodiments, the second recessed etching process may use the same etching process as the first recessed etching process. The first recessed etching process recesses the top surface of the isolation structure 116 to a first depth d1 from a horizontal plane at the same height as the top surface of the floating gate 120, and the second recessed etching process further recesses a portion of the top surface of the isolation structure 116 to a second depth d2 from a horizontal plane at the same height as the top surface of the isolation structure 116 after the recessed etching. Specifically, since the center line portion of the isolation structure 116 is not covered by the sacrificial spacer 121a or is covered with a thinner thickness, it will be etched deeper. On the contrary, the portion of the isolation structure 116 away from the center line is covered by the thicker sacrificial spacer 121a and will be etched shallower, thereby making the isolation structure 116 have a concave top surface facing the semiconductor substrate 102. Compared to Figure 8-9AIn the embodiment described above, the isolation structure 116 is etched to a deeper depth in this embodiment, which can further reduce the coupling effect between the floating gates 120, thereby improving the reliability of the device. It is worth noting that the second etch process still keeps the sidewalls of the lower portion 120a of the floating gate 120 and / or the sidewalls of the tunnel dielectric layer 104a not exposed, which helps to maintain the performance of the device. Therefore, during the second etch process, the liner 114 can be used to protect the lower portion 120a of the floating gate 120 and the tunnel dielectric layer 104a. The first etch process and the second etch process can be the same etching process, such as a plasma etching process. The horizontal plane of the lower end point of the first depth d1 is located between the horizontal planes of the top surface and the bottom surface of the upper portion 120b of the floating gate 120, and the horizontal plane of the lower end point of the second depth d2 is located between the horizontal planes of the top surface and the bottom surface of the lower portion 120a of the floating gate 120. The first width w1 of the upper portion 120 b of the floating gate 120 after the second etch-back process is about 65 nm to about 70 nm.

[0049] See also Fig.13 , conformably forming an inter-gate dielectric layer 122 on the semiconductor structure 200 to cover the top surface and sidewalls of the floating gate 120 and the top surface of the isolation structure 116. The formation method and related properties of the inter-gate dielectric layer 122 are similar to those for Figure 8 The description is not repeated here.

[0050] Finally, see Fig.14 , forming a control gate 124 on the inter-gate dielectric layer 122, thereby obtaining a semiconductor structure 200. The formation method and related properties of the control gate 124 are similar to those for Fig.9A The description is similar and will not be repeated here.

[0051] The various embodiments described in this application provide several advantages over the prior art. It should be understood that not all advantages are necessarily discussed here, not all embodiments need to have specific advantages, and other embodiments may provide different advantages. In summary, the embodiments of the present application form a liner covering the lower sidewall of the floating gate, so that the floating gate and / or the tunnel dielectric layer are protected during the etching process, and the corner thinning caused by damage to the tunnel dielectric layer is reduced.

[0052] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which the present application belongs can more easily understand the viewpoints of the embodiments of the present application. Those with ordinary knowledge in the technical field to which the present application belongs should understand that they can design or modify other processes and structures based on the embodiments of the present application to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present application belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present application, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: include; Providing a semiconductor substrate, on which a tunnel dielectric layer, a conductive layer, and a mask layer are sequentially formed; Etching the semiconductor substrate, the tunnel dielectric layer, the conductive layer, and the mask layer to define a plurality of stacked structures and a plurality of trenches between the plurality of stacked structures; forming a lining layer on the sidewalls of the plurality of stacked structures; forming an isolation structure in the plurality of trenches; removing the mask layer to form an opening to expose the conductive layer; Filling a conductive material in the opening, wherein the conductive material and the conductive layer together form a floating gate, wherein the floating gate includes a lower portion whose sidewall is covered by the liner and an upper portion whose sidewall is not covered by the liner; Etching the isolation structure to expose the sidewall of the upper portion of the floating gate, wherein the liner protects the tunnel dielectric layer during the etching process; forming an inter-gate dielectric layer on the isolation structure and the floating gate; and A control gate is formed on the inter-gate dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The liner surrounds the entire sidewall of the lower portion of the floating gate.

3. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the liner is performed by an on-site vapor generation method.

4. The method for forming a semiconductor structure according to claim 1, wherein: The step of recessing the isolation structure does not expose the lower portion of the floating gate and the liner.

5. The method for forming a semiconductor structure according to claim 1, wherein: The isolation structure has a flat top surface after recessing.

6. The method for forming a semiconductor structure according to claim 1, wherein: Before the isolation structure is recessed, the method further includes: forming a plurality of sacrificial spacers on the sidewall of the upper portion of the floating gate, and the isolation structure is further recessed, the method further includes: removing the plurality of sacrificial spacers and forming a concave top surface between the plurality of sacrificial spacers toward the semiconductor substrate.

7. A semiconductor structure, characterized in that: include: a semiconductor substrate; A plurality of tunnel dielectric layers are disposed on the semiconductor substrate; A plurality of floating gates are disposed on the plurality of tunnel dielectric layers, each of the floating gates comprising: an upper portion and a lower portion; A plurality of liner layers covering the sidewalls of the lower portions of the plurality of floating gates; an isolation structure disposed between the plurality of floating gates; an inter-gate dielectric layer disposed on the plurality of floating gates and the isolation structure; and A control gate is disposed on the inter-gate dielectric layer.

8. The semiconductor structure according to claim 7, wherein: A top surface of the isolation structure is between a top surface and a bottom surface of the upper portion of the floating gate.

9. The semiconductor structure according to claim 7, wherein: The thickness of the liner is 1 nm to 20 nm.

10. The semiconductor structure according to claim 7, wherein: The cross section of the upper portion of the floating gate is bowl-shaped.

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