A GaN HEMT Resistant to Single-Event Irradiation

Abstract

The present invention provides a GaN HEMT resistant to single particle irradiation. A stepped structure is arranged on the drain side of the p-GaN layer, which effectively alleviates the electric field aggregation near the drain side under the gate and suppresses the electric field spike, thereby improving the off-state blocking ability of the device under single particle irradiation. Etching holes are arranged on the stepped structure of the p-GaN layer, and metal is deposited to form an extraction electrode, which effectively extracts and discharges the excess holes induced by irradiation near the gate, avoiding electron injection caused by the accumulation of holes under the gate. The arrangement of the stepped structure and the extraction electrode can improve the single particle irradiation resistance of the device from the perspectives of weakening the electric field and extracting excess carriers respectively.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, relates to GaN power devices, and particularly relates to a GaN HEMT resistant to single particle irradiation. Background Art

[0002] Due to the presence of a two-dimensional electron gas with high concentration and high mobility at the heterojunction interface of GaN HEMT, it has advantages such as low on-resistance and high operating frequency, which is beneficial to the realization of a low-loss and miniaturized power supply system. In particular, it has broad application prospects in irradiation scenarios such as aerospace and satellite communication.

[0003] In an irradiation scenario, the incidence of high-energy particles will cause irradiation-induced carriers to be generated inside the device. For a GaN HEMT with a conventional structure, there is serious electric field aggregation at the gate edge near the drain side. The strong electric field in this region will further cause the impact ionization of irradiation-induced carriers, generating more non-equilibrium carriers, and then leading to an increase in leakage current or even device burnout.

[0004] Therefore, for the application and development of GaN HEMT in an irradiation scenario, corresponding improvements need to be made to the device structure to effectively suppress the electric field spike near the gate, extract non-equilibrium holes, and improve the single particle irradiation resistance of GaN HEMT. Summary of the Invention

[0005] To solve the above problems, the present invention provides a GaN HEMT resistant to single particle irradiation. The present invention sets a stepped structure on the p-GaN layer near the drain side, effectively alleviating the electric field aggregation near the drain side under the gate and suppressing the electric field spike, thereby improving the off-state blocking ability of the device under single particle irradiation; etching holes are set on the stepped structure of the p-GaN layer, and metal is deposited to form an extraction electrode, effectively extracting and discharging the excess holes induced by irradiation near the gate, and avoiding electron injection caused by the accumulation of holes under the gate. The setting of the stepped structure and the extraction electrode can improve the single particle irradiation resistance of the device from the perspectives of weakening the electric field and extracting excess carriers respectively.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention provides a GaN HEMT resistant to single - particle irradiation. The GaN HEMT resistant to single - particle irradiation includes a substrate, a buffer layer, a channel layer, a barrier layer, and a first passivation layer from bottom to top. A first source electrode and a drain electrode are respectively arranged on both sides of the channel layer. A p - GaN layer is arranged near the first source electrode side between the first source electrode and the drain electrode. At least one stepped structure from high to low is arranged near the drain electrode side of the p - GaN layer. The stepped - structure region is the non - gate region of the p - GaN layer, and the non - stepped - structure region near the first source electrode side of the p - GaN layer is the gate region of the p - GaN layer. A gate electrode is arranged on the gate region of the p - GaN layer; Etching holes arranged at intervals in the y - direction are arranged on the stepped structure of the p - GaN layer, and extraction electrodes are arranged in the etching holes. The extraction electrodes are in contact with the side wall and the bottom along the etching holes; A second source electrode is arranged near the first source electrode, and the first source electrode is connected to the extraction electrodes and the second source electrode through a metal interconnection layer; Except for the top surfaces of the extraction electrodes, the first source electrode, the second source electrode, and the drain electrode, the remaining regions of the surface are filled with a second passivation layer.

[0008] As a preferred embodiment of the present invention, the number of steps in the non - gate region of the p - GaN layer is one or more. The sizes of each step do not need to be equal. The distance from the bottom - most step to the drain electrode is greater than 0, and the height of the top - most step is less than the height of the gate region of the p - GaN layer.

[0009] In the present invention, the height of the step is defined as the distance from the top of the step to the upper surface of the barrier layer.

[0010] As a preferred embodiment of the present invention, the depth of the extraction electrode and the depth of the second source electrode are independent of each other.

[0011] As a preferred embodiment of the present invention, the etching holes are etched to the upper surface or inside of the buffer layer; or the etching holes are etched to the upper surface or inside of the channel layer. The shape of the etching cross - section of the etching holes in the xy - plane for forming the extraction electrodes is circular, elliptical, polygonal, or other irregular - shaped edges. The shapes and sizes of the etching cross - sections of adjacent etching holes in the xy - plane are the same or different; The ratio of the projection length of the etching holes in the y - direction to the length of the p - GaN layer in the y - direction is 5% - 90%.

[0012] As a preferred embodiment of the present invention, the second source electrode penetrates through the barrier layer and the channel layer and extends into the buffer layer; or the second source electrode penetrates through the barrier layer and extends into the channel layer; or the second source electrode penetrates through the barrier layer and the channel layer and contacts the upper surface of the buffer layer; or the second source electrode penetrates through the barrier layer and contacts the upper surface of the channel layer.

[0013] As a preferred embodiment of the present invention, the gate is one or a combination of a Schottky-type p-GaN gate, an ohmic p-GaN gate, a recessed gate structure, and a MIS gate, or a complex gate structure having the above gate structure characteristics.

[0014] As a preferred embodiment of the present invention, the doping concentration of the p-GaN layer is 1×10 17 cm -3 to 1×10 21 cm -3 , where the height of the gate region of the p-GaN layer is 50 nm to 150 nm, and the dimension in the x direction is 500 nm to 5000 nm; the height of each step of the non-gate region of the p-GaN layer is 5 nm to 120 nm, and the dimension of each step in the x direction is 500 nm to 5000 nm.

[0015] As a preferred embodiment of the present invention, the non-gate region of the p-GaN layer is a bevel structure, and the angle between the bevel and the upper surface of the barrier layer is ≥2°.

[0016] In the present invention, 2° ≤ the angle between the bevel and the upper surface of the barrier layer < 90°. When the angle between the bevel and the upper surface of the barrier layer is 90°, the bevel becomes a stepped structure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1) In the present invention, through fine parameter settings (such as the number of steps, the size of each step, etc.) of the non-gate region and the gate region of the p-GaN layer, in the blocking state, the stepped structure of the non-gate region of the p-GaN layer can be fully depleted, thereby effectively alleviating the electric field aggregation near the drain side under the gate, effectively reducing the peak electric field intensity, fully reducing the transient current caused by irradiation, and improving the single-event irradiation resistance of the device.

[0019] 2) In the present invention, through fine parameter settings (such as the position of the extraction electrode relative to the step, the size of the electrode, the ratio of the projection length of the extraction electrode in the y direction to the length of the p-GaN layer in the y direction, etc.) of the extraction electrode, the extraction electrode can fully collect and discharge the excess holes induced by irradiation, weaken the accumulation of holes in the region under the gate, and further improve the single-event irradiation resistance of the device.

[0020] 3) The stepped structure of the non-gate region of the p-GaN layer in the present invention is beneficial to alleviating the dynamic resistance problem related to electric field aggregation while alleviating the electric field aggregation and improving the irradiation resistance of the device, and improving the dynamic conduction performance of the device.

[0021] 4) The manufacturing process of the device structure in the present invention is completely compatible with the traditional process without adding additional complex processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1(a) is a schematic diagram of Embodiment 1 of the present invention.

[0024] Figure 1(b) is a sectional view taken along AA' in Figure 1(a).

[0025] Figure 1(c) is a sectional view taken along BB' in Figure 1(a).

[0026] Figure 2 is a schematic diagram of Step 1 of the present invention.

[0027] Figure 3 is a schematic diagram of Step 2 of the present invention.

[0028] Figure 4 is a schematic diagram of Step 3 of the present invention.

[0029] Figure 5 is a schematic diagram of Step 4 of the present invention.

[0030] Figure 6 is a schematic diagram of Step 5 of the present invention.

[0031] Figure 7 is a schematic diagram of Step 6 of the present invention.

[0032] Figure 8 is a schematic diagram of Step 7 of the present invention.

[0033] Figure 9 is a schematic diagram of Step 8 of the present invention.

[0034] Figure 10 is a schematic diagram of Step 9 of the present invention.

[0035] Figure 11 is a schematic diagram of Step 10 of the present invention.

[0036] Figure 12 is a schematic diagram of Step 11 of the present invention.

[0037] Figure 13 is a schematic diagram of Step 12 of the present invention.

[0038] Figure 14 is a schematic diagram of Step 13 of the present invention.

[0039] Figure 15It is a schematic diagram of step 14 of the present invention.

[0040] Figure 16 It is a schematic diagram of step 15 of the present invention.

[0041] Figure 17 It is a schematic diagram of step 16 of the present invention.

[0042] Figure 18(a) is a schematic diagram of Embodiment 2 of the present invention.

[0043] Figure 18(b) is a cross-sectional view of AA' in Figure 18(a).

[0044] Figure 18(c) is a cross-sectional view of BB' in Figure 18(a).

[0045] Figure 19(a) is a schematic diagram of Embodiment 3 of the present invention.

[0046] Figure 19(b) is a cross-sectional view of AA' in Figure 19(a).

[0047] Figure 19(c) is a cross-sectional view of BB' in Figure 19(a).

[0048] Figure 20(a) is a schematic diagram of Embodiment 4 of the present invention.

[0049] Figure 20(b) is a cross-sectional view of AA' in Figure 20(a).

[0050] Figure 20(c) is a cross-sectional view of BB' in Figure 20(a).

[0051] Figure 21(a) is a schematic diagram of Embodiment 5 of the present invention.

[0052] Figure 21(b) is a cross-sectional view of AA' in Figure 21(a).

[0053] Figure 21(c) is a cross-sectional view of BB' in Figure 21(a).

[0054] Figure 22 It is the electric field distribution diagram on the upper surface of the channel layer of a device with a stepped structure having the same thickness but different lengths and a device without a stepped structure under a 400V voltage.

[0055] In the figure: 1. Substrate; 2. Buffer layer; 3. Channel layer; 4. Barrier layer; 5. First passivation layer; 6. First source electrode; 7. Drain electrode; 8-1. p-GaN layer gate region, 8-2. p-GaN layer non-gate region; 9. Gate electrode; 10. Extraction electrode; 11. Second source electrode; 12. Metal interconnection layer; 13. Second passivation layer; 14. Hole storage layer. Detailed implementation manners

[0056] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0057] The preparation processes of the present invention are all existing processes, including the following steps:

[0058] 1) Select a substrate layer. The materials of the substrate layer include, but are not limited to, one of the materials such as silicon, silicon carbide, sapphire, gallium nitride, gallium oxide, and diamond, or several of these materials, or other complex materials with the above material components, or composite material substrates such as QST substrates. The size of the substrate layer includes, but is not limited to, two inches, four inches, and six inches.

[0059] 2) The growth methods of the buffer layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, and PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the buffer layer includes, but is not limited to, growing group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, etc., at a temperature of 0 to 1500 °C and a pressure of 0 to 300 Torr. One of these materials, or several of these materials, or other complex materials with the above material components are used as the device buffer layer. The buffer layer structure consists of at least one layer of material, and also includes, but is not limited to, one of various complex structure designs such as an AlGaN stress release layer with a gradually changing Al component, a superlattice structure, and a low-temperature grown AlN structure, or a combination of several of these complex structures, or other complex structures with the above structural characteristics.

[0060] 3) The growth methods of the channel layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, and PEALD, or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the channel layer includes, but is not limited to, growing group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, etc., at a temperature of 0 to 1500 °C and a pressure of 0 to 300 Torr. One of these materials, or several of these materials, or other complex materials with the above material components are used as the device channel layer. The channel layer is composed of at least one layer of semiconductor material and also includes, but is not limited to, various complex structure designs.

[0061] 4) The growth methods of the barrier layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the barrier layer includes, but is not limited to, growing one of the group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN or two-dimensional materials, or several of them, or other complex materials with the above material components as the device barrier layer under the conditions of temperature from 0 to 1500 °C and pressure from 0 to 300 Torr. The barrier layer is composed of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs.

[0062] 5) The growth methods of the p-GaN layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The growth process of the p-GaN layer includes, but is not limited to, growing the p-GaN layer under the conditions of temperature from 0 to 1500 °C and pressure from 0 to 300 Torr. The p-GaN layer is composed of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs.

[0063] 6) The etching methods of the p-GaN layer include, but are not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the p-GaN layer includes, but is not limited to, etching the p-GaN layer under the conditions of RF power from 0 to 600 W and pressure from 0 to 100 mTorr.

[0064] 7) The growth methods of the first source and drain include, but are not limited to, one or a combination of coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, etc., or other complex process flows involving multiple coating methods. The growth process of the first source and drain includes, but is not limited to, growing one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of them, or other complex materials with the above material components as the device first source and drain under the conditions of temperature from 0 to 1200 °C and pressure from 0 to 300 Torr. The annealing method includes, but is not limited to, annealing at 95 to 1500 °C.

[0065] 8) The deposition methods of the first passivation layer and the second passivation layer include, but are not limited to, one of the growth methods such as MBE, MOCVD, MPCVD, LPCVD, PLD, ALD, PEALD, etc., or a combination of several growth methods, or other complex process flows involving multiple growth methods. The deposition process of the first passivation layer and the second passivation layer includes, but is not limited to, depositing, under the conditions of a temperature of 0 - 1500 °C and a pressure of 0 - 300 Torr, including but not limited to (Al x Ga 1-x )2O3, Al2O3, AlN, SiN x , SiO2, HfO2, ZrO2, SOG, PI, SiON, HfZrO, etc., as the first passivation layer and the second passivation layer of the device, either one of these materials, or several of these materials, or a composite material composed of other multiple materials with the above material components. The structure of the first passivation layer and the second passivation layer consists of at least one layer, and includes, but is not limited to, various complex structure designs.

[0066] 9) The etching methods of the first passivation layer and the second passivation layer include, but are not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the first passivation layer and the second passivation layer includes, but is not limited to, etching the first passivation layer and the second passivation layer under the conditions of an RF power of 0 - 600 W and a pressure of 0 - 100 mTorr.

[0067] 10) The growth methods of the gate include, but are not limited to, one or a combination of coating methods such as E - beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, etc., or other complex process flows involving multiple coating methods. The growth process of the gate includes, but is not limited to, growing, under the conditions of a temperature of 0 - 1200 °C and a pressure of 0 - 300 Torr, including but not limited to Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., as the gate of the device, and the annealing method includes, but is not limited to, annealing at 95 - 1500 °C.

[0068] 11) The etching methods of the buffer layer, the channel layer and the barrier layer include, but are not limited to, one of the etching methods such as RIE, ICP, hydrogen fluoride release etching, wet etching, etc., or a combination of several etching methods, or other complex process flows involving multiple etching methods. The etching process of the buffer layer, the channel layer and the barrier layer includes, but is not limited to, etching under the conditions of an RF power of 0 - 600 W and a pressure of 0 - 100 mTorr.

[0069] 12) The growth methods of the extraction electrode, the second source electrode, and the metal interconnection layer include, but are not limited to, one or a combination of coating methods such as E-beam evaporation deposition, Sputter, LPCVD, PLD, ALD, PEALD, etc., or other complex process flows involving multiple coating methods. The growth process of the extraction electrode, the second source electrode, and the metal interconnection layer includes, but is not limited to, growing one, several, or other complex materials with the above material components such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc. as the device extraction electrode, the second source electrode, and the metal interconnection layer under the conditions of a temperature of 0 - 1200 °C and a pressure of 0 - 300 Torr. The annealing method includes, but is not limited to, annealing at 95 - 1500 °C.

[0070] Example 1

[0071] See Figures 1(a)-1(c) In this invention, a GaN HEMT resistant to single - particle irradiation is provided. The GaN HEMT resistant to single - particle irradiation includes, from bottom to top, a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a first passivation layer 5. A first source electrode 6 and a drain electrode 7 are respectively arranged on both sides of the channel layer 3. A p - GaN layer is arranged near the first source electrode 6 between the first source electrode 6 and the drain electrode 7. The p - GaN layer is composed of a p - GaN layer gate region 8 - 1 near the first source electrode 6 and a p - GaN layer non - gate region 8 - 2 near the drain electrode 7. A gate 9 is arranged on the p - GaN layer gate region 8 - 1. The p - GaN layer non - gate region 8 - 2 includes a stepped structure. Etching holes are arranged at intervals in the y - direction on the p - GaN layer non - gate region 8 - 2. The bottom of the etching holes is located inside the buffer layer 2. Extraction electrodes 10 are arranged in the etching holes; a second source electrode 11 is arranged near the first source electrode 6, and the first source electrode 6, the extraction electrodes 10, and the second source electrode 11 are connected by a metal interconnection layer 12. Except for the top surfaces of the extraction electrodes 10, the first source electrode 6, the second source electrode 11, and the drain electrode 7, the remaining regions of the surface are filled with a second passivation layer 13.

[0072] In this embodiment, the size of the p - GaN layer gate region in the x - direction is 3 μm, the size in the y - direction is 60 μm, and the height is 100 nm. The size of the p - GaN layer non - gate region in the x - direction is 3 μm, the size in the y - direction is 60 μm, and the height is 20 nm.

[0073] In this embodiment, the number of extraction electrodes arranged at intervals on the non-gate region of the p-GaN layer is 4. The etching holes of the extraction electrodes are rectangular in shape when opening on the first and second passivation layers, with a size of 2 μm in the x direction and 6 μm in the y direction, and the spacing between adjacent etching holes is 10 μm. The shapes and sizes of the openings of adjacent extraction electrodes on the first and second passivation layers are the same. The etching holes forming the extraction electrodes are rectangular in shape on the buffer layer, channel layer, and barrier layer, with a size of 1.2 μm in the x direction and 5 μm in the y direction.

[0074] The distance between the gate and the first source is 1 μm, and the distance between the gate and the drain is 15 μm; the size of the first source and the drain in the x direction is 3 μm; the distance between the second source and the first source is 1 μm, the size of the second source in the x direction is 3 μm, and the bottom of the second source is located inside the buffer layer, 50 nm away from the upper surface of the buffer layer.

[0075] The distance between the interconnecting metal connecting the extraction electrode, the second source, and the first source and the drain on the side close to the drain is 10 μm.

[0076] The substrate material of the device of the present invention includes, but is not limited to, one of silicon, silicon carbide, sapphire, gallium nitride, gallium oxide, diamond, etc., or several of these materials, or other complex materials with the above material components, or composite material substrates such as QST substrates. Silicon is selected as the substrate in this embodiment.

[0077] The buffer layer of the device of the present invention includes, but is not limited to, one of group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials with the above material components. The buffer layer structure of the device of the present invention consists of at least one layer of material, and also includes, but is not limited to, various complex structure designs such as an AlGaN stress relaxation layer with a gradually changing Al component, a superlattice structure, a low-temperature-grown AlN structure, etc., or a combination of several of these complex structures, or other complex structures with the above structural characteristics. In this embodiment, an AlN layer with a thickness of 50 nm and a GaN layer with a thickness of 3000 nm are selected as the buffer layer from bottom to top.

[0078] The channel layer of the device of the present invention includes, but is not limited to, one of group III nitrides such as AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials with the above material components. The channel layer is composed of at least one layer of semiconductor material and also includes, but is not limited to, various complex structure designs. GaN with a thickness of 300 nm is selected as the channel layer in this embodiment.

[0079] The barrier layer of the device of the present invention includes, but is not limited to, one of materials such as group III nitrides like AlN, AlGaN, GaN, InN, InGaN, InAlN, or two-dimensional materials, or several of these materials, or other complex materials with the above material components. The barrier layer is composed of at least one layer of semiconductor material and includes, but is not limited to, various complex structure designs. In this embodiment, AlGaN with an Al component of 0.20 and a thickness of 15 nm is selected as the barrier layer.

[0080] The Mg doping concentration of the p-GaN layer of the device of the present invention can be 1×10 17 ~1×10 21 cm -3 ⁻³, and the thickness can be 0 - 500 nm. In this embodiment, a p-GaN layer with a doping concentration of 1×10 19 cm -3 ⁻³ and a thickness of 100 nm is selected.

[0081] The gate material of the device of the present invention includes, but is not limited to, one of materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of these materials, or other complex materials with the above material components. The gate structure of the device of the present invention includes, but is not limited to, one or a combination of several of Schottky-type p-GaN gates, ohmic p-GaN gates, recessed gates, MIS gates, or other complex gate structures with the above gate characteristics. In this embodiment, 20 nm of Ni and 80 nm of Au are selected as the gate metal of the device to form a Schottky contact with the p-GaN layer.

[0082] The materials of the first source and drain of the device of the present invention include, but is not limited to, one of materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of these materials, or other complex materials with the above material components. The structure of the drain of the device of the present invention includes, but is not limited to, one or a combination of two of Schottky drains and ohmic drains, or other complex drain structures with the characteristics of Schottky drains and ohmic drains. The structure of the first source of the device of the present invention includes, but is not limited to, one or a combination of two of Schottky sources and ohmic sources, or other complex source structures with the characteristics of Schottky sources and ohmic sources. In this embodiment, 20 nm of Ti, 150 nm of Al, 50 nm of Ni, and 80 nm of Au are selected as the metals of the first source and drain of the device to form an ohmic contact with the channel layer.

[0083] The second source material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of these materials, or other complex materials having the above material components. The structure of the source electrode of the device of the present invention includes, but is not limited to, one or a combination of two of Schottky source and Ohmic source, or other complex source structures having the characteristics of Schottky source and Ohmic source. In this embodiment, 20 nm of Ni and 200 nm of Au are selected as the second source material of the device, and a Schottky contact is formed with the semiconductor layer on the sidewall and bottom of the etching hole.

[0084] The extraction electrode material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of these materials, or other complex materials having the above material components. In this embodiment, 20 nm of Ni and 200 nm of Au are selected as the extraction electrode material of the device, and a Schottky contact is formed with the semiconductor layer on the sidewall and bottom of the etching hole.

[0085] The metal interconnection layer material of the device of the present invention includes, but is not limited to, one of the materials such as Ti, Al, Ni, Au, Pd, Pt, Ag, Cu, W, Cr, TiN, polysilicon, etc., or several of these materials, or other complex materials having the above material components. In this embodiment, 20 nm of Ni and 200 nm of Au are selected as the metal interconnection layer material of the device.

[0086] See Figures 2-17 , this embodiment provides a preparation process of a GaN HEMT resistant to single - particle irradiation, and a GaN HEMT resistant to single - particle irradiation as shown in Figures 1(a)-1(c) is prepared. The specific steps are as follows:

[0087] 1) Select a substrate. In this embodiment, a two - inch Si(111) is used as the substrate. First, it is put into a mixed solution of three parts of sulfuric acid, one part of hydrogen peroxide and one part of water for pickling, then put into a 5% hydrofluoric acid solution to remove the surface oxide, and finally the surface of the substrate is cleaned successively with acetone, isopropyl alcohol, and absolute ethanol, and finally placed in water, taken out and dried, as shown in Figure 2 .

[0088] 2) Growth buffer layer. In this embodiment, trimethylaluminum (TMAl) and NH3 are introduced into the MOCVD reaction chamber to grow an AlN layer with a thickness of 50 nm on the substrate at a temperature of 1120 °C and a pressure of 70 Torr. Then, the introduction of TMAl is stopped, and NH3 is continuously introduced while the temperature is raised to 1200 °C for high-temperature treatment. After growing the AlN layer, trimethylgallium (TMGa) and NH3 are introduced into the MOCVD reaction chamber to grow a GaN layer with a thickness of 3000 nm at a temperature of 900 °C and a pressure of 70 Torr, as Figure 3 .

[0089] 3) Growth of the channel layer. In this embodiment, after growing the buffer layer, TMGa and NH3 are introduced into the MOCVD reaction chamber to grow a GaN layer with a thickness of 300 nm as the channel layer at a temperature of 900 °C and a pressure of 70 Torr, as Figure 4 .

[0090] 4) Growth of the barrier layer. In this embodiment, after growing the channel layer, TMAl is gradually introduced into the MOCVD reaction chamber while reducing TMGa, and AlGaN with an Al composition of 0.20 and a thickness of 15 nm is grown as the barrier layer at a temperature of 960 °C and a pressure of 70 Torr, as Figure 5 .

[0091] 5) Growth of the p-GaN layer. In this embodiment, after growing the barrier layer, a p-GaN layer is epitaxially grown. TMGa, bis(cyclopentadienyl)magnesium (Cp2Mg), NH3, and H2 are introduced into the MOCVD reaction chamber to grow a p-GaN layer with a doping concentration of 1×10 19 cm -3 and a thickness of 100 nm, and annealing is performed at a temperature of 700 °C, as Figure 6 .

[0092] 6) First etching of the p-GaN layer. In this embodiment, after growing the p-GaN layer, ICP etching is performed to remove 80 nm thick p-GaN in the area other than the gate region of the p-GaN layer. The ICP power is set to 100 W, the pressure is 5 mTorr, and Cl2, O2, and Ar are introduced, as Figure 7 .

[0093] 7) Second etching of the p-GaN layer. In this embodiment, after the first etching of the p-GaN layer, a second ICP etching is performed to remove 20 nm thick p-GaN layer in the area other than the non-gate region and the gate region of the p-GaN layer. The ICP power is set to 100 W, the pressure is 5 mTorr, and Cl2, O2, and Ar are introduced, as Figure 8 .

[0094] 8) Etch and deposit the drain and the first source. Use ICP etching to remove the barrier layer in the area under the first source and the drain. Set the ICP power to 100 W, the pressure to 5 mTorr, and introduce Cl2, O2, and Ar. Use E-beam evaporation to deposit 20 nm of Ti, 150 nm of Al, 50 nm of Ni, and 80 nm of Au in sequence. Selectively remove the metal outside the first source and drain areas by lift-off, and anneal at 830 °C, as Figure 9 .

[0095] 9) Grow the first passivation layer. Use PECVD to deposit 80 nm of SiO2 as the first passivation layer by introducing N2O and 5% SiH4 / N2 at a temperature of 300 °C and a pressure of 850 mTorr, as Figure 10 .

[0096] 10) Etch the first passivation layer. Use RIE etching to remove the first passivation layer in the gate area, extraction electrode area, first source area, drain area, and second source area. Set the RIE power to 200 W, the pressure to 3 - 10 mTorr, and introduce CHF3 and Ar, as Figure 11 .

[0097] 11) Deposit the gate. Use E-beam evaporation to deposit 20 nm of Ni and 80 nm of Au in sequence. Selectively remove the metal outside the gate area by lift-off, and anneal at 300 °C, as Figure 12 .

[0098] 12) Grow the second passivation layer. Use PECVD to deposit 500 nm of SiO2 as the second passivation layer by introducing N2O and 5% SiH4 / N2 at a temperature of 300 °C and a pressure of 850 mTorr, as Figure 13 .

[0099] 13) Etch the second passivation layer. Use RIE etching to remove the second passivation layer in the extraction electrode area, first source area, drain area, and second source area. Set the RIE power to 200 W, the pressure to 3 - 10 mTorr, and introduce CHF3 and Ar, as Figure 14 .

[0100] 14) Etch the barrier layer, channel layer, and part of the buffer layer in the second source area. Use ICP etching to remove the barrier layer, channel layer, and part of the buffer layer in the second source area. Set the ICP power to 100 W, the pressure to 5 mTorr, and introduce Cl2, O2, and Ar. In this embodiment, etch to 50 nm below the upper surface of the buffer layer, as Figure 15 .

[0101] 15) Etch the barrier layer, channel layer, and part of the buffer layer in the extraction electrode region. Use ICP etching to remove the barrier layer, channel layer, and part of the buffer layer in the extraction electrode region. Set the ICP power to 100 W, the pressure to 5 mTorr, and introduce Cl2, O2, and Ar. In this embodiment, etch to 50 nm below the upper surface of the buffer layer, as Figure 16 .

[0102] 16) Deposit the extraction electrode, the second source electrode, and the metal interconnection layer. Use E-beam evaporation deposition to sequentially deposit 20 nm of Ni and 200 nm of Au. Selectively remove the metal in the regions other than above the extraction electrode, the second source electrode, the metal interconnection layer, the first source electrode, and the drain through lift-off, as Figure 17 .

[0103] Example 2

[0104] As Figures 18(a)-18(c) , in this embodiment, a hole storage layer 14 is introduced between the buffer layer 2 and the channel layer 3 during the epitaxial layer growth process. The hole storage layer 14 can be AlGaN with an Al component of 0.20 and a thickness of 10 nm. The remaining structures and preparation processes are the same as those in Example 1.

[0105] Example 3

[0106] As Figures 19(a)-19(c) , in this embodiment, the number of steps in the non-gate region 8-2 of the p-GaN layer is 2. The bottom of the extraction electrode 10 is located inside the buffer layer 2. The remaining structures and preparation processes are the same as those in Example 1.

[0107] Example 4

[0108] As Figures 20(a)-20(c) , in this embodiment, the bottom of the second source electrode 11 is located inside the channel layer 3, and the bottom of the extraction electrode 10 is located inside the buffer layer 2. The remaining structures and preparation processes are the same as those in Example 1.

[0109] Example 5

[0110] As Figures 21(a)-21(c) , in this embodiment, the non-gate region 8-2 of the p-GaN layer is an inclined plane. In the present invention, 2° ≤ the angle between the inclined plane and the upper surface of the barrier layer < 90°. When the angle between the inclined plane and the upper surface of the barrier layer is 90°, the inclined plane becomes a stepped structure. In this embodiment, the angle between the inclined plane and the upper surface of the barrier layer is 4°. The remaining structures and preparation processes are the same as those in Example 1. The stepped region in the shape of an inclined plane can more effectively alleviate the electric field aggregation phenomenon near the drain side under the gate.

[0111] Figure 22The distances from the edge of the gate near the drain side to the drain are 10 μm. There is no stepped structure, and there is a stepped structure with a single step. The lengths of the steps in the x direction are 1 μm, 2 μm, and 3 μm respectively, and the height is 20 nm. In the blocking state (V DS = 400 V), the electric field intensity distribution diagrams at different positions on the upper surface of the channel layer are shown. It can be found that the setting of the stepped structure can effectively relieve the electric field concentration, reduce the peak value of the electric field intensity, and improve the radiation resistance of the device.

[0112] The above embodiments are only some possible structures of the present invention. In actual applications, parameters such as the material selection, thickness, and doping concentration design of each layer, as well as the specific HEMT structure design (such as whether there are other semiconductor layers between the buffer layer, channel layer, and barrier layer, whether there are other semiconductor layers between the substrate and the buffer layer, other gate types, SOI structure devices, gradually changing semiconductor layer components, drain similar designs), the number of steps in the non-gate area of the specific stepped p-GaN layer, the shape and size of each step, the position of the extraction electrode relative to the step, the size ratio of the extraction electrode relative to the p-GaN layer in the y direction, the depth of the etching hole specifically forming the extraction electrode, the shape and size of the etching hole specifically forming the extraction electrode, the shape and size of the specific gate electrode, the distance between the specific extraction electrode and the gate electrode, the depth of the specific second source, the shape and size of the specific second source, the shape and size of other key structures, the type of metal-semiconductor contact, and the position, depth, and shape of the metal-semiconductor contact formation can be appropriately changed according to different application conditions. In addition, the buffer layer, channel layer, and barrier layer mean that there should be at least one layer structure in this layer, rather than only one layer structure. Without departing from the principle of the present invention, these changes should also be regarded as the protection scope of the present invention.

[0113] The above is only the preferred embodiment of the present invention, and it does not limit the present invention in any formal or substantial way. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the method of the present invention, several improvements and supplements can still be made, and these improvements and supplements should also be regarded as the protection scope of the present invention. All those who are familiar with this professional technology, without departing from the spirit and scope of the present invention, when making some minor changes, modifications, and equivalent changes in the evolution using the technical content disclosed above, are all equivalent embodiments of the present invention; at the same time, all those who make any equivalent changes, modifications, and evolutions to the above embodiments based on the essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A GaN HEMT resistant to single particle irradiation, characterized in that: The single particle irradiation resistant GaN HEMT comprises, from bottom to top, a substrate, a buffer layer, a channel layer, a barrier layer, a p-GaN layer and a first passivation layer, wherein a first source and a drain are respectively arranged on both sides of the channel layer, the p-GaN layer is located between the first source and the drain and close to the first source, the p-GaN layer comprises a p-GaN layer gate region close to the first source and a p-GaN layer non-gate region close to the drain, and the p-GaN layer non-gate region comprises a stepped structure or an inclined structure with a height decreasing from the first source to the drain. The invention discloses a surface structure, wherein a gate is arranged on the gate region of the p-GaN layer; etching holes arranged at intervals along the y direction are arranged on the non-gate region of the p-GaN layer, and extraction electrodes are arranged in the etching holes, and the extraction electrodes are in contact with the side walls and the bottom of the etching holes along the etching holes; a second source electrode is arranged near the first source electrode, and the first source electrode is connected to the extraction electrode and the second source electrode through a metal interconnection layer; except for the top surfaces of the extraction electrode, the first source electrode, the second source electrode and the drain electrode, the rest of the surface area is filled with a second passivation layer.

2. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The number of steps in the non-gate region of the p-GaN layer is one or more, the spacing from the lowest step to the drain is greater than 0, and the height of the highest step is less than the height of the gate region of the p-GaN layer.

3. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The bottom of the etching hole is located on the upper surface or inside of the buffer layer; or the bottom of the etching hole is located on the upper surface or inside of the channel layer; the shape of the etching cross section of the etching hole in the xy plane is circular, elliptical, polygonal or other irregular edge shapes, and the shapes and sizes of the etching cross sections of adjacent etching holes in the xy plane are the same or different.

4. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: Adjacent etched holes have the same depth.

5. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: Adjacent etched holes have different depths.

6. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The extraction electrode forms a Schottky contact or an Ohmic contact with the semiconductor layer at the sidewall and bottom of the etched hole.

7. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The second source electrode extends into the buffer layer through the barrier layer and the channel layer; or the second source electrode extends into the channel layer through the barrier layer; or the second source electrode contacts the upper surface of the buffer layer through the barrier layer and the channel layer; or the second source electrode contacts the upper surface of the channel layer through the barrier layer.

8. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The gate is one of a Schottky-type p-GaN gate, an ohmic-type p-GaN gate, a recessed gate structure, and a MIS gate, or a combination of the two.

9. The single particle irradiation resistant GaN HEMT according to claim 1, characterized in that: The doping concentration of the p-GaN layer is 1×10 17 cm -3 Up to 1×10 21 cm -3 , wherein the height of the gate region of the p-GaN layer is 50nm to 150nm, and the size along the x-direction is 0.5μm to 5μm; the height of each step in the non-gate region of the p-GaN layer is 5nm to 120nm, and the size of each step along the x-direction is 0.5μm to 5μm.

10. A GaN HEMT resistant to single particle irradiation according to any one of claims 1 to 9, characterized in that the non-gate region of the p-GaN layer is a slope structure, and the angle between the slope and the upper surface of the barrier layer is ≥2°.

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