Electronic panel and electronic device

Abstract

The invention provides an electronic panel. The electronic panel comprises a substrate, a first semiconductor element and a first color conversion element, the substrate is provided with a functional area, and light can pass through the functional area. The first semiconductor element is disposed on the functional region, wherein the first semiconductor element includes a first electrode, a first semiconductor layer disposed on the first electrode, and a second electrode disposed on the first semiconductor layer. The first color conversion element is disposed on the first semiconductor element and overlaps the first semiconductor layer. In a plan view direction of the electronic panel, a center of the first color conversion element is offset from a center of the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to an electronic panel and an electronic device comprising the electronic panel, and in particular to an electronic panel with a pattern design of a light-transmitting layer and an electronic device comprising the electronic panel. Background Art

[0002] Photosensitive elements (such as cameras) can be applied to display panels to provide light sensing functions. However, the light shielding pattern in the display panel can produce diffraction, thereby affecting the performance of the photosensitive element. Therefore, how to reduce the impact of the diffraction phenomenon on the photosensitive element is one of the important issues in the field. Summary of the invention

[0003] The object of the present invention is to provide an electronic panel and an electronic device.

[0004] In some embodiments, the present invention provides an electronic panel, comprising a substrate, a first semiconductor element, and a first color conversion element. The substrate has a functional area, wherein light can pass through the functional area. The first semiconductor element is disposed on the functional area, wherein the first semiconductor element comprises a first electrode, a first semiconductor layer disposed on the first electrode, and a second electrode disposed on the first semiconductor layer. The first color conversion element is disposed on the first semiconductor element and overlaps the first semiconductor layer. In a top view direction of the electronic panel, a center of the first color conversion element is offset from a center of the first semiconductor layer.

[0005] In some embodiments, the present invention further provides an electronic device, comprising the above-mentioned electronic panel and a sensing module disposed under the functional area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic top view of an electronic panel according to a first embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a cross-sectional schematic diagram of an electronic panel according to a first embodiment of the present invention.

[0008] Figure 3 FIG. 4 is a schematic cross-sectional view of a functional area of ​​an electronic panel according to a second embodiment of the present invention.

[0009] Figure 4 FIG. 1 is a schematic top view of a functional area of ​​an electronic panel according to a second embodiment of the present invention.

[0010] Figure 5 FIG. 4 is a schematic top view of a functional area of ​​an electronic panel according to a third embodiment of the present invention.

[0011] Figure 6 FIG. 4 is a schematic top view of a functional area of ​​an electronic panel according to a fourth embodiment of the present invention.

[0012] Figure 7 FIG. 5 is a schematic cross-sectional view of a functional area of ​​an electronic panel according to a fifth embodiment of the present invention.

[0013] Figure 8 FIG. 4 is a cross-sectional schematic diagram of a functional area of ​​an electronic panel according to a sixth embodiment of the present invention.

[0014] Fig. 9 FIG. 4 is a cross-sectional schematic diagram of a functional area of ​​an electronic panel according to a seventh embodiment of the present invention.

[0015] Fig.10 FIG. 4 is a cross-sectional schematic diagram of a functional area of ​​an electronic panel according to an eighth embodiment of the present invention.

[0016] Fig.11 FIG. 4 is a schematic cross-sectional view of a functional area of ​​an electronic panel according to a ninth embodiment of the present invention.

[0017] Fig.12 FIG. 1 is a schematic cross-sectional view of a functional area of ​​an electronic panel according to a tenth embodiment of the present invention.

[0018] Fig.13 FIG. 1 is a cross-sectional schematic diagram of a functional area of ​​an electronic panel according to an eleventh embodiment of the present invention.

[0019] Fig.14 FIG. 1 is a cross-sectional schematic diagram of a functional area of ​​an electronic panel according to a twelfth embodiment of the present invention.

[0020] Fig.15 FIG. 4 is a cross-sectional diagram of an electronic device according to an embodiment of the present invention.

[0021] Explanation of reference numerals: BF-buffer layer; BM-black matrix layer; BP-bonding pad; CE-color conversion element; CE1-first color conversion element; CE2-second color conversion element; CI, CS, CC, CA-center; CL-circuit layer; CR-channel region; CW, CW1, CW2-connection wiring; D1, D2, D3-distance; DE-driving element; DR-display region; DRE-drain electrode; DRR-drain region; E1-first electrode; E2-second electrode; ED-electronic device; EP-electronic panel; FR-functional region domain; GE-gate electrode; H1, H2-height; IL1, IL2, IL3, I1, I2, I3, I4, PAV-insulating layer; INP, INP1, INP2, INP3, INP4-insulating pattern; L1, T1, R1, B1-first distance; L2, T2, R2, B2-second distance; L3, T3-third distance; L4, T4-fourth distance; L5-fifth distance; L6-sixth distance; LS, LS1, LS2, LS3-light shielding pattern layer; M1, M2, M3-conductive layer; OP, OP1, O P2, OP3, OP4-opening; P1, PP1-first point; P2, PP2-second point; P3-third point; P4-fourth point; P5-fifth point; P6-sixth point; P7-seventh point; P8-eighth point; PO1, PT1, PT2-part; PR-peripheral area; RS-groove; S1, S2, S3, S5-top surface; S4-bottom surface; SB-substrate; SE-semiconductor element; SE1-first semiconductor element; SE2-second semiconductor element; SE3-third semiconductor element; SE4-fourth semiconductor element; S EN-sensing module; SL1-first semiconductor layer; SL2-second semiconductor layer; SL3-third semiconductor layer; SL4-fourth semiconductor layer; SM, SL-semiconductor layers; SOE-source electrode; SOR-source region; SW-sidewall; TL-touch layer; V1, V2, V3, V4-perforation; VD1-vertical distance; VL, VL1, VL2-virtual straight line; W2, W1, W3, W4, W5, W6, X1, X2, X3, X4-width; Z, X, Y-direction; A-A', B-B'-tangent; θ1-angle. DETAILED DESCRIPTION

[0022] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the reader's understanding and for the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the device, and the specific elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the figure are only for illustration and are not intended to limit the scope of the present invention.

[0023] Certain words are used throughout the specification and the appended claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components with different names. This document does not intend to distinguish between components with the same function but different names.

[0024] In the present specification and claims, the words “including” and “comprising” are open-ended words, and thus should be interpreted as meaning “including but not limited to…”.

[0025] It should be understood that when an element or a film layer is referred to as being "disposed on" or "connected to" another element or film layer, it may be directly on or directly connected to this other element or film layer, or there may be an intervening element or film layer between the two (indirect case). Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or film layer, there may be no intervening element or film layer between the two. When an element or a film layer is referred to as being "electrically connected" to another element or film layer, it may be interpreted as a direct electrical connection or an indirect electrical connection. The electrical connection or coupling described in the present invention may refer to a direct connection or an indirect connection. In the case of a direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of an indirect connection, there is a switch, a diode, a capacitor, an inductor, a resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but is not limited thereto.

[0026] Although the terms "first", "second", "third" ... can be used to describe a variety of components, the components are not limited to these terms. These terms are only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third ... according to the order of the components declared in the claims. Therefore, in the following description, the first component may be the second component in the claims.

[0027] In the present invention, the thickness, length and width may be measured by an optical microscope, and the thickness or width may be measured by a cross-sectional image in an electron microscope, but the present invention is not limited thereto.

[0028] In addition, any two values ​​or directions used for comparison may have a certain error. The terms "approximately", "equal to", "equal to" or "same", "substantially" or "substantially" are generally interpreted as being within a range of plus or minus 20% of the given value, or within a range of plus or minus 10%, plus or minus 5%, plus or minus 3%, plus or minus 2%, plus or minus 1% or plus or minus 0.5% of the given value.

[0029] In addition, the phrases “a given range is from a first value to a second value” and “a given range falls within the range from a first value to a second value” mean that the given range includes the first value, the second value and other values ​​therebetween.

[0030] If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present invention belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0032] It should be noted that the following embodiments may be implemented by replacing, reorganizing, or mixing the technical features in several different embodiments without departing from the spirit of the present invention to complete other embodiments.

[0033] The electronic device of the present invention may include a display device, a sensing device, a backlight device, an antenna device, a splicing device or other suitable electronic devices, but is not limited thereto. The electronic device may be a bendable, flexible or stretchable electronic device. The display device may be applied to, for example, a laptop computer, a public display, a splicing display, a car display, a touch display, a television, a monitor, a smart phone, a tablet computer, a light source module, a lighting device or, for example, an electronic device applied to the above products, but is not limited thereto. The sensing device may include a biosensor, a touch sensor, a fingerprint sensor, a light sensor, other suitable sensors or a combination of the above types of sensors. The antenna device may include a liquid crystal antenna device or other suitable antenna devices. The splicing device may include, for example, a display splicing device or an antenna splicing device, but is not limited thereto. The appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges or other suitable shapes. The electronic device may include an electronic unit, wherein the electronic unit may include a semiconductor unit, and the semiconductor unit includes passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, sensors, integrated circuits, etc. The diode may include a light emitting diode or a photodiode or a varactor diode. The light emitting diode may include, for example, an organic light emitting diode (OLED) or an inorganic light emitting diode, and the inorganic light emitting diode may include, for example, a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED, but is not limited thereto. The semiconductor unit may include, but is not limited thereto, a semiconductor layer or an electronic unit manufactured by a semiconductor process. It should be noted that the electronic device of the present invention may be various combinations of the above devices, but is not limited thereto.

[0034] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic top view of an electronic panel according to a first embodiment of the present invention, Figure 2 FIG. 1 is a cross-sectional schematic diagram of an electronic panel according to a first embodiment of the present invention. Specifically, Figure 2 Shows Figure 1 The structure shown is a cross-sectional view along the tangent line A-A'. In order to simplify the drawings, Figure 1 Only some of the film layers and components of the electronic panel EP are shown, and the structure of the electronic panel EP can be referred to Figure 2 According to the present invention, the electronic device ED may include an electronic panel EP and other components applicable to the electronic panel EP. Figure 2As shown, the electronic panel EP includes a substrate SB, a circuit layer CL disposed on the substrate SB, a semiconductor element SE disposed on the circuit layer CL, and a color conversion element CE disposed on the semiconductor element SE, but not limited thereto. In the present embodiment, the electronic panel EP may include, for example, a display panel, but not limited thereto. In this case, the semiconductor element SE may include any element that can exhibit semiconductor characteristics, such as a transistor, a photodiode, a light emitting diode, but not limited thereto. In addition, the color or wavelength of the light emitted by the semiconductor element SE can be filtered or converted into light of various colors by the color conversion element CE. The structures of the various elements and film layers of the electronic panel EP will be described in detail below.

[0035] The substrate SB may include a rigid substrate or a flexible substrate. The rigid substrate may include, for example, glass, quartz, sapphire, ceramic, other suitable materials, or a combination of the above materials. The flexible substrate may include, for example, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), other suitable materials, or a combination of the above materials.

[0036] like Figure 1 As shown, the substrate SB may include a display area DR, a functional area FR and a peripheral area PR. The display area DR may be an area in the electronic panel EP that is mainly used to display images. The light-emitting element (i.e., semiconductor element SE) in the electronic panel EP may be arranged corresponding to the display area DR. The above-mentioned "semiconductor element SE corresponds to the display area DR" may refer to the semiconductor element SE overlapping the display area DR or at least partially overlapping the display area DR in the top view direction of the electronic panel EP (i.e., parallel to the direction Z, which will not be repeated below). Specifically, the semiconductor element SE may be arranged on the display area DR of the substrate SB. The functional area FR may be defined as an area in the substrate SB that corresponds to the photosensitive element. Specifically, the electronic panel EP may be integrated with the photosensitive element in the electronic device ED, and the photosensitive element may be arranged corresponding to the functional area FR of the substrate SB. The range of the functional area FR may be defined, for example, by the outer edge of the photosensitive element, but is not limited thereto. The photosensitive element may be arranged below the functional area FR of the substrate SB, or the photosensitive element may be arranged on the side of the functional area FR of the substrate SB opposite to the semiconductor element SE, but is not limited thereto. Light may pass through the functional area FR and be received by the photosensitive element. As Figure 1 and Figure 2As shown, one or more semiconductor elements SE may also be arranged corresponding to the functional area FR, that is, some semiconductor elements SE may be arranged on the functional area FR of the substrate SB. The semiconductor elements SE corresponding to the functional area FR may emit light to provide a display function. Specifically, the semiconductor elements SE corresponding to the functional area FR may be auxiliary light-emitting elements, and the semiconductor elements SE corresponding to the display area DR may be main light-emitting elements. In this case, the semiconductor elements SE corresponding to the functional area FR may form auxiliary pixels, and the semiconductor elements SE corresponding to the display area DR may form main pixels, but this is not limited to this. In some embodiments, as Figure 1 As shown, the element density of the semiconductor element SE corresponding to the functional area FR can be less than the element density of the semiconductor element SE corresponding to the display area DR, so as to improve the light transmittance of the functional area FR. The peripheral area PR can be other areas of the substrate SB except the display area DR and the functional area FR, which are used to set the peripheral elements of the electronic panel EP.

[0037] The circuit layer CL may include various wires, circuits, and electronic units (such as active components and / or passive components) that can be applied to the electronic panel EP, but is not limited thereto. For example, the circuit layer CL may include a driving element DE, wherein the driving element DE may be electrically connected to the semiconductor element SE to drive the semiconductor element SE. The driving element DE may, for example, include a thin film transistor (TFT), but is not limited thereto. Specifically, the circuit layer CL may include a semiconductor layer SM, a conductive layer M1, and a conductive layer M2, but is not limited thereto. The driving element DE may include a semiconductor layer SM, a gate electrode GE, a source electrode SOE, and a drain electrode DRE. The semiconductor layer SM may include a channel region CR, a source region SOR, and a drain region DRR. The conductive layer M1 may form a gate electrode GE of the driving element DE. In the top view direction of the electronic panel EP, the gate electrode GE may overlap the channel region CR of the semiconductor layer SM. The conductive layer M2 may form a source electrode SOE and a drain electrode DRE. The semiconductor layer SM may include a semiconductor material. The semiconductor material includes, for example, silicon or metal oxide, such as low temperature polysilicon (LTPS) semiconductor or amorphous silicon (a-Si) semiconductor, organic semiconductor, metal oxide semiconductor, and the metal oxide semiconductor may be, for example, indium gallium zinc oxide (IGZO) semiconductor or indium gallium oxide (IGO) semiconductor, but not limited thereto. The circuit layer CL may include a plurality of driving elements DE, and these driving elements DE may use different semiconductor materials, for example, one of the driving elements DE may include a low temperature polysilicon semiconductor, and another driving element DE may include a metal oxide semiconductor. The conductive layer M1 and the conductive layer M2 may include any suitable conductive material, such as a metal material, but not limited thereto. The circuit layer CL may also include an insulating layer IL1 located between the conductive layer M1 and the semiconductor layer SM, an insulating layer IL2 disposed on the conductive layer M1, and an insulating layer IL3 disposed on the conductive layer M2. The insulating layer IL1, the insulating layer IL2, and the insulating layer IL3 may include any suitable insulating material, such as an organic insulating material or an inorganic insulating material. The insulating layer IL1 may be, for example, a gate insulating layer of the driving element DE. In this embodiment, the electronic panel EP may further selectively include a buffer layer BF disposed between the substrate SB and the circuit layer CL, but is not limited thereto. The buffer layer BF may include any suitable insulating material. It should be noted that Figure 2 The structure of the circuit layer CL shown is merely exemplary, and the present embodiment is not limited thereto.

[0038] According to the present embodiment, the circuit layer CL may include two parts corresponding to the display region DR and the peripheral region PR, respectively. That is, the circuit layer CL may not be disposed corresponding to the functional region FR. Specifically, Figure 2 As shown, a portion of the circuit layer CL corresponding to the functional area FR (including a conductive layer, an insulating layer, etc.) can be removed to form an opening OP. The electronic panel EP of this embodiment may also include an insulating layer I1 disposed on the circuit layer CL, wherein the portion of the insulating layer I1 corresponding to the functional area FR can be filled in the opening OP. In this case, the semiconductor element SE corresponding to the display area DR can be electrically connected to the driving element DE in the circuit layer CL corresponding to the display area DR, and the semiconductor element SE corresponding to the functional area FR can be electrically connected to the driving element DE in the circuit layer CL corresponding to the peripheral area PR, but is not limited thereto. Specifically, the electronic panel EP may also include an insulating layer I2 disposed between the insulating layer I1 and the semiconductor element SE and a conductive layer M3 disposed between the insulating layer I1 and the insulating layer I2, wherein the conductive layer M3 may be disposed corresponding to the display area DR and the peripheral area PR. The insulating layer I1 and the insulating layer I2 may include any suitable insulating material, such as an organic insulating material, but is not limited thereto. The conductive layer M3 corresponding to the display region DR can be electrically connected to the driving element DE corresponding to the display region DR through the through hole V1 passing through the insulating layer I1 and the insulating layer IL3, and the semiconductor element SE corresponding to the display region DR (for example, the first electrode E1 of the semiconductor element SE) can be electrically connected to the conductive layer M3 corresponding to the display region DR through the through hole V2 passing through the insulating layer I2. In this way, the semiconductor element SE corresponding to the display region DR can be electrically connected to the driving element DE corresponding to the display region DR. In addition, the electronic panel EP may include a connecting wire CW arranged between the insulating layer I1 and the insulating layer I2, wherein the connecting wire CW may extend on the functional region FR and the peripheral region PR of the substrate SB. The connecting wire CW can be electrically connected to the conductive layer M3 corresponding to the peripheral region PR, and then electrically connected to the driving element DE corresponding to the peripheral region PR through the through hole V3 passing through the insulating layer I1 and the insulating layer IL3. The semiconductor element SE corresponding to the functional region FR (for example, the first electrode E1 of the semiconductor element SE) can be electrically connected to the connecting wire CW through the through hole V4 passing through the insulating layer I2. In this way, the semiconductor element SE corresponding to the functional region FR can be electrically connected to the driving element DE corresponding to the peripheral region PR. Figure 1As shown, in the top view of the electronic panel EP, the semiconductor elements SE corresponding to the display area DR can be electrically connected to a driving element DE corresponding to the display area DR, and the semiconductor elements SE corresponding to the functional area FR can be electrically connected to a driving element DE corresponding to the peripheral area PR through a connecting line CW extending from the functional area FR to the peripheral area PR, but not limited to this. By making the circuit layer CL (or the driving element DE) not corresponding to the functional area FR, the transmittance of the functional area FR can be improved. It should be noted that the above-mentioned electrical connection method between the semiconductor element SE and the driving element DE is only exemplary, and the present invention is not limited to this.

[0039] As described above, the semiconductor element SE of the present embodiment may include a light emitting element. The light emitting element includes, for example, a light emitting diode. The light emitting diode may include an inorganic light emitting diode or an organic light emitting diode (OLED). The inorganic light emitting diode may include a micro light emitting diode (micro LED), a sub-millimeter light emitting diode (mini LED) or a quantum dot light emitting diode (quantum dot LED, QLED), but is not limited thereto. For example, the semiconductor element SE of the present embodiment may include an organic light emitting diode element, which includes a first electrode E1, a semiconductor layer SL disposed on the first electrode E1, and a second electrode E2 disposed on the semiconductor layer SL. In other words, the semiconductor layer SL is disposed between the first electrode E1 and the second electrode E2. The semiconductor layer SL may include a light emitting layer. One of the first electrode E1 and the second electrode E2 may include a cathode, and the other may include an anode. The first electrode E1 and / or the second electrode E2 may include any suitable transparent conductive material, such as indium tin oxide (ITO), but is not limited thereto. The electronic panel EP may also include an insulating layer I3 disposed on the insulating layer I2. The insulating layer I3 may be disposed on the first electrode E1 and have an opening OP1. The opening OP1 may define the location of the semiconductor layer SL (or light emitting layer) of the semiconductor element SE. Specifically, the semiconductor layer SL may be disposed in the opening OP1 and electrically connected to the first electrode E1 through the opening OP1. The second electrode E2 may be a continuous film layer conformally disposed along the surface of the insulating layer I3 and the surface of the semiconductor layer SL, but is not limited thereto. The insulating layer I3 may serve as a pixel defining layer (PDL).

[0040] The electronic panel EP may further include an insulating layer I4, wherein the insulating layer I4 may be disposed between the semiconductor element SE and the color conversion element CE. The insulating layer I4 may serve as an encapsulation layer for encapsulating the semiconductor element SE and the elements and film layers thereunder. The insulating layer I4 may include a multilayer structure, for example, a structure formed by sequentially stacking an inorganic layer, an organic layer, and an inorganic layer, but is not limited thereto.

[0041] The color conversion element CE may be arranged corresponding to the semiconductor element SE to convert the wavelength or color of the light emitted by the corresponding semiconductor element SE. For example, one semiconductor element SE may correspond to one color conversion element CE, but is not limited thereto. The color conversion element CE may include a color filter, a quantum dot, a phosphorescent material, a fluorescent material, other suitable light conversion materials, or a combination of the above materials. For example, the color conversion element CE of the present embodiment may include a color filter element, but is not limited thereto. The electronic panel EP may also include a black matrix layer BM, wherein the black matrix layer BM may be arranged around the color conversion element CE corresponding to the display area DR. In other words, the black matrix layer BM may be arranged corresponding to the display area DR. Specifically, the black matrix layer BM may be arranged on the display area DR, and a plurality of openings OP2 may be defined, and the color conversion element CE corresponding to the display area DR may be arranged in the opening OP2. On the other hand, the black matrix layer BM may not be arranged corresponding to the functional area FR, that is, the black matrix layer BM is not arranged on the functional area FR of the substrate SB, and the color conversion element CE corresponding to the functional area FR may not be arranged in the opening OP2 of the black matrix layer BM. The above design can improve the light transmittance of the functional area FR. In this case, the color conversion element CE corresponding to the functional area FR can protrude from the semiconductor layer SL of the semiconductor element SE to which it corresponds. Figure 2 As shown, in the cross-sectional view of the electronic panel EP, one side of the color conversion element CE may protrude from one side of the semiconductor layer SL of the semiconductor element SE corresponding to the color conversion element CE by a distance D1. According to the present embodiment, the distance D1 may range from 0.01 micrometers to 21.285 micrometers. Therefore, the width W2 of the color conversion element CE in one direction may be greater than the width W1 of the semiconductor layer SL of the semiconductor element SE corresponding to it in the same direction, and the difference between the two may range from 0.02 micrometers (micrometer, μm) to 42.57 μm (i.e., 0.02 μm≤W2-W1≤42.57 μm), but is not limited thereto. Through the above-mentioned size design, the probability of large-angle light emitted from the semiconductor element SE not passing through the color conversion element CE can be reduced, thereby improving the display quality of the electronic panel EP.

[0042] The electronic panel EP of this embodiment may further include a touch layer TL, wherein the touch layer TL may be disposed between the insulating layer I4 and the color conversion element CE, but is not limited thereto. In some embodiments, the electronic panel EP may not include the touch layer TL. The touch layer TL may provide a touch function of the electronic panel EP, that is, the electronic panel EP may include a touch display panel. The touch layer TL may include one or more conductive layers and / or insulating layers, Figure 2 Only one film layer (such as a conductive layer) is used for representation, but the film layer combination is not represented by Figure 2 Limits shown.

[0043] According to the present embodiment, the electronic panel EP may include an insulating pattern INP disposed between a functional region FR of the substrate SB and a semiconductor element SE corresponding to the functional region FR. The insulating pattern INP may include any suitable inorganic insulating material or organic insulating material. The insulating pattern INP may, for example, include a patterned island pattern, but is not limited thereto. The insulating pattern INP may correspond to the semiconductor element SE disposed on the functional region FR. The insulating pattern INP has a center CI, and the semiconductor layer SL of the semiconductor element SE has a center CS, wherein the center CI of the insulating pattern INP is offset from the center CS of the semiconductor layer SL of the semiconductor element SE to which it corresponds. In other words, the center CI of the insulating pattern INP does not overlap with the center CS of the semiconductor layer SL of the semiconductor element SE to which it corresponds in the top view direction of the electronic panel EP. In addition, in the cross-sectional view of the electronic panel EP, one side of the insulating pattern INP may protrude from one side of the color conversion element CE corresponding to the insulating pattern INP and have a distance D2, and the other side of the insulating pattern INP may protrude from the other side of the color conversion element CE and have a distance D3, wherein the distance D2 is different from the distance D3. In other words, the protruding distance of the insulating pattern INP on both sides of the color conversion element CE may be different. Through the setting and pattern design of the insulating pattern INP, the irregularity of the film layer corresponding to the functional area FR can be increased, thereby reducing the effect of the diffraction phenomenon of light in the functional area FR on the photosensitive element. In some embodiments, the insulating pattern INP may be set on any film layer between the functional area FR and the semiconductor element SE corresponding to the functional area FR. In some embodiments, the insulating pattern INP may be formed by a buffer layer BF. Specifically, the insulating pattern INP corresponding to the functional area FR can be formed by patterning the buffer layer BF. The refractive index of the insulating pattern INP may be different from the refractive index of the insulating layer I4 or the refractive index of the buffer layer BF, but is not limited to this. In addition, in the present embodiment, the color conversion element CE has a center CC, wherein the center CC of the color conversion element CE may overlap with the center CS of the semiconductor layer SL of the semiconductor element SE to which it corresponds in the top view direction of the electronic panel EP, but is not limited to this. In other words, the center CI of the insulating pattern INP may be offset from the center CC of the color conversion element CE to which it corresponds. The feature that the electronic panel EP includes the insulating pattern INP in this embodiment can be applied to various embodiments of the present invention. It should be noted that the "center" of the element or film layer mentioned above refers to the geometric center of the top view of the element or film layer, and the subsequent embodiments also use the same definition and will not be repeated.

[0044] In the present invention, the center of the film layer can be defined by the shape of the projection of the film layer on a plane (e.g., plane XY) perpendicular to the top-view direction of the electronic panel EP (i.e., a pattern in the top-view direction or on the top view). In some embodiments, when the projection shape of the film layer on the plane perpendicular to the top-view direction of the electronic panel EP is circular or elliptical, the center of the film layer may be the center of the projection shape. In some embodiments, when the projection shape of the film layer on the plane perpendicular to the top-view direction of the electronic panel EP is rectangular, the center of the film layer may be the intersection of the diagonals of the projection shape. In some embodiments, when the projection shape of the film layer on the plane perpendicular to the top-view direction of the electronic panel EP is polygonal or irregular, the center of the film layer may be the intersection of the diagonals of the smallest rectangle enclosing the projection shape. The method for defining the center of each film layer in the present invention can be referred to above and will not be repeated hereafter.

[0045] The electronic panel EP of this embodiment may also include other suitable components and / or film layers, and is not limited to Figure 1 and Figure 2 The structures shown are limited.

[0046] Please refer to Figure 3 and Figure 4 , Figure 3 is a cross-sectional schematic diagram of a functional area of ​​an electronic panel according to a second embodiment of the present invention, Figure 4 Schematic diagram of a top view of the functional area of ​​the electronic panel of the second embodiment of the present invention. Specifically, Figure 3 Shows Figure 4 The structure shown is a cross-sectional view along the tangent line BB'. In order to simplify the drawings, Figure 4 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 , so no further details will be given. In this embodiment, Figure 4 The four semiconductor elements SE shown disposed on the functional region FR may, for example, form a pixel (i.e., the auxiliary pixel mentioned above), but the present invention is not limited thereto. Specifically, the semiconductor elements SE corresponding to the functional region DR may respectively form an auxiliary sub-pixel with the color conversion element CE corresponding thereto, and the four auxiliary sub-pixels may form an auxiliary pixel. A pixel of the present embodiment may, for example, be formed by two green sub-pixels, one red sub-pixel, and one blue sub-pixel, and these sub-pixels may be mixed to produce white light, but the present invention is not limited thereto. In other words, Figure 4 For example, a top view of a pixel disposed on the functional region FR is shown, but the present invention is not limited thereto. Figure 4 The four semiconductor elements SE shown may be included in different sub-pixels. The composition of the main pixel corresponding to the display region DR can refer to the composition of the auxiliary pixel, so it will not be repeated.

[0047] like Figure 3 As shown, the electronic panel EP includes a first semiconductor element SE1 disposed on a functional region FR of a substrate SB and a first color conversion element CE1 disposed on the first semiconductor element SE1. The first semiconductor element SE1 includes a first electrode E1, a first semiconductor layer SL1 disposed on the first electrode E1, and a second electrode E2 disposed on the first semiconductor layer SL1. The color conversion element CE1 may overlap the first semiconductor layer SL1 of the first semiconductor element SE1 in a top view direction of the electronic panel EP to convert the wavelength or color of light emitted by the first semiconductor element SE1. According to this embodiment, as Figure 4 As shown, in the top view direction of the electronic panel EP, the first semiconductor layer SL1 of the first semiconductor element SE1 has a center CS, and the first color conversion element CE1 has a center CC, wherein the center CC of the first color conversion element CE1 is offset from the center CS of the first semiconductor layer SL1. In this embodiment, the first semiconductor layer SL1 can be extended to change the position of the center CS, so that the center CS can be offset from the center CC of the first color conversion element CE1. In the present invention, the above-mentioned "extension of the first semiconductor layer SL1" may include any pattern change of the first semiconductor layer SL1 that changes the center CS of the first semiconductor layer SL1. Specifically, compared to Figure 2 In the structure shown, the center CS of the semiconductor layer SL overlaps the center CC of the color conversion element CE. In this embodiment, the first semiconductor layer SL1 can extend in a direction, so that the center of the first semiconductor layer SL1 can move (for example, move in the direction) and offset from the center CC of the first color conversion element CE1. The following definition of the extension of the film layer can refer to the above, so it is not repeated here.

[0048] According to this embodiment, in the top view direction of the electronic panel EP, the first semiconductor layer SL1 may, for example, extend and protrude from the first color conversion element CE1, but the present invention is not limited thereto. Figure 4As shown, the first semiconductor layer SL1 may extend in the direction X so that the center CS may move in the direction X. In this case, the center CS of the first semiconductor layer SL1 may be offset from the center CC of the first color conversion element CE1 in the direction X, or the center CC of the first color conversion element CE1 may be offset from the center CS of the first semiconductor layer SL1 in the direction -X. In some embodiments, the first semiconductor layer SL1 may extend in two opposite directions (e.g., the direction X and the direction -X, but not limited thereto), but the extension degrees in the two directions are different, so as to change the position of the center CS. In this case, the size or shape of the first color conversion element CE1 may be the same as the size or shape of the first electrode E1, so as to reduce the possibility of affecting the display effect of the electronic panel EP due to the deformation of the first semiconductor layer SL1. It should be noted that the first semiconductor layer SL1 may extend in any direction to change the position of the center CS. In this embodiment, the center CC of the first color conversion element CE1 may be offset from the center CS of the first semiconductor layer SL1 by a first distance L1. The first distance L1 may be the distance between the center CC of the first color conversion element CE1 and the center CS of the first semiconductor layer SL1 in the top view direction of the electronic panel EP. According to the present embodiment, the first distance L1 may range from 0.1 μm to 10 μm (i.e., 0.1 μm≤L1≤10 μm). In some embodiments, the first distance L1 may range from 0.3 μm to 9 μm (i.e., 0.3 μm≤L1≤9 μm). In some embodiments, the first distance L1 may range from 0.5 μm to 8 μm (i.e., 0.5 μm≤L1≤8 μm). By extending the pattern of the first semiconductor layer SL1 in one direction so that the center CS of the first semiconductor SL1 is offset from the center CC of the first color conversion element CE1, the arrangement irregularity of the film layer or element (e.g., the first semiconductor layer SL1) corresponding to the functional region FR may be increased, thereby reducing the possibility of light diffraction in the functional region FR and affecting the photosensitive element. When the first distance L1 is less than 0.1 μm, the irregularity of the pattern of the first semiconductor layer SL1 may not be obvious enough to effectively reduce the diffraction phenomenon. When the first distance L1 is greater than 10 μm, the overlap between the first semiconductor layer SL1 and the first color conversion element CE1 may be too small, thereby affecting the display effect of the electronic panel EP. In addition, in the present embodiment, the first electrode E1 may have a center CA, wherein the center CC of the first color conversion element CE1 may overlap the center CA of the first electrode E1 in the top view direction of the electronic panel EP, but the present invention is not limited thereto.

[0049] like Figure 4As shown, in the top view direction of the electronic panel EP, the center CS of the first semiconductor layer SL1 and the center CC of the first color conversion element CE1 may define a virtual straight line VL. The virtual straight line VL may be a straight line passing through the center CS and the center CC. The extension direction of the virtual straight line VL may be substantially parallel to the extension direction of the first semiconductor layer SL1 (or the direction in which the center CS is offset from the center CC), that is, the direction X. According to this embodiment, the virtual straight line VL may intersect with the edge of the first semiconductor layer SL1 at the first point P1 and the second point P2, and the virtual straight line VL may intersect with the edge of the first color conversion element CE1 at the third point P3 and the fourth point P4, wherein the third point P3 is located between the first point P1 and the center CC of the first color conversion element CE1, and the second point P2 is located between the fourth point P4 and the center CC of the first color conversion element CE1. That is, the first point P1 may protrude from the first color conversion element CE1, and the second point P2 may not protrude from the first color conversion element CE1. In other words, one side of the first semiconductor layer SL1 (for example, the side corresponding to the first point P1) may extend so that its edge may protrude from the edge of the first color conversion element CE1; and the edge of the other side of the first semiconductor layer SL1 (for example, the side corresponding to the second point P2) may not protrude from the edge of the first color conversion element CE1. Figure 2 In this embodiment, as shown. Figure 3 and Figure 4 As shown, there may be a second distance L2 between the first point P1 and the third point P3, and there may be a third distance L3 between the second point P2 and the fourth point P4, wherein the second distance L2 may be different from the third distance L3. That is, the protruding distance (i.e., the second distance L2) of the first semiconductor layer SL1 protruding from the first color conversion element CE1 on one side of the first color conversion element CE1 may be different from the third distance L3 between the first semiconductor layer SL1 and the first color conversion element CE1 on the other side of the first color conversion element CE1 opposite to the side of the first color conversion element CE1. In the present embodiment, the second distance L2 and the third distance L3 may range from 0.1 μm to 20 μm (i.e., 0.1 μm ≤ L2, L3 ≤ 20 μm), but are not limited thereto. In some embodiments, the second distance L2 and the third distance L3 may range from 0.3 μm to 18 μm (i.e., 0.3 μm ≤ L2, L3 ≤ 18 μm). In some embodiments, the second distance L2 and the third distance L3 may range from 0.5 μm to 16 μm (ie, 0.5 μm≤L2, L3≤16 μm). By making the second distance L2 and the third distance L3 different, the arrangement irregularity of the film layer or element corresponding to the functional region FR can be increased.

[0050] As mentioned above, although Figure 3 As not shown, the electronic panel EP of this embodiment may include Figure 2The insulating pattern INP is shown, wherein the insulating pattern INP may be disposed between the functional region FR of the substrate SB and the first semiconductor element SE1 , and the center CI of the insulating pattern INP may be offset from the center CS of the first semiconductor layer SL1 .

[0051] like Figure 3 and Figure 4 As shown, the electronic panel EP may further include a second semiconductor element SE2 disposed on the functional region FR of the substrate SB and a second color conversion element CE2 disposed on the second semiconductor element SE2. The second semiconductor element SE2 may include a first electrode E1, a second semiconductor layer SL2 disposed on the first electrode E1, and a second electrode E2 disposed on the second semiconductor layer SL2. The second semiconductor element SE2 may be located in the same auxiliary pixel as the first semiconductor element SE1, but is not limited thereto. In the present embodiment, the second semiconductor layer SL2 may extend in a direction so that the center CS of the second semiconductor layer SL2 may be offset from the center CC of the second color conversion element CE2, wherein the extension direction of the second semiconductor layer SL2 may be different from the extension direction of the first semiconductor layer SL1. For example, as Figure 3 and Figure 4 As shown, the first semiconductor layer SL1 may extend in a direction X, and the second semiconductor layer SL2 may extend in a direction -X, but the present invention is not limited thereto. In some embodiments, the first semiconductor layer SL1 may extend in a direction, and the second semiconductor layer SL2 may extend in another direction different from the direction, wherein the direction and the other direction may be any direction, and are not limited to the direction X and the direction Y. Therefore, the center CC of the first color conversion element CE1 may be offset from the center CS of the first semiconductor layer SL1 in a first direction, and the center CC of the second color conversion element CE2 may be offset from the center CS of the second semiconductor layer SL2 in a second direction, wherein the first direction may be different from the second direction. The above-mentioned first direction may be a direction from the center CS of the first semiconductor layer SL1 to the center CC of the first color conversion element CE1, and the second direction may be a direction from the center CS of the second semiconductor layer SL2 to the center CC of the second color conversion element CE2. For example, the first direction may be a direction -X, and the second direction may be a direction X, but the present invention is not limited thereto.

[0052] In addition, in the present embodiment, the center CC of the first color conversion element CE1 may be offset from the center CS of the first semiconductor layer SL1 to have a first distance L1, and the center CC of the second color conversion element CE2 may be offset from the center CS of the second semiconductor layer SL2 to have a fourth distance L4, wherein the first distance L1 may be different from the fourth distance L4. The range of the fourth distance L4 may refer to the range of the first distance L1 described above. In other words, the extension degree of the first semiconductor layer SL1 may be different from the extension degree of the second semiconductor layer SL2. In this way, the protrusion distance of the second semiconductor layer SL2 protruding from the second color conversion element CE2 may be different from the protrusion distance (e.g., the second distance L2) of the first semiconductor layer SL1 protruding from the first color conversion element CE1. Specifically, a virtual straight line VL1 may be defined by the center CC of the second color conversion element CE2 and the center CS of the second semiconductor layer SL2. The virtual straight line VL1 may intersect with the edge of the second semiconductor layer SL2 at the fifth point P5 and the sixth point P6, and intersect with the edge of the second color conversion element CE2 at the seventh point P7 and the eighth point P8, wherein the seventh point P7 is located between the fifth point P5 and the center CC of the second color conversion element CE2, and the sixth point P6 is located between the eighth point P8 and the center CC of the second color conversion element CE2. A fifth distance L5 may be provided between the fifth point P5 and the seventh point P7, and the fifth distance L5 may be a protruding distance of the second semiconductor layer SL2 protruding from the second color conversion element CE2, wherein the second distance L2 may be different from the fifth distance L5, but is not limited thereto. Similar to the structure of the first semiconductor element SE1, a sixth distance L6 may be provided between the sixth point P6 and the eighth point P8, wherein the sixth distance L6 may be different from the fifth distance L5.

[0053] By extending the semiconductor layers SL of different semiconductor elements SE corresponding to the functional area FR in different directions or by the above-mentioned distance design, the irregularity of the arrangement of the film layers or elements corresponding to the functional area FR can be increased, thereby reducing the possibility of light diffraction in the functional area FR and affecting the photosensitive element. Figure 4 As shown, the electronic panel EP may further include a third semiconductor element SE3 and a fourth semiconductor element SE4 corresponding to the functional region FR, each including a third semiconductor layer SL3 and a fourth semiconductor layer SL4. Figure 4 As shown, the third semiconductor layer SL3 may extend in direction X, and the fourth semiconductor layer SL4 may extend in direction -X. In some embodiments, the first semiconductor layer SL1 may extend in direction -X, the second semiconductor layer SL2 may extend in direction X, the third semiconductor layer SL3 may extend in direction -Y, and the fourth semiconductor layer SL4 may extend in direction Y.

[0054] It should be noted that although Figure 3Not shown, the connection wiring CW connected to the first semiconductor element SE1 and the second semiconductor element SE2 may be electrically connected to the driving element DE corresponding to the peripheral region PR. Figure 3 The structures of the other components, film layers, and the electronic panel EP corresponding to the display area DR and the peripheral area PR of the substrate SB can be referred to. Figure 2 As for the relevant content mentioned above, I will not go into details here.

[0055] Please refer to Figure 5 , Figure 5 FIG. 1 is a top view of the functional area of ​​the electronic panel of the third embodiment of the present invention. Figure 5 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 According to this embodiment, the color conversion element CE corresponding to the functional region FR (or corresponding to the semiconductor element SE on the functional region FR) may extend in one direction (for example, compared to Figure 2 The color conversion element CE shown may extend in one direction), so that the center CC of the color conversion element CE may be offset from the center CS of the semiconductor layer SL of the semiconductor element SE to which the color conversion element CE corresponds. Figure 5As shown, the first color conversion element CE1 corresponding to the first semiconductor element SE1 may extend in the direction -X, so that the center CC of the first color conversion element CE1 is offset from the center CS of the first semiconductor layer SL1 in the direction -X, but not limited thereto. The distance range of the center CC of the first color conversion element CE1 offset from the center CS of the first semiconductor layer SL1 may refer to the range of the first distance L1 mentioned above, but not limited thereto. In this case, in the top view direction of the electronic panel EP, the center CS of the first semiconductor layer SL1 and the center CC of the first color conversion element CE1 may define a virtual straight line VL, and the virtual straight line VL may intersect with the edge of the first semiconductor layer SL1 at the first point P1 and the second point P2, and the virtual straight line VL may intersect with the edge of the first color conversion element CE1 at the third point P3 and the fourth point P4, wherein the first point P1 is located between the third point P3 and the center CC of the first color conversion element CE1, and the second point P2 is located between the fourth point P4 and the center CC of the first color conversion element CE1. In other words, the first color conversion element CE1 may cover the first semiconductor layer SL1 in the top view direction of the electronic panel EP. There may be a first distance T1 between the first point P1 and the third point P3, and there may be a second distance T2 between the second point P2 and the fourth point P4, wherein the first distance T1 may be different from the second distance T2, for example, the first distance T1 may be smaller than the second distance T2, but not limited thereto. By extending the first color conversion element CE1 in one direction so that its center CC is offset from the center CS of the first semiconductor layer SL1, the irregularity of the arrangement of the film layer or element corresponding to the functional region FR may be increased, thereby reducing the possibility of light diffraction in the functional region FR and affecting the photosensitive element. It should be noted that, in addition to the above-mentioned first color conversion element CE1, other color conversion elements CE corresponding to the functional region FR may extend in one direction respectively, and different color conversion elements CE may randomly extend in any direction. In some embodiments, the first color conversion element CE1 may extend in two opposite directions (for example, direction X and direction -X, but not limited thereto), but the extension degrees in the two directions are different, so that the first distance T1 may be different from the second distance T2, thereby changing the position of the center CC. Furthermore, in this embodiment, the center CA of the first electrode E1 may overlap with the center CS of the first semiconductor layer SL1 , but the present invention is not limited thereto.

[0056] like Figure 5As shown, the electronic panel EP may also include a second semiconductor element SE2 corresponding to the functional region FR and a second color conversion element CE2 corresponding to the second semiconductor element SE2, wherein the second color conversion element CE2 may extend along a direction (e.g., direction X) so that the center CC of the second color conversion element CE2 is offset from the center CS of the second semiconductor layer SL2. In this case, in the top view direction of the electronic panel EP, the center CS of the second semiconductor layer SL2 and the center CC of the second color conversion element CE2 may define a virtual straight line VL1, and the virtual straight line VL1 may intersect with the edge of the second semiconductor layer SL2 at the fifth point P6 and the sixth point P6, and the virtual straight line VL1 may intersect with the edge of the second color conversion element CE2 at the seventh point P7 and the eighth point P8. Similarly, the third distance T3 between the fifth point P5 and the seventh point P7 may be different from the fourth distance T4 between the sixth point P6 and the eighth point P8. In addition, in this embodiment, the extension degrees of different color conversion elements CE corresponding to the functional region FR may be different. Specifically, as Figure 5 As shown, the extension of the first color conversion element CE1 can be represented by the second distance T2 between the second point P2 and the fourth point P4, and the extension of the second color conversion element CE2 can be represented by the third distance T3 between the fifth point P5 and the seventh point P7, wherein the second distance T2 can be different from the third distance T3. In this way, the arrangement irregularity of the film layer or element corresponding to the functional region FR can be increased.

[0057] Please refer to Figure 6 , Figure 6 FIG. 1 is a top view of the functional area of ​​the electronic panel of the fourth embodiment of the present invention. Figure 6 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 In this embodiment, the semiconductor layer SL of the semiconductor element SE corresponding to the functional region FR may extend in one direction (ie, compared to Figure 2 The semiconductor element SE shown may extend in one direction, so that the center of the semiconductor layer SL may be offset from the center of the corresponding color conversion element CE. Figure 6 As shown, the first semiconductor layer SL1 of the first semiconductor element SE1 disposed on the functional region FR may extend in the direction X, but is not limited thereto. Figure 6A structure in which the semiconductor layers SL of multiple semiconductor elements SE extend in the same direction is shown, but the present embodiment is not limited thereto. In the present embodiment, since the semiconductor layer SL of the semiconductor element SE may extend in one direction, the semiconductor layer SL may include a portion protruding from the color conversion element CE corresponding to the semiconductor element SE. For example, the first semiconductor layer SL1 may include a portion PO1 protruding from the first color conversion element CE1, but the present invention is not limited thereto. According to the present embodiment, the portion of the semiconductor layer SL of a semiconductor element SE protruding from the color conversion element CE corresponding to the semiconductor element SE may overlap or at least partially overlap with the connection trace CW electrically connected to the semiconductor element SE (for example, the first electrode E1 of the semiconductor element SE) in the top view direction of the electronic panel EP. Specifically, as Figure 6 As shown, the connection trace CW1 electrically connected to the first semiconductor element SE1 may overlap with the portion PO1 of the first semiconductor layer SL1 in the top view direction of the electronic panel EP, or in other words, in the top view of the electronic panel EP, the connection trace CW1 electrically connected to the first semiconductor element SE1 may pass through the portion PO1 of the first semiconductor layer SL1. By making the connection trace CW overlap with the portion of the semiconductor layer SL protruding from the color conversion element CE, the influence of the connection trace CW on the transmittance of the functional region FR can be reduced. In some embodiments, the portion of the semiconductor layer SL of a semiconductor element SE protruding from the color conversion element CE corresponding to the semiconductor element SE may also overlap or at least partially overlap with the connection trace CW electrically connected to other semiconductor elements SE in the top view direction of the electronic panel EP. For example, Figure 6 As shown, the portion PO1 of the first semiconductor layer SL1 may also overlap the connection trace CW2 electrically connected to the second semiconductor element SE2.

[0058] Please refer to Figure 7 , Figure 7 FIG. 5 is a cross-sectional view of the functional area of ​​the electronic panel according to the fifth embodiment of the present invention. Figure 7 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 , so it is not repeated here. The electronic panel EP of this embodiment may include a first semiconductor element SE1 disposed on the functional region FR, a first color conversion element CE1 disposed on the first semiconductor element SE1, and an insulating pattern INP1 disposed between the functional region FR and the first semiconductor element SE1. The insulating pattern INP1 may be disposed on the buffer layer BF and may correspond to the first semiconductor element SE1, but is not limited thereto. According to this embodiment, the first semiconductor layer SL1 of the first semiconductor element SE1 may extend in a direction (i.e., compared to Figure 2The semiconductor layer SL shown in the figure may extend in one direction), and the insulating pattern INP1 corresponding to the first semiconductor element SE1 may extend in another direction, wherein the extending direction of the first semiconductor layer SL1 may be different from the extending direction of the insulating pattern INP1, but is not limited thereto. Figure 7 As shown, the first semiconductor layer SL1 may extend in the direction X, and the insulating pattern INP1 may extend in the direction -X, but not limited thereto. In this case, the center CS of the first semiconductor layer SL1 and the center CI of the insulating pattern INP1 may be offset from the center CC of the first color conversion element CE1, wherein the center CS and the center CI may be on both sides of the center CC, respectively, but not limited thereto. In addition, the center CS of the first semiconductor layer SL1 may be offset from the center CI of the insulating pattern INP1. Similarly, the second semiconductor layer SL2 of the second semiconductor element SE2 may extend in the direction -X, and the insulating pattern INP2 corresponding to the second semiconductor element SE2 may extend in the direction X. It should be noted that although Figure 7 The structure in which the first semiconductor layer SL1 and the insulating pattern INP1 extend in opposite directions is shown, but the present embodiment is not limited thereto. In some embodiments, the extending direction of the first semiconductor layer SL1 may be opposite to the extending direction of the insulating pattern INP1. In some embodiments, the extending direction of the first semiconductor layer SL1 and the extending direction of the insulating pattern INP1 may be any two different directions. In addition, according to the present embodiment, Figure 7 As shown, one side of the first semiconductor layer SL1 may extend in the direction X and protrude from the first color conversion element CE1, and may have a first distance R1 between the first color conversion element CE1; and one side of the insulating pattern INP1 may extend in the direction -X and protrude from the first color conversion element CE1, and may have a second distance R2 between the first color conversion element CE1, wherein the first distance R1 may be different from the second distance R2. Through the pattern design or distance design of the semiconductor layer SL and the insulating pattern INP, the arrangement irregularity of the film layer or element corresponding to the functional region FR may be increased, thereby reducing the possibility of light diffraction in the functional region FR and affecting the photosensitive element.

[0059] Please refer to Figure 8 , Figure 8 FIG. 6 is a cross-sectional view of the functional area of ​​the electronic panel according to the sixth embodiment of the present invention. Figure 8 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 According to this embodiment, the electronic panel EP may include an insulating pattern INP disposed on the insulating layer I2, wherein the insulating pattern INP may be disposed adjacent to the first electrode E1 of the first semiconductor element SE1 (and / or the second semiconductor element SE2). Figure 8 As shown, the insulating pattern INP1 and the insulating pattern INP2 may be disposed adjacent to both sides of the first electrode E1, but are not limited thereto. In some embodiments, the insulating pattern INP may extend upward along the side of the first electrode E1 to the top surface S1 of the first electrode E1, but are not limited thereto. In this way, a portion of the insulating pattern INP may be disposed on the first electrode E1 and cover the first electrode E1. In this case, the insulating pattern INP may be disposed adjacent to the first semiconductor layer SL1. The insulating layer I3 may cover the insulating pattern INP. According to this embodiment, in the cross-sectional view of the electronic panel EP, the insulating patterns INP (e.g., the insulating pattern INP1 and the insulating pattern INP2) located on both sides of the first electrode E1 may have different widths. As Figure 8 As shown, the insulating pattern INP1 disposed on one side of the first electrode E1 of the first semiconductor element SE1 may have a width W3, and the insulating pattern INP2 disposed on the other side of the first electrode E1 of the first semiconductor element SE1 may have a width W4, wherein the width W3 may be different from the width W4, but is not limited thereto. The above-mentioned "width W3 of the insulating pattern INP1" may be defined as the width of the projection of the insulating pattern INP1 on a plane perpendicular to the top-view direction of the electronic panel EP, but is not limited thereto. The width W4 of the insulating pattern INP2 may be defined in the same manner, so it is not repeated here. Similarly, the width W5 of the insulating pattern INP3 disposed on one side of the first electrode E1 of the second semiconductor element SE2 may be different from the width W6 of the insulating pattern INP4 disposed on the other side of the first electrode E1 of the second semiconductor element SE2. In addition, the width W3, the width W4, the width W5 and the width W6 may be different from each other, but are not limited thereto. By setting the insulating pattern INP and / or designing the size of the insulating pattern INP, the arrangement irregularity of the film layer or element corresponding to the functional region FR can be increased, thereby reducing the possibility of light diffraction in the functional region FR and affecting the photosensitive element.

[0060] It should be noted that the structure of the insulating pattern INP in this embodiment is not based on Figure 8 The figure is limited. In some embodiments, the insulating pattern INP may not be disposed on the first electrode E1. For example, the insulating pattern INP may be disposed adjacent to the first electrode E1 without extending along the side of the first electrode E1. In some embodiments, in the cross-sectional view of the electronic panel EP, the insulating pattern INP may be disposed only on one side of the first electrode E1. For example, the electronic panel EP may include an insulating pattern INP1 or an insulating pattern INP2 disposed on one side of the first electrode E1 of the first semiconductor element SE1 and / or an insulating pattern INP3 or an insulating pattern INP4 disposed on one side of the first electrode E1 of the second semiconductor element SE2.

[0061] Please refer to Fig. 9 , Fig. 9FIG. 1 is a cross-sectional view of the functional area of ​​the electronic panel of the seventh embodiment of the present invention. Fig. 9 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 As described above, the electronic panel EP may include an insulating layer I3 disposed on the first electrode E1, wherein the insulating layer I3 may have an opening OP1, and the first semiconductor layer SL1 may enter the opening OP1 and be electrically connected to the first electrode E1 through the opening OP1. Fig. 9 ), the opening OP1 may be defined by the sidewall SW of the insulating layer I3, and the sidewall SW of the insulating layer I3 may have an angle θ1. The angle θ1 of the sidewall SW may be defined, for example, in the following manner. First, as Fig. 9 As shown, a first point PP1 where the side wall SW of the insulating layer I3 contacts the top surface S1 of the first electrode E1 may be defined first. Next, a second point PP2 may be defined on the side wall SW at a position corresponding to 0.1 times the height H1 of the insulating layer I3. Specifically, the second point PP2 on the side wall SW may have a height H2, and the height H2 may be defined as the vertical distance from the second point PP2 to the top surface S1 of the first electrode E1, wherein the height H2 may be 0.1 times the height H1. The above-mentioned "height H1 of the insulating layer I3" may be the vertical distance from the top surface S2 of the insulating layer I3 to the top surface S1 of the first electrode E1, but is not limited thereto. That is, the measurement reference plane of the height H1 and the height H2 may be the top surface S1 of the first electrode E1. After defining the first point PP1 and the second point PP2, a virtual straight line VL2 can be defined by the first point PP1 and the second point PP2, and the angle between the virtual straight line VL2 and the top surface S1 of the first electrode E1 (or the angle between the virtual straight line VL2 and the horizontal direction (e.g., direction X)) can be defined as the angle θ1 of the side wall SW. According to the present embodiment, the angle θ1 of the side wall SW can range from 30 degrees to 90 degrees (i.e., 30°≤θ1≤90°), but is not limited thereto. In some embodiments, the angle θ1 can range from 60 degrees to 90 degrees (i.e., 60°≤θ1≤90°). In some embodiments, the angle θ1 can range from 75 degrees to 90 degrees (i.e., 75°≤θ1≤90°). By making the angle θ1 of the side wall SW of the insulating layer I3 within the above range, the large-angle light emitted from the semiconductor element SE can be reduced, thereby reducing the possibility that the light does not pass through the color conversion element CE and affects the display quality of the electronic panel EP.

[0062] Please refer to Fig.10 , Fig.10 FIG. 8 is a cross-sectional view of the functional area of ​​the electronic panel of the eighth embodiment of the present invention. Fig.10Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 According to this embodiment, the semiconductor layer SL of a semiconductor element SE on the functional region FR of the substrate SB of the electronic panel EP may extend in one direction, and the color conversion element CE corresponding to the semiconductor element SE may extend in another direction, wherein the extension direction of the semiconductor layer SL may be different from the extension direction of the color conversion element CE. Fig.10 As shown, the first semiconductor layer SL1 of the first semiconductor element SE1 may extend in the direction X, and the first color conversion element CE1 corresponding to the first semiconductor element SE1 may extend in the direction -X, but is not limited thereto. In some embodiments, the extension direction of the first semiconductor layer SL1 may be perpendicular to the extension direction of the first color conversion element CE1. In some embodiments, the first semiconductor layer SL1 may extend in one direction, and the first color conversion element CE1 may extend in another direction different from the direction, wherein the direction and the other direction may be any direction. Similarly, the extension direction (e.g., direction -X) of the second semiconductor layer SL2 of the second semiconductor element SE2 may be different from the extension direction (e.g., direction X) of the second color conversion element CE2 corresponding to the second semiconductor element SE2. Through the above design, the center CS of the semiconductor layer SL of the semiconductor element SE disposed on the functional region FR may be offset from the center CC of the color conversion element CE corresponding to the semiconductor element SE, and the range of the offset distance may refer to the range of the above-mentioned first distance L1, so it will not be repeated. In addition, in the cross-sectional view of the electronic panel EP of the present embodiment, the distances between the semiconductor layer SL and the color conversion element CE on both sides of the semiconductor element SE may be different. For example, as Fig.10 As shown, on the right side of the first semiconductor element SE1, the first semiconductor layer SL1 may protrude from the first color conversion element CE1, and a first distance B1 may be provided between the side edge of the first color conversion element CE1 and the side edge of the first semiconductor layer SL1; on the left side of the first semiconductor element SE1, the first color conversion element CE1 may protrude from the first semiconductor layer SL1, and a second distance B2 may be provided between the side edge of the first color conversion element CE1 and the side edge of the first semiconductor layer SL1, wherein the first distance B1 may be different from the second distance B2, but is not limited thereto. In some embodiments, the first distance B1 may be the same as the second distance B2. By making the semiconductor layer SL of the semiconductor element SE disposed on the functional region FR and the color conversion element CE corresponding to the semiconductor element SE extend in different directions, the irregularity of the film layer corresponding to the functional region FR may be increased, thereby reducing the possibility of light diffraction in the functional region FR and affecting the photosensitive element.

[0063] Please refer to Fig.11 , Fig.11 FIG. 1 is a cross-sectional view of the functional area of ​​the electronic panel of the ninth embodiment of the present invention. Fig.11 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 In this embodiment, the color conversion element CE may be disposed on the surface of the insulating layer I4 (ie, the above-mentioned encapsulation layer). Fig.11 As shown, the first color conversion element CE1 may be disposed on the surface (i.e., the top surface S3) of the insulating layer I4, and the insulating layer I4 may be disposed between the first color conversion element CE1 and the first semiconductor element SE1. In detail, the insulating layer I4 has a top surface S3 facing the color conversion element CE (e.g., the first color conversion element CE1), wherein the top surface S3 may include a groove RS, and the color conversion element CE may be disposed in the groove RS. Here, "the color conversion element CE is disposed in the groove RS" may include a situation where at least a portion of the color conversion element CE is filled in the groove RS. The electronic panel EP may also include an insulating layer PAV disposed on the color conversion element CE. The insulating layer PAV may be disposed on the insulating layer I4 and cover the color conversion element CE. The insulating layer PAV may include any suitable insulating material. According to this embodiment, the groove RS may correspond to the semiconductor element SE, or the groove RS may at least partially overlap the semiconductor element SE in the top view direction of the electronic panel EP. Therefore, the color conversion element CE disposed in the groove RS may correspond to the semiconductor element SE. The groove RS may be formed by removing a portion of the insulating layer I4 corresponding to the semiconductor element SE. For example, a portion of the insulating layer I4 corresponding to the semiconductor element SE may be removed by half-tone exposure technology or other suitable methods to form the groove RS. In this embodiment, the grooves RS on the top surface S3 of the insulating layer I4 may correspond to a semiconductor element SE respectively, and the color conversion element CE may be disposed in the groove RS to correspond to the semiconductor element SE. Fig.11 As shown, the top surface S3 of the insulating layer I4 may include a groove RS overlapping the first semiconductor element SE1, and the first color conversion element CE1 may be disposed in the groove RS. By disposing the color conversion element CE on the top surface S3 of the insulating layer I4 and / or disposing the color conversion element CE in the groove RS, the vertical distance between the color conversion element CE and the semiconductor element SE to which it corresponds may be reduced. In this way, the possibility of large-angle light emitted by the semiconductor element SE passing through the color conversion element CE may be increased. Specifically, as Fig.11As shown, a vertical distance VD1 may exist between the bottom surface S4 of the first color conversion element CE1 and the top surface S5 of the first semiconductor layer SL1 (or a portion of the first semiconductor layer SL1 that contacts the first electrode E1), wherein the vertical distance VD1 may range from 3 μm to 8 μm (i.e., 3 μm ≤ VD1 ≤ 8 μm). In some embodiments, the vertical distance VD1 may range from 3 μm to 5 μm (i.e., 3 μm ≤ VD1 ≤ 5 μm). The vertical distance between the bottom surface of the second color conversion element CE2 and the top surface of the second semiconductor layer SL2 may be the same as or different from the vertical distance VD1. It should be noted that the pattern design of the semiconductor layer SL and the color conversion element CE in this embodiment may refer to the contents of the above embodiments and is not limited to the vertical distance VD1. Fig.11 Limits shown.

[0064] Please refer to Fig.12 , Fig.12 FIG. 1 is a cross-sectional view of a functional area of ​​an electronic panel according to a tenth embodiment of the present invention. Fig.12 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 , so it will not be repeated. According to the present embodiment, the electronic panel EP may include a shading pattern layer LS disposed on the insulating layer I2, wherein the shading pattern layer LS may be disposed corresponding to the semiconductor element SE. For example, the shading pattern layer LS may be disposed corresponding to the semiconductor element SE (i.e., the first semiconductor element SE1 and the second semiconductor element SE2) disposed on the functional region FR, but is not limited thereto. Specifically, although not shown in the figure, the shading pattern layer LS may surround the first electrode E1 of the semiconductor element SE disposed on the functional region FR in the top view direction of the electronic panel EP, but is not limited thereto. For example, the shading pattern layer LS1 may surround the first electrode E1 of the first semiconductor element SE1, and the shading pattern layer LS2 may surround the first electrode E1 of the second semiconductor element SE2. In some embodiments, the shading pattern layer LS may be partially disposed on the first electrode E1. The shading pattern layer LS may define an opening OP3, and the semiconductor layer SL (e.g., the first semiconductor layer SL1 and the second semiconductor layer SL2) may be disposed in the opening OP3, so as to be electrically connected to the first electrode E1. In other words, the shading pattern layer LS may serve as a pixel definition layer. The electronic panel EP of this embodiment may not include the above-mentioned insulating layer I3, but is not limited thereto. The light-shielding pattern layer LS may include any suitable light-shielding material, for example, may include the above-mentioned black matrix layer BM. The second electrode E2 may be conformally disposed on the semiconductor layer SL, the light-shielding pattern layer LS and the insulating layer I2, but is not limited thereto.

[0065] According to the present embodiment, the semiconductor layer SL of the semiconductor element SE disposed on the functional region FR may cross the light shielding pattern layer LS and extend outside the light shielding pattern layer LS. Specifically, the semiconductor layer SL may extend along the side and top surface of the light shielding pattern layer LS, and then extend to the outside of the light shielding pattern layer LS. In other words, at least a portion of the semiconductor layer SL may be located outside the light shielding pattern layer LS. For example, Fig.12 As shown, the first semiconductor layer SL1 of the first semiconductor element SE1 can extend in the direction X and cross the shading pattern layer LS1; and the second semiconductor layer SL2 of the second semiconductor element SE2 can extend in the direction -X and cross the shading pattern layer LS2, but it is not limited thereto. In this way, the center CS of the first semiconductor layer SL1 can be offset from the center CC of the first color conversion element CE1, and the center CS of the second semiconductor layer SL2 can be offset from the center CC of the second color conversion element CE2. By extending the semiconductor layer SL disposed on the functional region FR in one direction to cross the shading pattern layer LS, the irregularity of the film layer corresponding to the functional region FR can be increased, thereby reducing the possibility of light diffraction in the functional region FR and affecting the photosensitive element. In this embodiment, different semiconductor layers SL can extend in different directions and cross different sides of the shading pattern layer LS.

[0066] In some embodiments, the widths of the portions of different semiconductor layers SL located outside the light shielding pattern layer LS may be different. Fig.12 As shown, the portion of the first semiconductor layer SL1 located outside the light-shielding pattern layer LS1 may have a width X1, and the portion of the second semiconductor layer SL2 located outside the light-shielding pattern layer LS2 may have a width X2, wherein the width X1 may be different from the width X2. By making the portions of different semiconductor layers SL located outside the light-shielding pattern layer LS have different widths, the irregularity of the film layer corresponding to the functional region FR may be increased.

[0067] In some embodiments, in the cross-sectional view of the electronic panel EP, the widths of the portions of the light shielding pattern layer LS located on both sides of the first electrode E1 may be different. Fig.12 As shown, the shading pattern layer LS1 may include a portion PT1 on the left side of the first electrode E1 and a portion PT2 on the right side of the first electrode E1, the portion PT1 may have a width X3, and the portion PT2 may have a width X4, wherein the width X3 may be different from the width X4. The width X3 (or the width X4) may be defined as the maximum width of the portion PT1 (or the portion PT2) in the cross-sectional view of the electronic panel EP, but is not limited thereto. In some embodiments, one of the portions of the shading pattern layer LS located on both sides of the first electrode E1 that is not spanned by the semiconductor layer SL may have a larger width. For example, as Fig.12As shown, the first semiconductor layer SL1 may span the portion PT2 of the light shielding pattern layer LS, and the width X4 of the portion PT2 may be smaller than the width X3 of the portion PT1, but is not limited thereto. In some embodiments, the width X4 may be the same as the width X3. Through the above design, the irregularity of the film layer corresponding to the functional region FR may be increased.

[0068] Please refer to Fig.13 , Fig.13 FIG. 1 is a cross-sectional view of a functional area of ​​an electronic panel according to an eleventh embodiment of the present invention. Fig.13 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 According to this embodiment, the semiconductor element SE of the electronic panel EP may include an inorganic light emitting diode. Fig.13 As shown, the first semiconductor element SE1 and the second semiconductor element SE2 disposed on the functional region FR may include an inorganic light emitting diode. The first semiconductor layer SL1 (or the second semiconductor layer SL2) of the first semiconductor element SE1 (or the second semiconductor element SE2) may be a light emitting layer of the inorganic light emitting diode. Therefore, the center CS of the first semiconductor layer SL1 (or the second semiconductor layer SL2) may be defined as the center of the light emitting layer of the inorganic light emitting diode. The first electrode E1 and / or the second electrode E2 of the first semiconductor element SE1 (or the second semiconductor element SE2) may be electrically connected to the connecting wire CW through the bonding pad BP. In the present embodiment, the semiconductor element SE (e.g., the first semiconductor element SE1 and the second semiconductor element SE2) disposed on the functional region FR may include an inorganic light emitting diode that emits light of different colors (e.g., red, green, or blue), and the first color conversion element CE1 and the second color conversion element CE2 may include color filter elements, but are not limited thereto. According to the present embodiment, the color conversion element CE corresponding to the semiconductor element SE disposed on the functional region FR may extend in a direction so that the center CC of the color conversion element CE may be offset from the center CS of the semiconductor layer SL of the semiconductor element SE to which it corresponds. For example, as Fig.13 As shown in FIG. 1 , the first color conversion element CE1 may extend in the direction X, such that the center CC of the first color conversion element CE1 is offset from the center CS of the first semiconductor layer SL1 (light emitting layer) in the direction X; and the second color conversion element CE2 may extend in the direction X, such that the center CC of the second color conversion element CE2 is offset from the center CS of the second semiconductor layer SL2 (light emitting layer) in the direction X. It should be noted that the extension direction of the first color conversion element CE1 may be different from the extension direction of the second color conversion element CE2, and the extension direction is not necessarily the same. Fig.13 Limits shown.

[0069] In some embodiments, the electronic panel EP may further include an insulating pattern INP. In some embodiments, the insulating pattern INP may be disposed on the buffer layer BF and may correspond to the semiconductor element SE, and its features may refer to Figure 2 or Figure 7 In some embodiments, the insulating pattern INP may be disposed on the insulating layer I2 and adjacent to the bonding pad BP, and its features may refer to Figure 8 , so I won’t go into details.

[0070] Please refer to Fig.14 , Fig.14 FIG. 1 is a cross-sectional view of a functional area of ​​an electronic panel according to a twelfth embodiment of the present invention. Fig.14 Only some components or film layers of the electronic panel EP corresponding to the functional area FR of the substrate SB are shown, and the structures of the remaining components or film layers can be referred to. Figure 2 The semiconductor element SE of this embodiment may include an inorganic light emitting diode, and its structure may refer to Fig.13 According to this embodiment, if Fig.14 As shown, the electronic panel EP may include a shading pattern layer LS3 arranged corresponding to the functional region FR, wherein the shading pattern layer LS3 may be arranged around the color conversion element CE. Specifically, the shading pattern layer LS3 may define an opening OP4, and the color conversion element CE may be arranged in the opening OP4. In the present embodiment, the semiconductor element SE (e.g., the first semiconductor element SE1 and the second semiconductor element SE2) arranged on the functional region FR may include an inorganic light emitting diode that emits light of the same color (e.g., blue), and the first color conversion element CE1 and the second color conversion element CE2 may include suitable light conversion materials, such as quantum dots, but not limited thereto. In this way, the light (e.g., blue light) emitted from the first semiconductor element SE1 (or the second semiconductor element SE2) may be converted into light of a desired color by the first color conversion element CE1 (or the second color conversion element CE2). By arranging the shading pattern layer LS3 around the color conversion element CE, the large-angle light emitted from the semiconductor element SE may be reduced, thereby improving the display quality of the electronic panel EP.

[0071] In addition, in the present embodiment, the electronic panel EP may include an insulating pattern INP disposed between the semiconductor element SE and the functional region FR, wherein the insulating pattern INP may extend in one direction so that the center CI of the insulating pattern INP is offset from the center CS of the semiconductor layer SL or the center CC of the color conversion element CE. In this way, the irregularity of the film layer corresponding to the functional region FR may be increased. In the present embodiment, the center CS of the semiconductor layer SL may overlap the center CC of the color conversion element CE, but is not limited thereto.

[0072] Please refer to Fig.15 , Fig.15 FIG. 1 is a cross-sectional view of an electronic device according to an embodiment of the present invention. Fig.15 The structure of the electronic panel EP is shown in a single layer. The electronic panel EP of this embodiment can be any of the electronic panels EP described in the above embodiments or a combination thereof. According to this embodiment, Fig.15 As shown, the electronic device ED may include an electronic panel EP and a sensing module SEN, wherein the sensing module SEN may be arranged corresponding to a functional area FR of a substrate (not shown) of the electronic panel EP. Specifically, the sensing module SEN is arranged under the functional area FR, but is not limited thereto. In this case, the sensing module SEN may be arranged on both sides of the substrate respectively with the above-mentioned semiconductor elements SE, color conversion elements CE and other elements. The sensing module SEN of the present embodiment may include a light sensing module, wherein the light sensing module may include any suitable photosensitive element that can receive visible light or non-visible light. For example, the light sensing module may include a camera, an infrared detector or other suitable elements. It should be noted that, Fig.15 The sensing module SEN shown may include a single sensing element or a combination of multiple sensing elements. In other words, the electronic device ED may include multiple sensing elements, and these sensing elements may be arranged corresponding to the functional regions FR. As described above, since the film layer corresponding to the functional region FR in the electronic panel EP may have a pattern design to increase the irregularity of the film layer arrangement, the possibility of light diffraction in the functional region FR and affecting the sensing module SEN can be reduced, thereby improving the performance of the sensing module SEN.

[0073] In summary, the present invention provides an electronic device, which includes an electronic panel and a sensing module arranged in a functional area of ​​a substrate of the electronic panel. By extending the semiconductor layer or color conversion element arranged in the electronic panel in a direction corresponding to the functional area, or by making the electronic panel include an additional insulating pattern, the irregularity of the film layer corresponding to the functional area can be increased. In this way, the possibility of light diffraction in the functional area and affecting the photosensitive element can be reduced, thereby improving the performance of the sensing module.

[0074] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An electronic panel, characterized in that: include: a substrate having a functional region, wherein light can pass through the functional region; a first semiconductor element disposed on the functional area, wherein the first semiconductor element comprises a first electrode, a first semiconductor layer disposed on the first electrode, and a second electrode disposed on the first semiconductor layer; as well as a first color conversion element disposed on the first semiconductor element and overlapping the first semiconductor layer; Wherein, in a top-view direction of the electronic panel, a center of the first color conversion element is offset from a center of the first semiconductor layer.

2. The electronic panel according to claim 1, characterized in that: The center of the first color conversion element is offset from the center of the first semiconductor layer by a first distance, and the first distance ranges from 0.1 micrometers to 10 micrometers.

3. The electronic panel according to claim 1, characterized in that: In the top-view direction of the electronic panel, the center of the first semiconductor layer and the center of the first color conversion element define a virtual straight line, the virtual straight line intersects with an edge of the first semiconductor layer at a first point and a second point, the virtual straight line intersects with an edge of the first color conversion element at a third point and a fourth point, the first point has a second distance from the third point, the second point has a third distance from the fourth point, and the second distance is different from the third distance.

4. The electronic panel according to claim 3, characterized in that: The second distance ranges from 0.1 micrometers to 20 micrometers.

5. The electronic panel according to claim 3, characterized in that: The third distance ranges from 0.1 micrometers to 20 micrometers.

6. The electronic panel according to claim 3, characterized in that: The third point is located between the first point and the center of the first color conversion element.

7. The electronic panel according to claim 6, characterized in that: The second point is located between the fourth point and the center of the first color conversion element.

8. The electronic panel according to claim 3, characterized in that: The first point is located between the third point and the center of the first color conversion element, and the second point is located between the fourth point and the center of the first color conversion element.

9. The electronic panel according to claim 1, characterized in that: The invention also includes a second semiconductor element disposed on the functional region and a second color conversion element disposed on the second semiconductor element, wherein the second semiconductor element includes a second semiconductor layer.

10. The electronic panel according to claim 9, characterized in that: The center of the first color conversion element is offset from the center of the first semiconductor layer in a first direction, and a center of the second color conversion element is offset from the center of the second semiconductor layer in a second direction, and the first direction is different from the second direction.

11. The electronic panel according to claim 9, characterized in that: The center of the first color conversion element is offset from the center of the first semiconductor layer by a first distance, a center of the second color conversion element is offset from a center of the second semiconductor layer by a second distance, and the first distance is different from the second distance.

12. The electronic panel according to claim 1, characterized in that: The invention also includes an insulating pattern disposed between the functional area of ​​the substrate and the first semiconductor element, wherein a center of the insulating pattern is offset from the center of the first semiconductor layer.

13. The electronic panel according to claim 1, characterized in that: The invention also includes an insulating pattern, which is disposed on the first electrode and adjacent to the first semiconductor layer.

14. The electronic panel according to claim 1, characterized in that: It also includes an insulating layer, which is arranged on the first electrode and has an opening, and the first semiconductor layer is electrically connected to the first electrode through the opening, wherein in a cross-sectional view of the electronic panel, the opening is defined by a side wall of the insulating layer, and an angle of the side wall ranges from 30 degrees to 90 degrees.

15. The electronic panel according to claim 14, characterized in that: The angle of the side wall ranges from 60 degrees to 90 degrees.

16. The electronic panel according to claim 1, characterized in that: The invention also includes a packaging layer disposed between the first color conversion element and the first semiconductor element, wherein the packaging layer has a top surface facing the first color conversion element, the top surface has a groove, and the groove overlaps the first semiconductor element.

17. The electronic panel according to claim 1, characterized in that: The first semiconductor element is a light emitting element.

18. The electronic panel according to claim 1, characterized in that: The first color conversion element is a color filter element.

19. An electronic device, characterized in that: include: The electronic panel as claimed in claim 1; and A sensing module is arranged under the functional area.

20. The electronic device as claimed in claim 19, wherein: The sensing module is a light sensing module.

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